{ *************************************************************************** }
MODULE mod_tcs_io_DRV11J_handling ;
{ *************************************************************************** }
INCLUDE 
  mod_sys_service,
  mod_common_hard_io, 
  mod_handle_tracing,
  $PHYSICAL_ADDRESS,
  $KERNELMSG ;                                     { from ELN$:RTLOBJECT.OLB  }
{ *************************************************************************** }
EXPORT 
  proced_tcs_define_drv11j,     {PROCEDURE define DRV11j device               }
  proced_tcs_initialize_drv11j, {PROCEDURE initialize DRV11j card             }
  proced_tcs_read_drv11j_intr_reg,{PROCEDURE read DRV11j interrupt ctrl reg   }
  proced_tcs_enb_int,           {PROCEDURE enable interrupt on one REPLY line }
  proced_tcs_dis_int,           {PROCEDURE disable interrupt on one REPLY line}
  p_isr_vect_pilot,             {pointer to interrupt vector for pilot DRV11J }
  p_isr_vect_assist ;           {pointer to interrupt vector for assist DRV11J}
{ *************************************************************************** }
IMPORT
  PortA, PortB, PortC, PortD,   {from module MOD_COMMON_HARD_IO               }
  drv11j_registers,             {from module MOD_COMMON_HARD_IO               }
  reg_drv11j_pilot,             {from module MOD_COMMON_HARD_IO               }
  reg_drv11j_assist,            {from module MOD_COMMON_HARD_IO               }
  dev_drv11j_pilot,             {from module MOD_COMMON_HARD_IO               }
  dev_drv11j_assist,            {from module MOD_COMMON_HARD_IO               }
  outdbra, outdbrb, outdbrc,    {from module MOD_COMMON_HARD_IO               }
 {indbrd,}                      {from module MOD_COMMON_HARD_IO               }
  trg_alloc,                    {from module MOD_COMMON_HARD_IO               }

  find_dev_addr_and_map_mem,          {from module MOD_SYS_SERVICE            }

  handle_trc_inf,               {from module MOD_HANDLE_TRACING               }
  handle_trc_sta,               {from module MOD_HANDLE_TRACING               }
  handle_trc_err,               {from module MOD_HANDLE_TRACING               }
  handle_trc_sys,               {from module MOD_HANDLE_TRACING               }

  KER$_SUCCESS,                       {from module $KERNELMSG                 }
  KER$_DEBUG_SIGNAL,                  {from module $KERNELMSG                 }

  PHYSICAL_ADDRESS,             {from module $PHYSICAL_ADDRESS                } 
  ELN$PHYSICAL_ADDRESS ;        {from module $PHYSICAL_ADDRESS                } 

{ *************************************************************************** }

  %INCLUDE 'ELN$:KERNELDEF.PAS/LIST' {for SCR device record}
 
TYPE

  byte = [BYTE]   0..255   ;
  word = [WORD]   0..65535 ;

VAR

  statusbyte : byte ;                     { drv11j card status registe     ** } 
  p_isr_vect_pilot  :^INTEGER ; { pointer to DRV11J intr vector **  }
  p_isr_vect_assist :^INTEGER ; { pointer to DRV11J intr vector **  }

  KER$GA_DEVICE_LIST : [EXTERNAL] INTEGER ;

{ *************************************************************************** }
{ *************************************************************************** }
PROCEDURE proced_tcs_define_drv11j ;

VAR

  status     : INTEGER ;
  drv11j_ipl : INTEGER ;                  { DRV11J intr processor level   **  }

BEGIN

{ **** defines DRV11-J for Pilot COMINT                                  **** }
  handle_trc_sys ( TAG := 'INI/DRV%', 
               MESSAGE := ' Creating DRV11J_PILOT Device ' ) ;

  { **** defines DRV11-J ports A,B,C,D as dev[0,1,2,3]                   **** }
  CREATE_DEVICE (       'DRV11J_PILOT',
                         dev_drv11j_pilot,
                         SERVICE_ROUTINE := intserv_tcs_drv11j,
                         REGISTERS       := reg_drv11j_pilot,
                         VECTOR          := p_isr_vect_pilot,
                         PRIORITY        := drv11j_ipl,
                         STATUS          := status ) ;

  IF ( status <> KER$_SUCCESS )
  THEN BEGIN
    handle_trc_err ( TAG := 'INI/DRV%', 
                 MESSAGE := ' Unable to create Pilot DRV11J device' ) ;
    handle_trc_sta ( TAG := 'INI/DRV%', STATUS := status ) ;
    raise_exception ( KER$_DEBUG_SIGNAL ) ; {get debugger to investigate }
  END ;

  {CREATE_DEVICE does not return the register base address for the 4000}
  {So we have to retrieve the EBUILD device descritpion by hand}
  find_dev_addr_and_map_mem  ( DEV_NAME := 'DRV11J_PILOT',
                               REG_ADDR := reg_drv11j_pilot,
                               REG_SIZE := SIZE(drv11j_registers) ) ;

  handle_trc_inf ( TAG := 'INI/DRV%', 
               MESSAGE := ' DRV11J Register Base Address  = %X'
                        + HEX(PHYSICAL_ADDRESS(reg_drv11j_pilot)) ) ;
  handle_trc_inf ( TAG := 'INI/DRV%', 
               MESSAGE := ' DRV11J Interrupt Prior Level  = %D ' 
                        + CONVERT(STRING,drv11j_ipl) ) ;
  handle_trc_inf ( TAG := 'INI/DRV%', 
               MESSAGE := ' DRV11J Card Interrupt Vector  = %X'
                        + HEX(PHYSICAL_ADDRESS(p_isr_vect_pilot)) ) ;

{ **** defines DRV11-J for Assistant COMINT                              **** }

  handle_trc_sys ( TAG := 'INI/DRV%', 
               MESSAGE := ' Creating DRV11J_ASSIST Device ' );

  CREATE_DEVICE (       'DRV11J_ASSIST',
                         dev_drv11j_assist,
                         SERVICE_ROUTINE := intserv_tcs_drv11j,
                         REGISTERS       := reg_drv11j_assist,
                         VECTOR          := p_isr_vect_assist,
                         PRIORITY        := drv11j_ipl,
                         STATUS          := status);

  IF ( status <> KER$_SUCCESS )
  THEN BEGIN
    handle_trc_err ( TAG := 'INI/DRV%', 
                 MESSAGE := ' Unable to create Pilot DRV11J device' ) ;
    handle_trc_sta ( TAG := 'INI/DRV%', STATUS := status ) ;
    raise_exception ( KER$_DEBUG_SIGNAL ) ; {get debugger to investigate }
  END ;

  {CREATE_DEVICE does not return the register base address for the 4000}
  {So we have to retrieve the EBUILD device descritpion by hand}
  find_dev_addr_and_map_mem  ( DEV_NAME := 'DRV11J_ASSIST',
                               REG_ADDR := reg_drv11j_assist,
                               REG_SIZE := SIZE(drv11j_registers) ) ;

  handle_trc_inf ( TAG := 'INI/DRV%', 
               MESSAGE := ' DRV11J Register Base Address  = %X'
                        + HEX(PHYSICAL_ADDRESS(reg_drv11j_assist)) ) ;
  handle_trc_inf ( TAG := 'INI/DRV%', 
               MESSAGE := ' DRV11J Interrupt Prior Level  = %D ' 
                        + CONVERT(STRING,drv11j_ipl) ) ;
  handle_trc_inf ( TAG := 'INI/DRV%', 
               MESSAGE := ' DRV11J Card Interrupt Vector  = %X'
                        + HEX(PHYSICAL_ADDRESS(p_isr_vect_assist)) ) ;

  trg_alloc.allocated := FALSE ;
  trg_alloc.owner := NIL ;
  CREATE_EVENT ( trg_alloc.released, EVENT$CLEARED, STATUS := status ) ;
  handle_trc_sta ( TAG := 'CRE/EVE%trgalloc%', STATUS := status ) ;
  
END;
{ *************************************************************************** }
{ This INTERRUPT_SERVICE routine, is indirectly called by ZRL's PQBA_ISR macro}
INTERRUPT_SERVICE intserv_tcs_drv11j
               ( p_drv11j : ^drv11j_registers ; p_isr_mess : ^ANYTYPE ) ;

VAR
  statusbyte : BYTE ;
  portnum    : INTEGER ;
BEGIN

{ **** read group 2 intrpt service reg                                   **** }
  WRITE_REGISTER ( p_drv11j^[PortC].csreg.ctrl::BYTE, 128+32                ) ;
  statusbyte := READ_REGISTER ( p_drv11j^[PortD].csreg.ctrl::BYTE           ) ;

{ **** parse interrupt service mask to find and signal interrupting port **** }
  statusbyte := statusbyte DIV 16 ;
  FOR portnum := PortA TO PortD
  DO BEGIN
    IF ( ( statusbyte MOD 2 ) <> 0 ) 
    THEN BEGIN

      { **** mask the active interrupt line                               *** }
      WRITE_REGISTER( p_drv11j^[PortC].csreg.ctrl::BYTE,    32+16+8+4+portnum);

      { **** clear the interrupt service bit                              *** }
      WRITE_REGISTER( p_drv11j^[PortC].csreg.ctrl::BYTE, 64+32+16+8+4+portnum);

      SIGNAL_DEVICE ( DEVICE_NUMBER := portnum ) ;

    END ;

    statusbyte := statusbyte DIV 2 ;
  END ;

END ;
{ *************************************************************************** }
{ *************************************************************************** }
PROCEDURE proced_tcs_initialize_drv11j ;
VAR 
  isr_progr : INTEGER ;
BEGIN

{ *************************************************************************** }
{ *************************************************************************** }
{ ****                         Pilot DRV11J Card                         **** }
{ *************************************************************************** }
{ *************************************************************************** }

  handle_trc_sys ( TAG := 'INI/DRV%', 
               MESSAGE := ' Programming DRV11J_PILOT Card ' ) ;

{ ****************** reset Am9519 Interrupt Hanling Chips ******************* }
{ **** reset group 1 interrupt                                           **** }
   WRITE_REGISTER ( reg_drv11j_pilot^[PortA].csreg.ctrl::BYTE,       0      ) ;
   statusbyte := READ_REGISTER ( reg_drv11j_pilot^[PortA].csreg.ctrl::BYTE  ) ;
{  WRITELN('TCS_IO_INIT: reset/mask group 1 interrupt = ',BIN(statusbyte));   }

{ **** reset group 2 interrupt                                           **** }
   WRITE_REGISTER ( reg_drv11j_pilot^[PortC].csreg.ctrl::BYTE,       0      ) ;
   statusbyte := READ_REGISTER ( reg_drv11j_pilot^[PortC].csreg.ctrl::BYTE  ) ;
{  WRITELN('TCS_IO_INIT: reset/mask group 2 interrupt = ',BIN(statusbyte));   }

{ ****************** setup ports direction assignment *********************** }
{ **** set interrupt enable                                              **** }
{ **** set port A write direction,  write 0 on port A                    **** }
   WRITE_REGISTER ( reg_drv11j_pilot^[PortA].csreg, dir := 1, ie := 1       ) ;
{  WRITELN ( 'TCS_IO_INIT: port A control/status reg    = ', 
{                BIN(READ_REGISTER(reg_drv11j_pilot^[PortA].csreg::WORD)) ) ; }

   outdbra::WORD := 0 ;
   WRITE_REGISTER ( reg_drv11j_pilot^[PortA].buffer::WORD,  outdbra::WORD   ) ;

{ **** set port B write direction,  write 0 on port B                    **** }
   WRITE_REGISTER ( reg_drv11j_pilot^[PortB].csreg, dir := 1                ) ;
   outdbrb::WORD := 0 ;
   WRITE_REGISTER ( reg_drv11j_pilot^[PortB].buffer::WORD, outdbrb::WORD    ) ;

{ **** set port C write direction,  write 0 on port C                    **** }
   WRITE_REGISTER ( reg_drv11j_pilot^[PortC].csreg, dir := 1                ) ;
   outdbrc.dataout           := 0 ;
   outdbrc.comctrl.disdbb    := 0 ;
   outdbrc.comctrl.disfrmwrk := 0 ;  
   outdbrc.comctrl.togglebuf := 0 ;  
   outdbrc.comctrl.readspy   := 0 ;  
   outdbrc.comctrl.spynextdb := 0 ;  
   outdbrc.comctrl.disdbsend := 0 ;  
   outdbrc.comctrl.cbusreqst := 0 ;  
   outdbrc.comctrl.startdb   := 0 ;  
   WRITE_REGISTER (reg_drv11j_pilot^[PortC].buffer::WORD, outdbrc::WORD     ) ;
 
{ **** set port D read direction                                         **** }
   WRITE_REGISTER ( reg_drv11j_pilot^[PortD].csreg, dir := 0                ) ;


{ ****************** Setup Am9519 Interrupt Hanling Chips ******************* }
{ ***************************** GROUP 1 ************************************* }
{ **** set common vector interrupt and active positive-going transition  **** }
{ **** set fixed priority and interrupt mode   GROUP 1                   **** }
{ **** note: gr 1 and gr 2 intrpt mode MUST be identical to generate GINT**** }
   WRITE_REGISTER ( reg_drv11j_pilot^[PortA].csreg.ctrl::BYTE, 128+16+2     ) ;
   statusbyte := READ_REGISTER ( reg_drv11j_pilot^[PortA].csreg.ctrl::BYTE  ) ;
{  WRITELN ('TCS_IO_INIT: group 1 fixed prio/ com vect = ',BIN(statusbyte)) ; }

{ **** set group 1 interrupt armed (all lines still masked)              **** }
{ **** note: if gr 1 intrpt is not armed, gr 2 will not be enabled (EI)  **** }
   WRITE_REGISTER ( reg_drv11j_pilot^[PortA].csreg.ctrl::BYTE, 128+32+1     ) ;
   statusbyte := READ_REGISTER ( reg_drv11j_pilot^[PortA].csreg.ctrl::BYTE  ) ;
{  WRITELN ('TCS_IO_INIT: set group 1 intrpt armed     = ',BIN(statusbyte)) ; }

{ ***************************** GROUP 2 ************************************* }
{ **** set common vector interrupt and active positive-going transition  **** }
{ **** set fixed priority and interrupt mode                             **** }
   WRITE_REGISTER ( reg_drv11j_pilot^[PortC].csreg.ctrl::BYTE, 128+16+2     ) ;
   statusbyte := READ_REGISTER ( reg_drv11j_pilot^[PortC].csreg.ctrl::BYTE  ) ;
{  WRITELN ('TCS_IO_INIT: group 2 fixed prio/ com vect = ',BIN(statusbyte)) ; }

{ **** set group 2 interrupt armed (all lines still masked)              **** }
   WRITE_REGISTER ( reg_drv11j_pilot^[PortC].csreg.ctrl::BYTE, 128+32+1     ) ;
   statusbyte := READ_REGISTER ( reg_drv11j_pilot^[PortC].csreg.ctrl::BYTE  ) ;
{  WRITELN ('TCS_IO_INIT: set group 2 intrpt armed     = ',BIN(statusbyte)) ; }

{ **** preselect vector address memory for writing 1 byte common vector  **** }
   WRITE_REGISTER ( reg_drv11j_pilot^[PortC].csreg.ctrl::BYTE, 128+64+32    ) ;

{ **** write Interrupt Vector                                            **** }
{ **** This HAS TO MATCH what was defined in EBUILD, since               **** }
{ **** CREATE_DEVICE has already connected the ISR to this vector        **** }
{ **** This is for the Pilot DRV11J/COMINT                               **** }
{ ****               /-3-\ /-4-\ /-0-\                    octal          **** }
{ **** 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0   resulting vector binary         **** }
{ ****             7 6 5 4 3 2 1 0       use CSRD bit number             **** }
{  WRITE_REGISTER ( reg_drv11j_pilot^[PortD].csreg.ctrl::BYTE, 32+16+8      ) ;}
{  11-NOV-1993 use EBUILD data instead }
   isr_progr := (p_isr_vect_pilot::INTEGER MOD 512) DIV 4 ;
   WRITE_REGISTER ( reg_drv11j_pilot^[PortD].csreg.ctrl::BYTE, isr_progr    ) ;
  handle_trc_inf ( TAG := 'INI/DRV%', 
               MESSAGE := ' Pilot DRV11J has Interrupt Vector Number '
                        + CONVERT(STRING,isr_progr) ) ;

   statusbyte := READ_REGISTER ( reg_drv11j_pilot^[PortC].csreg.ctrl::BYTE  ) ;
{  WRITELN ('TCS_IO_INIT: common vector written        = ',BIN(statusbyte)) ; }


{ *************************************************************************** }
{ *************************************************************************** }
{ ****                     Assistant DRV11J Card                         **** }
{ *************************************************************************** }
{ *************************************************************************** }


  handle_trc_sys ( TAG := 'INI/DRV%', 
               MESSAGE := ' Programming DRV11J_ASSIST Card ' ) ;

{ ****************** reset Am9519 Interrupt Hanling Chips ******************* }
{ **** reset group 1 interrupt                                           **** }
   WRITE_REGISTER ( reg_drv11j_assist^[PortA].csreg.ctrl::BYTE,       0     ) ;
   statusbyte := READ_REGISTER ( reg_drv11j_assist^[PortA].csreg.ctrl::BYTE ) ;
{  WRITELN('TCS_IO_INIT: reset/mask group 1 interrupt = ',BIN(statusbyte));   }

{ **** reset group 2 interrupt                                           **** }
   WRITE_REGISTER ( reg_drv11j_assist^[PortC].csreg.ctrl::BYTE,       0     ) ;
   statusbyte := READ_REGISTER ( reg_drv11j_assist^[PortC].csreg.ctrl::BYTE ) ;
{  WRITELN('TCS_IO_INIT: reset/mask group 2 interrupt = ',BIN(statusbyte));   }

{ ****************** setup ports direction assignment *********************** }
{ **** set interrupt enable                                              **** }
{ **** set port A write direction,  write 0 on port A                    **** }
   WRITE_REGISTER ( reg_drv11j_assist^[PortA].csreg, dir := 1, ie := 1      ) ;
{  WRITELN ( 'TCS_IO_INIT: port A control/status reg    = ', 
{               BIN(READ_REGISTER(reg_drv11j_assist^[PortA].csreg::WORD)) ) ; }
   outdbra::WORD := 0 ;
   WRITE_REGISTER ( reg_drv11j_assist^[PortA].buffer::WORD,  outdbra::WORD  ) ;

{ **** set port B write direction,  write 0 on port B                    **** }
   WRITE_REGISTER ( reg_drv11j_assist^[PortB].csreg, dir := 1               ) ;
   outdbrb::WORD := 0 ;
   WRITE_REGISTER ( reg_drv11j_assist^[PortB].buffer::WORD, outdbrb::WORD   ) ;

{ **** set port C write direction,  write 0 on port C                    **** }
   WRITE_REGISTER ( reg_drv11j_assist^[PortC].csreg, dir := 1               ) ;
   WRITE_REGISTER (reg_drv11j_assist^[PortC].buffer::WORD, outdbrc::WORD    ) ;
 
{ **** set port D read direction                                         **** }
   WRITE_REGISTER ( reg_drv11j_assist^[PortD].csreg, dir := 0               ) ;

{ ****************** Setup Am9519 Interrupt Hanling Chips ******************* }
{ ***************************** GROUP 1 ************************************* }
{ **** set common vector interrupt and active positive-going transition  **** }
{ **** set fixed priority and interrupt mode   GROUP 1                   **** }
{ **** note: gr 1 and gr 2 intrpt mode MUST be identical to generate GINT**** }
   WRITE_REGISTER ( reg_drv11j_assist^[PortA].csreg.ctrl::BYTE, 128+16+2    ) ;
   statusbyte := READ_REGISTER ( reg_drv11j_assist^[PortA].csreg.ctrl::BYTE ) ;
{  WRITELN ('TCS_IO_INIT: group 1 fixed prio/ com vect = ',BIN(statusbyte)) ; }

{ **** set group 1 interrupt armed (all lines still masked)              **** }
{ **** note: if gr 1 intrpt is not armed, gr 2 will not be enabled (EI)  **** }
   WRITE_REGISTER ( reg_drv11j_assist^[PortA].csreg.ctrl::BYTE, 128+32+1    ) ;
   statusbyte := READ_REGISTER ( reg_drv11j_assist^[PortA].csreg.ctrl::BYTE ) ;
{  WRITELN ('TCS_IO_INIT: set group 1 intrpt armed     = ',BIN(statusbyte)) ; }

{ ***************************** GROUP 2 ************************************* }
{ **** set common vector interrupt and active positive-going transition  **** }
{ **** set fixed priority and interrupt mode                             **** }
   WRITE_REGISTER ( reg_drv11j_assist^[PortC].csreg.ctrl::BYTE, 128+16+2    ) ;
   statusbyte := READ_REGISTER ( reg_drv11j_assist^[PortC].csreg.ctrl::BYTE ) ;
{  WRITELN ('TCS_IO_INIT: group 2 fixed prio/ com vect = ',BIN(statusbyte)) ; }

{ **** set group 2 interrupt armed (all lines still masked)              **** }
   WRITE_REGISTER ( reg_drv11j_assist^[PortC].csreg.ctrl::BYTE, 128+32+1    ) ;
   statusbyte := READ_REGISTER ( reg_drv11j_assist^[PortC].csreg.ctrl::BYTE ) ;
{  WRITELN ('TCS_IO_INIT: set group 2 intrpt armed     = ',BIN(statusbyte)) ; }

{ **** preselect vector address memory for writing 1 byte common vector  **** }
   WRITE_REGISTER ( reg_drv11j_assist^[PortC].csreg.ctrl::BYTE, 128+64+32   ) ;

{ **** write Interrupt Vector                                            **** }
{ **** This HAS TO MATCH what was defined in EBUILD, since               **** }
{ **** CREATE_DEVICE has already connected the ISR to this vector        **** }
{ **** This is for the Assistant DRV11J/COMINT                           **** }
{ ****               /-3-\ /-5-\ /-0-\                    octal          **** }
{ **** 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0   resulting vector binary         **** }
{ ****             7 6 5 4 3 2 1 0       use CSRD bit number             **** }
{  WRITE_REGISTER ( reg_drv11j_assist^[PortD].csreg.ctrl::BYTE, 32+16+8+2   ) ;}
{  11-NOV-1993 use EBUILD data instead }
   isr_progr := (p_isr_vect_assist::INTEGER MOD 512) DIV 4 ;
   WRITE_REGISTER ( reg_drv11j_assist^[PortD].csreg.ctrl::BYTE, isr_progr    ) ;
  handle_trc_inf ( TAG := 'INI/DRV%', 
               MESSAGE := ' Assistant DRV11J has Interrupt Vector Number '
                        + CONVERT(STRING,isr_progr) ) ;

   statusbyte := READ_REGISTER ( reg_drv11j_assist^[PortC].csreg.ctrl::BYTE ) ;
{  WRITELN ('TCS_IO_INIT: common vector written        = ',BIN(statusbyte)) ; }


{ **** read status registers and all internal registers                  **** }
{  proced_tcs_read_drv11j_intr_reg ;                                          }

END;
{ *************************************************************************** }
{ *************************************************************************** }
PROCEDURE proced_tcs_read_drv11j_intr_reg ( p_drv11j : ^drv11j_registers ) ;

BEGIN

{ **** read status registers and all internal reg for group 1 & 2        **** }

{ ****                    group 1 status register                        **** }
   statusbyte := READ_REGISTER ( p_drv11j^[PortA].csreg.ctrl::BYTE          ) ;
   handle_trc_inf ( TAG := 'DRV/INT%', 
                MESSAGE := ' group 1 status register    = %B'
                         + BIN(statusbyte) ) ;

{ ****                     group 1 intrpt service reg                    **** }
   DISABLE_SWITCH ;
   WRITE_REGISTER ( p_drv11j^[PortA].csreg.ctrl::BYTE, 128+32               ) ;
   statusbyte := READ_REGISTER ( p_drv11j^[PortB].csreg.ctrl::BYTE          ) ;
   ENABLE_SWITCH ;
   handle_trc_inf ( TAG := 'DRV/INT%', 
                MESSAGE := ' group 1 intrpt service reg = %B'
                         + BIN(statusbyte) ) ;

{ ****                     group 1 intrpt mask    reg                    **** }
   DISABLE_SWITCH ;
   WRITE_REGISTER ( p_drv11j^[PortA].csreg.ctrl::BYTE, 128+32+4             ) ;
   statusbyte := READ_REGISTER ( p_drv11j^[PortB].csreg.ctrl::BYTE          ) ;
   ENABLE_SWITCH ;
   handle_trc_inf ( TAG := 'DRV/INT%', 
                MESSAGE := ' group 1 intrpt mask    reg = %B'
                         + BIN(statusbyte) ) ;

{ ****                     group 1 intrpt request reg                    **** }
   DISABLE_SWITCH ;
   WRITE_REGISTER ( p_drv11j^[PortA].csreg.ctrl::BYTE, 128+32+8             ) ;
   statusbyte := READ_REGISTER ( p_drv11j^[PortB].csreg.ctrl::BYTE          ) ;
   ENABLE_SWITCH ;
   handle_trc_inf ( TAG := 'DRV/INT%', 
                MESSAGE := ' group 1 intrpt request reg = %B'
                         + BIN(statusbyte) ) ;

{ ****                     group 1 auto clear     reg                    **** }
   DISABLE_SWITCH ;
   WRITE_REGISTER ( p_drv11j^[PortA].csreg.ctrl::BYTE, 128+32+8+4           ) ;
   statusbyte := READ_REGISTER ( p_drv11j^[PortB].csreg.ctrl::BYTE          ) ;
   ENABLE_SWITCH ;
   handle_trc_inf ( TAG := 'DRV/INT%', 
                MESSAGE := ' group 1 auto clear     reg = %B'
                         + BIN(statusbyte) ) ;

{ ****                    group 2 status register                        **** }

   statusbyte := READ_REGISTER ( p_drv11j^[PortC].csreg.ctrl::BYTE          ) ;
   handle_trc_inf ( TAG := 'DRV/INT%', 
                MESSAGE := ' group 2 status register    = %B'
                         + BIN(statusbyte) ) ;

{ ****                     group 2 intrpt service reg                    **** }
   DISABLE_SWITCH ;
   WRITE_REGISTER ( p_drv11j^[PortC].csreg.ctrl::BYTE, 128+32               ) ;
   statusbyte := READ_REGISTER ( p_drv11j^[PortD].csreg.ctrl::BYTE          ) ;
   ENABLE_SWITCH ;
   handle_trc_inf ( TAG := 'DRV/INT%', 
                MESSAGE := ' group 2 intrpt service reg = %B'
                         + BIN(statusbyte) ) ;

{ ****                     group 2 intrpt mask    reg                    **** } 
   DISABLE_SWITCH ;
   WRITE_REGISTER ( p_drv11j^[PortC].csreg.ctrl::BYTE, 128+32+4             ) ;
   statusbyte := READ_REGISTER ( p_drv11j^[PortD].csreg.ctrl::BYTE          ) ;
   ENABLE_SWITCH ;
   handle_trc_inf ( TAG := 'DRV/INT%', 
                MESSAGE := ' group 2 intrpt mask    reg = %B'
                         + BIN(statusbyte) ) ;

{ ****                     group 2 intrpt request reg                    **** }
   DISABLE_SWITCH ;
   WRITE_REGISTER ( p_drv11j^[PortC].csreg.ctrl::BYTE, 128+32+8             ) ;
   statusbyte := READ_REGISTER ( p_drv11j^[PortD].csreg.ctrl::BYTE          ) ;
   ENABLE_SWITCH ;
   handle_trc_inf ( TAG := 'DRV/INT%', 
                MESSAGE := ' group 2 intrpt request reg = %B'
                         + BIN(statusbyte) ) ;

{ ****                     group 2 auto clear     reg                    **** }
   DISABLE_SWITCH ;
   WRITE_REGISTER ( p_drv11j^[PortC].csreg.ctrl::BYTE, 128+32+8+4           ) ;
   statusbyte := READ_REGISTER ( p_drv11j^[PortD].csreg.ctrl::BYTE          ) ;
   ENABLE_SWITCH ;
   handle_trc_inf ( TAG := 'DRV/INT%', 
                MESSAGE := ' group 2 auto clear     reg = %B'
                         + BIN(statusbyte) ) ;
END ;
{ *************************************************************************** }
{ *************************************************************************** }
PROCEDURE proced_tcs_enb_int ( p_drv11j : ^drv11j_registers ;
                                   chan : INTEGER ) ;

BEGIN

  DISABLE_SWITCH ;

{ **** clear interrupt service bit for the requested Port                **** }
  WRITE_REGISTER( p_drv11j^[PortC].csreg.ctrl::BYTE, 64+32+16+8+4 + chan ) ;

{ ****  enable USER RPLY interrupt for the requested Port                **** }
{ ****  and clear the corresponding interrupt request bit                **** }
  WRITE_REGISTER( p_drv11j^[PortC].csreg.ctrl::BYTE,       16+8+4 + chan ) ;

  ENABLE_SWITCH ;

END;
{ *************************************************************************** }
{ *************************************************************************** }
PROCEDURE proced_tcs_dis_int ( p_drv11j : ^drv11j_registers ;
                                   chan : INTEGER ) ;

BEGIN

{ **** disable USER RPLY interrupt for the requested Port               **** }
  WRITE_REGISTER( p_drv11j^[PortC].csreg.ctrl::BYTE, 32+16+8+4 + chan ) ;

END;
{ *************************************************************************** }
{ *************************************************************************** }
END .