{ *************************************************************************** } MODULE mod_def_hardware_tables ; { Created 5-APR-1989 MICHIGAN STATE UNIVERSITY, TRIGGER CONTROL SOFTWARE } { Updated 24-JAN-1994 Move L1, L1.5 FWks, Caltrig Readout,... to Cbus #2 } { *************************************************************************** } INCLUDE mod_common_global_flags, mod_handle_tracing ; { *************************************************************************** } EXPORT def_hardware_table, {PROCEDURE define hardware tables } find_card_pointer, {PROCEDURE finds pointer to card from physical address } find_reg_pointer, {PROCEDURE finds pointer to register from card and fa } trc_err_init_hdb_fw, {FLAG trace error while initializing framework } trc_err_init_hdb_ct, {FLAG trace error while initializing cal trigger } object_status, {TYPE of object working status } card_header, {TYPE of generic card reference } reg_singularities, {ENUMERATED TYPE of possible singularities of reg type } reg_class, {TYPE SET OF register singularities } histdep, { history dependent register : } { modify and restore might not replace } { the trigger in the same state (even offline)} multidef, { register defined more than once } multir, { multiple read register (e.g. SBSC) } multiw, { multiple write register (e.g. PRESCALER) } dobbuf, { double buffered register } ronly, { read only register } aux_class1, aux_class2, cbus_register, {description of a card's cbus register properties } bbb_card, {RECORD TYPE Bus Buffer Board } mbd_card, {RECORD TYPE Mother Board Driver Card } iml_card, {RECORD TYPE Intermediate Latch Card } imlro_card, {RECORD TYPE Intermediate Latch Readout Card } imlroaux_card, {RECORD TYPE Auxiliary Intermediate Latch Readout Card } andor_card, {RECORD TYPE Andor Card } fstd_card, {RECORD TYPE Final Specific Trigger Decision Card } dbsc_card, {RECORD TYPE Double Buffer Scaler Card } dbsctrgnum_card, {RECORD TYPE Trigger Number Double Buffer Scaler Card } dbscbeamx_card, {RECORD TYPE Beam Crossing Double Buffer Scaler Card } sbsc_card, {RECORD TYPE Single Buffer Scaler Card } tlm_card, {RECORD TYPE Trigger Latch Module Card } dgm_stdig_card, {RECORD TYPE Start Digitize Digimem Card } dgm_bzdis_card, {RECORD TYPE Front End Busy Digimem Card } mtg_card, {RECORD TYPE Master Timing Generator Card } mtg_twb_card, {RECORD TYPE MTG modified for Trouble Warning Bits input } dbsc_L0_P1_P4_card, {RECORD TYPE Level 0 Bunch P1..4 DBSC card } dbsc_L0_P5_P6_card, {RECORD TYPE L0 P5..6, L1.5 Skip, DBB Request DBSC card } dbsc_aux_card, {RECORD TYPE L1.5 Cycle, L1.5 Pot, L0 Good DBSC card } dbsc_foreign_card, {RECORD TYPE Foreign Scalers DBSC card } frw_bbb_type, {ENUMERATED TYPE trigger framework bus buffer names } frw_backplane_type, {ENUMERATED TYPE trigger framework bakcplane names } sptrg_per_aobackp, {ENUMERATED TYPE sptrg per andor backplane } aoterm_per_aobackp, {ENUMERATED TYPE andor term per andor backplane } sptrg_per_fstd, {ENUMERATED TYPE sptrg per fstd card } sptrg_number, {ENUMERATED TYPE sptrg list } sptrg_per_dbsc, {ENUMERATED TYPE sptrg per dbsc card } geosec_per_digm, {ENUMERATED TYPE geographic section per digimem card } sptrg_per_digm, {ENUMERATED TYPE specific trigger per digimem card } geosec_per_tlm, {ENUMERATED TYPE geographic section per tlm card } fired_cable_per_tlm, {ENUMERATED TYPE sptrg fired cabel per tlm card } scaler_per_dbsc, {ENUMERATED TYPE scaler type per dbsc card } relative_sptrg, {ENUMERATED TYPE relative sptrg per fstd card } relative_geo_section,{ENUMERATED TYPE relative geog section per digimem card} bbb_tss, { 1 bus buffer board } mbd_tss, { 1 mother board driver card } mbd_scaler, { 1 mother board driver card } bbb_frw, {ARRAY OF 2 bus buffer boards } mbd_frw, {ARRAY OF 8 mother board driver cards } imlinput, {ARRAY OF 2 by 2 intermediate latch cards input to andor net } imlroinput, {ARRAY OF 2 by 2 intermediate latch readout cards } andor, {ARRAY OF 2 by 32 andor cards } fstd, {ARRAY OF 8 final specific trigger decision cards } dbsc, {ARRAY OF 16 double buffer scaler cards } sbscdis, {ARRAY OF 8 single buffer scaler cards } sbscaofired, { 1 single buffer card andor fired counter } sbscstdig, { 1 single buffer card start digitize Counter } sbscfebz, { 1 single buffer card front end busy } tlmfired, { 1 trigger latch module for sp trg fired fan out } imlrofired, { 1 intermediate latch readout card for sptrg fired } dgmstdig, {ARRAY OF 8 start digitize digimem cards } tlmbusy, { 1 tirgger latch module for front end busy signals } imlrobusy, { 1 intermediate latch readout card for busy signals } dgmbzdis, {ARRAY OF 8 front end disabel sptrg digimem cards } tlmtrgnum, {ARRAY OF 4 trigger latch module for trigger number } tlmstdig, { 1 trigger latch module for start digitize } tlmfiredstb, { 1 trigger latch module for sptrg fired strobe } tlmfiredout, {ARRAY OF 2 trigger latch module for sptrg fired fan out } imlroaux, { 1 auxialary intermediate latch readout card } mtgdirin, { 1 direct in test trigger master timing generator } mtgholdtx, { 1 hold transfer master timing generator card } mtgstdig, { 1 start digitize master timing generator card } mtgbusy, { 1 front end busy master timing generator card } mtgfwtss, { 1 framework timing signal master timing generator } mtgtwb, { 1 framework MTG read TWB } dbsctrgnum, { 1 trigger number double buffered scaler card } dbscbeamx, { 1 beam crossing number double buffered scaler card } dbscvtprep, { 1 Vtrans prepare data double buffered scaler card } dbscwaitvbd, { 1 Vtrans wait VBD buff double buffered scaler card } dbscL0_P1_4, { 1 Level 0 Bunch P1..4 double buffered scaler card } dbscL0_P5_6, { 1 L0 Bunch P5..6, L1.5 Skip, DBB Request DBSC card } dbscaux, { 1 L1.5 Cycle, L1.5 Potential, L0 Good DBSC card } dbscforeign, {ARRAY OF 11 Foreign Scalers double buffered scaler card } {CONST MTG programming values } tss_Force_High, {25 computer force high } tss_Force_Low, { 9 computer force low } tss_Sel_Rom, {12 select rom pattern } tss_ROM_Gated, { 4 select ROM with External Gate } tss_Ext_Bit, {10 select External Bit } tss_Ext_Gated, { 2 select External Bit and External Gate } tss_Map_Low, { 0 map select line always low } tss_Map_Low_High, { 2 map select line low for 1st lookup, high for 2nd} tss_Map_High_Low, { 1 map select line high for 1st lookup, low for 2nd} tss_Map_High, {16 map select line always high } tss_l15_veto_enb, { 0 L1.5 veto MTG PAL normal Level 1.5 operation } tss_l15_veto_low, { 3 L1.5 veto MTG PAL force low } tss_l15_veto_high, { 1 L1.5 veto MTG PAL force high after 1/2 cycle } tss_l15_confirm_enb, { 0 L1.5 confirm MTG PAL normal Level 1.5 operation } tss_l15_confirm_low, { 1 L1.5 confirm MTG PAL force low } tss_l15_confirm_high, { 3 L1.5 confirm MTG PAL force high after 1/2 cycle } tss_l15_receive_enb, { 0 L1.5 receive MTG PAL normal Level 1.5 operation } tss_l15_receive_low, { 1 L1.5 receive MTG PAL force low } tss_l15_receive_high, { 3 L1.5 receive MTG PAL force high } {FA of Framework MTG TSS {Ch: Description } tss_fw_IML_Simu, { 1: IML SELECT HIGH ==> TEST DATA } tss_fw_IML_Latch, { 2: IML CLOCK LOW ==> TRNSPARENT} tss_fw_Read_AB, { 3: 29520 READ A/B HIGH ==> A. } tss_fw_Latch_Shift, { 4: 29520 LATCH/SHIFT RAIS ==> LATCH/SHFT} tss_fw_Write_AB, { 5: 29520 WRITE A/B HIGH ==> A. } tss_fw_for_COMINT { 6: reserved for COMINT -- ==> -- } tss_fw_ANDOR_Strobe, { 7: FSTD AO STROBE HIGH ==> ENABLE. } tss_fw_FSTD_Dis_Latch, { 8: FSTD DISBLE UPDATE CLK. RAIS ==> LATCH } tss_fw_SBSC_Clock, { 9: SBSC SCALER INCRMNT CLCK. FALL ==> COUNT } tss_fw_SBSC_Load, {10: SBSC SCAN RESET & LOAD RAIS ==> LATCH } tss_fw_Busy_Latch, {11: BUSY TLM CLOCK FALL ==> LATCH } tss_fw_Start_Dig_Latch, {12: START DIGITIZE TLM CLCK. FALL ==> LATCH } tss_fw_DBSC_Clock, {13: DBSC INCRMNT CLCK (FSTD) RAIS ==> COUNT } tss_fw_incr_stdigt_num, {14: St.Digt. Number DBSC clk -- ==> -- } tss_fw_skip_one_beam_X, {15: Skip 1 BeamX Andor Term -- ==> -- } tss_fw_LED_on, {16: LED's ON HIGH ==> ENABLE } tss_fw_skip_two_beam_X, {17: Skip 2 BeamX Andor Term -- ==> -- } tss_fw_skip_ten_beam_X, {18: Skip 10 BeamX Andor Term -- ==> -- } tss_fw_l1_per_bunch_clk,{19: L1 per Bunch DBSC clck RAIS ==> COUNT } tss_fw_incr_transf_num, {20: Transfer Number DBSC clk RAIS ==> COUNT } tss_fw_st_fired_strobe, {21: SpTrg Fired Strobe Shape HIGH ==> Strobe } tss_fw_COMINT_clock, {22: COMINT Card Clock RAIS ==> CLOCK } tss_fw_1st_ticks_beamX, {23: First 4 Ticks Each BeamX HIGH ==> 4 Ticks } tss_fw_last_ticks_beamX,{24: Last 4 Ticks Each BeamX HIGH ==> 4 Ticks } tss_fw_P1_crossing_gate,{25: P1 Scalers Gate HIGH ==> Enable P1 } tss_fw_P2_crossing_gate,{26: P2 Scalers Gate HIGH ==> Enable P2 } tss_fw_P3_crossing_gate,{27: P3 Scalers Gate HIGH ==> Enable P3 } tss_fw_P4_crossing_gate,{28: P4 Scalers Gate HIGH ==> Enable P4 } tss_fw_P5_crossing_gate,{29: P5 Scalers Gate HIGH ==> Enable P5 } tss_fw_P6_crossing_gate,{30: P6 Scalers Gate HIGH ==> Enable P6 } tss_fw_last_ticks_turn, {31: Last 4 Ticks End Turn HIGH ==> 4 Ticks } tss_fw_past_end_turn, {32: 4 Ticks past End Turn HIGH ==> 4 Ticks } { *** level 1.5 trigger hardware } imlro_L15_card, {RECORD TYPE L1.5 Intermediate Latch ReadOut card } dgm_L15_control_card, {RECORD TYPE L1.5 control DiGiMem card } dbsc_L15_card, {RECORD TYPE L1.5 Double Buffered SCaler card } tlmL15_fan, {1 Multiplexed L1.5 Terms Trigger Latch Module card } dgmL15_ans, {ARRAY OF 8 start digitize DiGiMem cards } imlroL15, {1 Intermediate Latch ReadOut card } dgmL15_ctrl, {1 L1.5 Control DiGiMem card } mtgL15_vc, {1 Veto/Confirm Master Timing Generator card } mtgL15_mux, {1 L1.5 Term MUX Master Timing Generator card } mtgL15_ctrl, {1 L1.5 Control Master Timing Generator card } dbscL15, {1 Global Double Buffer SCaler card } sbscL15_cnf_rej, {1 Confirm and Reject Single Buffer SCaler card } sbscL15_cyc_skp, {1 Cycle and Skip Single Buffer SCaler card } sbscL15_dead_to, {1 Dead X and Timeout Single Buffer SCaler card } mbdl15, {1 Mother Board Driver card } {FA of L1.5 Ctrl MTG TSS {Ch: Description } tss_L15_potential_incr, { 1: Potential Level 1.5 to M114 DBSC } tss_L15_skip_incr, { 2: Skip Level 1.5 to M114 DBSC } tss_L15_skip, { 3: Skip Level 1.5 to control MTG } tss_L15_start, { 4: Start Level 1.5 } tss_L15_stop, { 5: Stop Level 1.5 } {tss_L15_spare,} { 6: } tss_L15_sgl_start, { 7: Single Start to control MTG } tss_L15_sgl_start_incr, { 8: Single Start to M114 DBSC } tss_L15_sgl_stop, { 9: Single Stop } tss_L15_stretch_local1, {10: L1.5 Stretch to control MTG } tss_L15_stretch_local2, {11: L1.5 Stretch to control MTG } tss_L15_stretch_fwtss1, {12: L1.5 Stretch to FW TSS MTG } tss_L15_stretch_fwtss2, {13: L1.5 Stretch to FW TSS MTG } tss_L15_beg_end_latch, {14: Reserved for DBSC Begin/End Latch } tss_L15_cycle_local, {15: L1.5 Cycle to control MTG } tss_L15_cycle_glob_ext, {16: L1.5 Cyc. to Rec.MTG and V/C MTG } tss_L15_msk_strt_dblock,{17: L1.5 Mask Start Data Block } tss_L15_fired_latch, {18: Final ST Fired Latch to L1.5 IMLRO } tss_L15_status_latch, {19: Status Latch for L1.5 IMLRO } tss_L15_answer_latch, {20: Answer Latch for L1.5 IMLRO } tss_L15_done_latch, {21: Done Latch for L1.5 IMLRO } tss_L15_cycle_clk, {22: Start L1.5 Clock to SBSC Cycle } tss_L15_skip_clk, {23: Start L1.5 Clock to SBSC Skip } tss_L15_veto_conf_clk, {24: End L1.5 Clock for SBSC V/C } {tss_L15_spare,} {25: } tss_L15_dead_X_clk, {26: Dead Beam X Clk to DBSC Ch#1 & SBSC } tss_L15_accept_incr, {27: L1.5 accept Clock to DBSC Ch#2 } tss_L15_reject_incr, {28: L1.5 reject Clock to DBSC Ch#3 } tss_L15_short_timeout, {29: Short Timeout } tss_L15_long_timeout, {30: Long Timeout } tss_L15_stdigt_glob_ext,{31: L1.5 Control of Start Digitize MTG } tss_L15_hldtsf_glob_ext,{32: L1.5 Control of Hold Transfer MTG } { *** calorimeter trigger hardware } mtgcttss, { 1 caltrig timing signal master timing generator } {FA of Cal Trig MTG TSS {Ch: description } tss_ct_ADC_Clock, { 1: ADC Clock FALL ==> LATCH/SHFT} tss_ct_2X_Clock, { 2: 2X Clock RAIS ==> reg PROM } tss_ct_X_Clock, { 3: X Clock RAIS ==> LATCH } tss_ct_Read_AB, { 4: Read A/B Control HIGH ==> A. } tss_ct_Latch_Shift, { 5: Latch-Shift 29525 (and 399) RAIS ==> LATCH/SHFT} tss_ct_Write_AB, { 6: Write A/B Control HIGH ==> A. } tss_ct_CHTCR_Latch, { 7: CHTCR Input Clock FALL ==> LATCH } {tss_ct_not_assigned, { 8: Not Yet Assigned -- ==> -- } tss_ct_ENR_Map_MSB, { 9: Select Energy Page MSB HIGH ==> ONE } tss_ct_ENR_Map_MDB, {10: Select Energy Page MDB HIGH ==> ONE } tss_ct_ENR_Map_LSB, {11: Select Energy Page LSB HIGH ==> ONE } tss_ct_MOM_Map_MSB, {12: Select Momentum Page MSB HIGH ==> ONE } tss_ct_MOM_Map_MDB, {13: Select Momentum Page MDB HIGH ==> ONE } tss_ct_MOM_Map_LSB, {14: Select Momentum Page LSB HIGH ==> ONE } tss_ct_T2_CNT_Latch, {15: Tier 2 Counter CAT2 RAIS ==> LATCH } tss_ct_T3_CNT_Latch, {16: Tier 3 Counter CAT2 RAIS ==> LATCH } tss_ct_T1_ENR_Latch, {17: Tier 1 Energy CAT2 1st/2nd RAIS ==> LATCH } tss_ct_T2_ENR_Latch, {18: Tier 2 Energy CAT2 1st/2nd RAIS ==> LATCH } tss_ct_T3_1st_ENR_Latch,{19: Tier 3 Energy CAT3 1st RAIS ==> LATCH } tss_ct_T3_2nd_ENR_Latch,{20: Tier 3 Energy CAT3 2nd RAIS ==> LATCH } tss_ct_T3_1st_TOT_Latch,{21: Tier 4 Tot Et CAT3 1st RAIS ==> LATCH } tss_ct_T3_2nd_TOT_Latch,{22: Tier 4 Tot CAT3 2nd RAIS ==> LATCH } {tss_ct_not_assigned, {23: Not Yet Assigned -- ==> -- } {tss_ct_not_assigned, {24: Not Yet Assigned -- ==> -- } tss_ct_T1_MOM_Latch, {25: Tier 1 Momentum CAT2 RAIS ==> LATCH } tss_ct_T2_MOM_Latch, {26: Tier 2 Momentum CAT2 RAIS ==> LATCH } tss_ct_T3_MOM_Latch, {27: Tier 3 Momentum CAT3 RAIS ==> LATCH } tss_ct_FMLN_Latch, {28: Tier 4 Momentum FMLN RAIS ==> LATCH } tss_ct_IMLRO_Cnt_latch, {29: Tower Count IMLRO RAIS ==> LATCH } tss_ct_IMLRO_1st_latch, {30: EM&HD Et, Px&Py IMLRO RAIS ==> LATCH } tss_ct_IMLRO_2nd_latch, {31: Tot Et, EM&HD&Tot L2 IMLRO RAIS ==> LATCH } {tss_ct_not_assigned, {32: Not Yet Assigned -- ==> -- } ctfe_card_low_half, {TYPE ctfe card base card address } ctfe_card_high_half, {TYPE ctfe card supplemental card address } cat2_t1_card, {TYPE cat2 card for tier1 } chtcr_card_low_half, {TYPE chtcr card base address } chtcr_card_high_half, {TYPE chtcr card supplemental address } imlro_energy_1_card, {TYPE IMLRO card for Et EM, Et HD, Px, Py } imlro_energy_2_card, {TYPE IMLRO card for E EM, E HD, TOT Et, TOT E } imlro_tower_counts_card, {TYPE IMLRO card for EM Et & TOT Et counts 1,2,3,4 } imlro_caltrig_aux, {TYPE IMLRO card for L0 fast Z, Miss Pt, and spares} jet_list_prog_andor_card,{TYPE andor card transfer jet list progr to 68k } LT_list_prog_andor_card, {TYPE andor card transfer Lg Tile list progr to 68k} cat2_card, {TYPE CAT2 card } cat3_card, {TYPE CAT3 card } fmln_card, {TYPE FMLN card } relative_eta, {ENUMERATED TYPE relative eta on ctfe card } relative_phi, {ENUMERATED TYPE relative eta on cat2 card } adc_data_type_per_ctfe_channel, {ENUMERATED TYPE input type per ctfe channel} threshold_reference_set_type, {ENUMERATED TYPE ctfe threshold refe set typ} threshold_reference_set_number, {ENUMERATED TYPE threshold ref set number } eta_polarity, {ENUMERATED TYPE eta polarity } eta_magnitude, {ENUMERATED TYPE all eta values } magn_eta_per_fe_cell, {ENUMERATED TYPE eta range per ctfe backpl } eta_per_rack_pair, {ENUMERATED TYPE eta range per ctfe rack set} phi_value, {ENUMERATED TYPE all phi values } phi_per_fe_cell, {ENUMERATED TYPE phi range per ctfe cell } phi_per_fe_half_cell, {ENUMERATED TYPE phi range per ctfe 1/2 cell} prom_type, {ENUMERATED TYPE PROM quantity data type } lookup_data_type, {ENUMERATED TYPE lookup quantity data type } lookup_data_topic, {ENUMERATED TYPE Eng quants of equal scale } comparison_number, {ENUMERATED TYPE comparison number } cat2_bit_field, {ENUMERATED TYPE cat2 operand reg bit range } threshold_comparison_type, {ENUMERATED TYPE threshold comparison type } coordinate_type, {ENUMERATED TYPE coordinate type } hot_tower_number, {ENUMERATED TYPE hot tower number } byte_number, {ENUMERATED TYPE byte ordinal reference } prom_page_value, {ENUMERATED TYPE lookup prom page number } global_energy_quantities, {ENUMERATED TYPE global enrgy sum quantities} global_energy_thresholds, {ENUMERATED TYPE global enrgy thresholds } Momentum_sign, {ENUMERATED TYPE Px/Py Momentum sign } cat3_cmp_field, {ENUMERATED TYPE Cat3 compar reg bit fields } cat3_cor_field, {ENUMERATED TYPE Cat3 correc reg bit fields } bbb_calfe, {ARRAY OF 6 bus buffer cards for cal trig f-end /tier 1 } mbd_calfe, {ARRAY OF 24 mother board driver for cal trig f-end /tier 1 } bbb_tier2, {ARRAY OF 3 bus buffer cards for cal trig tier 2 } mbd_tier2, {ARRAY OF 3 mother board driver for cal trig tier 2 } bbb_tier3_4, { 1 bus buffer cards for cal trig tier 3 / 4 } mbd_tier3_4, { 1 mother board driver for cal trig tier 3 / 4 } bbb_readout, { 1 bus buffer cards for cal trig fw exp/readout} mbd_readout, { 1 mother board driver for cal trig fw exp/readout} ctfe_data, {ARRAY OF 384 calorimeter trigger front end card / base addr } ctfe_ctrl, {ARRAY OF 384 calorimeter trigger front end card / supl addr } cat2_EME_t1, {ARRAY OF 48 cal trig adder tree card - tier 1 - EM Energy } cat2_HDE_t1, {ARRAY OF 48 cal trig adder tree card - tier 1 - HD Energy } cat2_PxM_t1, {ARRAY OF 48 cal trig adder tree card - tier 1 - Px Momentum} cat2_PyM_t1, {ARRAY OF 48 cal trig adder tree card - tier 1 - Py Momentum} chtcr_inputs, {ARRAY OF 48 cal trig counting®istering card / base addr } chtcr_sum, {ARRAY OF 48 cal trig counting®istering card / supl addr } cat2_EME_t2, {ARRAY OF 6 cal trig adder tree card - tier 2 - EM Energy } cat2_HDE_t2, {ARRAY OF 6 cal trig adder tree card - tier 2 - HD Energy } cat2_EMC_t2, {ARRAY OF 24 cal trig adder tree card - tier 2 - EM Count } cat2_TOTC_t2, {ARRAY OF 24 cal trig adder tree card - tier 2 - TOT Count } cat2_PxM_t2, {ARRAY OF 6 cal trig adder tree card - tier 2 - Px Momt. } cat2_PyM_t2, {ARRAY OF 6 cal trig adder tree card - tier 2 - Py Momt. } cat3_Py_t3, { 1 cal trig adder tree card - tier 3 - Py Momt. } cat3_Px_t3, { 1 cal trig adder tree card - tier 3 - Px Momt. } cat3_EM_Et_t3, {ARRAY OF 4 cal trig adder tree card - tier 3 - EM 1st Lkp} cat3_EM_L2_t3, { 1 cal trig adder tree card - tier 3 - EM 2nd Lkp} cat3_HD_Et_t3, {ARRAY OF 4 cal trig adder tree card - tier 3 - HD 1st Lkp} cat3_HD_L2_t3, { 1 cal trig adder tree card - tier 3 - HD 2nd Lkp} fmln_compare, { 1 cal trig FMLN card - tier 4 - Missing Pt} fmln_compute, { 1 cal trig FMLN card - compute Missing Pt} cat2_EM_cnt_t3, {ARRAY OF 4 cal trig adder tree card - tier 3 - EM Count } cat2_TOT_cnt_t3,{ARRAY OF 4 cal trig adder tree card - tier 3 - TOT Count } cat3_TOT_Et_t4, {ARRAY OF 3 cal trig adder tree card - tier 4 - EM Energy } cat3_TOT_L2_t4, { 1 cal trig adder tree card - tier 4 - EM Energy } imlro_eng1, { 1 intermediate latch readout card Et EM, Et HD, Px, Py } imlro_eng2, { 1 intermediate latch readout card E EM, E HD, Et TOT, E TOT} imlro_cnts, { 1 intermediate latch readout card EM Et & TOT Et 1,2,3,4 } imlro_ct_aux, { 1 intermediate latch readout card L0 fast Z, MPt and spares} jet_list_aoc, {andor card for transfer of jet list programming to 68k } LT_list_aoc, {andor card for transfer of Lrg Tile list programming to 68k } ERPB_MTG, { 1 L1.5 CT MTG card for ERPB control } cardscanner ; {ARRAY OF POINTERS used to sequentially access all cards/reg } { *************************************************************************** } IMPORT status_type, ok, {already_done, io_failure,} not_found, {from module MOD_COMMON_GLOBAL_FLAGS } state_type, {ON, OFF,} {from module MOD_HANDLE_TRACING } handle_trc_sys ; {from module MOD_HANDLE_TRACING } { *************************************************************************** } { *************************************************************************** } %INCLUDE 'SITE_DEPENDENT.CST/LIST' CONST cbus_0 = 0 ; cbus_1 = 1 ; cbus_2 = 2 ; tss_Force_High = 25 ; tss_Force_Low = 9 ; tss_Sel_ROM = 12 ; tss_ROM_Gated = 4 ; tss_Ext_Bit = 10 ; tss_Ext_Gated = 2 ; tss_Map_Low = 0 ; tss_Map_Low_High = 2 ; tss_Map_High_Low = 1 ; tss_Map_High = 16 ; tss_l15_veto_enb = 0 ; tss_l15_veto_low = 3 ; tss_l15_veto_high = 1 ; tss_l15_confirm_enb = 0 ; tss_l15_confirm_low = 1 ; tss_l15_confirm_high = 3 ; tss_l15_receive_enb = 0 ; tss_l15_receive_low = 1 ; tss_l15_receive_high = 3 ; tss_fw_IML_Simu = 0 ; tss_fw_IML_Latch = 1 ; tss_fw_Read_AB = 2 ; tss_fw_Latch_Shift = 3 ; tss_fw_Write_AB = 4 ; tss_fw_for_COMINT = 5 ; tss_fw_ANDOR_Strobe = 6 ; tss_fw_FSTD_Dis_Latch = 7 ; tss_fw_SBSC_Clock = 8 ; tss_fw_SBSC_Load = 9 ; tss_fw_Busy_Latch = 10 ; tss_fw_Start_Dig_Latch = 11 ; tss_fw_DBSC_Clock = 12 ; tss_fw_incr_stdigt_num = 13 ; tss_fw_skip_one_beam_X = 14 ; tss_fw_LED_on = 15 ; tss_fw_skip_two_beam_X = 16 ; tss_fw_skip_ten_beam_X = 17 ; tss_fw_l1_per_bunch_clk = 18 ; tss_fw_incr_transf_num = 19 ; tss_fw_st_fired_strobe = 20 ; tss_fw_COMINT_clock = 21 ; tss_fw_1st_ticks_beamX = 22 ; tss_fw_last_ticks_beamX = 23 ; tss_fw_P1_crossing_gate = 24 ; tss_fw_P2_crossing_gate = 25 ; tss_fw_P3_crossing_gate = 26 ; tss_fw_P4_crossing_gate = 27 ; tss_fw_P5_crossing_gate = 28 ; tss_fw_P6_crossing_gate = 29 ; tss_fw_last_ticks_turn = 30 ; tss_fw_past_end_turn = 31 ; tss_L15_potential_incr = 0 ; tss_L15_skip_incr = 1 ; tss_L15_stop = 2 ; tss_L15_skip = 3 ; tss_L15_start = 4 ; {tss_L15_spare = 5 ;} tss_L15_sgl_start = 6 ; tss_L15_sgl_start_incr = 7 ; tss_L15_sgl_stop = 8 ; tss_L15_stretch_local1 = 9 ; tss_L15_stretch_local2 = 10 ; tss_L15_stretch_fwtss1 = 11 ; tss_L15_stretch_fwtss2 = 12 ; tss_L15_beg_end_latch = 13 ; tss_L15_cycle_local = 14 ; tss_L15_cycle_glob_ext = 15 ; tss_L15_msk_strt_dblock = 16 ; tss_L15_fired_latch = 17 ; tss_L15_status_latch = 18 ; tss_L15_answer_latch = 19 ; tss_L15_done_latch = 20 ; tss_L15_cycle_clk = 21 ; tss_L15_skip_clk = 22 ; tss_L15_veto_conf_clk = 23 ; {tss_L15_spare = 24 ;} tss_L15_dead_X_clk = 25 ; tss_L15_accept_incr = 26 ; tss_L15_reject_incr = 27 ; tss_L15_short_timeout = 28 ; tss_L15_long_timeout = 29 ; tss_L15_stdigt_glob_ext = 30 ; tss_L15_hldtsf_glob_ext = 31 ; tss_ct_ADC_Clock = 0 ; tss_ct_2X_Clock = 1 ; tss_ct_X_Clock = 2 ; tss_ct_Read_AB = 3 ; tss_ct_Latch_Shift = 4 ; tss_ct_Write_AB = 5 ; tss_ct_CHTCR_Latch = 6 ; {tss_ct_not_assigned = 7 ;} tss_ct_ENR_Map_MSB = 8 ; tss_ct_ENR_Map_MDB = 9 ; tss_ct_ENR_Map_LSB = 10 ; tss_ct_MOM_Map_MSB = 11 ; tss_ct_MOM_Map_MDB = 12 ; tss_ct_MOM_Map_LSB = 13 ; tss_ct_T2_CNT_Latch = 14 ; tss_ct_T3_CNT_Latch = 15 ; tss_ct_T1_ENR_Latch = 16 ; tss_ct_T2_ENR_Latch = 17 ; tss_ct_T3_1st_ENR_Latch = 18 ; tss_ct_T3_2nd_ENR_Latch = 19 ; tss_ct_T3_1st_TOT_Latch = 20 ; tss_ct_T3_2nd_TOT_Latch = 21 ; {tss_ct_not_assigned = 22 ;} {tss_ct_not_assigned = 23 ;} tss_ct_T1_MOM_Latch = 24 ; tss_ct_T2_MOM_Latch = 25 ; tss_ct_T3_MOM_Latch = 26 ; tss_ct_FMLN_Latch = 27 ; tss_ct_IMLRO_Cnt_latch = 28 ; tss_ct_IMLRO_1st_latch = 29 ; tss_ct_IMLRO_2nd_latch = 30 ; {tss_ct_not_assigned = 31 ;} max_card = 1500 ; TYPE byte = [BYTE] 0..255 ; %INCLUDE 'TABLE_ENUM.TYP/LIST' %INCLUDE 'TABLE_CBUS_REG.TYP/LIST' %INCLUDE 'TABLE_CBUS_CARDS.TYP/LIST' VAR trc_err_init_hdb_fw : state_type ; trc_err_init_hdb_ct : state_type ; cardscanner : ARRAY [0..max_card] OF ^card_header ; total_card : INTEGER ; bbb_tss : bbb_card ; mbd_tss : mbd_card ; mbd_scaler : mbd_card ; bbb_frw : ARRAY [bbb_m101..bbb_m102] OF bbb_card ; mbd_frw : ARRAY [mbd_it_128_255_st_0_15..mbd_tlm_sd] OF mbd_card ; imlinput : ARRAY [it_0_127..it_128_255,st_0_15..st_16_31] OF iml_card ; imlroinput : ARRAY [it_0_127..it_128_255,st_0_15..st_16_31] OF imlro_card ; andor : ARRAY [it_0_127..it_128_255,st_0..st_31] OF andor_card ; fstd : ARRAY [st_0_3..st_28_31] OF fstd_card ; dbsc : ARRAY [st_0_1..st_30_31] OF dbsc_card ; sbscdis : ARRAY [st_0_3..st_28_31] OF sbsc_card ; sbscaofired : sbsc_card ; sbscstdig : sbsc_card ; sbscfebz : sbsc_card ; tlmfired : tlm_card ; imlrofired : imlro_card ; dgmstdig : ARRAY [gs_0_3..gs_28_31] OF dgm_stdig_card ; tlmbusy : tlm_card ; imlrobusy : imlro_card ; dgmbzdis : ARRAY [st_0_3..st_28_31] OF dgm_bzdis_card ; tlmtrgnum : ARRAY [gs_0_7..gs_24_31] OF tlm_card ; tlmstdig : tlm_card ; tlmfiredstb : tlm_card ; tlmfiredout : ARRAY [fc_0_3..fc_4_7] OF tlm_card ; imlroaux : imlroaux_card ; mtgdirin : mtg_card ; mtgholdtx : mtg_card ; mtgstdig : mtg_card ; mtgbusy : mtg_card ; mtgfwtss : mtg_card ; mtgtwb : mtg_twb_card ; dbsctrgnum : dbsctrgnum_card ; dbscbeamx : dbscbeamx_card ; dbscvtprep : dbsc_vtrans_run_card ; dbscwaitvbd : dbsc_vtrans_wait_vbd_card ; dbscL0_P1_4 : dbsc_L0_P1_P4_card ; dbscL0_P5_6 : dbsc_L0_P5_P6_card ; dbscaux : dbsc_aux_card ; dbscforeign : ARRAY [1..11] OF dbsc_foreign_card ; { *** Level 1.5 Trigger Hardware } tlmL15_fan : tlm_card ; dgmL15_ans : ARRAY [st_0_3..st_12_15] OF dgm_bzdis_card ; imlroL15 : imlro_L15_card ; dgmL15_ctrl : dgm_L15_control_card ; mtgL15_vc : mtg_card ; mtgL15_mux : mtg_card ; mtgL15_ctrl : mtg_card ; dbscL15 : dbsc_L15_card ; sbscL15_cyc_skp : sbsc_card ; sbscL15_dead_to : sbsc_card ; sbscL15_cnf_rej : sbsc_card ; mbdL15 : mbd_card ; { *** Calorimeter Trigger Hardware } mtgcttss : mtg_card ; bbb_calfe : ARRAY [e_1_8..e_17_24,p_1_16..p_17_32] OF bbb_card ; mbd_calfe : ARRAY [pos_e..neg_e,e_1_4..e_21_24,p_1_16..p_17_32] OF mbd_card ; bbb_tier2 : ARRAY [e_1_8..e_17_24] OF bbb_card ; mbd_tier2 : ARRAY [e_1_8..e_17_24] OF mbd_card ; bbb_tier3_4 : bbb_card ; mbd_tier3_4 : mbd_card ; bbb_readout : bbb_card ; mbd_readout : mbd_card ; {Tier # 1} ctfe_data : ARRAY [pos_e..neg_e,e_1_4..e_21_24,p_1..p_32] OF ctfe_card_low_half ; ctfe_ctrl : ARRAY [pos_e..neg_e,e_1_4..e_21_24,p_1..p_32] OF ctfe_card_high_half ; cat2_EME_t1 : ARRAY [pos_e..neg_e,e_1_4..e_21_24,p_1_8..p_25_32] OF cat2_t1_card ; cat2_HDE_t1 : ARRAY [pos_e..neg_e,e_1_4..e_21_24,p_1_8..p_25_32] OF cat2_t1_card ; cat2_PxM_t1 : ARRAY [pos_e..neg_e,e_1_4..e_21_24,p_1_8..p_25_32] OF cat2_t1_card ; cat2_PyM_t1 : ARRAY [pos_e..neg_e,e_1_4..e_21_24,p_1_8..p_25_32] OF cat2_t1_card ; chtcr_inputs : ARRAY [pos_e..neg_e,e_1_4..e_21_24,p_1_8..p_25_32] OF chtcr_card_low_half ; chtcr_sum : ARRAY [pos_e..neg_e,e_1_4..e_21_24,p_1_8..p_25_32] OF chtcr_card_high_half ; {Tier # 2} cat2_EME_t2 : ARRAY [e_1_4..e_21_24] OF cat2_card ; cat2_HDE_t2 : ARRAY [e_1_4..e_21_24] OF cat2_card ; cat2_EMC_t2 : ARRAY [ref_0..ref_3,e_1_4..e_21_24] OF cat2_card ; cat2_TOTC_t2 : ARRAY [ref_0..ref_3,e_1_4..e_21_24] OF cat2_card ; cat2_PxM_t2 : ARRAY [pos_m..neg_m,e_1_8..e_17_24] OF cat2_card ; cat2_PyM_t2 : ARRAY [pos_m..neg_m,e_1_8..e_17_24] OF cat2_card ; {Tier # 3} cat3_Py_t3 : cat3_card ; cat3_Px_t3 : cat3_card ; cat3_EM_Et_t3 : ARRAY [0..3] OF cat3_card ; cat3_EM_L2_t3 : cat3_card ; cat3_HD_Et_t3 : ARRAY [0..3] OF cat3_card ; cat3_HD_L2_t3 : cat3_card ; cat2_EM_cnt_t3 : ARRAY [ref_0..ref_3] OF cat2_card ; cat2_TOT_cnt_t3 : ARRAY [ref_0..ref_3] OF cat2_card ; {Tier # 4} cat3_TOT_Et_t4 : ARRAY [0..2] OF cat3_card ; cat3_TOT_L2_t4 : cat3_card ; fmln_compare : fmln_card ; fmln_compute : fmln_card ; {readout} imlro_eng1 : imlro_energy_1_card ; imlro_eng2 : imlro_energy_2_card ; imlro_cnts : imlro_tower_counts_card ; imlro_ct_aux : imlro_caltrig_aux ; {argument to 68k} jet_list_aoc : jet_list_prog_andor_card ; LT_list_aoc : LT_list_prog_andor_card ; ERPB_MTG : mtg_card ; { *************************************************************************** } { **************************************************************************** } PROCEDURE def_hardware_table ; VAR st_ao : sptrg_number ; st_fd : sptrg_per_fstd ; st_ds : sptrg_per_dbsc ; gs_dg : geosec_per_digm ; st_dg : sptrg_per_digm ; relst : relative_sptrg ; relgs : relative_geo_section ; gs_tl : geosec_per_tlm ; fc_tl : fired_cable_per_tlm ; i,j,k : INTEGER ; e_pol : eta_polarity ; e_fe : magn_eta_per_fe_cell ; phi : phi_value ; p_cell: phi_per_fe_cell ; e_rp : eta_per_rack_pair ; rele : relative_eta ; relp : relative_phi ; ch_typ: adc_data_type_per_ctfe_channel ; rf_typ: threshold_reference_set_type ; rf_num: threshold_reference_set_number ; p_quad: phi_per_fe_half_cell ; bit_f : cat2_bit_field ; cmpnum: comparison_number ; cmptyp: threshold_comparison_type ; coord : coordinate_type ; ht_num: hot_tower_number ; byte_num : byte_number ; e_tier2 : eta_per_rack_pair ; m_sign : momentum_sign ; BEGIN trc_err_init_hdb_fw := CONVERT(state_type, ini_fw_hdb_trc_err ) ; trc_err_init_hdb_ct := CONVERT(state_type, ini_ct_hdb_trc_err ) ; handle_trc_sys ( TAG := 'INI/HDB%', MESSAGE := ' Define Hardware Description Data Base ' ) ; cardscanner := ZERO ; total_card := 0 ; { *** bus buffer boards *** } bbb_tss := ZERO ; bbb_tss.status.implemented := TRUE ; bbb_tss.status.working := TRUE ; bbb_tss.cbus := cbus_2 ; bbb_tss.regtotal := 0 ; inline_add_card ( ADDRESS( bbb_tss ) ) ; bbb_frw := ZERO ; bbb_frw[bbb_m101].status.implemented := TRUE ; bbb_frw[bbb_m101].status.working := TRUE ; bbb_frw[bbb_m101].cbus := cbus_2 ; bbb_frw[bbb_m101].regtotal := 0 ; inline_add_card ( ADDRESS( bbb_frw[bbb_m101] ) ) ; bbb_frw[bbb_m102].status.implemented := TRUE ; bbb_frw[bbb_m102].status.working := TRUE ; bbb_frw[bbb_m102].cbus := cbus_2 ; bbb_frw[bbb_m102].regtotal := 0 ; inline_add_card ( ADDRESS( bbb_frw[bbb_m102] ) ) ; { *** mother-board driver boards *** } mbd_tss := ZERO ; mbd_tss.status.implemented := TRUE ; mbd_tss.status.working := TRUE ; mbd_tss.cbus := bbb_tss.cbus ; mbd_tss.mba := 105 ; mbd_tss.regtotal := 0 ; inline_add_card ( ADDRESS( mbd_tss ) ) ; mbd_scaler := ZERO ; mbd_scaler.status.implemented := TRUE ; mbd_scaler.status.working := TRUE ; mbd_scaler.cbus := bbb_tss.cbus ; mbd_scaler.mba := 106 ; mbd_scaler.regtotal := 0 ; inline_add_card ( ADDRESS( mbd_scaler ) ) ; mbd_frw := ZERO ; mbd_frw[mbd_it_128_255_st_0_15].status.implemented := TRUE ; mbd_frw[mbd_it_128_255_st_0_15].status.working := TRUE ; mbd_frw[mbd_it_128_255_st_0_15].cbus := bbb_frw[bbb_m101].cbus ; mbd_frw[mbd_it_128_255_st_0_15].mba := 129 ; mbd_frw[mbd_it_128_255_st_0_15].regtotal := 0 ; inline_add_card ( ADDRESS( mbd_frw[mbd_it_128_255_st_0_15] ) ) ; mbd_frw[mbd_it_0_127_st_0_15].status.implemented := TRUE ; mbd_frw[mbd_it_0_127_st_0_15].status.working := TRUE ; mbd_frw[mbd_it_0_127_st_0_15].cbus := bbb_frw[bbb_m101].cbus ; mbd_frw[mbd_it_0_127_st_0_15].mba := 130 ; mbd_frw[mbd_it_0_127_st_0_15].regtotal := 0 ; inline_add_card ( ADDRESS( mbd_frw[mbd_it_0_127_st_0_15] ) ) ; mbd_frw[mbd_fstd_st_0_15].status.implemented := TRUE ; mbd_frw[mbd_fstd_st_0_15].status.working := TRUE ; mbd_frw[mbd_fstd_st_0_15].cbus := bbb_frw[bbb_m101].cbus ; mbd_frw[mbd_fstd_st_0_15].mba := 132 ; mbd_frw[mbd_fstd_st_0_15].regtotal := 0 ; inline_add_card ( ADDRESS( mbd_frw[mbd_fstd_st_0_15] ) ) ; mbd_frw[mbd_mtg_bz].status.implemented := TRUE ; mbd_frw[mbd_mtg_bz].status.working := TRUE ; mbd_frw[mbd_mtg_bz].cbus := bbb_frw[bbb_m101].cbus ; mbd_frw[mbd_mtg_bz].mba := 135 ; mbd_frw[mbd_mtg_bz].regtotal := 0 ; inline_add_card ( ADDRESS( mbd_frw[mbd_mtg_bz] ) ) ; mbd_frw[mbd_it_128_255_st_16_31].status.implemented := TRUE ; mbd_frw[mbd_it_128_255_st_16_31].status.working := TRUE ; mbd_frw[mbd_it_128_255_st_16_31].cbus := bbb_frw[bbb_m102].cbus ; mbd_frw[mbd_it_128_255_st_16_31].mba := 65 ; mbd_frw[mbd_it_128_255_st_16_31].regtotal := 0 ; inline_add_card ( ADDRESS( mbd_frw[mbd_it_128_255_st_16_31] ) ) ; mbd_frw[mbd_it_0_127_st_16_31].status.implemented := TRUE ; mbd_frw[mbd_it_0_127_st_16_31].status.working := TRUE ; mbd_frw[mbd_it_0_127_st_16_31].cbus := bbb_frw[bbb_m102].cbus ; mbd_frw[mbd_it_0_127_st_16_31].mba := 66 ; mbd_frw[mbd_it_0_127_st_16_31].regtotal := 0 ; inline_add_card ( ADDRESS( mbd_frw[mbd_it_0_127_st_16_31] ) ) ; mbd_frw[mbd_fstd_st_16_31].status.implemented := TRUE ; mbd_frw[mbd_fstd_st_16_31].status.working := TRUE ; mbd_frw[mbd_fstd_st_16_31].cbus := bbb_frw[bbb_m102].cbus ; mbd_frw[mbd_fstd_st_16_31].mba := 68 ; mbd_frw[mbd_fstd_st_16_31].regtotal := 0 ; inline_add_card ( ADDRESS( mbd_frw[mbd_fstd_st_16_31] ) ) ; mbd_frw[mbd_tlm_sd].status.implemented := TRUE ; mbd_frw[mbd_tlm_sd].status.working := TRUE ; mbd_frw[mbd_tlm_sd].cbus := bbb_frw[bbb_m102].cbus ; mbd_frw[mbd_tlm_sd].mba := 71 ; mbd_frw[mbd_tlm_sd].regtotal := 0 ; inline_add_card ( ADDRESS( mbd_frw[mbd_tlm_sd] ) ) ; { *** IML cards *** } imlinput := ZERO ; imlinput[it_0_127,st_0_15].status.implemented := TRUE ; imlinput[it_0_127,st_0_15].status.working := TRUE ; imlinput[it_0_127,st_0_15].cbus := mbd_frw[mbd_it_0_127_st_0_15].cbus ; imlinput[it_0_127,st_0_15].mba := mbd_frw[mbd_it_0_127_st_0_15].mba ; imlinput[it_0_127,st_0_15].ca := 45 ; imlinput[it_0_127,st_0_15].regtotal := 16 ; FOR i := 0 TO 15 DO def_standard_reg ( FA := i, REGISTER := ADDRESS(imlinput[it_0_127,st_0_15].simureg[i]) ) ; inline_add_card ( ADDRESS( imlinput[it_0_127,st_0_15] ) ) ; imlinput[it_128_255,st_0_15].status.implemented := TRUE ; imlinput[it_128_255,st_0_15].status.working := TRUE ; imlinput[it_128_255,st_0_15].cbus := mbd_frw[mbd_it_128_255_st_0_15].cbus ; imlinput[it_128_255,st_0_15].mba := mbd_frw[mbd_it_128_255_st_0_15].mba ; imlinput[it_128_255,st_0_15].ca := 45 ; imlinput[it_128_255,st_0_15].regtotal := 16 ; FOR i := 0 TO 15 DO def_standard_reg ( FA := i, REGISTER := ADDRESS(imlinput[it_128_255,st_0_15].simureg[i])); inline_add_card ( ADDRESS( imlinput[it_128_255,st_0_15] ) ) ; imlinput[it_0_127,st_16_31].status.implemented := TRUE ; imlinput[it_0_127,st_16_31].status.working := TRUE ; imlinput[it_0_127,st_16_31].cbus := mbd_frw[mbd_it_0_127_st_16_31].cbus ; imlinput[it_0_127,st_16_31].mba := mbd_frw[mbd_it_0_127_st_16_31].mba ; imlinput[it_0_127,st_16_31].ca := 45 ; imlinput[it_0_127,st_16_31].regtotal := 16 ; FOR i := 0 TO 15 DO def_standard_reg ( FA := i, REGISTER := ADDRESS(imlinput[it_0_127,st_16_31].simureg[i])); inline_add_card ( ADDRESS( imlinput[it_0_127,st_16_31] ) ) ; imlinput[it_128_255,st_16_31].status.implemented := TRUE ; imlinput[it_128_255,st_16_31].status.working := TRUE ; imlinput[it_128_255,st_16_31].cbus := mbd_frw[mbd_it_128_255_st_16_31].cbus ; imlinput[it_128_255,st_16_31].mba := mbd_frw[mbd_it_128_255_st_16_31].mba ; imlinput[it_128_255,st_16_31].ca := 45 ; imlinput[it_128_255,st_16_31].regtotal := 16 ; FOR i := 0 TO 15 DO def_standard_reg ( FA := i, REGISTER := ADDRESS(imlinput[it_128_255,st_16_31].simureg[i])); inline_add_card ( ADDRESS( imlinput[it_128_255,st_16_31] ) ) ; { *** IMLRO cards *** } imlroinput := ZERO ; imlroinput[it_0_127,st_0_15].status.implemented := TRUE ; imlroinput[it_0_127,st_0_15].status.working := TRUE ; imlroinput[it_0_127,st_0_15].cbus := mbd_frw[mbd_it_0_127_st_0_15].cbus ; imlroinput[it_0_127,st_0_15].mba := mbd_frw[mbd_it_0_127_st_0_15].mba ; imlroinput[it_0_127,st_0_15].ca := 50 ; imlroinput[it_0_127,st_0_15].regtotal := 16 ; FOR i := 0 TO 15 DO def_29520_reg ( FA := i, REGISTER := ADDRESS(imlroinput[it_0_127,st_0_15].roreg[i]) ) ; inline_add_card ( ADDRESS( imlroinput[it_0_127,st_0_15] ) ) ; imlroinput[it_128_255,st_0_15].status.implemented := TRUE ; imlroinput[it_128_255,st_0_15].status.working := TRUE ; imlroinput[it_128_255,st_0_15].cbus := mbd_frw[mbd_it_128_255_st_0_15].cbus ; imlroinput[it_128_255,st_0_15].mba := mbd_frw[mbd_it_128_255_st_0_15].mba ; imlroinput[it_128_255,st_0_15].ca := 50 ; imlroinput[it_128_255,st_0_15].regtotal := 16 ; FOR i := 0 TO 15 DO def_29520_reg ( FA := i, REGISTER := ADDRESS(imlroinput[it_128_255,st_0_15].roreg[i]) ) ; inline_add_card ( ADDRESS( imlroinput[it_128_255,st_0_15] ) ) ; imlroinput[it_0_127,st_16_31].status.implemented := TRUE ; imlroinput[it_0_127,st_16_31].status.working := TRUE ; imlroinput[it_0_127,st_16_31].cbus := mbd_frw[mbd_it_0_127_st_16_31].cbus ; imlroinput[it_0_127,st_16_31].mba := mbd_frw[mbd_it_0_127_st_16_31].mba ; imlroinput[it_0_127,st_16_31].ca := 50 ; imlroinput[it_0_127,st_16_31].regtotal := 16 ; FOR i := 0 TO 15 DO def_29520_reg ( FA := i, REGISTER := ADDRESS(imlroinput[it_0_127,st_16_31].roreg[i]) ) ; inline_add_card ( ADDRESS( imlroinput[it_0_127,st_16_31] ) ) ; imlroinput[it_128_255,st_16_31].status.implemented := TRUE ; imlroinput[it_128_255,st_16_31].status.working := TRUE ; imlroinput[it_128_255,st_16_31].cbus := mbd_frw[mbd_it_128_255_st_16_31].cbus ; imlroinput[it_128_255,st_16_31].mba := mbd_frw[mbd_it_128_255_st_16_31].mba ; imlroinput[it_128_255,st_16_31].ca := 50 ; imlroinput[it_128_255,st_16_31].regtotal := 16 ; FOR i := 0 TO 15 DO def_29520_reg ( FA := i, REGISTER := ADDRESS(imlroinput[it_128_255,st_16_31].roreg[i]) ) ; inline_add_card ( ADDRESS( imlroinput[it_128_255,st_16_31] ) ) ; imlrofired := ZERO ; imlrofired.status.implemented := TRUE ; imlrofired.status.working := TRUE ; imlrofired.cbus := mbd_frw[mbd_tlm_sd].cbus ; imlrofired.mba := mbd_frw[mbd_tlm_sd].mba ; imlrofired.ca := 50 ; imlrofired.regtotal := 16 ; FOR i := 0 TO 15 DO def_29520_reg ( FA := i, REGISTER := ADDRESS(imlrofired.roreg[i]) ) ; inline_add_card ( ADDRESS( imlrofired ) ) ; imlrobusy := ZERO ; imlrobusy.status.implemented := TRUE ; imlrobusy.status.working := TRUE ; imlrobusy.cbus := mbd_frw[mbd_mtg_bz].cbus ; imlrobusy.mba := mbd_frw[mbd_mtg_bz].mba ; imlrobusy.ca := 50 ; imlrobusy.regtotal := 16 ; FOR i := 0 TO 15 DO def_29520_reg ( FA := i, REGISTER := ADDRESS(imlrobusy.roreg[i]) ) ; inline_add_card ( ADDRESS( imlrobusy ) ) ; imlroaux := ZERO ; imlroaux.status.implemented := TRUE ; imlroaux.status.working := TRUE ; imlroaux.cbus := mbd_frw[mbd_mtg_bz].cbus ; imlroaux.mba := mbd_frw[mbd_mtg_bz].mba ; imlroaux.ca := 51 ; imlroaux.regtotal := 16 ; FOR i := 0 TO 3 DO def_29520_reg ( FA := i, REGISTER := ADDRESS(imlroaux.rostdigreg[i]) ) ; FOR i := 0 TO 3 DO def_29520_reg ( FA := i+4, REGISTER := ADDRESS(imlroaux.robzdisreg[i]) ) ; FOR i := 0 TO 3 DO def_29520_reg ( FA := i+8, REGISTER := ADDRESS(imlroaux.rol2disreg[i]) ) ; FOR i := 0 TO 3 DO def_29520_reg ( FA := i+12, REGISTER := ADDRESS(imlroaux.roauxreg[i]) ) ; inline_add_card ( ADDRESS( imlroaux ) ) ; { *** ANDOR cards *** } andor := ZERO ; FOR st_ao := st_0 TO st_15 DO BEGIN andor[it_0_127,st_ao].status.implemented := TRUE ; andor[it_0_127,st_ao].status.working := TRUE ; andor[it_0_127,st_ao].cbus := mbd_frw[mbd_it_0_127_st_0_15].cbus ; andor[it_0_127,st_ao].mba := mbd_frw[mbd_it_0_127_st_0_15].mba ; andor[it_0_127,st_ao].ca := ORD(st_ao) + 1 ; andor[it_0_127,st_ao].regtotal := 32 ; andor[it_128_255,st_ao].status.implemented := TRUE ; andor[it_128_255,st_ao].status.working := TRUE ; andor[it_128_255,st_ao].cbus := mbd_frw[mbd_it_128_255_st_0_15].cbus ; andor[it_128_255,st_ao].mba := mbd_frw[mbd_it_128_255_st_0_15].mba ; andor[it_128_255,st_ao].ca := ORD(st_ao) + 1 ; andor[it_128_255,st_ao].regtotal := 32 ; END ; FOR st_ao := st_16 TO st_31 DO BEGIN andor[it_0_127,st_ao].status.implemented := TRUE ; andor[it_0_127,st_ao].status.working := TRUE ; andor[it_0_127,st_ao].cbus := mbd_frw[mbd_it_0_127_st_16_31].cbus ; andor[it_0_127,st_ao].mba := mbd_frw[mbd_it_0_127_st_16_31].mba ; andor[it_0_127,st_ao].ca := ORD(st_ao) - 15 ; andor[it_0_127,st_ao].regtotal := 32 ; andor[it_128_255,st_ao].status.implemented := TRUE ; andor[it_128_255,st_ao].status.working := TRUE ; andor[it_128_255,st_ao].cbus := mbd_frw[mbd_it_128_255_st_16_31].cbus ; andor[it_128_255,st_ao].mba := mbd_frw[mbd_it_128_255_st_16_31].mba ; andor[it_128_255,st_ao].ca := ORD(st_ao) - 15 ; andor[it_128_255,st_ao].regtotal := 32 ; END ; FOR st_ao := st_0 TO st_31 DO BEGIN FOR i := 0 TO 31 DO BEGIN def_standard_reg ( FA := i, REGISTER := ADDRESS(andor[it_0_127,st_ao].netreg[i]) ) ; def_standard_reg ( FA := i, REGISTER := ADDRESS(andor[it_128_255,st_ao].netreg[i])); END ; inline_add_card ( ADDRESS( andor[it_0_127,st_ao] ) ) ; inline_add_card ( ADDRESS( andor[it_128_255,st_ao] ) ) ; END ; { *** FSTD cards *** } fstd := ZERO ; FOR st_fd := st_0_3 TO st_12_15 DO BEGIN fstd[st_fd].status.implemented := TRUE ; fstd[st_fd].status.working := TRUE ; fstd[st_fd].cbus := mbd_frw[mbd_fstd_st_0_15].cbus ; fstd[st_fd].mba := mbd_frw[mbd_fstd_st_0_15].mba ; fstd[st_fd].ca := 4 * ORD(st_fd) + 1 ; fstd[st_fd].regtotal := 12 ; END ; FOR st_fd := st_16_19 TO st_28_31 DO BEGIN fstd[st_fd].status.implemented := TRUE ; fstd[st_fd].status.working := TRUE ; fstd[st_fd].cbus := mbd_frw[mbd_fstd_st_16_31].cbus ; fstd[st_fd].mba := mbd_frw[mbd_fstd_st_16_31].mba ; fstd[st_fd].ca := 4 * ORD(st_fd) + 1 ; fstd[st_fd].regtotal := 12 ; END ; FOR st_fd := st_0_3 TO st_28_31 DO BEGIN FOR relst := relst_0 TO relst_3 DO BEGIN def_presc_ctrl_reg ( FA := ORD(relst)*2, REGISTER := ADDRESS(fstd[st_fd].psctrlreg[relst]) ) ; def_presc_data_reg ( FA := ORD(relst)*2+1, REGISTER := ADDRESS(fstd[st_fd].psdatareg[relst]) ) ; def_fstd_enab_reg ( FA := ORD(relst)+8, REGISTER := ADDRESS(fstd[st_fd].enabreg[relst]) ) ; END ; inline_add_card ( ADDRESS( fstd[st_fd] ) ) ; END ; { *** DBSC cards *** } dbsc := ZERO ; FOR st_ds := st_0_1 TO st_14_15 DO BEGIN dbsc[st_ds].status.implemented := TRUE ; dbsc[st_ds].status.working := TRUE ; dbsc[st_ds].cbus := mbd_frw[mbd_fstd_st_0_15].cbus ; dbsc[st_ds].mba := mbd_frw[mbd_fstd_st_0_15].mba ; dbsc[st_ds].regtotal := 24 ; END ; FOR st_ds := st_16_17 TO st_30_31 DO BEGIN dbsc[st_ds].status.implemented := TRUE ; dbsc[st_ds].status.working := TRUE ; dbsc[st_ds].cbus := mbd_frw[mbd_fstd_st_16_31].cbus ; dbsc[st_ds].mba := mbd_frw[mbd_fstd_st_16_31].mba ; dbsc[st_ds].regtotal := 24 ; END ; dbsc[st_0_1].ca := 3 ; dbsc[st_2_3].ca := 2 ; dbsc[st_4_5].ca := 7 ; dbsc[st_6_7].ca := 6 ; dbsc[st_8_9].ca := 11 ; dbsc[st_10_11].ca := 10 ; dbsc[st_12_13].ca := 15 ; dbsc[st_14_15].ca := 14 ; dbsc[st_16_17].ca := 19 ; dbsc[st_18_19].ca := 18 ; dbsc[st_20_21].ca := 23 ; dbsc[st_22_23].ca := 22 ; dbsc[st_24_25].ca := 27 ; dbsc[st_26_27].ca := 26 ; dbsc[st_28_29].ca := 31 ; dbsc[st_30_31].ca := 30 ; FOR st_ds := st_0_1 TO st_30_31 DO BEGIN FOR relst := relst_0 TO relst_1 DO BEGIN def_dbsc_reset_reg(FA := 16*ORD(relst)+1, REGISTER := ADDRESS(dbsc[st_ds].resetreg[relst,exposc])); def_dbsc_reset_reg(FA := 16*ORD(relst)+9, REGISTER := ADDRESS(dbsc[st_ds].resetreg[relst,firedsc])); FOR i := 0 TO 4 DO BEGIN def_29520_reg(FA:= 16*ORD(relst)+1+i, REGISTER:= ADDRESS(dbsc[st_ds].scalreg[relst,exposc,i])); def_29520_reg(FA:= 16*ORD(relst)+9+i, REGISTER:= ADDRESS(dbsc[st_ds].scalreg[relst,firedsc,i])); END ; END ; inline_add_card ( ADDRESS( dbsc[st_ds] ) ) ; END ; dbsctrgnum := ZERO ; dbsctrgnum.status.implemented := TRUE ; dbsctrgnum.status.working := TRUE ; dbsctrgnum.cbus := mbd_frw[mbd_mtg_bz].cbus ; dbsctrgnum.mba := mbd_frw[mbd_mtg_bz].mba ; dbsctrgnum.ca := 43 ; dbsctrgnum.regtotal := 24 ; def_dbsc_reset_reg ( FA := 1, REGISTER := ADDRESS(dbsctrgnum.trgnumresetreg) ) ; def_dbsc_reset_reg ( FA := 9, REGISTER := ADDRESS(dbsctrgnum.dbnumresetreg) ) ; def_dbsc_reset_reg ( FA := 17, REGISTER := ADDRESS(dbsctrgnum.L1_P5_resetreg) ) ; def_dbsc_reset_reg ( FA := 25, REGISTER := ADDRESS(dbsctrgnum.L1_P6_resetreg) ) ; FOR i := 0 TO 4 DO BEGIN def_29520_reg ( FA := 1+i, REGISTER := ADDRESS(dbsctrgnum.trgnumreg[i]) ) ; def_29520_reg ( FA := 9+i, REGISTER := ADDRESS(dbsctrgnum.dbnumreg[i]) ) ; def_29520_reg ( FA := 17+i, REGISTER := ADDRESS(dbsctrgnum.L1_P5_reg[i]) ) ; def_29520_reg ( FA := 25+i, REGISTER := ADDRESS(dbsctrgnum.L1_P6_reg[i]) ) ; END ; inline_add_card ( ADDRESS( dbsctrgnum ) ) ; dbscbeamx := ZERO ; dbscbeamx.status.implemented := TRUE ; dbscbeamx.status.working := TRUE ; dbscbeamx.cbus := mbd_frw[mbd_mtg_bz].cbus ; dbscbeamx.mba := mbd_frw[mbd_mtg_bz].mba ; dbscbeamx.ca := 45 ; dbscbeamx.regtotal := 24 ; def_dbsc_reset_reg ( FA := 1, REGISTER := ADDRESS(dbscbeamx.beamxresetreg) ) ; def_dbsc_reset_reg ( FA := 9, REGISTER := ADDRESS(dbscbeamx.gated_Bx_resetreg) ) ; def_dbsc_reset_reg ( FA := 17, REGISTER := ADDRESS(dbscbeamx.L1_P3_resetreg) ) ; def_dbsc_reset_reg ( FA := 25, REGISTER := ADDRESS(dbscbeamx.L1_P4_resetreg) ) ; FOR i := 0 TO 4 DO BEGIN def_29520_reg ( FA := 1+i, REGISTER := ADDRESS(dbscbeamx.beamxreg[i]) ) ; def_29520_reg ( FA := 9+i, REGISTER := ADDRESS(dbscbeamx.gated_Bx_reg[i]) ) ; def_29520_reg ( FA := 17+i, REGISTER := ADDRESS(dbscbeamx.L1_P3_reg[i]) ) ; def_29520_reg ( FA := 25+i, REGISTER := ADDRESS(dbscbeamx.L1_P4_reg[i]) ) ; END ; inline_add_card ( ADDRESS( dbscbeamx ) ) ; dbscvtprep := ZERO ; dbscvtprep.status.implemented := TRUE ; dbscvtprep.status.working := TRUE ; dbscvtprep.cbus := mbd_frw[mbd_mtg_bz].cbus ; dbscvtprep.mba := mbd_frw[mbd_mtg_bz].mba ; dbscvtprep.ca := 33 ; dbscvtprep.regtotal := 24 ; def_dbsc_reset_reg ( FA := 1, REGISTER := ADDRESS(dbscvtprep.vt_prep_resetreg) ) ; def_dbsc_reset_reg ( FA := 9, REGISTER := ADDRESS(dbscvtprep.DBB_busy_resetreg) ) ; def_dbsc_reset_reg ( FA := 17, REGISTER := ADDRESS(dbscvtprep.L1_P1_resetreg) ) ; def_dbsc_reset_reg ( FA := 25, REGISTER := ADDRESS(dbscvtprep.L1_P2_resetreg) ) ; FOR i := 0 TO 4 DO BEGIN def_29520_reg ( FA := 1+i, REGISTER := ADDRESS(dbscvtprep.vt_prep_reg[i]) ) ; def_29520_reg ( FA := 9+i, REGISTER := ADDRESS(dbscvtprep.DBB_busy_reg[i]) ) ; def_29520_reg ( FA := 17+i, REGISTER := ADDRESS(dbscvtprep.L1_P1_reg[i]) ) ; def_29520_reg ( FA := 25+i, REGISTER := ADDRESS(dbscvtprep.L1_P2_reg[i]) ) ; END ; inline_add_card ( ADDRESS( dbscvtprep ) ) ; dbscwaitvbd := ZERO ; dbscwaitvbd.status.implemented := TRUE ; dbscwaitvbd.status.working := TRUE ; dbscwaitvbd.cbus := mbd_frw[mbd_mtg_bz].cbus ; dbscwaitvbd.mba := mbd_frw[mbd_mtg_bz].mba ; dbscwaitvbd.ca := 35 ; dbscwaitvbd.regtotal := 24 ; def_dbsc_reset_reg ( FA := 1, REGISTER := ADDRESS(dbscwaitvbd.vt_waitVBD_resetreg) ) ; def_dbsc_reset_reg ( FA := 9, REGISTER := ADDRESS(dbscwaitvbd.vt_waitDMA_resetreg) ) ; def_dbsc_reset_reg ( FA := 17, REGISTER := ADDRESS(dbscwaitvbd.vt_idle_resetreg) ) ; def_dbsc_reset_reg ( FA := 25, REGISTER := ADDRESS(dbscwaitvbd.vt_display_resetreg) ) ; FOR i := 0 TO 4 DO BEGIN def_29520_reg ( FA := 1+i, REGISTER := ADDRESS(dbscwaitvbd.vt_waitVBD_reg[i]) ) ; def_29520_reg ( FA := 9+i, REGISTER := ADDRESS(dbscwaitvbd.vt_waitDMA_reg[i]) ) ; def_29520_reg ( FA := 17+i, REGISTER := ADDRESS(dbscwaitvbd.vt_idle_reg[i]) ) ; def_29520_reg ( FA := 25+i, REGISTER := ADDRESS(dbscwaitvbd.vt_display_reg[i]) ) ; END ; inline_add_card ( ADDRESS( dbscwaitvbd ) ) ; dbscL0_P1_4 := ZERO ; dbscL0_P1_4.status.implemented := TRUE ; dbscL0_P1_4.status.working := TRUE ; dbscL0_P1_4.cbus := mbd_scaler.cbus ; dbscL0_P1_4.mba := mbd_scaler.mba ; dbscL0_P1_4.ca := 17 ; dbscL0_P1_4.regtotal := 24 ; FOR j := 1 TO 4 DO BEGIN def_dbsc_reset_reg ( FA := 8*(j-1)+1, REGISTER := ADDRESS(dbscL0_P1_4.L0_Pi_resetreg[j]) ) ; FOR i := 0 TO 4 DO def_29520_reg ( FA := 8*(j-1)+1+i, REGISTER := ADDRESS(dbscL0_P1_4.L0_Pi_reg[j,i]) ) ; END ; inline_add_card ( ADDRESS( dbscL0_P1_4 ) ) ; dbscL0_P5_6 := ZERO ; dbscL0_P5_6.status.implemented := TRUE ; dbscL0_P5_6.status.working := TRUE ; dbscL0_P5_6.cbus := mbd_scaler.cbus ; dbscL0_P5_6.mba := mbd_scaler.mba ; dbscL0_P5_6.ca := 20 ; dbscL0_P5_6.regtotal := 24 ; FOR j := 5 TO 6 DO BEGIN def_dbsc_reset_reg ( FA := 8*(j-5)+1, REGISTER := ADDRESS(dbscL0_P5_6.L0_Pi_resetreg[j]) ) ; FOR i := 0 TO 4 DO def_29520_reg ( FA := 8*(j-5)+1+i, REGISTER := ADDRESS(dbscL0_P5_6.L0_Pi_reg[j,i]) ) ; END ; def_dbsc_reset_reg ( FA := 17, REGISTER := ADDRESS(dbscL0_P5_6.L15_Skip_Resetreg) ) ; def_dbsc_reset_reg ( FA := 25, REGISTER := ADDRESS(dbscL0_P5_6.DBB_rqst_resetreg) ) ; FOR i := 0 TO 4 DO BEGIN def_29520_reg ( FA := 17+i, REGISTER := ADDRESS(dbscL0_P5_6.L15_Skip_reg[i]) ) ; def_29520_reg ( FA := 25+i, REGISTER := ADDRESS(dbscL0_P5_6.DBB_rqst_reg[i]) ) ; END ; inline_add_card ( ADDRESS( dbscL0_P5_6 ) ) ; dbscaux := ZERO ; dbscaux.status.implemented := TRUE ; dbscaux.status.working := TRUE ; dbscaux.cbus := mbd_scaler.cbus ; dbscaux.mba := mbd_scaler.mba ; dbscaux.ca := 23 ; dbscaux.regtotal := 24 ; def_dbsc_reset_reg ( FA := 1, REGISTER := ADDRESS(dbscaux.L15_Cycl_Resetreg) ) ; def_dbsc_reset_reg ( FA := 9, REGISTER := ADDRESS(dbscaux.L15_Pot_resetreg) ) ; def_dbsc_reset_reg ( FA := 17, REGISTER := ADDRESS(dbscaux.L0_Good_Resetreg) ) ; def_dbsc_reset_reg ( FA := 25, REGISTER := ADDRESS(dbscaux.Spare_resetreg) ) ; FOR i := 0 TO 4 DO BEGIN def_29520_reg ( FA := 1+i, REGISTER := ADDRESS(dbscaux.L15_Cycl_reg[i]) ) ; def_29520_reg ( FA := 9+i, REGISTER := ADDRESS(dbscaux.L15_Pot_reg[i]) ) ; def_29520_reg ( FA := 17+i, REGISTER := ADDRESS(dbscaux.L0_Good_reg[i]) ) ; def_29520_reg ( FA := 25+i, REGISTER := ADDRESS(dbscaux.Spare_reg[i]) ) ; END ; inline_add_card ( ADDRESS( dbscaux ) ) ; dbscforeign := ZERO ; FOR k := 1 TO 11 DO BEGIN dbscforeign[k].status.implemented := TRUE ; dbscforeign[k].status.working := TRUE ; dbscforeign[k].cbus := mbd_scaler.cbus ; dbscforeign[k].mba := mbd_scaler.mba ; dbscforeign[k].ca := 59 - 3*k ; dbscforeign[k].regtotal := 24 ; FOR j := 0 TO 3 DO BEGIN def_dbsc_reset_reg ( FA := 8*j+1, REGISTER := ADDRESS(dbscforeign[k].scaler_resetreg[j]) ) ; FOR i := 0 TO 4 DO def_29520_reg ( FA := 8*j+1+i, REGISTER := ADDRESS(dbscforeign[k].scaler_reg[j,i]) ) ; END ; inline_add_card ( ADDRESS( dbscforeign[k] ) ) ; END ; { *** SBSC cards *** } sbscdis := ZERO ; FOR st_fd := st_0_3 TO st_12_15 DO BEGIN sbscdis[st_fd].status.implemented := TRUE ; sbscdis[st_fd].status.working := TRUE ; sbscdis[st_fd].cbus := mbd_frw[mbd_fstd_st_0_15].cbus ; sbscdis[st_fd].mba := mbd_frw[mbd_fstd_st_0_15].mba ; sbscdis[st_fd].ca := 4 * ORD(st_fd) + 4 ; sbscdis[st_fd].regtotal := 10 ; END ; FOR st_fd := st_16_19 TO st_28_31 DO BEGIN sbscdis[st_fd].status.implemented := TRUE ; sbscdis[st_fd].status.working := TRUE ; sbscdis[st_fd].cbus := mbd_frw[mbd_fstd_st_16_31].cbus ; sbscdis[st_fd].mba := mbd_frw[mbd_fstd_st_16_31].mba ; sbscdis[st_fd].ca := 4 * ORD(st_fd) + 4 ; sbscdis[st_fd].regtotal := 10 ; END ; FOR st_fd := st_0_3 TO st_28_31 DO BEGIN FOR i := 0 TO 7 DO def_sbsc_ctrl_reg ( FA := i, REGISTER := ADDRESS(sbscdis[st_fd].ctrlreg[i]) ) ; def_sbsc_load_reg ( FA := 64, REGISTER := ADDRESS(sbscdis[st_fd].loadreg) ) ; def_sbsc_data_reg ( FA := 32, REGISTER := ADDRESS(sbscdis[st_fd].datareg) ) ; inline_add_card ( ADDRESS( sbscdis[st_fd] ) ) ; END ; sbscaofired := ZERO ; sbscaofired.status.implemented := TRUE ; sbscaofired.status.working := TRUE ; sbscaofired.cbus := mbd_frw[mbd_fstd_st_16_31].cbus ; sbscaofired.mba := mbd_frw[mbd_fstd_st_16_31].mba ; sbscaofired.ca := 55 ; sbscaofired.regtotal := 10 ; FOR i := 0 TO 7 DO def_sbsc_ctrl_reg ( FA := i, REGISTER := ADDRESS(sbscaofired.ctrlreg[i]) ) ; def_sbsc_load_reg ( FA := 64, REGISTER := ADDRESS(sbscaofired.loadreg) ) ; def_sbsc_data_reg ( FA := 32, REGISTER := ADDRESS(sbscaofired.datareg) ) ; inline_add_card ( ADDRESS( sbscaofired ) ) ; sbscstdig := ZERO ; sbscstdig.status.implemented := TRUE ; sbscstdig.status.working := TRUE ; sbscstdig.cbus := mbd_frw[mbd_fstd_st_16_31].cbus ; sbscstdig.mba := mbd_frw[mbd_fstd_st_16_31].mba ; sbscstdig.ca := 47 ; sbscstdig.regtotal := 10 ; FOR i := 0 TO 7 DO def_sbsc_ctrl_reg ( FA := i, REGISTER := ADDRESS(sbscstdig.ctrlreg[i]) ) ; def_sbsc_load_reg ( FA := 64, REGISTER := ADDRESS(sbscstdig.loadreg) ) ; def_sbsc_data_reg ( FA := 32, REGISTER := ADDRESS(sbscstdig.datareg) ) ; inline_add_card ( ADDRESS( sbscstdig ) ) ; sbscfebz := ZERO ; sbscfebz.status.implemented := TRUE ; sbscfebz.status.working := TRUE ; sbscfebz.cbus := mbd_frw[mbd_fstd_st_16_31].cbus ; sbscfebz.mba := mbd_frw[mbd_fstd_st_16_31].mba ; sbscfebz.ca := 39 ; sbscfebz.regtotal := 10 ; FOR i := 0 TO 7 DO def_sbsc_ctrl_reg ( FA := i, REGISTER := ADDRESS(sbscfebz.ctrlreg[i]) ) ; def_sbsc_load_reg ( FA := 64, REGISTER := ADDRESS(sbscfebz.loadreg) ) ; def_sbsc_data_reg ( FA := 32, REGISTER := ADDRESS(sbscfebz.datareg) ) ; inline_add_card ( ADDRESS( sbscfebz ) ) ; { *** DIGIMEM cards *** } dgmstdig := ZERO ; dgmbzdis := ZERO ; FOR gs_dg := gs_0_3 TO gs_28_31 DO BEGIN dgmstdig[gs_dg].status.implemented := TRUE ; dgmstdig[gs_dg].status.working := TRUE ; dgmstdig[gs_dg].cbus := mbd_frw[mbd_tlm_sd].cbus ; dgmstdig[gs_dg].mba := mbd_frw[mbd_tlm_sd].mba ; dgmstdig[gs_dg].ca := 4 * ORD(gs_dg) + 1 ; dgmstdig[gs_dg].regtotal := 32 ; FOR relgs := relgs_0 TO relgs_3 DO FOR i := 0 TO 7 DO def_standard_reg ( FA := 8*ORD(relgs)+i, REGISTER := ADDRESS(dgmstdig[gs_dg].netreg[relgs,i]) ) ; inline_add_card ( ADDRESS( dgmstdig[gs_dg] ) ) ; END ; FOR st_dg := st_0_3 TO st_28_31 DO BEGIN dgmbzdis[st_dg].status.implemented := TRUE ; dgmbzdis[st_dg].status.working := TRUE ; dgmbzdis[st_dg].cbus := mbd_frw[mbd_mtg_bz].cbus ; dgmbzdis[st_dg].mba := mbd_frw[mbd_mtg_bz].mba ; dgmbzdis[st_dg].ca := 4 * ORD(st_dg) + 1 ; dgmbzdis[st_dg].regtotal := 32 ; FOR relst := relst_0 TO relst_3 DO FOR i := 0 TO 7 DO def_standard_reg ( FA := 8*ORD(relst)+i, REGISTER := ADDRESS(dgmbzdis[st_dg].netreg[relst,i]) ) ; inline_add_card ( ADDRESS( dgmbzdis[st_dg] ) ) ; END ; { *** tirgger latch module cards *** } tlmbusy := ZERO ; tlmbusy.status.implemented := TRUE ; tlmbusy.status.working := TRUE ; tlmbusy.cbus := mbd_frw[mbd_mtg_bz].cbus ; tlmbusy.mba := mbd_frw[mbd_mtg_bz].mba ; tlmbusy.ca := 0 ; tlmbusy.regtotal := 0 ; inline_add_card ( ADDRESS( tlmbusy ) ) ; tlmfired := ZERO ; tlmfired.status.implemented := TRUE ; tlmfired.status.working := TRUE ; tlmfired.cbus := mbd_frw[mbd_tlm_sd].cbus ; tlmfired.mba := mbd_frw[mbd_tlm_sd].mba ; tlmfired.ca := 0 ; tlmfired.regtotal := 0 ; inline_add_card ( ADDRESS( tlmfired ) ) ; tlmtrgnum := ZERO ; FOR gs_tl := gs_0_7 TO gs_24_31 DO BEGIN tlmtrgnum[gs_tl].status.implemented := TRUE ; tlmtrgnum[gs_tl].status.working := TRUE ; tlmtrgnum[gs_tl].cbus := mbd_frw[mbd_tlm_sd].cbus ; tlmtrgnum[gs_tl].mba := mbd_frw[mbd_tlm_sd].mba ; tlmtrgnum[gs_tl].ca := 0 ; tlmtrgnum[gs_tl].regtotal := 0 ; inline_add_card ( ADDRESS( tlmtrgnum[gs_tl] ) ) ; END ; tlmstdig := ZERO ; tlmstdig.status.implemented := TRUE ; tlmstdig.status.working := TRUE ; tlmstdig.cbus := mbd_frw[mbd_tlm_sd].cbus ; tlmstdig.mba := mbd_frw[mbd_tlm_sd].mba ; tlmstdig.ca := 0 ; tlmstdig.regtotal := 0 ; inline_add_card ( ADDRESS( tlmstdig ) ) ; tlmfiredstb := ZERO ; tlmfiredstb.status.implemented := TRUE ; tlmfiredstb.status.working := TRUE ; tlmfiredstb.cbus := mbd_frw[mbd_tlm_sd].cbus ; tlmfiredstb.mba := mbd_frw[mbd_tlm_sd].mba ; tlmfiredstb.ca := 0 ; tlmfiredstb.regtotal := 0 ; inline_add_card ( ADDRESS( tlmfiredstb ) ) ; tlmfiredout := ZERO ; FOR fc_tl := fc_0_3 TO fc_4_7 DO BEGIN tlmfiredout[fc_tl].status.implemented := TRUE ; tlmfiredout[fc_tl].status.working := TRUE ; tlmfiredout[fc_tl].cbus := mbd_frw[mbd_tlm_sd].cbus ; tlmfiredout[fc_tl].mba := mbd_frw[mbd_tlm_sd].mba ; tlmfiredout[fc_tl].ca := 0 ; tlmfiredout[fc_tl].regtotal := 0 ; inline_add_card ( ADDRESS( tlmfiredout[fc_tl] ) ) ; END ; { *** master timing generator cards *** } { *** upgraded to rev B MTG 23-AUG-1990 *** } mtgdirin := zero ; mtgdirin.status.implemented := TRUE ; mtgdirin.status.working := TRUE ; mtgdirin.cbus := mbd_frw[mbd_mtg_bz].cbus ; mtgdirin.mba := mbd_frw[mbd_mtg_bz].mba ; mtgdirin.ca := 49 ; mtgdirin.regtotal := 39 ; def_mtg_set_prom_addr_lsb ( FA := 33, REGISTER := ADDRESS(mtgdirin.start_lsb) ) ; def_mtg_set_prom_addr_msb ( FA := 34, REGISTER := ADDRESS(mtgdirin.start_msb) ) ; def_mtg_set_prom_addr_lsb ( FA := 35, REGISTER := ADDRESS(mtgdirin.stop_lsb) ) ; def_mtg_set_prom_addr_msb ( FA := 36, REGISTER := ADDRESS(mtgdirin.stop_msb) ) ; def_mtg_control_status_reg ( FA := 37, REGISTER := ADDRESS(mtgdirin.controlreg) ) ; def_mtg_read_prom_addr_lsb ( FA := 38, REGISTER := ADDRESS(mtgdirin.count_lsb) ) ; def_mtg_read_prom_addr_msb ( FA := 39, REGISTER := ADDRESS(mtgdirin.count_msb) ) ; { All Channels are direct in test trigger bits } { they use a PAL 16R4 instead of 16R6 } { expanded to all direct-in 24-JAN-1991 } FOR i := 0 TO 31 DO def_mtg_directin_reg ( FA := i, REGISTER := ADDRESS(mtgdirin.channelreg[i]) ) ; inline_add_card ( ADDRESS( mtgdirin ) ) ; mtgholdtx := zero ; mtgholdtx.status.implemented := TRUE ; mtgholdtx.status.working := TRUE ; mtgholdtx.cbus := mbd_frw[mbd_mtg_bz].cbus ; mtgholdtx.mba := mbd_frw[mbd_mtg_bz].mba ; mtgholdtx.ca := 39 ; mtgholdtx.regtotal := 39 ; def_mtg_set_prom_addr_lsb ( FA := 33, REGISTER := ADDRESS(mtgholdtx.start_lsb) ) ; def_mtg_set_prom_addr_msb ( FA := 34, REGISTER := ADDRESS(mtgholdtx.start_msb) ) ; def_mtg_set_prom_addr_lsb ( FA := 35, REGISTER := ADDRESS(mtgholdtx.stop_lsb) ) ; def_mtg_set_prom_addr_msb ( FA := 36, REGISTER := ADDRESS(mtgholdtx.stop_msb) ) ; def_mtg_control_status_reg ( FA := 37, REGISTER := ADDRESS(mtgholdtx.controlreg) ) ; def_mtg_read_prom_addr_lsb ( FA := 38, REGISTER := ADDRESS(mtgholdtx.count_lsb) ) ; def_mtg_read_prom_addr_msb ( FA := 39, REGISTER := ADDRESS(mtgholdtx.count_msb) ) ; FOR i := 0 TO 31 DO BEGIN def_mtg_channel_reg ( FA := i, REGISTER := ADDRESS(mtgholdtx.channelreg[i]) ) ; mtgholdtx.channelreg[i].rmsk := 1 + 2 + 4 + 16 ; mtgholdtx.channelreg[i].wmsk := 1 + 2 + 16 ; END ; inline_add_card ( ADDRESS( mtgholdtx ) ) ; mtgstdig := zero ; mtgstdig.status.implemented := TRUE ; mtgstdig.status.working := TRUE ; mtgstdig.cbus := mbd_frw[mbd_mtg_bz].cbus ; mtgstdig.mba := mbd_frw[mbd_mtg_bz].mba ; mtgstdig.ca := 37 ; mtgstdig.regtotal := 39 ; def_mtg_set_prom_addr_lsb ( FA := 33, REGISTER := ADDRESS(mtgstdig.start_lsb) ) ; def_mtg_set_prom_addr_msb ( FA := 34, REGISTER := ADDRESS(mtgstdig.start_msb) ) ; def_mtg_set_prom_addr_lsb ( FA := 35, REGISTER := ADDRESS(mtgstdig.stop_lsb) ) ; def_mtg_set_prom_addr_msb ( FA := 36, REGISTER := ADDRESS(mtgstdig.stop_msb) ) ; def_mtg_control_status_reg ( FA := 37, REGISTER := ADDRESS(mtgstdig.controlreg) ) ; def_mtg_read_prom_addr_lsb ( FA := 38, REGISTER := ADDRESS(mtgstdig.count_lsb) ) ; def_mtg_read_prom_addr_msb ( FA := 39, REGISTER := ADDRESS(mtgstdig.count_msb) ) ; FOR i := 0 TO 31 DO BEGIN def_mtg_channel_reg ( FA := i, REGISTER := ADDRESS(mtgstdig.channelreg[i]) ) ; mtgstdig.channelreg[i].rmsk := 1 + 2 + 8 + 16 ; mtgstdig.channelreg[i].wmsk := 1 + 2 + 4 + 8 + 16 ; END ; inline_add_card ( ADDRESS( mtgstdig ) ) ; mtgbusy := zero ; mtgbusy.status.implemented := TRUE ; mtgbusy.status.working := TRUE ; mtgbusy.cbus := mbd_frw[mbd_mtg_bz].cbus ; mtgbusy.mba := mbd_frw[mbd_mtg_bz].mba ; mtgbusy.ca := 41 ; mtgbusy.regtotal := 39 ; def_mtg_set_prom_addr_lsb ( FA := 33, REGISTER := ADDRESS(mtgbusy.start_lsb) ) ; def_mtg_set_prom_addr_msb ( FA := 34, REGISTER := ADDRESS(mtgbusy.start_msb) ) ; def_mtg_set_prom_addr_lsb ( FA := 35, REGISTER := ADDRESS(mtgbusy.stop_lsb) ) ; def_mtg_set_prom_addr_msb ( FA := 36, REGISTER := ADDRESS(mtgbusy.stop_msb) ) ; def_mtg_control_status_reg ( FA := 37, REGISTER := ADDRESS(mtgbusy.controlreg) ) ; def_mtg_read_prom_addr_lsb ( FA := 38, REGISTER := ADDRESS(mtgbusy.count_lsb) ) ; def_mtg_read_prom_addr_msb ( FA := 39, REGISTER := ADDRESS(mtgbusy.count_msb) ) ; FOR i := 0 TO 31 DO def_mtg_channel_reg ( FA := i, REGISTER := ADDRESS(mtgbusy.channelreg[i]) ) ; inline_add_card ( ADDRESS( mtgbusy ) ) ; { *** 20-OCT-1992 MTG Ch #2 @FA 1 for Geo Sect #1 is an FEBzGS01 } mtgbusy.channelreg[1].rmsk := 1 + 2 ; mtgbusy.channelreg[1].wmsk := 1 + 2 ; mtgfwtss := zero ; mtgfwtss.status.implemented := TRUE ; mtgfwtss.status.working := TRUE ; mtgfwtss.cbus := mbd_tss.cbus ; mtgfwtss.mba := mbd_tss.mba ; mtgfwtss.ca := 35 ; mtgfwtss.regtotal := 39 ; def_mtg_set_prom_addr_lsb ( FA := 33, REGISTER := ADDRESS(mtgfwtss.start_lsb) ) ; def_mtg_set_prom_addr_msb ( FA := 34, REGISTER := ADDRESS(mtgfwtss.start_msb) ) ; def_mtg_set_prom_addr_lsb ( FA := 35, REGISTER := ADDRESS(mtgfwtss.stop_lsb) ) ; def_mtg_set_prom_addr_msb ( FA := 36, REGISTER := ADDRESS(mtgfwtss.stop_msb) ) ; def_mtg_control_status_reg ( FA := 37, REGISTER := ADDRESS(mtgfwtss.controlreg) ) ; def_mtg_read_prom_addr_lsb ( FA := 38, REGISTER := ADDRESS(mtgfwtss.count_lsb) ) ; def_mtg_read_prom_addr_msb ( FA := 39, REGISTER := ADDRESS(mtgfwtss.count_msb) ) ; FOR i := 0 TO 31 DO def_mtg_channel_reg ( FA := i, REGISTER := ADDRESS(mtgfwtss.channelreg[i]) ) ; { *** 9-JUN-1992 MTG TSS #2 @FA 1 is an L15MTG06 } mtgfwtss.channelreg[tss_fw_IML_Latch].rmsk := 1 + 2 + 4 + 8 + 16 ; mtgfwtss.channelreg[tss_fw_IML_Latch].wmsk := 1 + 2 + 4 + 8 ; { *** 20-OCT-1992 MTG TSS # 4 @FA 3 is an L15MTG05 } mtgfwtss.channelreg[tss_fw_Latch_Shift].rmsk := 1 + 2 + 4 + 8 + 16 ; mtgfwtss.channelreg[tss_fw_Latch_Shift].wmsk := 1 + 2 + 4 + 8 ; { *** 5-OCT-1989: MTG TSS #5 @FA 4 is WRITE A/B to Am2952x. } { *** It uses a PAL 16R4 instead of 16R6 } def_mtg_write_ab_reg ( FA := tss_fw_write_AB, REGISTER := ADDRESS(mtgfwtss.channelreg[tss_fw_write_AB]) ) ; { *** 9-JUN-1992 MTG TSS #7 @FA 6 is an L15MTG06 } mtgfwtss.channelreg[tss_fw_ANDOR_Strobe].rmsk := 1 + 2 + 4 + 8 + 16 ; mtgfwtss.channelreg[tss_fw_ANDOR_Strobe].wmsk := 1 + 2 + 4 + 8 ; { *** 9-JUN-1992 MTG TSS #8 @FA 7 is an L15MTG05 } mtgfwtss.channelreg[tss_fw_FSTD_Dis_Latch].rmsk := 1 + 2 + 4 + 8 + 16 ; mtgfwtss.channelreg[tss_fw_FSTD_Dis_Latch].wmsk := 1 + 2 + 4 + 8 ; { *** 9-JUN-1992 MTG TSS #9 @FA 8 is an L15MTG06 } mtgfwtss.channelreg[tss_fw_SBSC_Clock].rmsk := 1 + 2 + 4 + 8 + 16 ; mtgfwtss.channelreg[tss_fw_SBSC_Clock].wmsk := 1 + 2 + 4 + 8 ; { *** 9-JUN-1992 MTG TSS #13 @FA 12 is an L15MTG05 } mtgfwtss.channelreg[tss_fw_DBSC_Clock].rmsk := 1 + 2 + 4 + 8 + 16 ; mtgfwtss.channelreg[tss_fw_DBSC_Clock].wmsk := 1 + 2 + 4 + 8 ; { *** 9-JUN-1992 MTG TSS #14 @FA 13 is an STDGNINC } mtgfwtss.channelreg[tss_fw_incr_stdigt_num].rmsk := 1 ; mtgfwtss.channelreg[tss_fw_incr_stdigt_num].wmsk := 1 ; { *** 9-JUN-1992 MTG TSS #15, 17 and 18 are the skip 1, 2, 8 beam X terms } { *** They use PALS BX1SKIP, BX2SKIP, BX7SKIP } mtgfwtss.channelreg[tss_fw_skip_one_beam_X].rmsk := 1 ; mtgfwtss.channelreg[tss_fw_skip_one_beam_X].wmsk := 1 ; mtgfwtss.channelreg[tss_fw_skip_two_beam_X].rmsk := 1 ; mtgfwtss.channelreg[tss_fw_skip_two_beam_X].wmsk := 1 ; mtgfwtss.channelreg[tss_fw_skip_ten_beam_X].rmsk := 1 ; mtgfwtss.channelreg[tss_fw_skip_ten_beam_X].wmsk := 1 ; { *** 9-JUN-1992 MTG TSS #19 @FA 18 is an L15MTG05 } mtgfwtss.channelreg[tss_fw_l1_per_bunch_clk].rmsk := 1 + 2 + 4 + 8 + 16 ; mtgfwtss.channelreg[tss_fw_l1_per_bunch_clk].wmsk := 1 + 2 + 4 + 8 ; { *** 9-JUN-1992 MTG TSS #20 @FA 19 is an L15MTG05 } mtgfwtss.channelreg[tss_fw_incr_transf_num].rmsk := 1 + 2 + 4 + 8 + 16 ; mtgfwtss.channelreg[tss_fw_incr_transf_num].wmsk := 1 + 2 + 4 + 8 ; { *** 9-JUN-1992 MTG TSS #21 @FA 20 is an L15MTG05 } mtgfwtss.channelreg[tss_fw_st_fired_strobe].rmsk := 1 + 2 + 4 + 8 + 16 ; mtgfwtss.channelreg[tss_fw_st_fired_strobe].wmsk := 1 + 2 + 4 + 8 ; inline_add_card ( ADDRESS( mtgfwtss ) ) ; { *** add a MTG to read TWB 10-APR-1991 *** } mtgtwb := zero ; mtgtwb.status.implemented := TRUE ; mtgtwb.status.working := TRUE ; mtgtwb.cbus := mbd_tss.cbus ; mtgtwb.mba := mbd_tss.mba ; mtgtwb.ca := 8 ; mtgtwb.regtotal := 9 ; def_read_only_reg ( FA := 0, REGISTER := ADDRESS(mtgtwb.twbreg) ) ; FOR i := 24 TO 31 DO def_mtg_channel_reg ( FA := i, REGISTER := ADDRESS(mtgtwb.channelreg[i]) ) ; inline_add_card ( ADDRESS( mtgtwb ) ) ; { *** Level 1.5 Trigger cards *** *** *** *** *** *** *** *** *** *** *** *** } mbdL15 := ZERO ; mbdL15.status.implemented := TRUE ; mbdL15.status.working := TRUE ; mbdL15.cbus := cbus_2 ; mbdL15.mba := 57 ; mbdL15.regtotal := 0 ; inline_add_card ( ADDRESS( mbdL15 ) ) ; tlmL15_fan := ZERO ; tlmL15_fan.status.implemented := TRUE ; tlmL15_fan.status.working := TRUE ; tlmL15_fan.cbus := mbdL15.cbus ; tlmL15_fan.mba := mbdL15.mba ; tlmL15_fan.ca := 0 ; tlmL15_fan.regtotal := 0 ; inline_add_card ( ADDRESS( tlmL15_fan ) ) ; dgmL15_ans := ZERO ; FOR st_dg := st_0_3 TO st_12_15 DO BEGIN dgmL15_ans[st_dg].status.implemented := TRUE ; dgmL15_ans[st_dg].status.working := TRUE ; dgmL15_ans[st_dg].cbus := mbdL15.cbus ; dgmL15_ans[st_dg].mba := mbdL15.mba ; dgmL15_ans[st_dg].ca := 3*ORD(st_dg) + 28 ; dgmL15_ans[st_dg].regtotal := 32 ; FOR relst := relst_0 TO relst_3 DO FOR i := 0 TO 7 DO def_standard_reg ( FA := 8*ORD(relst)+i, REGISTER := ADDRESS(dgmL15_ans[st_dg].netreg[relst,i]) ) ; inline_add_card ( ADDRESS( dgmL15_ans[st_dg] ) ) ; END ; imlroL15 := ZERO ; imlroL15.status.implemented := TRUE ; imlroL15.status.working := TRUE ; imlroL15.cbus := mbdL15.cbus ; imlroL15.mba := mbdL15.mba ; imlroL15.ca := 25 ; imlroL15.regtotal := 16 ; FOR i := 0 TO 1 DO def_29520_reg ( FA := i, REGISTER := ADDRESS(imlroL15.fired[i]) ) ; def_29520_reg ( FA := 2, REGISTER := ADDRESS(imlroL15.ctrlstat) ) ; def_29520_reg ( FA := 3, REGISTER := ADDRESS(imlroL15.spare ) ) ; FOR i := 0 TO 1 DO def_29520_reg ( FA := i+4, REGISTER := ADDRESS(imlroL15.confirm[i]) ) ; FOR i := 0 TO 1 DO def_29520_reg ( FA := i+6, REGISTER := ADDRESS(imlroL15.veto[i]) ) ; FOR i := 0 TO 3 DO def_29520_reg ( FA := i+8, REGISTER := ADDRESS(imlroL15.answer[i]) ) ; FOR i := 0 TO 3 DO def_29520_reg ( FA := i+12, REGISTER := ADDRESS(imlroL15.done[i]) ) ; inline_add_card ( ADDRESS( imlroL15 ) ) ; dgmL15_ctrl := ZERO ; dgmL15_ctrl.status.implemented := TRUE ; dgmL15_ctrl.status.working := TRUE ; dgmL15_ctrl.cbus := mbdL15.cbus ; dgmL15_ctrl.mba := mbdL15.mba ; dgmL15_ctrl.ca := 1 ; dgmL15_ctrl.regtotal := 32 ; FOR i := 0 TO 7 DO BEGIN def_standard_reg ( FA := 0+i, REGISTER := ADDRESS(dgmL15_ctrl.spare[i]) ) ; def_standard_reg ( FA := 8+i, REGISTER := ADDRESS(dgmL15_ctrl.L15_confirmed[i]) ) ; def_standard_reg ( FA := 16+i, REGISTER := ADDRESS(dgmL15_ctrl.L15_fired[i]) ) ; def_standard_reg ( FA := 24+i, REGISTER := ADDRESS(dgmL15_ctrl.PL1_fired[i]) ) ; END ; inline_add_card ( ADDRESS( dgmL15_ctrl ) ) ; mtgL15_vc := ZERO ; mtgL15_vc.status.implemented := TRUE ; mtgL15_vc.status.working := TRUE ; mtgL15_vc.cbus := mbdL15.cbus ; mtgL15_vc.mba := mbdL15.mba ; mtgL15_vc.ca := 19 ; mtgL15_vc.regtotal := 39 ; def_mtg_set_prom_addr_lsb ( FA := 33, REGISTER := ADDRESS(mtgL15_vc.start_lsb) ) ; def_mtg_set_prom_addr_msb ( FA := 34, REGISTER := ADDRESS(mtgL15_vc.start_msb) ) ; def_mtg_set_prom_addr_lsb ( FA := 35, REGISTER := ADDRESS(mtgL15_vc.stop_lsb) ) ; def_mtg_set_prom_addr_msb ( FA := 36, REGISTER := ADDRESS(mtgL15_vc.stop_msb) ) ; def_mtg_control_status_reg ( FA := 37, REGISTER := ADDRESS(mtgL15_vc.controlreg) ) ; def_mtg_read_prom_addr_lsb ( FA := 38, REGISTER := ADDRESS(mtgL15_vc.count_lsb) ) ; def_mtg_read_prom_addr_msb ( FA := 39, REGISTER := ADDRESS(mtgL15_vc.count_msb) ) ; FOR i := 0 TO 31 DO BEGIN def_mtg_channel_reg ( FA := i, REGISTER := ADDRESS(mtgL15_vc.channelreg[i]) ) ; mtgL15_vc.channelreg[i].rmsk := 1 + 4 ; mtgL15_vc.channelreg[i].wmsk := 1 + 2 ; END ; inline_add_card ( ADDRESS( mtgL15_vc ) ) ; mtgL15_mux := ZERO ; mtgL15_mux.status.implemented := TRUE ; mtgL15_mux.status.working := TRUE ; mtgL15_mux.cbus := mbdL15.cbus ; mtgL15_mux.mba := mbdL15.mba ; mtgL15_mux.ca := 22 ; mtgL15_mux.regtotal := 39 ; def_mtg_set_prom_addr_lsb ( FA := 33, REGISTER := ADDRESS(mtgL15_mux.start_lsb) ) ; def_mtg_set_prom_addr_msb ( FA := 34, REGISTER := ADDRESS(mtgL15_mux.start_msb) ) ; def_mtg_set_prom_addr_lsb ( FA := 35, REGISTER := ADDRESS(mtgL15_mux.stop_lsb) ) ; def_mtg_set_prom_addr_msb ( FA := 36, REGISTER := ADDRESS(mtgL15_mux.stop_msb) ) ; def_mtg_control_status_reg ( FA := 37, REGISTER := ADDRESS(mtgL15_mux.controlreg) ) ; def_mtg_read_prom_addr_lsb ( FA := 38, REGISTER := ADDRESS(mtgL15_mux.count_lsb) ) ; def_mtg_read_prom_addr_msb ( FA := 39, REGISTER := ADDRESS(mtgL15_mux.count_msb) ) ; FOR i := 0 TO 31 DO BEGIN def_mtg_channel_reg ( FA := i, REGISTER := ADDRESS(mtgL15_mux.channelreg[i]) ) ; mtgL15_mux.channelreg[i].rmsk := 1 + 2 ; mtgL15_mux.channelreg[i].wmsk := 1 + 2 ; END ; inline_add_card ( ADDRESS( mtgL15_mux ) ) ; mtgL15_ctrl := ZERO ; mtgL15_ctrl.status.implemented := TRUE ; mtgL15_ctrl.status.working := TRUE ; mtgL15_ctrl.cbus := mbdL15.cbus ; mtgL15_ctrl.mba := mbdL15.mba ; mtgL15_ctrl.ca := 4 ; mtgL15_ctrl.regtotal := 39 ; def_mtg_set_prom_addr_lsb ( FA := 33, REGISTER := ADDRESS(mtgL15_ctrl.start_lsb) ) ; def_mtg_set_prom_addr_msb ( FA := 34, REGISTER := ADDRESS(mtgL15_ctrl.start_msb) ) ; def_mtg_set_prom_addr_lsb ( FA := 35, REGISTER := ADDRESS(mtgL15_ctrl.stop_lsb) ) ; def_mtg_set_prom_addr_msb ( FA := 36, REGISTER := ADDRESS(mtgL15_ctrl.stop_msb) ) ; def_mtg_control_status_reg ( FA := 37, REGISTER := ADDRESS(mtgL15_ctrl.controlreg) ) ; def_mtg_read_prom_addr_lsb ( FA := 38, REGISTER := ADDRESS(mtgL15_ctrl.count_lsb) ) ; def_mtg_read_prom_addr_msb ( FA := 39, REGISTER := ADDRESS(mtgL15_ctrl.count_msb) ) ; FOR i := 0 TO 31 DO def_mtg_channel_reg ( FA := i, REGISTER := ADDRESS(mtgL15_ctrl.channelreg[i]) ) ; { *** L1.5 MTG TSS #14 @FA 13 is an BEGENDLT } mtgL15_ctrl.channelreg[tss_L15_beg_end_latch].rmsk := 1 + 2 ; mtgL15_ctrl.channelreg[tss_L15_beg_end_latch].wmsk := 1 + 2 ; { *** L1.5 MTG TSS #17 @FA 16 is an L15MTG05 } mtgL15_ctrl.channelreg[tss_L15_msk_strt_dblock].rmsk := 1 + 2 + 4 + 8 + 16 ; mtgL15_ctrl.channelreg[tss_L15_msk_strt_dblock].wmsk := 1 + 2 + 4 + 8 ; { *** L1.5 MTG TSS #27 @FA 26 is an L15MTG05 } mtgL15_ctrl.channelreg[tss_L15_accept_incr].rmsk := 1 + 2 + 4 + 8 + 16 ; mtgL15_ctrl.channelreg[tss_L15_accept_incr].wmsk := 1 + 2 + 4 + 8 ; { *** L1.5 MTG TSS #28 @FA 27 is an L15MTG05 } mtgL15_ctrl.channelreg[tss_L15_reject_incr].rmsk := 1 + 2 + 4 + 8 + 16 ; mtgL15_ctrl.channelreg[tss_L15_reject_incr].wmsk := 1 + 2 + 4 + 8 ; { *** L1.5 MTG TSS #29 @FA 28 is an LonGout } mtgL15_ctrl.channelreg[tss_L15_short_timeout].rmsk := 0 ; mtgL15_ctrl.channelreg[tss_L15_short_timeout].wmsk := 0 ; { *** L1.5 MTG TSS #30 @FA 29 is an LonGout } mtgL15_ctrl.channelreg[tss_L15_long_timeout].rmsk := 0 ; mtgL15_ctrl.channelreg[tss_L15_long_timeout].wmsk := 0 ; inline_add_card ( ADDRESS( mtgL15_ctrl ) ) ; dbscL15 := ZERO ; dbscL15.status.implemented := TRUE ; dbscL15.status.working := TRUE ; dbscL15.cbus := mbdL15.cbus ; dbscL15.mba := mbdL15.mba ; dbscL15.ca := 7 ; dbscL15.regtotal := 24 ; def_dbsc_reset_reg ( FA := 1, REGISTER := ADDRESS(dbscL15.cycle_resetreg) ) ; def_dbsc_reset_reg ( FA := 9, REGISTER := ADDRESS(dbscL15.skip_resetreg) ) ; def_dbsc_reset_reg ( FA := 17, REGISTER := ADDRESS(dbscL15.deadx_resetreg) ) ; def_dbsc_reset_reg ( FA := 25, REGISTER := ADDRESS(dbscL15.timeout_resetreg) ) ; FOR i := 0 TO 4 DO BEGIN def_29520_reg ( FA := 1+i, REGISTER := ADDRESS(dbscL15.cycle_reg[i]) ) ; def_29520_reg ( FA := 9+i, REGISTER := ADDRESS(dbscL15.skip_reg[i]) ) ; def_29520_reg ( FA := 17+i, REGISTER := ADDRESS(dbscL15.timeout_reg[i]) ) ; def_29520_reg ( FA := 25+i, REGISTER := ADDRESS(dbscL15.deadx_reg[i]) ) ; END ; inline_add_card ( ADDRESS( dbscL15 ) ) ; sbscL15_cyc_skp := ZERO ; sbscL15_cyc_skp.status.implemented := TRUE ; sbscL15_cyc_skp.status.working := TRUE ; sbscL15_cyc_skp.cbus := mbdL15.cbus ; sbscL15_cyc_skp.mba := mbdL15.mba ; sbscL15_cyc_skp.ca := 10 ; sbscL15_cyc_skp.regtotal := 10 ; FOR i := 0 TO 7 DO def_sbsc_ctrl_reg ( FA := i, REGISTER := ADDRESS(sbscL15_cyc_skp.ctrlreg[i]) ) ; def_sbsc_load_reg ( FA := 64, REGISTER := ADDRESS(sbscL15_cyc_skp.loadreg) ) ; def_sbsc_data_reg ( FA := 32, REGISTER := ADDRESS(sbscL15_cyc_skp.datareg) ) ; inline_add_card ( ADDRESS( sbscL15_cyc_skp ) ) ; sbscL15_dead_to := ZERO ; sbscL15_dead_to.status.implemented := TRUE ; sbscL15_dead_to.status.working := TRUE ; sbscL15_dead_to.cbus := mbdL15.cbus ; sbscL15_dead_to.mba := mbdL15.mba ; sbscL15_dead_to.ca := 13 ; sbscL15_dead_to.regtotal := 10 ; FOR i := 0 TO 7 DO def_sbsc_ctrl_reg ( FA := i, REGISTER := ADDRESS(sbscL15_dead_to.ctrlreg[i]) ) ; def_sbsc_load_reg ( FA := 64, REGISTER := ADDRESS(sbscL15_dead_to.loadreg) ) ; def_sbsc_data_reg ( FA := 32, REGISTER := ADDRESS(sbscL15_dead_to.datareg) ) ; inline_add_card ( ADDRESS( sbscL15_dead_to ) ) ; sbscL15_cnf_rej := ZERO ; sbscL15_cnf_rej.status.implemented := TRUE ; sbscL15_cnf_rej.status.working := TRUE ; sbscL15_cnf_rej.cbus := mbdL15.cbus ; sbscL15_cnf_rej.mba := mbdL15.mba ; sbscL15_cnf_rej.ca := 16 ; sbscL15_cnf_rej.regtotal := 10 ; FOR i := 0 TO 7 DO def_sbsc_ctrl_reg ( FA := i, REGISTER := ADDRESS(sbscL15_cnf_rej.ctrlreg[i]) ) ; def_sbsc_load_reg ( FA := 64, REGISTER := ADDRESS(sbscL15_cnf_rej.loadreg) ) ; def_sbsc_data_reg ( FA := 32, REGISTER := ADDRESS(sbscL15_cnf_rej.datareg) ) ; inline_add_card ( ADDRESS( sbscL15_cnf_rej ) ) ; { *** CALORIMETER TRIGGER CARDS * *** *** *** *** *** *** *** *** *** *** *** } mtgcttss := zero ; mtgcttss.status.implemented := TRUE ; mtgcttss.status.working := TRUE ; mtgcttss.cbus := mbd_tss.cbus ; mtgcttss.mba := mbd_tss.mba ; mtgcttss.ca := 53 ; mtgcttss.regtotal := 39 ; def_mtg_set_prom_addr_lsb ( FA := 33, REGISTER := ADDRESS(mtgcttss.start_lsb) ) ; def_mtg_set_prom_addr_msb ( FA := 34, REGISTER := ADDRESS(mtgcttss.start_msb) ) ; def_mtg_set_prom_addr_lsb ( FA := 35, REGISTER := ADDRESS(mtgcttss.stop_lsb) ) ; def_mtg_set_prom_addr_msb ( FA := 36, REGISTER := ADDRESS(mtgcttss.stop_msb) ) ; def_mtg_control_status_reg ( FA := 37, REGISTER := ADDRESS(mtgcttss.controlreg) ) ; def_mtg_read_prom_addr_lsb ( FA := 38, REGISTER := ADDRESS(mtgcttss.count_lsb) ) ; def_mtg_read_prom_addr_msb ( FA := 39, REGISTER := ADDRESS(mtgcttss.count_msb) ) ; FOR i := 0 TO 31 DO def_mtg_channel_reg ( FA := i, REGISTER := ADDRESS(mtgcttss.channelreg[i]) ) ; { *** 20-OCT-1992 MTG TSS # 5 @FA 6 is an L15MTG06 } mtgcttss.channelreg[tss_ct_Latch_Shift].rmsk := 1 + 2 + 4 + 8 + 16 ; mtgcttss.channelreg[tss_ct_Latch_Shift].wmsk := 1 + 2 + 4 + 8 ; { *** 20-OCT-1992 MTG TSS #29 @FA 28 is an L15MTG05 } mtgcttss.channelreg[tss_ct_IMLRO_Cnt_latch].rmsk := 1 + 2 + 4 + 8 + 16 ; mtgcttss.channelreg[tss_ct_IMLRO_Cnt_latch].wmsk := 1 + 2 + 4 + 8 ; inline_add_card ( ADDRESS( mtgcttss ) ) ; bbb_calfe := ZERO ; FOR e_rp := e_1_8 TO e_17_24 DO BEGIN FOR p_cell := p_1_16 TO p_17_32 DO BEGIN bbb_calfe[e_rp,p_cell].status.implemented := TRUE ; bbb_calfe[e_rp,p_cell].status.working := TRUE ; bbb_calfe[e_rp,p_cell].cbus := ORD(p_cell) ; bbb_calfe[e_rp,p_cell].regtotal := 0 ; inline_add_card ( ADDRESS( bbb_calfe[e_rp,p_cell] ) ) ; END ; END ; bbb_tier2 := ZERO ; FOR e_tier2 := e_1_8 TO e_17_24 DO BEGIN bbb_tier2[e_tier2].status.implemented := TRUE ; bbb_tier2[e_tier2].status.working := TRUE ; bbb_tier2[e_tier2].cbus := cbus_2 ; bbb_tier2[e_tier2].regtotal := 0 ; inline_add_card ( ADDRESS( bbb_tier2[e_tier2] ) ) ; END ; bbb_tier3_4 := ZERO ; bbb_tier3_4.status.implemented := TRUE ; bbb_tier3_4.status.working := TRUE ; bbb_tier3_4.cbus := cbus_2 ; bbb_tier3_4.regtotal := 0 ; inline_add_card ( ADDRESS( bbb_tier3_4 ) ) ; bbb_readout := ZERO ; bbb_readout.status.implemented := TRUE ; bbb_readout.status.working := TRUE ; bbb_readout.cbus := cbus_2 ; bbb_readout.regtotal := 0 ; inline_add_card ( ADDRESS( bbb_readout ) ) ; mbd_calfe := ZERO ; FOR e_fe := e_1_4 TO e_21_24 DO BEGIN FOR e_pol := pos_e TO neg_e DO BEGIN FOR p_cell := p_1_16 TO p_17_32 DO BEGIN e_rp := CONVERT(eta_per_rack_pair,ORD(e_fe) DIV 2) ; mbd_calfe[e_pol,e_fe,p_cell].status.implemented := TRUE ; mbd_calfe[e_pol,e_fe,p_cell].status.working := TRUE ; mbd_calfe[e_pol,e_fe,p_cell].cbus := bbb_calfe[e_rp,p_cell].cbus ; mbd_calfe[e_pol,e_fe,p_cell].regtotal := 0 ; inline_add_card ( ADDRESS( mbd_calfe[e_pol,e_fe,p_cell] ) ) ; END ; END ; END ; mbd_calfe[pos_e,e_1_4,p_1_16].mba := 21*8 + 1 ; mbd_calfe[pos_e,e_1_4,p_17_32].mba := 21*8 + 1 ; mbd_calfe[neg_e,e_1_4,p_1_16].mba := 21*8 + 4 ; mbd_calfe[neg_e,e_1_4,p_17_32].mba := 21*8 + 4 ; mbd_calfe[pos_e,e_5_8,p_1_16].mba := 21*8 + 2 ; mbd_calfe[pos_e,e_5_8,p_17_32].mba := 21*8 + 2 ; mbd_calfe[neg_e,e_5_8,p_1_16].mba := 21*8 + 7 ; mbd_calfe[neg_e,e_5_8,p_17_32].mba := 21*8 + 7 ; mbd_calfe[pos_e,e_9_12,p_1_16].mba := 25*8 + 1 ; mbd_calfe[pos_e,e_9_12,p_17_32].mba := 25*8 + 1 ; mbd_calfe[neg_e,e_9_12,p_1_16].mba := 25*8 + 4 ; mbd_calfe[neg_e,e_9_12,p_17_32].mba := 25*8 + 4 ; mbd_calfe[pos_e,e_13_16,p_1_16].mba := 25*8 + 2 ; mbd_calfe[pos_e,e_13_16,p_17_32].mba := 25*8 + 2 ; mbd_calfe[neg_e,e_13_16,p_1_16].mba := 25*8 + 7 ; mbd_calfe[neg_e,e_13_16,p_17_32].mba := 25*8 + 7 ; mbd_calfe[pos_e,e_17_20,p_1_16].mba := 28*8 + 1 ; mbd_calfe[pos_e,e_17_20,p_17_32].mba := 28*8 + 1 ; mbd_calfe[neg_e,e_17_20,p_1_16].mba := 28*8 + 4 ; mbd_calfe[neg_e,e_17_20,p_17_32].mba := 28*8 + 4 ; mbd_calfe[pos_e,e_21_24,p_1_16].mba := 28*8 + 2 ; mbd_calfe[pos_e,e_21_24,p_17_32].mba := 28*8 + 2 ; mbd_calfe[neg_e,e_21_24,p_1_16].mba := 28*8 + 7 ; mbd_calfe[neg_e,e_21_24,p_17_32].mba := 28*8 + 7 ; mbd_tier2 := ZERO ; FOR e_tier2 := e_1_8 TO e_17_24 DO BEGIN mbd_tier2[e_tier2].status.implemented := TRUE ; mbd_tier2[e_tier2].status.working := TRUE ; mbd_tier2[e_tier2].cbus := bbb_tier2[e_tier2].cbus ; mbd_tier2[e_tier2].regtotal := 0 ; inline_add_card ( ADDRESS( mbd_tier2[e_tier2] ) ) ; END ; mbd_tier2[e_1_8].mba := 22*8 + 1 ; mbd_tier2[e_9_16].mba := 26*8 + 1 ; mbd_tier2[e_17_24].mba := 31*8 + 1 ; mbd_tier3_4 := ZERO ; mbd_tier3_4.status.implemented := TRUE ; mbd_tier3_4.status.working := TRUE ; mbd_tier3_4.cbus := bbb_tier3_4.cbus ; mbd_tier3_4.regtotal := 0 ; inline_add_card ( ADDRESS( mbd_tier3_4 ) ) ; mbd_tier3_4.mba := 19*8 + 1 ; mbd_readout := ZERO ; mbd_readout.status.implemented := TRUE ; mbd_readout.status.working := TRUE ; mbd_readout.cbus := bbb_readout.cbus ; mbd_readout.regtotal := 0 ; inline_add_card ( ADDRESS( mbd_readout ) ) ; mbd_readout.mba := 19*8 + 2 ; FOR e_pol := pos_e TO neg_e DO BEGIN FOR e_fe := e_1_4 TO e_21_24 DO BEGIN FOR phi := p_1 TO p_32 DO BEGIN p_cell := CONVERT(phi_per_fe_cell,(ORD(phi)-1) DIV 16) ; ctfe_data[e_pol,e_fe,phi] := ZERO ; ctfe_data[e_pol,e_fe,phi].status.implemented := TRUE ; ctfe_data[e_pol,e_fe,phi].status.working := TRUE ; ctfe_data[e_pol,e_fe,phi].cbus := mbd_calfe[e_pol,e_fe,p_cell].cbus ; ctfe_data[e_pol,e_fe,phi].mba := mbd_calfe[e_pol,e_fe,p_cell].mba ; ctfe_data[e_pol,e_fe,phi].ca := 32 + 2*( (ORD(phi)-1) MOD 16 ) ; ctfe_data[e_pol,e_fe,phi].regtotal := 8 ; inline_add_card ( ADDRESS( ctfe_data[e_pol,e_fe,phi] ) ) ; ctfe_ctrl[e_pol,e_fe,phi] := ZERO ; ctfe_ctrl[e_pol,e_fe,phi].status.implemented := TRUE ; ctfe_ctrl[e_pol,e_fe,phi].status.working := TRUE ; ctfe_ctrl[e_pol,e_fe,phi].cbus := mbd_calfe[e_pol,e_fe,p_cell].cbus ; ctfe_ctrl[e_pol,e_fe,phi].mba := mbd_calfe[e_pol,e_fe,p_cell].mba ; ctfe_ctrl[e_pol,e_fe,phi].ca := 33 + 2* ( (ORD(phi)-1) MOD 16 ) ; ctfe_ctrl[e_pol,e_fe,phi].regtotal := 60 ; inline_add_card ( ADDRESS( ctfe_ctrl[e_pol,e_fe,phi] ) ) ; FOR rele := rele_0 TO rele_3 DO BEGIN FOR ch_typ := EMEtZ0 TO HDEtZ0 DO BEGIN def_29525_reg ( FA := 2*ORD(rele) + ORD(ch_typ) , REGISTER := ADDRESS(ctfe_data[e_pol,e_fe,phi].muxout[rele,ch_typ])); def_standard_reg ( FA := 2*ORD(rele) + ORD(ch_typ) , REGISTER := ADDRESS(ctfe_ctrl[e_pol,e_fe,phi].pedreg[rele,ch_typ])); END ; {ch_typ} FOR rf_typ := EMEt_ref TO TOTEt_ref DO BEGIN FOR rf_num := ref_0 TO ref_3 DO BEGIN def_standard_reg ( FA := 16*(ORD(rele)+1) + 4*ORD(rf_typ) + ORD(rf_num) , REGISTER := ADDRESS(ctfe_ctrl[e_pol,e_fe,phi].thrreg[rele,rf_typ,rf_num])); END ; {rf_num} END ; {rf_typ} END ; {rele} def_ctfe_board_ctrl_reg ( FA := 80, REGISTER := ADDRESS(ctfe_ctrl[e_pol,e_fe,phi].brdctrl)); def_standard_reg ( FA := 81, REGISTER := ADDRESS(ctfe_ctrl[e_pol,e_fe,phi].chanctrl)); def_ctfe_load_simu_data_reg ( FA := 82, REGISTER := ADDRESS(ctfe_ctrl[e_pol,e_fe,phi].loadsimreg)); def_ctfe_read_simu_data_reg ( FA := 82, REGISTER := ADDRESS(ctfe_ctrl[e_pol,e_fe,phi].readsimreg)); END ; {phi} END ; {e_fe} END ; {e_pol} { define one set of tier #1 cat2 in detail... } FOR e_pol := pos_e TO neg_e DO BEGIN FOR e_fe := e_1_4 TO e_21_24 DO BEGIN FOR p_quad := p_1_8 TO p_25_32 DO BEGIN p_cell := CONVERT(phi_per_fe_cell, ORD(p_quad) DIV 2) ; cat2_EME_t1[e_pol,e_fe,p_quad] := ZERO ; cat2_EME_t1[e_pol,e_fe,p_quad].status.implemented := TRUE ; cat2_EME_t1[e_pol,e_fe,p_quad].status.working := TRUE ; cat2_EME_t1[e_pol,e_fe,p_quad].cbus := mbd_calfe[e_pol,e_fe,p_cell].cbus ; cat2_EME_t1[e_pol,e_fe,p_quad].mba := mbd_calfe[e_pol,e_fe,p_cell].mba ; cat2_EME_t1[e_pol,e_fe,p_quad].regtotal := 35 ; FOR relp := relp_0 TO relp_7 DO FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_op_6bit_reg ( FA := 2*ORD(relp) + ORD(bit_f) , REGISTER := ADDRESS(cat2_EME_t1[e_pol,e_fe,p_quad].inopreg[relp,bit_f])); FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_thr_6bit_reg ( FA := 16 + ORD(bit_f) , REGISTER := ADDRESS(cat2_EME_t1[e_pol,e_fe,p_quad].corrreg[bit_f])); bit_f := bit_12_14 ; def_cat2_thr_3bit_reg ( FA := 18, REGISTER := ADDRESS(cat2_EME_t1[e_pol,e_fe,p_quad].corrreg[bit_f])); FOR cmpnum := cmp_0 TO cmp_3 DO BEGIN FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_thr_6bit_reg ( FA := 19 + 3*ORD(cmpnum) + ORD(bit_f), REGISTER := ADDRESS(cat2_EME_t1[e_pol,e_fe,p_quad].compreg[cmpnum,bit_f])); bit_f := bit_12_14 ; def_cat2_thr_3bit_reg ( FA := 19 + 3*ORD(cmpnum) + ORD(bit_f), REGISTER := ADDRESS(cat2_EME_t1[e_pol,e_fe,p_quad].compreg[cmpnum,bit_f])); def_cat2_comp_out_reg ( FA := 21 + 3*ORD(cmpnum), REGISTER := ADDRESS(cat2_EME_t1[e_pol,e_fe,p_quad].compout[cmpnum])); END ; {cmpnum} END ; {p_quad} END ; {e_fe} END ; {e_pol} { ...define the other tier #1 cat2 as close cousins } FOR e_pol := pos_e TO neg_e DO BEGIN FOR e_fe := e_1_4 TO e_21_24 DO BEGIN FOR p_quad := p_1_8 TO p_25_32 DO BEGIN cat2_HDE_t1[e_pol,e_fe,p_quad] := cat2_EME_t1[e_pol,e_fe,p_quad] ; cat2_PxM_t1[e_pol,e_fe,p_quad] := cat2_EME_t1[e_pol,e_fe,p_quad] ; cat2_PyM_t1[e_pol,e_fe,p_quad] := cat2_EME_t1[e_pol,e_fe,p_quad] ; cat2_HDE_t1[e_pol,e_fe,p_quad].ca := 16 + ( ORD(p_quad) MOD 2 ) ; inline_add_card ( ADDRESS( cat2_HDE_t1[e_pol,e_fe,p_quad] ) ) ; cat2_PyM_t1[e_pol,e_fe,p_quad].ca := 20 + ( ORD(p_quad) MOD 2 ) ; inline_add_card ( ADDRESS( cat2_PyM_t1[e_pol,e_fe,p_quad] ) ) ; cat2_PxM_t1[e_pol,e_fe,p_quad].ca := 24 + ( ORD(p_quad) MOD 2 ) ; inline_add_card ( ADDRESS( cat2_PxM_t1[e_pol,e_fe,p_quad] ) ) ; cat2_EME_t1[e_pol,e_fe,p_quad].ca := 28 + ( ORD(p_quad) MOD 2 ) ; inline_add_card ( ADDRESS( cat2_EME_t1[e_pol,e_fe,p_quad] ) ) ; END ; {p_quad} END ; {e_fe} END ; {e_pol} FOR e_pol := pos_e TO neg_e DO BEGIN FOR e_fe := e_1_4 TO e_21_24 DO BEGIN FOR p_quad := p_1_8 TO p_25_32 DO BEGIN p_cell := CONVERT(phi_per_fe_cell, ORD(p_quad) DIV 2) ; chtcr_inputs[e_pol,e_fe,p_quad] := ZERO ; chtcr_inputs[e_pol,e_fe,p_quad].status.implemented := TRUE ; chtcr_inputs[e_pol,e_fe,p_quad].status.working := TRUE ; chtcr_inputs[e_pol,e_fe,p_quad].cbus := mbd_calfe[e_pol,e_fe,p_cell].cbus ; chtcr_inputs[e_pol,e_fe,p_quad].mba := mbd_calfe[e_pol,e_fe,p_cell].mba ; chtcr_inputs[e_pol,e_fe,p_quad].ca := 2 + 2 * ( ORD(p_quad) MOD 2 ) ; chtcr_inputs[e_pol,e_fe,p_quad].regtotal := 32 ; FOR cmptyp := EMEt_cmp TO TOTEt_cmp DO FOR rf_num := ref_0 TO ref_3 DO FOR rele := rele_0 TO rele_3 DO def_29525_reg ( FA := 16*ORD(cmptyp) + 4*ORD(rf_num) + ORD(rele), REGISTER := ADDRESS(chtcr_inputs[e_pol,e_fe,p_quad].inmskreg[cmptyp,rf_num,rele])); inline_add_card ( ADDRESS( chtcr_inputs[e_pol,e_fe,p_quad] ) ) ; chtcr_sum[e_pol,e_fe,p_quad] := ZERO ; chtcr_sum[e_pol,e_fe,p_quad].status.implemented := TRUE ; chtcr_sum[e_pol,e_fe,p_quad].status.working := TRUE ; chtcr_sum[e_pol,e_fe,p_quad].cbus := mbd_calfe[e_pol,e_fe,p_cell].cbus ; chtcr_sum[e_pol,e_fe,p_quad].mba := mbd_calfe[e_pol,e_fe,p_cell].mba ; chtcr_sum[e_pol,e_fe,p_quad].ca := 3 + 2 * ( ORD(p_quad) MOD 2 ) ; chtcr_sum[e_pol,e_fe,p_quad].regtotal := 17 ; FOR ht_num := ht_1 TO ht_8 DO FOR coord := eta_coord TO phi_coord DO def_read_only_reg ( FA := 2*ORD(ht_num) + ORD(coord), REGISTER := ADDRESS(chtcr_sum[e_pol,e_fe,p_quad].hottwrreg[ht_num,coord])); def_read_only_reg ( FA := 32, REGISTER := ADDRESS(chtcr_sum[e_pol,e_fe,p_quad].hintreg)); inline_add_card ( ADDRESS( chtcr_sum[e_pol,e_fe,p_quad] ) ) ; END ; {p_quad} END ; {e_fe} END ; {e_pol} {Tier # 2} FOR e_fe := e_1_4 TO e_21_24 DO BEGIN e_tier2 := CONVERT(eta_per_rack_pair, (ORD(e_fe) DIV 2) ) ; cat2_EME_t2[e_fe] := ZERO ; cat2_EME_t2[e_fe].status.implemented := TRUE ; cat2_EME_t2[e_fe].status.working := TRUE ; cat2_EME_t2[e_fe].cbus := mbd_tier2[e_tier2].cbus ; cat2_EME_t2[e_fe].mba := mbd_tier2[e_tier2].mba ; cat2_EME_t2[e_fe].regtotal := 35 ; FOR i := 1 TO 8 DO FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_op_6bit_reg ( FA := 2*(i-1) + ORD(bit_f) , REGISTER := ADDRESS(cat2_EME_t2[e_fe].inopreg[i,bit_f])); FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_thr_6bit_reg ( FA := 16 + ORD(bit_f) , REGISTER := ADDRESS(cat2_EME_t2[e_fe].corrreg[bit_f])); bit_f := bit_12_14 ; def_cat2_thr_3bit_reg ( FA := 18, REGISTER := ADDRESS(cat2_EME_t2[e_fe].corrreg[bit_f])); FOR cmpnum := cmp_0 TO cmp_3 DO BEGIN FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_thr_6bit_reg ( FA := 19 + 3*ORD(cmpnum) + ORD(bit_f), REGISTER := ADDRESS(cat2_EME_t2[e_fe].compreg[cmpnum,bit_f])); bit_f := bit_12_14 ; def_cat2_thr_3bit_reg ( FA := 19 + 3*ORD(cmpnum) + ORD(bit_f), REGISTER := ADDRESS(cat2_EME_t2[e_fe].compreg[cmpnum,bit_f])); def_cat2_comp_out_reg ( FA := 21 + 3*ORD(cmpnum), REGISTER := ADDRESS(cat2_EME_t2[e_fe].compout[cmpnum])); END ; {cmpnum} inline_add_card ( ADDRESS( cat2_EME_t2[e_fe] ) ) ; END ; {e_fe} cat2_EME_t2[e_1_4].ca := 42 ; cat2_EME_t2[e_5_8].ca := 44 ; cat2_EME_t2[e_9_12].ca := 42 ; cat2_EME_t2[e_13_16].ca := 44 ; cat2_EME_t2[e_17_20].ca := 42 ; cat2_EME_t2[e_21_24].ca := 44 ; FOR e_fe := e_1_4 TO e_21_24 DO BEGIN e_tier2 := CONVERT(eta_per_rack_pair, (ORD(e_fe) DIV 2) ) ; cat2_HDE_t2[e_fe] := ZERO ; cat2_HDE_t2[e_fe].status.implemented := TRUE ; cat2_HDE_t2[e_fe].status.working := TRUE ; cat2_HDE_t2[e_fe].cbus := mbd_tier2[e_tier2].cbus ; cat2_HDE_t2[e_fe].mba := mbd_tier2[e_tier2].mba ; cat2_HDE_t2[e_fe].regtotal := 35 ; FOR i := 1 TO 8 DO FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_op_6bit_reg ( FA := 2*(i-1) + ORD(bit_f) , REGISTER := ADDRESS(cat2_HDE_t2[e_fe].inopreg[i,bit_f])); FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_thr_6bit_reg ( FA := 16 + ORD(bit_f) , REGISTER := ADDRESS(cat2_HDE_t2[e_fe].corrreg[bit_f])); bit_f := bit_12_14 ; def_cat2_thr_3bit_reg ( FA := 18, REGISTER := ADDRESS(cat2_HDE_t2[e_fe].corrreg[bit_f])); FOR cmpnum := cmp_0 TO cmp_3 DO BEGIN FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_thr_6bit_reg ( FA := 19 + 3*ORD(cmpnum) + ORD(bit_f), REGISTER := ADDRESS(cat2_HDE_t2[e_fe].compreg[cmpnum,bit_f])); bit_f := bit_12_14 ; def_cat2_thr_3bit_reg ( FA := 19 + 3*ORD(cmpnum) + ORD(bit_f), REGISTER := ADDRESS(cat2_HDE_t2[e_fe].compreg[cmpnum,bit_f])); def_cat2_comp_out_reg ( FA := 21 + 3*ORD(cmpnum), REGISTER := ADDRESS(cat2_HDE_t2[e_fe].compout[cmpnum])); END ; {cmpnum} inline_add_card ( ADDRESS( cat2_HDE_t2[e_fe] ) ) ; END ; {e_fe} cat2_HDE_t2[e_1_4].ca := 46 ; cat2_HDE_t2[e_5_8].ca := 48 ; cat2_HDE_t2[e_9_12].ca := 46 ; cat2_HDE_t2[e_13_16].ca := 48 ; cat2_HDE_t2[e_17_20].ca := 46 ; cat2_HDE_t2[e_21_24].ca := 48 ; FOR e_fe := e_1_4 TO e_21_24 DO FOR rf_num := ref_0 TO ref_3 DO BEGIN e_tier2 := CONVERT(eta_per_rack_pair, (ORD(e_fe) DIV 2) ) ; cat2_EMC_t2[rf_num,e_fe] := ZERO ; cat2_EMC_t2[rf_num,e_fe].status.implemented := TRUE ; cat2_EMC_t2[rf_num,e_fe].status.working := TRUE ; cat2_EMC_t2[rf_num,e_fe].cbus := mbd_tier2[e_tier2].cbus ; cat2_EMC_t2[rf_num,e_fe].mba := mbd_tier2[e_tier2].mba ; cat2_EMC_t2[rf_num,e_fe].regtotal := 35 ; FOR i := 1 TO 8 DO FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_op_6bit_reg ( FA := 2*(i-1) + ORD(bit_f) , REGISTER := ADDRESS(cat2_EMC_t2[rf_num,e_fe].inopreg[i,bit_f])); FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_thr_6bit_reg ( FA := 16 + ORD(bit_f) , REGISTER := ADDRESS(cat2_EMC_t2[rf_num,e_fe].corrreg[bit_f])); bit_f := bit_12_14 ; def_cat2_thr_3bit_reg ( FA := 18, REGISTER := ADDRESS(cat2_EMC_t2[rf_num,e_fe].corrreg[bit_f])); FOR cmpnum := cmp_0 TO cmp_3 DO BEGIN FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_thr_6bit_reg ( FA := 19 + 3*ORD(cmpnum) + ORD(bit_f), REGISTER := ADDRESS(cat2_EMC_t2[rf_num,e_fe].compreg[cmpnum,bit_f])); bit_f := bit_12_14 ; def_cat2_thr_3bit_reg ( FA := 19 + 3*ORD(cmpnum) + ORD(bit_f), REGISTER := ADDRESS(cat2_EMC_t2[rf_num,e_fe].compreg[cmpnum,bit_f])); def_cat2_comp_out_reg ( FA := 21 + 3*ORD(cmpnum), REGISTER := ADDRESS(cat2_EMC_t2[rf_num,e_fe].compout[cmpnum])); END ; {cmpnum} inline_add_card ( ADDRESS( cat2_EMC_t2[rf_num,e_fe] ) ) ; END ; {rf_num & e_fe} cat2_EMC_t2[ref_0,e_1_4].ca := 2 ; cat2_EMC_t2[ref_1,e_1_4].ca := 4 ; cat2_EMC_t2[ref_2,e_1_4].ca := 6 ; cat2_EMC_t2[ref_3,e_1_4].ca := 8 ; cat2_EMC_t2[ref_0,e_5_8].ca := 12 ; cat2_EMC_t2[ref_1,e_5_8].ca := 14 ; cat2_EMC_t2[ref_2,e_5_8].ca := 16 ; cat2_EMC_t2[ref_3,e_5_8].ca := 18 ; cat2_EMC_t2[ref_0,e_9_12].ca := 2 ; cat2_EMC_t2[ref_1,e_9_12].ca := 4 ; cat2_EMC_t2[ref_2,e_9_12].ca := 6 ; cat2_EMC_t2[ref_3,e_9_12].ca := 8 ; cat2_EMC_t2[ref_0,e_13_16].ca := 12 ; cat2_EMC_t2[ref_1,e_13_16].ca := 14 ; cat2_EMC_t2[ref_2,e_13_16].ca := 16 ; cat2_EMC_t2[ref_3,e_13_16].ca := 18 ; cat2_EMC_t2[ref_0,e_17_20].ca := 2 ; cat2_EMC_t2[ref_1,e_17_20].ca := 4 ; cat2_EMC_t2[ref_2,e_17_20].ca := 6 ; cat2_EMC_t2[ref_3,e_17_20].ca := 8 ; cat2_EMC_t2[ref_0,e_21_24].ca := 12 ; cat2_EMC_t2[ref_1,e_21_24].ca := 14 ; cat2_EMC_t2[ref_2,e_21_24].ca := 16 ; cat2_EMC_t2[ref_3,e_21_24].ca := 18 ; FOR e_fe := e_1_4 TO e_21_24 DO FOR rf_num := ref_0 TO ref_3 DO BEGIN e_tier2 := CONVERT(eta_per_rack_pair, (ORD(e_fe) DIV 2) ) ; cat2_TOTC_t2[rf_num,e_fe] := ZERO ; cat2_TOTC_t2[rf_num,e_fe].status.implemented := TRUE ; cat2_TOTC_t2[rf_num,e_fe].status.working := TRUE ; cat2_TOTC_t2[rf_num,e_fe].cbus := mbd_tier2[e_tier2].cbus ; cat2_TOTC_t2[rf_num,e_fe].mba := mbd_tier2[e_tier2].mba ; cat2_TOTC_t2[rf_num,e_fe].regtotal := 35 ; FOR i := 1 TO 8 DO FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_op_6bit_reg ( FA := 2*(i-1) + ORD(bit_f) , REGISTER := ADDRESS(cat2_TOTC_t2[rf_num,e_fe].inopreg[i,bit_f])); FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_thr_6bit_reg ( FA := 16 + ORD(bit_f) , REGISTER := ADDRESS(cat2_TOTC_t2[rf_num,e_fe].corrreg[bit_f])); bit_f := bit_12_14 ; def_cat2_thr_3bit_reg ( FA := 18, REGISTER := ADDRESS(cat2_TOTC_t2[rf_num,e_fe].corrreg[bit_f])); FOR cmpnum := cmp_0 TO cmp_3 DO BEGIN FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_thr_6bit_reg ( FA := 19 + 3*ORD(cmpnum) + ORD(bit_f), REGISTER := ADDRESS(cat2_TOTC_t2[rf_num,e_fe].compreg[cmpnum,bit_f])); bit_f := bit_12_14 ; def_cat2_thr_3bit_reg ( FA := 19 + 3*ORD(cmpnum) + ORD(bit_f), REGISTER := ADDRESS(cat2_TOTC_t2[rf_num,e_fe].compreg[cmpnum,bit_f])); def_cat2_comp_out_reg ( FA := 21 + 3*ORD(cmpnum), REGISTER := ADDRESS(cat2_TOTC_t2[rf_num,e_fe].compout[cmpnum])); END ; {cmpnum} inline_add_card ( ADDRESS( cat2_TOTC_t2[rf_num,e_fe] ) ) ; END ; {rf_num & e_fe} cat2_TOTC_t2[ref_0,e_1_4].ca := 22 ; cat2_TOTC_t2[ref_1,e_1_4].ca := 24 ; cat2_TOTC_t2[ref_2,e_1_4].ca := 26 ; cat2_TOTC_t2[ref_3,e_1_4].ca := 28 ; cat2_TOTC_t2[ref_0,e_5_8].ca := 32 ; cat2_TOTC_t2[ref_1,e_5_8].ca := 34 ; cat2_TOTC_t2[ref_2,e_5_8].ca := 36 ; cat2_TOTC_t2[ref_3,e_5_8].ca := 38 ; cat2_TOTC_t2[ref_0,e_9_12].ca := 22 ; cat2_TOTC_t2[ref_1,e_9_12].ca := 24 ; cat2_TOTC_t2[ref_2,e_9_12].ca := 26 ; cat2_TOTC_t2[ref_3,e_9_12].ca := 28 ; cat2_TOTC_t2[ref_0,e_13_16].ca := 32 ; cat2_TOTC_t2[ref_1,e_13_16].ca := 34 ; cat2_TOTC_t2[ref_2,e_13_16].ca := 36 ; cat2_TOTC_t2[ref_3,e_13_16].ca := 38 ; cat2_TOTC_t2[ref_0,e_17_20].ca := 22 ; cat2_TOTC_t2[ref_1,e_17_20].ca := 24 ; cat2_TOTC_t2[ref_2,e_17_20].ca := 26 ; cat2_TOTC_t2[ref_3,e_17_20].ca := 28 ; cat2_TOTC_t2[ref_0,e_21_24].ca := 32 ; cat2_TOTC_t2[ref_1,e_21_24].ca := 34 ; cat2_TOTC_t2[ref_2,e_21_24].ca := 36 ; cat2_TOTC_t2[ref_3,e_21_24].ca := 38 ; FOR e_tier2 := e_1_8 TO e_17_24 DO FOR m_sign := pos_m TO neg_m DO BEGIN cat2_PxM_t2[m_sign,e_tier2] := ZERO ; cat2_PxM_t2[m_sign,e_tier2].status.implemented := TRUE ; cat2_PxM_t2[m_sign,e_tier2].status.working := TRUE ; cat2_PxM_t2[m_sign,e_tier2].cbus := mbd_tier2[e_tier2].cbus ; cat2_PxM_t2[m_sign,e_tier2].mba := mbd_tier2[e_tier2].mba ; cat2_PxM_t2[m_sign,e_tier2].regtotal := 35 ; FOR i := 1 TO 8 DO FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_op_6bit_reg ( FA := 2*(i-1) + ORD(bit_f) , REGISTER := ADDRESS(cat2_PxM_t2[m_sign,e_tier2].inopreg[i,bit_f])); FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_thr_6bit_reg ( FA := 16 + ORD(bit_f) , REGISTER := ADDRESS(cat2_PxM_t2[m_sign,e_tier2].corrreg[bit_f])); bit_f := bit_12_14 ; def_cat2_thr_3bit_reg ( FA := 18, REGISTER := ADDRESS(cat2_PxM_t2[m_sign,e_tier2].corrreg[bit_f])); FOR cmpnum := cmp_0 TO cmp_3 DO BEGIN FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_thr_6bit_reg ( FA := 19 + 3*ORD(cmpnum) + ORD(bit_f), REGISTER := ADDRESS(cat2_PxM_t2[m_sign,e_tier2].compreg[cmpnum,bit_f])); bit_f := bit_12_14 ; def_cat2_thr_3bit_reg ( FA := 19 + 3*ORD(cmpnum) + ORD(bit_f), REGISTER := ADDRESS(cat2_PxM_t2[m_sign,e_tier2].compreg[cmpnum,bit_f])); def_cat2_comp_out_reg ( FA := 21 + 3*ORD(cmpnum), REGISTER := ADDRESS(cat2_PxM_t2[m_sign,e_tier2].compout[cmpnum])); END ; {cmpnum} inline_add_card ( ADDRESS( cat2_PxM_t2[m_sign,e_tier2] ) ) ; END ; {m_sign & e_fe} cat2_PxM_t2[pos_m,e_1_8].ca := 54 ; cat2_PxM_t2[neg_m,e_1_8].ca := 52 ; cat2_PxM_t2[pos_m,e_9_16].ca := 54 ; cat2_PxM_t2[neg_m,e_9_16].ca := 52 ; cat2_PxM_t2[pos_m,e_17_24].ca := 54 ; cat2_PxM_t2[neg_m,e_17_24].ca := 52 ; FOR e_tier2 := e_1_8 TO e_17_24 DO FOR m_sign := pos_m TO neg_m DO BEGIN cat2_PyM_t2[m_sign,e_tier2] := ZERO ; cat2_PyM_t2[m_sign,e_tier2].status.implemented := TRUE ; cat2_PyM_t2[m_sign,e_tier2].status.working := TRUE ; cat2_PyM_t2[m_sign,e_tier2].cbus := mbd_tier2[e_tier2].cbus ; cat2_PyM_t2[m_sign,e_tier2].mba := mbd_tier2[e_tier2].mba ; cat2_PyM_t2[m_sign,e_tier2].regtotal := 35 ; FOR i := 1 TO 8 DO FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_op_6bit_reg ( FA := 2*(i-1) + ORD(bit_f) , REGISTER := ADDRESS(cat2_PyM_t2[m_sign,e_tier2].inopreg[i,bit_f])); FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_thr_6bit_reg ( FA := 16 + ORD(bit_f) , REGISTER := ADDRESS(cat2_PyM_t2[m_sign,e_tier2].corrreg[bit_f])); bit_f := bit_12_14 ; def_cat2_thr_3bit_reg ( FA := 18, REGISTER := ADDRESS(cat2_PyM_t2[m_sign,e_tier2].corrreg[bit_f])); FOR cmpnum := cmp_0 TO cmp_3 DO BEGIN FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_thr_6bit_reg ( FA := 19 + 3*ORD(cmpnum) + ORD(bit_f), REGISTER := ADDRESS(cat2_PyM_t2[m_sign,e_tier2].compreg[cmpnum,bit_f])); bit_f := bit_12_14 ; def_cat2_thr_3bit_reg ( FA := 19 + 3*ORD(cmpnum) + ORD(bit_f), REGISTER := ADDRESS(cat2_PyM_t2[m_sign,e_tier2].compreg[cmpnum,bit_f])); def_cat2_comp_out_reg ( FA := 21 + 3*ORD(cmpnum), REGISTER := ADDRESS(cat2_PyM_t2[m_sign,e_tier2].compout[cmpnum])); END ; {cmpnum} inline_add_card ( ADDRESS( cat2_PyM_t2[m_sign,e_tier2] ) ) ; END ; {m_sign & e_fe} cat2_PyM_t2[pos_m,e_1_8].ca := 58 ; cat2_PyM_t2[neg_m,e_1_8].ca := 56 ; cat2_PyM_t2[pos_m,e_9_16].ca := 58 ; cat2_PyM_t2[neg_m,e_9_16].ca := 56 ; cat2_PyM_t2[pos_m,e_17_24].ca := 58 ; cat2_PyM_t2[neg_m,e_17_24].ca := 56 ; {Tier # 3} cat3_Py_t3 := ZERO ; cat3_Py_t3.status.implemented := TRUE ; cat3_Py_t3.status.working := TRUE ; cat3_Py_t3.cbus := mbd_tier3_4.cbus ; cat3_Py_t3.mba := mbd_tier3_4.mba ; cat3_Py_t3.regtotal := 40 ; FOR i := 0 TO 15 DO def_cat2_op_6bit_reg ( FA := i, REGISTER := ADDRESS(cat3_Py_t3.inopreg[i]) ); FOR cmpnum := cmp_0 TO cmp_3 DO BEGIN def_cat2_thr_6bit_reg ( FA := 16 + 8*ORD(cmpnum) + 3, REGISTER := ADDRESS(cat3_Py_t3.compreg[cmpnum,cat3_cmp_0_5])); def_cat2_thr_6bit_reg ( FA := 16 + 8*ORD(cmpnum) + 0, REGISTER := ADDRESS(cat3_Py_t3.compreg[cmpnum,cat3_cmp_6_11])); def_cat2_thr_6bit_reg ( FA := 16 + 8*ORD(cmpnum) + 2, REGISTER := ADDRESS(cat3_Py_t3.compreg[cmpnum,cat3_cmp_12_17])); def_cat3_thr_1bit_reg ( FA := 16 + 8*ORD(cmpnum) + 1, REGISTER := ADDRESS(cat3_Py_t3.compreg[cmpnum,cat3_cmp_18])); def_cat2_comp_out_reg ( FA := 17 + 8*ORD(cmpnum), REGISTER := ADDRESS(cat3_Py_t3.compout[cmpnum])); END ; {cmpnum} def_cat2_thr_6bit_reg ( FA := 51, REGISTER := ADDRESS(cat3_Py_t3.corrreg[cat3_cor_0_5])); def_cat2_thr_6bit_reg ( FA := 48, REGISTER := ADDRESS(cat3_Py_t3.corrreg[cat3_cor_6_11])); def_cat2_thr_6bit_reg ( FA := 50, REGISTER := ADDRESS(cat3_Py_t3.corrreg[cat3_cor_12_17])); def_cat2_thr_6bit_reg ( FA := 49, REGISTER := ADDRESS(cat3_Py_t3.corrreg[cat3_cor_18_23])); inline_add_card ( ADDRESS( cat3_Py_t3 ) ) ; cat3_Py_t3.ca := 39 ; cat3_Px_t3 := ZERO ; cat3_Px_t3.status.implemented := TRUE ; cat3_Px_t3.status.working := TRUE ; cat3_Px_t3.cbus := mbd_tier3_4.cbus ; cat3_Px_t3.mba := mbd_tier3_4.mba ; cat3_Px_t3.regtotal := 40 ; FOR i := 0 TO 15 DO def_cat2_op_6bit_reg ( FA := i, REGISTER := ADDRESS(cat3_Px_t3.inopreg[i]) ); FOR cmpnum := cmp_0 TO cmp_3 DO BEGIN def_cat2_thr_6bit_reg ( FA := 16 + 8*ORD(cmpnum) + 3, REGISTER := ADDRESS(cat3_Px_t3.compreg[cmpnum,cat3_cmp_0_5])); def_cat2_thr_6bit_reg ( FA := 16 + 8*ORD(cmpnum) + 0, REGISTER := ADDRESS(cat3_Px_t3.compreg[cmpnum,cat3_cmp_6_11])); def_cat2_thr_6bit_reg ( FA := 16 + 8*ORD(cmpnum) + 2, REGISTER := ADDRESS(cat3_Px_t3.compreg[cmpnum,cat3_cmp_12_17])); def_cat3_thr_1bit_reg ( FA := 16 + 8*ORD(cmpnum) + 1, REGISTER := ADDRESS(cat3_Px_t3.compreg[cmpnum,cat3_cmp_18])); def_cat2_comp_out_reg ( FA := 17 + 8*ORD(cmpnum), REGISTER := ADDRESS(cat3_Px_t3.compout[cmpnum])); END ; {cmpnum} def_cat2_thr_6bit_reg ( FA := 51, REGISTER := ADDRESS(cat3_Px_t3.corrreg[cat3_cor_0_5])); def_cat2_thr_6bit_reg ( FA := 48, REGISTER := ADDRESS(cat3_Px_t3.corrreg[cat3_cor_6_11])); def_cat2_thr_6bit_reg ( FA := 50, REGISTER := ADDRESS(cat3_Px_t3.corrreg[cat3_cor_12_17])); def_cat2_thr_6bit_reg ( FA := 49, REGISTER := ADDRESS(cat3_Px_t3.corrreg[cat3_cor_18_23])); inline_add_card ( ADDRESS( cat3_Px_t3 ) ) ; cat3_Px_t3.ca := 37 ; FOR j := 0 TO 3 DO BEGIN cat3_EM_Et_t3[j] := ZERO ; cat3_EM_Et_t3[j].status.implemented := TRUE ; cat3_EM_Et_t3[j].status.working := TRUE ; cat3_EM_Et_t3[j].cbus := mbd_tier3_4.cbus ; cat3_EM_Et_t3[j].mba := mbd_tier3_4.mba ; cat3_EM_Et_t3[j].regtotal := 40 ; FOR i := 0 TO 15 DO def_cat2_op_6bit_reg ( FA := i, REGISTER := ADDRESS(cat3_EM_Et_t3[j].inopreg[i]) ); FOR cmpnum := cmp_0 TO cmp_3 DO BEGIN def_cat2_thr_6bit_reg ( FA := 16 + 8*ORD(cmpnum) + 3, REGISTER := ADDRESS(cat3_EM_Et_t3[j].compreg[cmpnum,cat3_cmp_0_5])); def_cat2_thr_6bit_reg ( FA := 16 + 8*ORD(cmpnum) + 0, REGISTER := ADDRESS(cat3_EM_Et_t3[j].compreg[cmpnum,cat3_cmp_6_11])); def_cat2_thr_6bit_reg ( FA := 16 + 8*ORD(cmpnum) + 2, REGISTER := ADDRESS(cat3_EM_Et_t3[j].compreg[cmpnum,cat3_cmp_12_17])); def_cat3_thr_1bit_reg ( FA := 16 + 8*ORD(cmpnum) + 1, REGISTER := ADDRESS(cat3_EM_Et_t3[j].compreg[cmpnum,cat3_cmp_18])); def_cat2_comp_out_reg ( FA := 17 + 8*ORD(cmpnum), REGISTER := ADDRESS(cat3_EM_Et_t3[j].compout[cmpnum])); END ; {cmpnum} def_cat2_thr_6bit_reg ( FA := 51, REGISTER := ADDRESS(cat3_EM_Et_t3[j].corrreg[cat3_cor_0_5])); def_cat2_thr_6bit_reg ( FA := 48, REGISTER := ADDRESS(cat3_EM_Et_t3[j].corrreg[cat3_cor_6_11])); def_cat2_thr_6bit_reg ( FA := 50, REGISTER := ADDRESS(cat3_EM_Et_t3[j].corrreg[cat3_cor_12_17])); def_cat2_thr_6bit_reg ( FA := 49, REGISTER := ADDRESS(cat3_EM_Et_t3[j].corrreg[cat3_cor_18_23])); inline_add_card ( ADDRESS( cat3_EM_Et_t3[j] ) ) ; END ; cat3_EM_Et_t3[0].ca := 17 ; cat3_EM_Et_t3[1].ca := 19 ; cat3_EM_Et_t3[2].ca := 21 ; cat3_EM_Et_t3[3].ca := 23 ; cat3_EM_L2_t3 := ZERO ; cat3_EM_L2_t3.status.implemented := TRUE ; cat3_EM_L2_t3.status.working := TRUE ; cat3_EM_L2_t3.cbus := mbd_tier3_4.cbus ; cat3_EM_L2_t3.mba := mbd_tier3_4.mba ; cat3_EM_L2_t3.regtotal := 40 ; FOR i := 0 TO 15 DO def_cat2_op_6bit_reg ( FA := i, REGISTER := ADDRESS(cat3_EM_L2_t3.inopreg[i]) ); FOR cmpnum := cmp_0 TO cmp_3 DO BEGIN def_cat2_thr_6bit_reg ( FA := 16 + 8*ORD(cmpnum) + 3, REGISTER := ADDRESS(cat3_EM_L2_t3.compreg[cmpnum,cat3_cmp_0_5])); def_cat2_thr_6bit_reg ( FA := 16 + 8*ORD(cmpnum) + 0, REGISTER := ADDRESS(cat3_EM_L2_t3.compreg[cmpnum,cat3_cmp_6_11])); def_cat2_thr_6bit_reg ( FA := 16 + 8*ORD(cmpnum) + 2, REGISTER := ADDRESS(cat3_EM_L2_t3.compreg[cmpnum,cat3_cmp_12_17])); def_cat3_thr_1bit_reg ( FA := 16 + 8*ORD(cmpnum) + 1, REGISTER := ADDRESS(cat3_EM_L2_t3.compreg[cmpnum,cat3_cmp_18])); def_cat2_comp_out_reg ( FA := 17 + 8*ORD(cmpnum), REGISTER := ADDRESS(cat3_EM_L2_t3.compout[cmpnum])); END ; {cmpnum} def_cat2_thr_6bit_reg ( FA := 51, REGISTER := ADDRESS(cat3_EM_L2_t3.corrreg[cat3_cor_0_5])); def_cat2_thr_6bit_reg ( FA := 48, REGISTER := ADDRESS(cat3_EM_L2_t3.corrreg[cat3_cor_6_11])); def_cat2_thr_6bit_reg ( FA := 50, REGISTER := ADDRESS(cat3_EM_L2_t3.corrreg[cat3_cor_12_17])); def_cat2_thr_6bit_reg ( FA := 49, REGISTER := ADDRESS(cat3_EM_L2_t3.corrreg[cat3_cor_18_23])); inline_add_card ( ADDRESS( cat3_EM_L2_t3 ) ) ; cat3_EM_L2_t3.ca := 25 ; FOR j := 0 TO 3 DO BEGIN cat3_HD_Et_t3[j] := ZERO ; cat3_HD_Et_t3[j].status.implemented := TRUE ; cat3_HD_Et_t3[j].status.working := TRUE ; cat3_HD_Et_t3[j].cbus := mbd_tier3_4.cbus ; cat3_HD_Et_t3[j].mba := mbd_tier3_4.mba ; cat3_HD_Et_t3[j].regtotal := 40 ; FOR i := 0 TO 15 DO def_cat2_op_6bit_reg ( FA := i, REGISTER := ADDRESS(cat3_HD_Et_t3[j].inopreg[i]) ); FOR cmpnum := cmp_0 TO cmp_3 DO BEGIN def_cat2_thr_6bit_reg ( FA := 16 + 8*ORD(cmpnum) + 3, REGISTER := ADDRESS(cat3_HD_Et_t3[j].compreg[cmpnum,cat3_cmp_0_5])); def_cat2_thr_6bit_reg ( FA := 16 + 8*ORD(cmpnum) + 0, REGISTER := ADDRESS(cat3_HD_Et_t3[j].compreg[cmpnum,cat3_cmp_6_11])); def_cat2_thr_6bit_reg ( FA := 16 + 8*ORD(cmpnum) + 2, REGISTER := ADDRESS(cat3_HD_Et_t3[j].compreg[cmpnum,cat3_cmp_12_17])); def_cat3_thr_1bit_reg ( FA := 16 + 8*ORD(cmpnum) + 1, REGISTER := ADDRESS(cat3_HD_Et_t3[j].compreg[cmpnum,cat3_cmp_18])); def_cat2_comp_out_reg ( FA := 17 + 8*ORD(cmpnum), REGISTER := ADDRESS(cat3_HD_Et_t3[j].compout[cmpnum])); END ; {cmpnum} def_cat2_thr_6bit_reg ( FA := 51, REGISTER := ADDRESS(cat3_HD_Et_t3[j].corrreg[cat3_cor_0_5])); def_cat2_thr_6bit_reg ( FA := 48, REGISTER := ADDRESS(cat3_HD_Et_t3[j].corrreg[cat3_cor_6_11])); def_cat2_thr_6bit_reg ( FA := 50, REGISTER := ADDRESS(cat3_HD_Et_t3[j].corrreg[cat3_cor_12_17])); def_cat2_thr_6bit_reg ( FA := 49, REGISTER := ADDRESS(cat3_HD_Et_t3[j].corrreg[cat3_cor_18_23])); inline_add_card ( ADDRESS( cat3_HD_Et_t3[j] ) ) ; END ; cat3_HD_Et_t3[0].ca := 29 ; cat3_HD_Et_t3[1].ca := 31 ; cat3_HD_Et_t3[2].ca := 33 ; cat3_HD_Et_t3[3].ca := 35 ; cat3_HD_L2_t3 := ZERO ; cat3_HD_L2_t3.status.implemented := TRUE ; cat3_HD_L2_t3.status.working := TRUE ; cat3_HD_L2_t3.cbus := mbd_tier3_4.cbus ; cat3_HD_L2_t3.mba := mbd_tier3_4.mba ; cat3_HD_L2_t3.regtotal := 40 ; FOR i := 0 TO 15 DO def_cat2_op_6bit_reg ( FA := i, REGISTER := ADDRESS(cat3_HD_L2_t3.inopreg[i]) ); FOR cmpnum := cmp_0 TO cmp_3 DO BEGIN def_cat2_thr_6bit_reg ( FA := 16 + 8*ORD(cmpnum) + 3, REGISTER := ADDRESS(cat3_HD_L2_t3.compreg[cmpnum,cat3_cmp_0_5])); def_cat2_thr_6bit_reg ( FA := 16 + 8*ORD(cmpnum) + 0, REGISTER := ADDRESS(cat3_HD_L2_t3.compreg[cmpnum,cat3_cmp_6_11])); def_cat2_thr_6bit_reg ( FA := 16 + 8*ORD(cmpnum) + 2, REGISTER := ADDRESS(cat3_HD_L2_t3.compreg[cmpnum,cat3_cmp_12_17])); def_cat3_thr_1bit_reg ( FA := 16 + 8*ORD(cmpnum) + 1, REGISTER := ADDRESS(cat3_HD_L2_t3.compreg[cmpnum,cat3_cmp_18])); def_cat2_comp_out_reg ( FA := 17 + 8*ORD(cmpnum), REGISTER := ADDRESS(cat3_HD_L2_t3.compout[cmpnum])); END ; {cmpnum} def_cat2_thr_6bit_reg ( FA := 51, REGISTER := ADDRESS(cat3_HD_L2_t3.corrreg[cat3_cor_0_5])); def_cat2_thr_6bit_reg ( FA := 48, REGISTER := ADDRESS(cat3_HD_L2_t3.corrreg[cat3_cor_6_11])); def_cat2_thr_6bit_reg ( FA := 50, REGISTER := ADDRESS(cat3_HD_L2_t3.corrreg[cat3_cor_12_17])); def_cat2_thr_6bit_reg ( FA := 49, REGISTER := ADDRESS(cat3_HD_L2_t3.corrreg[cat3_cor_18_23])); inline_add_card ( ADDRESS( cat3_HD_L2_t3 ) ) ; cat3_HD_L2_t3.ca := 27 ; FOR rf_num := ref_0 TO ref_3 DO BEGIN cat2_EM_cnt_t3[rf_num] := ZERO ; cat2_EM_cnt_t3[rf_num].status.implemented := TRUE ; cat2_EM_cnt_t3[rf_num].status.working := TRUE ; cat2_EM_cnt_t3[rf_num].cbus := mbd_tier3_4.cbus ; cat2_EM_cnt_t3[rf_num].mba := mbd_tier3_4.mba ; cat2_EM_cnt_t3[rf_num].regtotal := 35 ; FOR i := 1 TO 8 DO FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_op_6bit_reg ( FA := 2*(i-1) + ORD(bit_f) , REGISTER := ADDRESS(cat2_EM_cnt_t3[rf_num].inopreg[i,bit_f])); FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_thr_6bit_reg ( FA := 16 + ORD(bit_f) , REGISTER := ADDRESS(cat2_EM_cnt_t3[rf_num].corrreg[bit_f])); bit_f := bit_12_14 ; def_cat2_thr_3bit_reg ( FA := 18, REGISTER := ADDRESS(cat2_EM_cnt_t3[rf_num].corrreg[bit_f])); FOR cmpnum := cmp_0 TO cmp_3 DO BEGIN FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_thr_6bit_reg ( FA := 19 + 3*ORD(cmpnum) + ORD(bit_f), REGISTER := ADDRESS(cat2_EM_cnt_t3[rf_num].compreg[cmpnum,bit_f])); bit_f := bit_12_14 ; def_cat2_thr_3bit_reg ( FA := 19 + 3*ORD(cmpnum) + ORD(bit_f), REGISTER := ADDRESS(cat2_EM_cnt_t3[rf_num].compreg[cmpnum,bit_f])); def_cat2_comp_out_reg ( FA := 21 + 3*ORD(cmpnum), REGISTER := ADDRESS(cat2_EM_cnt_t3[rf_num].compout[cmpnum])); END ; {cmpnum} inline_add_card ( ADDRESS( cat2_EM_cnt_t3[rf_num] ) ) ; END ; {rf_num & e_fe} cat2_EM_cnt_t3[ref_0].ca := 1 ; cat2_EM_cnt_t3[ref_1].ca := 3 ; cat2_EM_cnt_t3[ref_2].ca := 5 ; cat2_EM_cnt_t3[ref_3].ca := 7 ; FOR rf_num := ref_0 TO ref_3 DO BEGIN cat2_TOT_cnt_t3[rf_num] := ZERO ; cat2_TOT_cnt_t3[rf_num].status.implemented := TRUE ; cat2_TOT_cnt_t3[rf_num].status.working := TRUE ; cat2_TOT_cnt_t3[rf_num].cbus := mbd_tier3_4.cbus ; cat2_TOT_cnt_t3[rf_num].mba := mbd_tier3_4.mba ; cat2_TOT_cnt_t3[rf_num].regtotal := 35 ; FOR i := 1 TO 8 DO FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_op_6bit_reg ( FA := 2*(i-1) + ORD(bit_f) , REGISTER := ADDRESS(cat2_TOT_cnt_t3[rf_num].inopreg[i,bit_f])); FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_thr_6bit_reg ( FA := 16 + ORD(bit_f) , REGISTER := ADDRESS(cat2_TOT_cnt_t3[rf_num].corrreg[bit_f])); bit_f := bit_12_14 ; def_cat2_thr_3bit_reg ( FA := 18, REGISTER := ADDRESS(cat2_TOT_cnt_t3[rf_num].corrreg[bit_f])); FOR cmpnum := cmp_0 TO cmp_3 DO BEGIN FOR bit_f := bit_0_5 TO bit_6_11 DO def_cat2_thr_6bit_reg ( FA := 19 + 3*ORD(cmpnum) + ORD(bit_f), REGISTER := ADDRESS(cat2_TOT_cnt_t3[rf_num].compreg[cmpnum,bit_f])); bit_f := bit_12_14 ; def_cat2_thr_3bit_reg ( FA := 19 + 3*ORD(cmpnum) + ORD(bit_f), REGISTER := ADDRESS(cat2_TOT_cnt_t3[rf_num].compreg[cmpnum,bit_f])); def_cat2_comp_out_reg ( FA := 21 + 3*ORD(cmpnum), REGISTER := ADDRESS(cat2_TOT_cnt_t3[rf_num].compout[cmpnum])); END ; {cmpnum} inline_add_card ( ADDRESS( cat2_TOT_cnt_t3[rf_num] ) ) ; END ; {rf_num & e_fe} cat2_TOT_cnt_t3[ref_0].ca := 9 ; cat2_TOT_cnt_t3[ref_1].ca := 11 ; cat2_TOT_cnt_t3[ref_2].ca := 13 ; cat2_TOT_cnt_t3[ref_3].ca := 15 ; {Tier # 4} FOR j := 0 TO 2 DO BEGIN cat3_TOT_Et_t4[j] := ZERO ; cat3_TOT_Et_t4[j].status.implemented := TRUE ; cat3_TOT_Et_t4[j].status.working := TRUE ; cat3_TOT_Et_t4[j].cbus := mbd_tier3_4.cbus ; cat3_TOT_Et_t4[j].mba := mbd_tier3_4.mba ; cat3_TOT_Et_t4[j].regtotal := 40 ; FOR i := 0 TO 15 DO def_cat2_op_6bit_reg ( FA := i, REGISTER := ADDRESS(cat3_TOT_Et_t4[j].inopreg[i]) ); FOR cmpnum := cmp_0 TO cmp_3 DO BEGIN def_cat2_thr_6bit_reg ( FA := 16 + 8*ORD(cmpnum) + 3, REGISTER := ADDRESS(cat3_TOT_Et_t4[j].compreg[cmpnum,cat3_cmp_0_5])); def_cat2_thr_6bit_reg ( FA := 16 + 8*ORD(cmpnum) + 0, REGISTER := ADDRESS(cat3_TOT_Et_t4[j].compreg[cmpnum,cat3_cmp_6_11])); def_cat2_thr_6bit_reg ( FA := 16 + 8*ORD(cmpnum) + 2, REGISTER := ADDRESS(cat3_TOT_Et_t4[j].compreg[cmpnum,cat3_cmp_12_17])); def_cat3_thr_1bit_reg ( FA := 16 + 8*ORD(cmpnum) + 1, REGISTER := ADDRESS(cat3_TOT_Et_t4[j].compreg[cmpnum,cat3_cmp_18])); def_cat2_comp_out_reg ( FA := 17 + 8*ORD(cmpnum), REGISTER := ADDRESS(cat3_TOT_Et_t4[j].compout[cmpnum])); END ; {cmpnum} def_cat2_thr_6bit_reg ( FA := 51, REGISTER := ADDRESS(cat3_TOT_Et_t4[j].corrreg[cat3_cor_0_5])); def_cat2_thr_6bit_reg ( FA := 48, REGISTER := ADDRESS(cat3_TOT_Et_t4[j].corrreg[cat3_cor_6_11])); def_cat2_thr_6bit_reg ( FA := 50, REGISTER := ADDRESS(cat3_TOT_Et_t4[j].corrreg[cat3_cor_12_17])); def_cat2_thr_6bit_reg ( FA := 49, REGISTER := ADDRESS(cat3_TOT_Et_t4[j].corrreg[cat3_cor_18_23])); inline_add_card ( ADDRESS( cat3_TOT_Et_t4[j] ) ) ; END ; cat3_TOT_Et_t4[0].ca := 43 ; cat3_TOT_Et_t4[1].ca := 45 ; cat3_TOT_Et_t4[2].ca := 47 ; cat3_TOT_L2_t4 := ZERO ; cat3_TOT_L2_t4.status.implemented := TRUE ; cat3_TOT_L2_t4.status.working := TRUE ; cat3_TOT_L2_t4.cbus := mbd_tier3_4.cbus ; cat3_TOT_L2_t4.mba := mbd_tier3_4.mba ; cat3_TOT_L2_t4.regtotal := 40 ; cat3_TOT_L2_t4.ca := 41 ; FOR i := 0 TO 15 DO def_cat2_op_6bit_reg ( FA := i, REGISTER := ADDRESS(cat3_TOT_L2_t4.inopreg[i]) ); FOR cmpnum := cmp_0 TO cmp_3 DO BEGIN def_cat2_thr_6bit_reg ( FA := 16 + 8*ORD(cmpnum) + 3, REGISTER := ADDRESS(cat3_TOT_L2_t4.compreg[cmpnum,cat3_cmp_0_5])); def_cat2_thr_6bit_reg ( FA := 16 + 8*ORD(cmpnum) + 0, REGISTER := ADDRESS(cat3_TOT_L2_t4.compreg[cmpnum,cat3_cmp_6_11])); def_cat2_thr_6bit_reg ( FA := 16 + 8*ORD(cmpnum) + 2, REGISTER := ADDRESS(cat3_TOT_L2_t4.compreg[cmpnum,cat3_cmp_12_17])); def_cat3_thr_1bit_reg ( FA := 16 + 8*ORD(cmpnum) + 1, REGISTER := ADDRESS(cat3_TOT_L2_t4.compreg[cmpnum,cat3_cmp_18])); def_cat2_comp_out_reg ( FA := 17 + 8*ORD(cmpnum), REGISTER := ADDRESS(cat3_TOT_L2_t4.compout[cmpnum])); END ; {cmpnum} def_cat2_thr_6bit_reg ( FA := 51, REGISTER := ADDRESS(cat3_TOT_L2_t4.corrreg[cat3_cor_0_5])); def_cat2_thr_6bit_reg ( FA := 48, REGISTER := ADDRESS(cat3_TOT_L2_t4.corrreg[cat3_cor_6_11])); def_cat2_thr_6bit_reg ( FA := 50, REGISTER := ADDRESS(cat3_TOT_L2_t4.corrreg[cat3_cor_12_17])); def_cat2_thr_6bit_reg ( FA := 49, REGISTER := ADDRESS(cat3_TOT_L2_t4.corrreg[cat3_cor_18_23])); inline_add_card ( ADDRESS( cat3_TOT_L2_t4 ) ) ; fmln_compare := ZERO ; fmln_compare.status.implemented := TRUE ; fmln_compare.status.working := TRUE ; fmln_compare.cbus := mbd_tier3_4.cbus ; fmln_compare.mba := mbd_tier3_4.mba ; fmln_compare.regtotal := 8 ; fmln_compare.ca := 51 ; def_standard_reg ( FA := 0, REGISTER := ADDRESS(fmln_compare.controlreg) ); fmln_compare.controlreg.class := [ histdep ] ; def_standard_reg ( FA := 1, REGISTER := ADDRESS(fmln_compare.wr_protect) ); def_standard_reg ( FA := 2, REGISTER := ADDRESS(fmln_compare.ovf_ovrule) ); def_standard_reg ( FA := 3, REGISTER := ADDRESS(fmln_compare.write_data) ); fmln_compare.write_data.rmsk := 0 ; fmln_compare.write_data.class := [ histdep ] ; def_read_only_reg ( FA := 4, REGISTER := ADDRESS(fmln_compare.read_thrsh) ); FOR i := 1 TO 3 DO BEGIN def_read_only_reg ( FA := 4+i, REGISTER := ADDRESS(fmln_compare.addr_gen[i]) ); fmln_compare.addr_gen[i].rmsk := 63 ; END ; inline_add_card ( ADDRESS( fmln_compare ) ) ; fmln_compute := ZERO ; fmln_compute.status.implemented := TRUE ; fmln_compute.status.working := TRUE ; fmln_compute.cbus := mbd_tier3_4.cbus ; fmln_compute.mba := mbd_tier3_4.mba ; fmln_compute.regtotal := 8 ; fmln_compute.ca := 49 ; def_standard_reg ( FA := 0, REGISTER := ADDRESS(fmln_compute.controlreg) ); fmln_compute.controlreg.class := [ histdep ] ; def_standard_reg ( FA := 1, REGISTER := ADDRESS(fmln_compute.wr_protect) ); def_standard_reg ( FA := 2, REGISTER := ADDRESS(fmln_compute.ovf_ovrule) ); def_standard_reg ( FA := 3, REGISTER := ADDRESS(fmln_compute.write_data) ); fmln_compute.write_data.rmsk := 0 ; fmln_compute.write_data.class := [ histdep ] ; def_read_only_reg ( FA := 4, REGISTER := ADDRESS(fmln_compute.read_thrsh) ); FOR i := 1 TO 3 DO BEGIN def_read_only_reg ( FA := 4+i, REGISTER := ADDRESS(fmln_compute.addr_gen[i]) ); fmln_compute.addr_gen[i].rmsk := 63 ; END ; inline_add_card ( ADDRESS( fmln_compute ) ) ; {readout} imlro_eng1 := ZERO ; imlro_eng1.status.implemented := TRUE ; imlro_eng1.status.working := TRUE ; imlro_eng1.cbus := mbd_readout.cbus ; imlro_eng1.mba := mbd_readout.mba ; imlro_eng1.ca := 10 ; imlro_eng1.regtotal := 16 ; FOR byte_num := first_byte TO third_byte DO BEGIN def_29520_reg ( FA := 0 + ORD(byte_num), REGISTER := ADDRESS(imlro_eng1.EM_Et_eng[byte_num]) ) ; def_29520_reg ( FA := 4 + ORD(byte_num), REGISTER := ADDRESS(imlro_eng1.HD_Et_eng[byte_num]) ) ; def_29520_reg ( FA := 8 + ORD(byte_num), REGISTER := ADDRESS(imlro_eng1.Px_moment[byte_num]) ) ; def_29520_reg ( FA := 12 + ORD(byte_num), REGISTER := ADDRESS(imlro_eng1.Py_moment[byte_num]) ) ; END ; def_29520_reg ( FA := 3, REGISTER := ADDRESS(imlro_eng1.spare1) ) ; def_29520_reg ( FA := 7, REGISTER := ADDRESS(imlro_eng1.spare2) ) ; def_29520_reg ( FA := 11, REGISTER := ADDRESS(imlro_eng1.spare3) ) ; def_29520_reg ( FA := 15, REGISTER := ADDRESS(imlro_eng1.spare4) ) ; inline_add_card ( ADDRESS( imlro_eng1 ) ) ; imlro_eng2 := ZERO ; imlro_eng2.status.implemented := TRUE ; imlro_eng2.status.working := TRUE ; imlro_eng2.cbus := mbd_readout.cbus ; imlro_eng2.mba := mbd_readout.mba ; imlro_eng2.ca := 11 ; imlro_eng2.regtotal := 16 ; FOR byte_num := first_byte TO third_byte DO BEGIN def_29520_reg ( FA := 0 + ORD(byte_num), REGISTER := ADDRESS(imlro_eng2.EM_L2_eng[byte_num]) ) ; def_29520_reg ( FA := 4 + ORD(byte_num), REGISTER := ADDRESS(imlro_eng2.HD_L2_eng[byte_num]) ) ; def_29520_reg ( FA := 8 + ORD(byte_num), REGISTER := ADDRESS(imlro_eng2.TOT_Et_eng[byte_num]) ) ; def_29520_reg ( FA := 12 + ORD(byte_num), REGISTER := ADDRESS(imlro_eng2.TOT_L2_eng[byte_num]) ) ; END ; def_29520_reg ( FA := 3, REGISTER := ADDRESS(imlro_eng2.spare1) ) ; def_29520_reg ( FA := 7, REGISTER := ADDRESS(imlro_eng2.spare2) ) ; def_29520_reg ( FA := 11, REGISTER := ADDRESS(imlro_eng2.spare3) ) ; def_29520_reg ( FA := 15, REGISTER := ADDRESS(imlro_eng2.spare4) ) ; inline_add_card ( ADDRESS( imlro_eng2 ) ) ; imlro_cnts := ZERO ; imlro_cnts.status.implemented := TRUE ; imlro_cnts.status.working := TRUE ; imlro_cnts.cbus := mbd_readout.cbus ; imlro_cnts.mba := mbd_readout.mba ; imlro_cnts.ca := 12 ; imlro_cnts.regtotal := 16 ; FOR rf_num := ref_0 TO ref_3 DO FOR byte_num := first_byte TO second_byte DO BEGIN def_29520_reg ( FA := 0 + 2*ORD(rf_num) + ORD(byte_num), REGISTER := ADDRESS(imlro_cnts.EM_Et_cnt[rf_num,byte_num]) ) ; def_29520_reg ( FA := 8 + 2*ORD(rf_num) + ORD(byte_num), REGISTER := ADDRESS(imlro_cnts.TOT_Et_cnt[rf_num,byte_num]) ) ; END ; inline_add_card ( ADDRESS( imlro_cnts ) ) ; imlro_ct_aux := ZERO ; imlro_ct_aux.status.implemented := TRUE ; imlro_ct_aux.status.working := TRUE ; imlro_ct_aux.cbus := mbd_readout.cbus ; imlro_ct_aux.mba := mbd_readout.mba ; imlro_ct_aux.ca := 9 ; imlro_ct_aux.regtotal := 16 ; FOR i := 0 TO 3 DO def_29520_reg ( FA := ORD(byte_num), REGISTER := ADDRESS(imlro_ct_aux.L0_fast_Z[i]) ) ; def_29520_reg ( FA := 4, REGISTER := ADDRESS(imlro_ct_aux.Miss_Pt) ) ; FOR i := 5 TO 15 DO def_29520_reg ( FA := i, REGISTER := ADDRESS(imlro_ct_aux.reserved[i]) ) ; inline_add_card ( ADDRESS( imlro_ct_aux ) ) ; jet_list_aoc := ZERO ; jet_list_aoc.status.implemented := TRUE ; jet_list_aoc.status.working := TRUE ; jet_list_aoc.cbus := mbd_scaler.cbus ; jet_list_aoc.mba := mbd_scaler.mba ; jet_list_aoc.ca := 14 ; jet_list_aoc.regtotal := 32 ; FOR rf_num := ref_0 TO ref_3 DO BEGIN FOR i := 0 TO 3 DO BEGIN def_standard_reg ( FA := 4 * ORD(rf_num) + i, REGISTER := ADDRESS(jet_list_aoc.maskreg[EMEt_cmp,rf_num,i]) ) ; def_standard_reg ( FA := 16 + 4 * ORD(rf_num) + i, REGISTER := ADDRESS(jet_list_aoc.maskreg[TOTEt_cmp,rf_num,i])) ; END ; END ; inline_add_card ( ADDRESS( jet_list_aoc ) ) ; LT_list_aoc := ZERO ; LT_list_aoc.status.implemented := TRUE ; LT_list_aoc.status.working := TRUE ; LT_list_aoc.cbus := mbd_scaler.cbus ; LT_list_aoc.mba := mbd_scaler.mba ; LT_list_aoc.ca := 11 ; LT_list_aoc.regtotal := 32 ; FOR rf_num := ref_0 TO ref_7 DO BEGIN FOR i := 0 TO 3 DO BEGIN def_standard_reg ( FA := 4 * ORD(rf_num) + i, REGISTER := ADDRESS(LT_list_aoc.maskreg[rf_num,i]) ) ; END ; END ; inline_add_card ( ADDRESS( LT_list_aoc ) ) ; { *** L1.5 CALORIMETER TRIGGER CARDS * *** *** *** *** *** *** *** *** *** } { ** 4-AUG-1994 add L1.5 Cal Trig ERPB-MTG Card } erpb_mtg := zero ; erpb_mtg.status.implemented := TRUE ; erpb_mtg.status.working := TRUE ; erpb_mtg.cbus := 3 ; erpb_mtg.mba := 89 ; erpb_mtg.ca := 35 ; erpb_mtg.regtotal := 39 ; def_mtg_set_prom_addr_lsb ( FA := 33, REGISTER := ADDRESS(erpb_mtg.start_lsb) ) ; def_mtg_set_prom_addr_msb ( FA := 34, REGISTER := ADDRESS(erpb_mtg.start_msb) ) ; def_mtg_set_prom_addr_lsb ( FA := 35, REGISTER := ADDRESS(erpb_mtg.stop_lsb) ) ; def_mtg_set_prom_addr_msb ( FA := 36, REGISTER := ADDRESS(erpb_mtg.stop_msb) ) ; def_mtg_control_status_reg ( FA := 37, REGISTER := ADDRESS(erpb_mtg.controlreg) ) ; def_mtg_read_prom_addr_lsb ( FA := 38, REGISTER := ADDRESS(erpb_mtg.count_lsb) ) ; def_mtg_read_prom_addr_msb ( FA := 39, REGISTER := ADDRESS(erpb_mtg.count_msb) ) ; { all PALs are MTGBit2, and MTGBit7, which have the standard bit assignment } FOR i := 0 TO 31 DO def_mtg_channel_reg ( FA := i, REGISTER := ADDRESS(erpb_mtg.channelreg[i]) ) ; {... Except for channel # 7 and 8 which are MTGBit8, i.e. direct in PALs } def_mtg_directin_reg ( FA := 6, REGISTER := ADDRESS(erpb_mtg.channelreg[6]) ) ; def_mtg_directin_reg ( FA := 7, REGISTER := ADDRESS(erpb_mtg.channelreg[7]) ) ; inline_add_card ( ADDRESS( erpb_mtg ) ) ; handle_trc_sys ( TAG := 'INI/HDB%', MESSAGE := ' Hardware Description Data Base now has ' + CONVERT(STRING,total_card) + ' cards (max array is ' + CONVERT(STRING,max_card) + ')' ) ; END ; { *************************************************************************** } { *************************************************************************** } [INLINE] PROCEDURE inline_add_card ( card_pointer : ^ANYTYPE ) ; VAR i : INTEGER ; BEGIN cardscanner[total_card]::BYTE_DATA := card_pointer::BYTE_DATA ; total_card := total_card + 1 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_standard_reg ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 255 ; register^.wmsk := 255 ; register^.class := [] ; register^.pipelen := 0 ; register^.xdepth := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_29520_reg ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 255 ; register^.wmsk := 0 ; register^.class := [ dobbuf, ronly ] ; register^.pipelen := 2 ; register^.xdepth := 1 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_presc_ctrl_reg ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 255 ; register^.wmsk := 255 ; register^.class := [ histdep ] ; register^.pipelen := 0 ; register^.xdepth := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_presc_data_reg ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 255 ; register^.wmsk := 255 ; register^.class := [ multir, multiw ] ; register^.pipelen := 0 ; register^.xdepth := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_fstd_enab_reg ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 255 ; register^.wmsk := 255 ; register^.class := [ histdep ] ; register^.pipelen := 0 ; register^.xdepth := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_dbsc_reset_reg ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 0 ; register^.wmsk := 5 ; register^.class := [ histdep, multidef ] ; register^.pipelen := 0 ; register^.xdepth := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_sbsc_ctrl_reg ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 255 ; register^.wmsk := 255 ; register^.class := [ histdep ] ; register^.pipelen := 0 ; register^.xdepth := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_sbsc_load_reg ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 0 ; register^.wmsk := 0 ; register^.pipelen := 0 ; register^.xdepth := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_sbsc_data_reg ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 255 ; register^.wmsk := 0 ; register^.class := [ multir ] ; register^.pipelen := 0 ; register^.xdepth := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_mtg_set_prom_addr_lsb ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 255 ; register^.wmsk := 255 ; register^.pipelen := 0 ; register^.xdepth := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_mtg_set_prom_addr_msb ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 3 ; register^.wmsk := 3 ; register^.pipelen := 0 ; register^.xdepth := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_mtg_control_status_reg ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 255 - 64 ; register^.wmsk := 255 - 64 ; register^.pipelen := 0 ; register^.xdepth := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_mtg_read_prom_addr_lsb ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 255 ; register^.wmsk := 0 ; register^.class := [ ronly ] ; register^.pipelen := 0 ; register^.xdepth := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_mtg_read_prom_addr_msb ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 7 ; register^.wmsk := 0 ; register^.class := [ ronly ] ; register^.pipelen := 0 ; register^.xdepth := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_mtg_channel_reg ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 63 ; register^.wmsk := 31 ; register^.class := [] ; register^.pipelen := 0 ; register^.xdepth := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_mtg_directin_reg ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 30 ; register^.wmsk := 30 ; register^.class := [] ; register^.pipelen := 0 ; register^.xdepth := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_mtg_write_ab_reg ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 1 + 2 ; register^.wmsk := 1 + 2 ; register^.class := [] ; register^.pipelen := 0 ; register^.xdepth := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_29525_reg ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 255 ; register^.wmsk := 0 ; register^.class := [ dobbuf, ronly ] ; register^.pipelen := 8 ; register^.xdepth := 1 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_ctfe_board_ctrl_reg ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 227 ; register^.wmsk := 227 ; register^.class := [ histdep ] ; register^.pipelen := 0 ; register^.xdepth := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_ctfe_load_simu_data_reg ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 0 ; register^.wmsk := 255 ; register^.class := [ histdep, multidef ] ; register^.pipelen := 0 ; register^.xdepth := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_ctfe_read_simu_data_reg ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 255 ; register^.wmsk := 0 ; register^.class := [ multidef ] ; register^.pipelen := 0 ; register^.xdepth := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_cat2_op_6bit_reg ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 63 ; register^.wmsk := 0 ; register^.class := [ ronly ] ; register^.pipelen := 0 ; register^.xdepth := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_cat2_thr_6bit_reg ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 63 ; register^.wmsk := 63 ; register^.class := [ ] ; register^.pipelen := 0 ; register^.xdepth := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_cat2_thr_3bit_reg ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 7 ; register^.wmsk := 7 ; register^.class := [ multidef ] ; register^.pipelen := 0 ; register^.xdepth := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_cat2_comp_out_reg ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 8 + 16 + 32 ; register^.wmsk := 0 ; register^.class := [ multidef, ronly ] ; register^.pipelen := 0 ; register^.xdepth := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_cat3_thr_1bit_reg ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 1 ; register^.wmsk := 1 ; register^.class := [ multidef ] ; register^.pipelen := 0 ; register^.xdepth := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE def_read_only_reg ( register :^cbus_register ; fa : byte ) ; BEGIN register^.fa := fa ; register^.status.implemented := TRUE ; register^.status.working := TRUE ; register^.content := 0 ; register^.rmsk := 255 ; register^.wmsk := 0 ; register^.class := [ ronly ] ; register^.pipelen := 0 ; register^.xdepth := 0 ; END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE find_card_pointer ( cbus, mba, ca : INTEGER ; VAR card :^ANYTYPE ; VAR status :[OPTIONAL] status_type ) ; VAR current_card : INTEGER ; BEGIN IF PRESENT(status) THEN status := ok ; card := NIL ; current_card := 0 ; WHILE ( cardscanner[current_card] <> NIL ) DO BEGIN IF ( ( cbus = cardscanner[current_card]^.cbus ) AND ( mba = cardscanner[current_card]^.mba ) AND ( ca = cardscanner[current_card]^.ca ) ) THEN BEGIN card::BYTE_DATA := cardscanner[current_card]::BYTE_DATA ; GOTO return_from_card_finder ; END ; current_card := current_card + 1 ; END ; IF PRESENT(status) THEN status := not_found ; return_from_card_finder : END ; { *************************************************************************** } { *************************************************************************** } PROCEDURE find_reg_pointer ( fa : INTEGER ; card :^ANYTYPE ; VAR register :^cbus_register ; VAR status :[OPTIONAL] status_type ) ; VAR generic_card :^card_header ; i : INTEGER ; BEGIN IF PRESENT(status) THEN status := ok ; generic_card::BYTE_DATA := card::BYTE_DATA ; register := NIL ; FOR i := 0 TO generic_card^.regtotal-1 DO IF ( fa = generic_card^.register[i].fa ) THEN BEGIN register := ADDRESS(generic_card^.register[i]) ; GOTO return_from_register_finder ; END ; IF PRESENT(status) THEN status := not_found ; return_from_register_finder : END ; { *************************************************************************** } { *************************************************************************** } END.