ADF-2 Pedestal DAC Programming ---------------------------------- Original Rev. 30-NOV-2004 Current Rev. 15-DEC-2004 The purpose of this file is to describe the programming of the Pedestal DAC's on the ADF-2 cards. Each of the 32 channels on the ADF-2 card has a Pedestal DAC associated with it to control the "zero energy response" of that channel. This document has the following sections: Numbering of the Channels on the ADF-2 card Component Used for the Pedestal DAC's Serial Data String of 4 Octal DAC Chips Mapping DAC Chip Outputs to ADF-2 Channels Electrical Signals Used to Control the Pedestal DAC's Registers in the BC PAL that Are Used to Program the Ped DAC's Typical Sequence of Programming Steps Typical Serial Data Strings Typical System Response Numbering of the Channels on the ADF-2 card ------------------------------------------- The first step is to review the standardized numbering of the 32 channels on the ADF-2 card. The ADF-2 card channels are numbered 0-EM, 0-HD, through 15-EM, 15-HD. As used in the Run 2B Cal Trig these channels have a standardized location in relative eta,phi space. This arrangement is: ADF-2 Relative |____________________ Ch (15:0) eta,phi | |- ------------- ----------- | | | 0 EM,HD 0,0 EM,HD | | | 1 0,1 | | | P1 2 0,2 Front | FPGA |_| 3 0,3 Panel | _________ | | / \ | 4 1,0 | F1 F0 |- 5 1,1 | | | 6 1,2 | |_| P0 7 1,3 |Ch12 Ch08 Ch04 Ch00 | | | 8 2,0 |Ch13 Ch09 Ch05 Ch01 |- 9 2,1 | | | 10 2,2 |Ch14 Ch10 Ch06 Ch02 | | 11 2,3 | | | P2 |Ch15 Ch11 Ch07 Ch03 |_| 12 3,0 |____________________| 13 3,1 | 14 3,2 15 3,3 Component Used for the Pedestal DAC's ------------------------------------- Linear Technology LTC2620 octal 12 bit serial DAC's are used for the pedestal control. The data sheet for this part is in the web component information section, i.e. run2b/l1cal/hardware/component_information/. The data sheet contains a detailed description of controlling this part via its serial interface. General points to note are: The first 8 bits of the 32 bit string that goes into each device are "don't care bits". On the ADF-2 card we need to use "32 bit data" with these DAC's because they are tied together in a serial string. The last 4 bits of the 32 bit string that goes into each device are "don't care bits". These are needed because the Linear Technology data format remains consistent up to their 16 bit DAC). Even though this device has a power down mode, we do not need to send a separate explicit "wake up" operation to the device (as we have needed to do in other equipment that used a different serial DAC). Serial Data String of 4 Octal DAC Chips --------------------------------------- Serial data from the Board Control PAL first enters Ped DAC U1451. From there it flows through U1452, U1453, U1454, and then returns to the BC PAL. Serial Data String Board Ped Ped Ped Ped Board Control ---> DAC ---> DAC ---> DAC ---> DAC ---> Control PAL U1451 U1452 U1453 U1454 PAL Mapping DAC Chip Outputs to ADF-2 Channels ------------------------------------------ Pedestal DAC Provides Reference Designator Pedestal Control and Output to ADF-2 Channel -------------------- ---------------- U1451 Output A Ch #0 EM U1451 Output B Ch #0 HD U1451 Output C Ch #1 EM U1451 Output D Ch #1 HD U1451 Output E Ch #2 EM U1451 Output F Ch #2 HD U1451 Output G Ch #3 EM U1451 Output H Ch #3 HD U1452 Output A Ch #4 EM U1452 Output B Ch #4 HD U1452 Output C Ch #5 EM U1452 Output D Ch #5 HD U1452 Output E Ch #6 EM U1452 Output F Ch #6 HD U1452 Output G Ch #7 EM U1452 Output H Ch #7 HD U1453 Output A Ch #8 EM U1453 Output B Ch #8 HD U1453 Output C Ch #9 EM U1453 Output D Ch #9 HD U1453 Output E Ch #10 EM U1453 Output F Ch #10 HD U1453 Output G Ch #11 EM U1453 Output H Ch #11 HD U1454 Output A Ch #12 EM U1454 Output B Ch #12 HD U1454 Output C Ch #13 EM U1454 Output D Ch #13 HD U1454 Output E Ch #14 EM U1454 Output F Ch #14 HD U1454 Output G Ch #15 EM U1454 Output H Ch #15 HD Electrical Signals Used to Control the Pedestal DAC's ----------------------------------------------------- There are 4 electrical signals which are involved with the programming of the Pedestal DAC's. These signals are described below. DAC_CHIP_SELECT_B The DAC_CHIP_SELECT_B signal comes from the BC PAL and goes to all 4 Ped DAC's in parallel. The name of this signal was based on the pin name that it connected to on the now not used Maxim DAC chips. With the Linear Technology DAC chips this signals connects to their CS/LD pin. In either case this signal has the same function. In the asserted (Low Voltage) state this signal allows serial data to be shifted into the DAC chips. On the transition from asserted (Low Voltage) state to non-asserted (High Voltage) state this signal causes the DAC chip to "ingest" the data bits that are currently residing in it and to take action based on those data bits. The DAC_CHIP_SELECT_B is controlled by a bit in a BC PAL control register and is "protected", i.e. blocked from being asserted, by another bit in a different BC PAL control register. See the next section for details. DAC_SERIAL_DATA_CLOCK The DAC_SERIAL_DATA_CLOCK signal comes from the BC PAL and goes to all 4 Ped DAC's in parallel. The transitions from the Low Voltage state to the High Voltage state cause DAC Serial Data to be shifted. The DAC_SERIAL_DATA_CLOCK signal is "protected" by a bit in a BC PAL control register. When this control register bit is set to Block loading of the PED DAC's then the DAC_SERIAL_DATA_CLOCK signal is forced to its Low Voltage state. When this control register bit is set to Enable loading of the PED DAC's then VME Write cycles that are addressed to the BC PAL's DAC Data Register will cause the DAC_SERIAL_DATA_CLOCK signal to pulse to its High Voltage state and then return back to its Low Voltage state. DATA_TO_FIRST_DAC_INPUT The DATA_TO_FIRST_DAC_INPUT signal comes from the BC PAL and goes to the Serial Data Input pin on Ped DAC chip U1451. The state of this signal is control by the value of the VME LSB Data Bit when VME Write cycles are done to the BC PAL's DAC Data Register. LAST_DAC_OUTPUT_DATA The LAST_DAC_OUTPUT_DATA signal carries the signal from the Serial Data Output pin on Ped DAC U1454 back to the BC PAL. The state of this signal can then be read by examining the state of a bit in a BC PAL status register. The intent of this connection is to allow for testing the Ped DAC serial data string. Registers in the BC PAL that Are Used to Program the Ped DAC's -------------------------------------------------------------- The Pedestal DAC's are controlled via registers in the Board Control PAL. Only the Board Control PAL registers that are directly involved with controlling the Pedestal DAC's will be described here. The full description of the Board Control PAL is in the file: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/general/ board_control_pal_description.txt Board Level Control Register #1 RW Register Reg Address = 0 Bit #5 of this control register is used to protect the data in the Pedestal DAC's. Writing a "0" to this control register bit protects the data in the Ped DAC's. Specifically writing a "0" holds the DAC_CHIP_SELECT_B signal in its non-asserted state and holds the DAC_SERIAL_DATA_CLOCK signal in its quiescent state. Writing a "1" to this control register bit Enables programming of the Ped DAC's. Specifically writing a "1" allows: the state of the DAC_CHIP_SELECT_B signal to be controlled by bit #6 in the Board Level Control Register #2 and enables the DAC_SERIAL_DATA_CLOCK signal to pulse high in response to VME Write cycles to the BC PAL's DAC Data Register. Board Level Control Register #2 RW Register Reg Address = 1 If programming of the Ped DAC's has been enable as explained in the description of the control register above, then bit #6 of this Control Register sets the state of the DAC_CHIP_SELECT_B signal. Writing a "0" to bit #6 of this control register sets the DAC_CHIP_SELECT_B to its active Low Voltage state and that enables serial data to be shifted into the Ped DAC's.. Subsequently writing a "1" to bit #6 of this control register sets the DAC_CHIP_SELECT_B back to its inactive High Voltage state and causes the DAC's to ingest and act upon the data that has been shifted into them. Board Level Status Register #2 R only Register Reg Address = 3 Reading the state of bit #4 in this register indicates the current state of the LAST_DAC_OUTPUT_DATA signal. DAC Data Register W only Register Reg Address = 4 If programming of the Ped DAC's has been enable as explained above, then when TCC does a VME write to this register in the BC PAL, the data on the LSB VME data line will be sent out on the DATA_TO_FIRST_DAC_INPUT signal. After DATA_TO_FIRST_DAC_INPUT has had time to settle, a positive pulse is automatically sent to the DAC's on the DAC_SERIAL_DATA_CLOCK line. If programming of the Ped DAC's has been not been enabled then writing to this register has no effect. Typical Sequence of Programming Steps ------------------------------------- 1. Enable Ped DAC Programming Do this by writing a "1" to bit location #5 in the Board Level Control Register #1 RW Register Reg Address = 0. 2. Set DAC_CHIP_SELECT_B active (Voltage Low). Do this by writing a "0" to bit location #6 in the Board Level Control Register #2 RW Register Reg Address = 1. 3. Shift out 4x 32 bits. Do this by 4x 32 VME Write Cycles to the DAC Data Register W only Register Reg Address = 4. The serial DAC data is placed in the LSBit of the 16 bit VME Word. 4. Set DAC_CHIP_SELECT_B inactive (Voltage High). Do this by writing a "1" to bit location #6 in the Board Level Control Register #2 RW Register Reg Address = 1. 5. Repeat steps 2:4 as necessary 6. Disable Ped DAC Programming. Do this by writing a "0" to bit location #5 in the Board Level Control Register #1 RW Register Reg Address = 0. Typical Serial Data Strings --------------------------- 32 bits of serial data is sent to each DAC in the following format. 8 don't care bits - this is sent first 4 Command Bits C3:C0 with C3 is sent first select DAC operation 4 Address Bits A3:A0 with A3 sent first select DAC channel 12 Data Bits D11(MSB):D0(LSB) with D11 sent first DAC control data 4 don't care bits - this is sent last Useful Commands: C3 C2 C1 C0 -- -- -- -- 0 0 1 1 Write to and Update and Power Up (if necessary) DAC "n" 1 1 1 1 No operation on any of the 8 DAC's in this chip DAC Channel Addressing: A3 A2 A1 A0 -- -- -- -- 0 0 0 0 Select DAC "A" 0 0 0 1 Select DAC "B" 0 0 1 0 Select DAC "C" 0 0 1 1 Select DAC "D" 0 1 0 0 Select DAC "E" 0 1 0 1 Select DAC "F" 0 1 1 0 Select DAC "G" 0 1 1 1 Select DAC "H" 1 1 1 1 Select all 8 DAC's in this chip for this operation DAC Data: The DAC Data is a value between 0 and 4095 decimal inclusive. This is converted to a DAC output voltage by the following equation: DAC_Data DAC_Output_Volts = -------- x 4.096 Volts 4096 4.096 Volts is the value of the Voltage Reference that is supplied to the DAC chips on the ADF-2 card. This gives the DAC chips an output of 1.0 mV per count. Typical System Response ----------------------- The intent of this section is to describe the typical range of values that will be used in the Pedestal DAC's and relate this to the resulting digital output from the ADC's when there is zero energy signal from the BLS system. For now this section will just cover the "Gain of 0.489" ADF-2 cards that are being assembled in the initial build of 10 cards. ADC Response The digital output from the AD9218 dual 10 bit ADC's is related to its differential analog input in the following way. Analog Input Pin Input Level Voltage Levels ADC Output Code --------------- -------------------- --------------- Smallest Input Ain = Vdd/3 - 0.5V $000 Ain_B = Vdd/3 + 0.5V Center of Range Ain = Vdd/3 $1ff - $200 Ain_B = Vdd/3 Largest Input Ain = Vdd/3 + 0.5V $3ff Ain_B = Vdd/3 - 0.5V The full data sheet for the AD9218 is in the web component information section, i.e. run2b/l1cal/hardware/component_information/. Notes about how the AD9218 is used on the ADF-2 card: Besides the ADC Clock signals (separate for each half for the AD9218) there are 3 additional digital control inputs to this chip. DFS/GAIN pin #4 This pin controls the ADC output data format and the analog input signal range. On the ADF-2 card this pin is left floating. Floating this pin results in "offset binary" output data format and a 2 Volt pp analog input range, i.e. an input range of 1.955 mV per ADC output count. User Select No. 1 (aka "S1") pin #8 This pin works with the S2 pin to control the Power Down mode and the Output Data Alignment from the ADC chip. On the ADF-2 card the S1 pin is controlled by bit #7 of the Board Level Control Register #1 RW Register Reg Address = 0 in the Board Control PAL. This bit and the resulting net on the ADF-2 card are called ADC_Enable. When ADC_Enable is set to "0" both channels of the ADC chip are powered down. When ADC_Enable is set to "1" both channels of the ADC chip are powered up and you have normal rationally aligned data coming out of the ADC, i.e. the special staggered data alignment feature of the ADC is not turn on. The Board Control PAL was designed so that its ADC_ENABLE bit will wake up at power up in the "0" state. When TCC sets this bit to "1" the ADF-2 card will begin drawing about 3.8 Amps from the 3.3 Volt backplane supply. This is a total load in the crate of about 77 Amps on the 3.3 Volt supply. When "initializing" the crate we probably want to set the ADC_ENABLE bit to "1", one ADF-2 card at a time, with a delay of 0.2 seconds between cards. User Select No. 2 (aka "S2") pin #9 This pin works with the S1 pin to control the Power Down mode and the Output Data Alignment of the ADC chip. On the ADF-2 card this pin is connected to Ground. Because this pin is hardwired to Ground we do not have access to a Power Down mode that would turn off only half of the ADC chip or to a special data alignment mode that would delay the B channel data by an extra 1/2 clock cycle. ADC Output Response wrt the BLS Input Signal The first 10 ADF-2 cards were built with 1.02 K Ohm input resistors and 499 Ohm feedback resistors. This gives a gain of 0.489 between the BLS signal input pins and the ADC analog input pins. This results in an "input sensitivity" at the ADF-2 BLS Input pins of about 3.996 mV differential per ADC output count. This is the change in differential input Voltage that is necessary to move the ADC from the center of a given output code to the center of an adjacent output code. The following 3 tables show the BLS input Voltage (differential amplitude of the "bump") that is required to give: Smallest, Mid Scale, Full Scale, and ZER output from the ADC with the Pedestal DAC set for 3 different Zero Energy Responses (ZER). Ped DAC Set for ADC Output Equal to $000 with Zero BLS Input BLS Input Signal Volts Differential ADC Output Code ------------------ -------------------- 0.000 V $000 Smallest & ZER 2.042 V $1ff Mid Scale 4.088 V $3ff Full Scale Ped DAC Set for ADC Output Equal to $008 with Zero BLS Input BLS Input Signal Volts Differential ADC Output Code ------------------ -------------------- -0.032 V $000 Smallest 0.000 V $008 ZER 2.010 V $1ff Mid Scale 4.056 V $3ff Full Scale Ped DAC Set for ADC Output Equal to $1ff with Zero BLS Input BLS Input Signal Volts Differential ADC Output Code ------------------ --------------------- -2.042 V $000 Smallest 0.000 V $1ff Mid Scale & ZER +2.046 V $3ff Full Scale For the above tables I picked the ADC output code of $1ff as representative of mid scale. There are an even number of ADC output codes so true mid scale is straddled by codes $1ff - $200. ADC Output Response wrt the Pedestal DAC Value As with previous systems the Pedestal DAC's work "up side down". Operating the Ped DAC this way simplifies the analog circuit design and results in the same overall system functionality. "Up side down" means that with a code of $000 loaded into the 12 bit Ped DAC the ADC output will be near mid scale, e.g. ADC Output code $1ff. With full scale ($fff) loaded into the Ped DAC the ADC output will be near zero. In detail the circuit is designed so that: With the Ped DAC loaded with its zero code, $000, and no additional offsets in the circuit components, then the ADC would be right at mid scale, i.e. straddling ADC output codes $1ff - $200. With the Ped DAC loaded with its full scale code, $fff, the ADC output is guaranteed to be slightly below zero. With no additional offsets in the circuit components the Ped DAC can drive the ADC output 57 counts below zero, i.e. about 10% below zero. The intent of this is to guarantee that even when various circuit tolerances are taken into consideration, that the Ped DAC output stage is still comfortably within its range of linear operation when it holds the ADC output at a ZER of about $008 for normal Physics operation. The following table shows the expected ADC output for various values loaded into the Pedestal DAC with zero signal present at the BLS input. Value Loaded in Resulting ADC Output Code the Ped DAC with Zero BLS Input Signal --------------- -------------------------------- $000 = 0 $1ff - $200 ADC Mid Scale $734 = 1844 $0ff - $100 ADC 1/4 Scale $e67 = 3687 $000 center of ADC zero code >$e68 = >3688 $000 ADC is below zero It typically requires 7.21 DAC counts per ADC count.