------------------------------------------------------------------------------------- ADF-2 Board Control PAL ---------------------------- Original Rev. 14-APR-2004 Most Recent Rev. 16-Feb-2005 This file is a description of the Board Control PAL that is part on each ADF-2 circuit board. The structure of this file is the following: A description of each function of the Board Control PAL A description of the signals in the Board Control PAL A description of the registers in the Board Control PAL While reading this please refer to the following pdf and ps diagrams on the web: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/drawings/ adf_2_pal_top_level_schematic.pdf & ps board_control_pal_board_level_control.pdf & ps board_control_pal_fpga_configuration.pdf & ps board_control_pal_vme_interface.pdf & ps clock_bx_x8_generation.pdf & ps adf_2_pal_vme_invalid_cycle_timing_diagrams.pdf & ps adf_2_pal_vme_read_timing_diagrams.pdf & ps adf_2_pal_vme_write_timing_diagrams.pdf & ps List of Functions Performed by the Board Control PAL ---------------------------------------------------- All functions performed by the Board Control PAL are divided into 6 different functions. These are Board Level Control, VME Interface, FPGA Configuration, BX X8 Clock Generation, On Card Bus Output, and PAL ACCESS signals. Board Level Control ------------------- The Board Level Control function comprises of 2 read-write control registers, 2 read-only status registers,one write only data register, logic to drive DAC programming signals, and logic to drive a register controlled front panel LED. The control registers provide bits for the following: -FPGA configure enabling -Pedestal DAC program enabling -Enable bit for PAL ACCESS signal outputs -Pedestal DAC chip select signal -ADC enabling -Two communication bits to the SCLD -A 4-bit vector of status bits to all ADF cards in the same crate -Deskew and DC balance control for the channel link chips -Control for a front panel LED The status registers provide bits for the following: -A 4-bit vector of status from each FPGA -A 4-bit vector of status that can be driven by every card in a crate -DAC data from the last DAC in the daisy chain for confirmation of DAC programming The write only data register is for Pedestal DAC data programming. Initial Test ------------ The two read-write control registers in the Board Level Control can be used after power up to check the VME Bus communication with the ADF-2 card. Enable Bit Error Protection --------------------------- An enable bit is located in a separate register from the bits associated with the function it enables. This protects from a erroneous write to a register from both enabling the function and performing it in the same I/O cycle, otherwise a multi-bit error could erase the FPGA's or shift bits in the DAC's and change their set value. FPGA Configuration ----------------------------------- Without the ENABLE_FPGA_CONFIGURATION bit enable being set the Board Control PAL can not generate asserted CNFG_PROB_B signals to the FPGA's nor can it generate CNFG_CCLK pulses to the FPGA's. DAC Programming --------------- Writing data into the write only DAC data register will cause the least significant bit on the On Card Bus to be put on the DATA_TO_FIRST_DAC_INPUT line and the DAC_SERIAL_DATA_CLOCK to pulse. Data is captured on the rising edge of the DAC_SERIAL_DATA_CLOCK. The ENABLE_LOADING_DACS bit must be asserted for the DAC_CHIP_SELECT_B to be asserted or the DAC_SERIAL_DATA_CLOCK to pulse. DAC Data Confirmation --------------------- Another bit in a status register is the Data Out signal from the last pedestal DAC in the serial chain. By reading this information back, the looping of data through the serial chain of 4 pedestal DAC's can be verified. SCLD Communication ------------------- The 2 bits for SCLD communication will be used to control the 2 CRATE_TO_SCLD signals. After these signals leave the PAL they go through LVDS drivers before being send to the SCLD. These signals exist in all ADF cards but are only meaningful in the Maestro ADF. CRATE STATUS ------------ There are signals to both drive and read the Crate Status bus. The backplane Drive Crate Status signals are open collector lines that are driven by INVERTING drivers. TCC writes a "1" to drive the line to it low Voltage state. Any ADF-2 card can drive a Crate Status line to its low Voltage state. One of the status registers in the Board Level Control contains 4 bits that are the Backplane Crate Status signals. The Crate Status signals are Low Voltage active on the open collector backplane bus but these signals are inverted back to "positive logic" before they appear in the TCC readable register. FPGA STATUS ----------- A status register in the Board Level Control contains 4 status bits from each FPGA. VME Interface ------------- The VME Interface function of the Board Control PAL translates address, control and handshaking signals between the VME bus and the "On Card Bus". The output from the VME Interface Section is the "On Card Bus" that allows VME communication with registers and memories in the FPGA's and PAL. This same On Card Bus is used for VME communication with the registers in the Board Control PAL itself. All net names involved with the On Card Bus begin with OCB. A full description of the OCB is in a separate document on the web at: www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/general/ on_card_bus_description.txt The VME interface also contains the state machine for the PAL and the internal control lines WRITE_TO_PAL, READ_FROM_PAL and register select addressing lines. FPGA Configuration ------------------ The FPGA Configuration function of the Board Control PAL translates commands from the TCC to handshaking and clock transitions needed to configure the FPGA with the program that is placed on the On Card Bus. There are three registers in the FPGA Configuration Section of the Board Control PAL. A read-write control register, a read-only status register and a write-only configure data register. FPGA Configuration Control Register ----------------------------------- The signals CNFG_RDWR_B, CNFG_PROG_B(0:1), and CNFG_CS_B(0:1) are all the electrical outputs from bits in a TCC controlled read/write register in the Configuration Section of the Board Control PAL. If the ENABLE_FPGA_CONFIGURATION bit has not been set then the CNFG_PROG_B(0:1) lines from the Board Control PAL will never be in their asserted state no matter what data is written into the Configuration Section register bit CNF_POROG_B_REQ(0:1). After configuration the CNF_CS_B(0:1) signals can be re-used as auxiliary control lines from this TCC controlled register to the FPGA's. This Configuration Section read/write register can also be used after power up to verify correct VME communication with the ADF-2 card. FPGA Configuration Status Register ---------------------------------- The signals CNFG_INIT_B(0:1), CNFG_BUSY(0:1), and CNF_DONE(0:1) are all electrical inputs to a read only register in the Configuration Section of the Board Control PAL. After configuration the CNFG_INIT_B(0:1) and CNFG_BUSY(0:1) signals can be re-used as auxiliary status lines from the FPGA to this TCC readable register in the Board Control PAL. FPGA Configuration DATA Register -------------------------------- The configuration clock, CNFG_CCLK, is generated not by a register but by logic in the Board Control PAL. This logic makes a 132 nsec high FPGA configuration CCLK pulse when the Board Level Control register bit ENABLE_FPGA_ CONFIGURATION has been asserted and then configuration data is written to the "FPGA Configuration Data Register" in the Board Control PAL. PAL ACCESS ---------- The PAL ACCESS bus is a collection of signals from inside the PAL that are output to pins and routed to a connector on the circuit board for debugging purposes or additional connections to the PAL. The PAL ACCESS section assigns the signal connections and enables the output drivers for the bus. Production versions of the firmware are to have the PAL ACCESS outputs disabled. Output to On Card Bus --------------------- This section collects signals from the registers in the Board Level Control and the FPGA Configuration sections and multiplexes them to the On Card Bus bi-directional I/O blocks. The signals are selected based on which register in the PAL has been addressed. The I/O block outputs are enabled based on if the current VME I/O cycle is a read cycle targeted for the PAL on this card. BX X8 Clock Generation ---------------------- This section of the PAL is operates separately from the other 5 sections. Available PAL I/O blocks and macrocells are used to help control a phase locked loop that synchronizes the PAL_BX_CLOCK and the BX_X8_CLOCK with the beam crossing clock. List of Input, Output and Internal Control Signals in the Board Control PAL --------------------------------------------------------------------------- Signal Into, Out from or Internal Signal Name wrt PAL Details --------------- -------- -------------------- --- Global --- PAL_BX_CLOCK In 7.59 MHz Clk common to PAL and FPGA's. --- Board Level Control Section --- DRV_CRATE_TO_SCLD(0:1) Out These are two outputs from the PAL that control two Crate to SCLD signals from the Maestro ADF-2 in each crate. These signals go through LVDS drivers before being sent to the SCLD. These signals are only meaningful in the Maestro ADF-2 card in each crate. In the other 19 ADF-2 cards these Crate to SCLD signals do not go anywhere. The SCLD receives a total of 8 of these signals. They are used to control when the SCLD asserts Save Monitor Data. Initially these signals will come from a TCC controlled read/write register in the PAL. SER_DESKEW_B Out This signal goes to all Channel Link chips. When this signal is LOW the Channel Link performs a deskew operation. This is a TCC controlled read/write register bit. SER_DC_BALANCE Out This signal goes to all Channel Link chips. When this signal is HIGH the Channel Link operates in DC Balance mode. This is a TCC controlled read/write register bit. ADC_ENABLE Out This signal goes to all 16 ADC chips. When it is LOW the ADC's are powered down. When it is HIGH the ADC's operate normally. This is a TCC controlled read/write register bit. FPGA_0_STATUS(0:3) In These are Status Line(s) from the FPGA's FPGA_1_STATUS(0:3) that go to the Board Control PAL. In the Board Control PAL these signals go to a TCC readable register and may go to logic for other functions. A possible "other function" is requesting an immediate Capture Monitor Data. If necessary we could turn some of these lines around and use them to send a signal from the Board Control PAL to the FPGA's. DRV_CRATE_STATUS(0:3) Out These are output signals from the Board Control PAL that go to INVERTING drivers for the open collector backplane Crate Status lines. These signals come from a TCC controlled register in the Board Control PAL. In the future they may also come from some Board Control PAL logic to implement a function like requesting crate or ADF system wide immediate Capture Monitor Data. This signal is asserted HIGH. CRATE_STATUS_B(0:3) In These are the Crate Status lines from the backplane to the Board Control PAL. In the Board Control PAL these signals go to a TCC readable register and may go to logic for other functions. A possible "other function" is requesting immediate Capture Monitor Data. On the backplane these signals are Low Voltage Active. These backplane signals are inverted before they are taken to any registers or logic in the Board Control PAL. CRATE_STATUS(0:3) INT These signals are the inverse of CRATE_STATUS_B. These signals are asserted HIGH. DAC_SERIAL_DATA_CLOCK Out This signal from the Board Control PAL is the serial data clock for the DAC serial data. It is generated by logic as described above. This signal goes to all 4 DAC's in the chain. If the ENABLE_LOADING_DACS bit in the Board Level Control register has not been set then DAC_SERIAL_DATA_CLOCK is not generated. The clock is active on its rising edge. DAC_CHIP_SELECT_B_REQ Int This signal is a bit in Board Level Control Register 2. TCC asserts/sets HIGH this bit to request DAC_CHIP_SELECT_B to be asserted. If the signal ENABLE_LOADING_DACS and DAC_CHIP_SELECT_B_REQ are asserted then DAC_CHIP_SELECT_B is asserted. DAC_CHIP_SELECT_B Out This signal from the Board Control PAL is the LOW active chip select that must be asserted to load the DAC's. This signal goes to all DAC's in the chain. If the ENABLE_LOADING_DACS bit in the Board Level Control register has not been set then DAC_CHIP_SELECT_B is not put in its asserted state no matter what value is written in DAC_CHIP_SELECT_B_REQ. DATA_TO_FIRST_DAC_INPUT Out This signal from the Board Control PAL is the serial data to the first DAC in the chain. The least significant bit of the OCB_DATA and is put on this signal when the target address of a VME write is the Board Level Dac Register in the Pal. LAST_DAC_OUTPUT_DATA In This input signal to the Board Control PAL comes from the data out pin on the last DAC in the chain of 4 and goes to a bit in a TCC readable register. Reading this bit allows TCC to verify the serial data path through the 4 pedestal DAC's. CNTRL_PAL_LED_1 Out This signal controls an LED on the ADF card. It is a TCC controlled register bit in the Board Level Control Register 1. The signal is asserted when HIGH and turns the LED on. DRV_PAL_LED(1) Out This is an output signals that controls a front panel LED. It is asserted when LOW. DRV_PAL_LED(1) is controlled by TCC through the CNTRL_PAL_LED_1 register bit. It is the inverse of CNTRL_PAL_LED_1 so when CNTRL_PAL_LED_1 is asserted HIGH the LED is on. ENABLE_LOADING_DACS Out Without this enable being set the Board Control PAL can not generate DAC_SERIAL_DATA_CLOCK pulses to the Pedestal DAC's. If this enable bit is set then with each TCC write to the Board Level Control Section Program DAC register a pulse is generated on the DAC_SERIAL_DATA_CLOCK line to the DAC's. Also, if the ENABLE_LOADING_DACS is not set then the DAC_CHIP_SELECT_B line from the Board Control PAL is never put into its asserted state. ENABLE_FPGA_ Out Without this enable being set the Board Control PAL CONFIGURATION can not generate asserted CNFG_PROB_B signals to the FPGA's nor can it generate CNFG_CCLK pulses to the FPGA's. ENABLE_PAL_ACCESS_ Out This signal controls the output buffers for the PAL OUTPUT ACCESS signals. When this signal is asserted the PAL ACCESS output buffers are enabled. --- VME Interface Section --- See http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/general/ /on_card_bus_description.txt and /adf_2_vme_addressing.txt OCB_ADRS(1:23) In These 23 signals are the latched copy of the A24 VME Address lines. LTCHD_AM(0:5) In These 6 signals are the latched copy of the VME Address Modifier lines. LTCHD_IACK_B In This signal is the latched copy of the VME IACK* line. LTCHD_WRITE_B In This signal is the latched copy of the VME WRITE* line. VME_LTCH_CLK Out This is a signal that is generated by the VME section of the Board Control PAL. A positive edge on this signals causes the VME Latch to update. This signal is generated in response to VME line DS1* going LOW. VME_GEO_B(0:4) In These are the 5 Geographic Address signals from the backplane. VME_SYSRESET_B In This is the VME SYSRESET* line. RCVD_DS1 In This is the received and inverted copy of the VME DS1* line. DRV_DTACK Out This is a signal that is generated by the VME section of the Board Control PAL. This signal goes to an inverting driver and becomes the VME_DTACK_B line. DATA_BUF_DIR Out This is a signal that is generated by the VME section of the Board Control PAL. This signal controls the direction of the VME Data Buffer. HIGH -> on card data goes to the VME Bus this is a VME Read LOW -> VME Bus data goes to the on card bus this is a VME Write DATA_BUF_ENB_B Out This is a signal that is generated by the VME section of the Board Control PAL. This signal is the Enable_B to the VME Data Buffer. HIGH -> the buses are isolated. LOW -> data flows through the VME Data Buffer in the direction controlled by the DATA_BUF_DIR signal. OCB_CHIP_SEL_B(0:1) Out This is a signal that is generated by the OCB_CHIP_SEL_B(2) Int VME section of the Board Control PAL. This signal selects one of the FPGAs or PAL for an I/O cycle. This signal is a "decode" of the high order VME Address lines that are not passed to the FPGA's. This is a LOW active signal going to the FPGA's. There are 3 of these signals. 0 and 1 are select lines for the FPGA's and 2 is the internal select signal for the PAL. OCB_WRITE_STRB_B Out This is a signal that is generated by the VME section of the Board Control PAL. This signal is the LOW active Write Strobe that is generated by the Board Control PAL and goes to all FPGA's on the ADF-2 card. OCB_DIRECTION Out This is a signal that is generated by the VME section of the Board Control PAL. This signal is LOW when the VME Bus is Writing to the ADF-2. This signal is HIGH when VME is Reading from the ADF-2. This signal goes to all FPGA's. SYSRESET_DEBOUNCED Out This signal is a inverted debounced copy of the VME_SYSRESET_B signal. If VME_SYSRESET_B is asserted low for three clock cycles then SYSRESET_DEBOUNCED is asserted high. DRV_PAL_LED(0) Out This is an output signals that controls a front panel LED. It is asserted when LOW. DRV_PAL_LED(0) is a time stretched copy of VALID_CYCLE that drives PAL_LED_0. This signal is asserted LOW so that when VALID_CYCLE is asserted the LED is on. VALID_CYCLE is generated internally and indicates that the current VME I/O cycle is valid for this card. This implies that LTCHD_IACK_B is not asserted, LTCHD_AM corresponds to either Standard Non-Privileged Data Access or Standard Supervisory Data Access, and that the VME_GEO_B(0:4) signals match the OCB_ADRS(18:23). WRITE_TO_PAL Internal This is an internal control signal that indicates that data is to be written to the PAL during the current I/O cycle. READ_FROM_PAL Internal This is an internal control signal that indicates that data is to be read from the PAL during the current I/O cycle. REGISTER_SEL lines Internal These are control lines that indicate when a register has been addressed inside the PAL. These lines are: BOARD_CONTROL_REGISTER_1_SEL BOARD_CONTROL_REGISTER_2_SEL BOARD_STATUS_REGISTER_1_SEL BOARD_STATUS_REGISTER_2_SEL CNFG_CONTROL_REGISTER_SEL CNFG_STATUS_REGISTER_SEL --- FPGA Configuration Section --- CNFG_CCLK Out This signal is the Configuration Clock. It is generated by logic in the Board Control PAL's FPGA Configuration Section when TCC does VME Writes to the Board Control PAL's Configuration Data Register. This signal goes to all FPGA's on the ADF-2. This signal is not generated if the ENABLE_FPGA_CONFIGURATION bit is not set in the Board Level Control Register 1. This signal is active on its rising edge. CNFG_RDWR_B Out This signal is the configuration RDWR_B (read write bar) signal to the FPGA's. It goes to all FPGA's on the ADF-2 card. It comes from a TCC controlled register. This signal is LOW to write Configuration Data to the FPGA's. CNFG_PROG_B(0:1) Out These signals are the configuration PROG_B signals to the FPGA's. There is a separate CNFG_PROG_B signal to each FPGA. These signals come from a TCC controlled register. The state of these signals needs to be carefully protected. A LOW on one of these signals asynchronously starts the FPGA configuration process. These signals can not go to their asserted state if the ENABLE_FPGA_CONFIGURATION bit is not set in the Board Level Control Register 1. CNFG_CS_B(0:1) Out These signals are the configuration Chip Select signals. They are used to control which subset of the FPGA's receive the configuration data. These signals are LOW active. These signals come from a TCC controlled register. There is a separate CNFG_CS_B signal to each FPGA. CNFG_INIT_B(0:1) In These signals are the configuration INIT_B signal from each FPGA. There is a separate CNFG_INIT_B signal from each FPGA. During configuration, when the CNFG_INIT_B signal is LOW, it indicates that the FPGA's configuration memory is being cleared. In the Board Control PAL these signals are electrical inputs to a read only register. After configuration this pin on the FPGA becomes a user I/O pin which we can use to carry auxiliary status information from the FPGA to this read only register in the Board Control PAL. CNFG_BUSY(0:1) In These signals are the configuration BUSY signal from each FPGA. There is a separate CNFG_BUSY signal from each FPGA. During configuration, when CNFG_BUSY is HIGH, the FPGA can not accept another byte of configuration data. In the Board Control PAL these signals are electrical inputs to a read only register. After configuration this pin on the FPGA becomes a user I/O pin which we can use to carry auxiliary status information from the FPGA to this read only register in the Board Control PAL. CNFG_DONE(0:1) In These signals are the configuration DONE signal from each FPGA. There is a separate CNFG_DONE signal from each FPGA. The FPGA DONE pins remain dedicated to this function even after the completion of configuration. After a successful configuration CNFG_DONE goes HIGH. In the Board Control PAL these signals are electrical inputs to a read only register. The following is a list of configuration signal pins that are usable as I/O pins on the FPGAs after configuration and could be used as additional control or status lines between the PAL and the FPGAs. For the signals CNFG_CS_B, CNFG_INIT_B, and CNFG_CS_B there are individual connections between each FPGA and the PAL. For CNFG_RDWR_B there is a single wire that connects both FPGAs and the PAL. Configure Signals Reusable As I/O After Configuration -------------------------- Signal Direction (With respect to PAL) -------------- --------- CNFG_CS_B(0) Out CNFG_INIT_B(0) In CNFG_BUSY(0) In CNFG_CS_B(1) Out CNFG_INIT_B(1) In CNFG_BUSY(1) In *CNFG_RDWR_B Out *Connects to both FPGA's --- PAL ACCESS Signals --- PAL_ACCESS(0:16) In/Out These signals are spare and can have existing signals routed to them or be used for new signals. They may be used for debugging the functionality of the PAL, monitoring the On Card Bus or used for extra external connections to other devices on the ADF card. The output buffers for these signals are controlled by the ENABLE_PAL_ACCESS_OUTPUT register bit. ENABLE_PAL_ACCESS Internal This signal is the enable bit for the output buffers _OUTPUT of the PAL_ACCESS bus. This signal is asserted when HIGH and enables the PAL_ACCESS outputs. It is deasserted at power up and must be asserted by TCC before PAL ACCESS operation. The PAL ACCESS signals are deasserted by default in order to prevent noise on the outputs of the PAL_ACCESS bus from the PLL signals. The PAL_ACCESS signals can affect the PLL signals because the PAL_ACCESS signals share a functional block with the PLL signals. --- OCB Output Signals --- OCB_DATA(0:7) In/Out These signals are the lower 8 bits of the on card data bus. Only bits (0:7) are connect to the PAL since data transfers to the PAL are only 8 bits wide. --- Phase Locked Loop Signals --- See http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/Pictures/ clock_bx_x8_generation.pdf clock_generation_timing.pdf RCVD_BX_CLOCK In This is the Reference clock signal from the backplane. This is a Global CLOCK Net in the PAL. PAL_BX_X8_CLOCK In This is the BX_X8_CLOCK to the PLL Pre-Scaler. This is a Global Clock Net in the PAL. LOOP_FILTER_REF Out This is the Reference voltage to Loop Filter 1/2 Vdd. PHASE_DET_OUT Out This is the Phase Detector Output to the Loop Filter. PAL_FIRST_X8_EDGE Out This the the FIRST_X8_EDGE signal to the 2 FPGAs. CNT_BIT_VAL_4 Out This is the 7.59 MHz Pre-Scaler output. It is looped back to PAL_BX_CLOCK. FIRST_X8_EDGE Out This signal identifies which PAL_BX_X8_CLOCK edge corresponds with the rising edge jf backplane BX_CLOCK. Register Summary ----------------- The following table lists the registers in the Board Control PAL and their addresses. The address bits are bits 1:4 of OCB_ADRS(1:23). See http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/hardware/adf_2/general/ adf_2_vme_addressing.txt ------------------------------------------------------------------------------------- |Reg | Addr Bit| Register |Address| 4 3 2 1 | Name ------------------------------------------------------------------------------------- | 0 | 0 0 0 0 | Board Level Control Register #1: Channel Link & Enables | 1 | 0 0 0 1 | Board Level Control Register #2: Drive Crate Status & | | | DAC Programming | 2 | 0 0 1 0 | Board Level Status Register #1: FPGA Status | 3 | 0 0 1 1 | Board Level Status Register #2: Crate_Status & DAC Output | 4 | 0 1 0 0 | Board Level DAC Data Register | 5 | 0 1 0 1 | Configuration Control Register | 6 | 0 1 1 0 | Configuration Data Register | 7 | 0 1 1 1 | Configuration Status Register ------------------------------------------------------------------------------------- | | 1 x x x | Unused Addresses ------------------------------------------------------------------------------------- Board Level Control Section Registers ------------------------------------- Board Level Control Register #1 RW Register Reg Address = 0 ------------------------------- Bit # Function ----- --------------------------------- 0 controls SER_DESKEW_B of all 3x Channel Link Transmitters 0: perform deskew calibration (in DC balance mode only) 1: normal operation 1 controls SER_DC_BALANCE of all 3x Channel Link Transmitters 0: standard mode 1: DC balance mode 2 unallocated 3 controls CNTRL_PAL_LED_1 0: front panel LED off 1: front panel LED on 4 controls ENABLE_FPGA_CONFIGURATION * 0: normal operation 1: enable FPGA configuration 5 controls ENABLE_LOADING_DACS * 0: normal operation 1: enable serial DAC programming 6 controls ENABLE_PAL_ACCESS_OUTPUT * 0: normal operation 1: enable spare PAL_ACCESS(0:16) signals as outputs 7 controls ADC_ENABLE of all 16x ADCs 0: power down ADCs 1: normal operation * These signals are not external to the Board Control PAL Board Level Control Register #2 RW Register Reg Address = 1 ------------------------------- Bit # Function ----- --------------------------------- 0 controls DRV_CRATE_STATUS(0) 1 controls DRV_CRATE_STATUS(1) 2 controls DRV_CRATE_STATUS(2) 3 controls DRV_CRATE_STATUS(3) 0: Set CRATE_STATUS(N) Low (i.e. no contribution) 1: Set CRATE_STATUS(N) High (i.e. force active on backplane) 4 controls DRV_CRATE_TO_SCLD(0) 5 controls DRV_CRATE_TO_SCLD(1) 0: Set CRATE_TO_SCLD(N) Low 1: Set CRATE_TO_SCLD(N) High 6 controls DAC_CHIP_SELECT_B_REQ 0: Request that DAC_CHIP_SELECT_B be set low (i.e. active) for programming the Serial DACs Note that the ENABLE_LOADING_DACS bit in Board Level Control Register #1 must be set to 1 before the Board Control PAL will actually negate the DAC_CHIP_SELECT_B signal going to the DACs 1: normal operation 7 unallocated Board Level Status Register #1 R only Register Reg Address = 2 ------------------------------ Bit # Function ----- ------------------------------ 0 reads FPGA_0_STATUS(0) 1 reads FPGA_0_STATUS(1) 2 reads FPGA_0_STATUS(2) 3 reads FPGA_0_STATUS(3) current state of FPGA_STATUS(N) from FPGA #0 4 reads FPGA_1_STATUS(0) 5 reads FPGA_1_STATUS(1) 6 reads FPGA_1_STATUS(2) 7 reads FPGA_1_STATUS(3) current state of FPGA_STATUS(N) from FPGA #1 Board Level Status Register #2 R only Register Reg Address = 3 ------------------------------ Bit # Function ----- ------------------------------ 0 reads CRATE_STATUS(0) 1 reads CRATE_STATUS(1) 2 reads CRATE_STATUS(2) 3 reads CRATE_STATUS(3) current state of CRATE_STATUS(N) on the backplane 4 reads LAST_DAC_OUTPUT_DATA current state of the serial output bit off of the last of the 4 DACs in the programming chain. 5 unallocated 6 unallocated 7 unallocated Note: The CRATE_STATUS_B(0:3) lines from the Backplane are inverted in the I/O Block that receives them before they appear in Board Level Status Register #2. Thus, writing a "1" to a DRV_CRATE_STATUS(n) bit in the Board Level Control Register #2 will result in reading a "1" in the appropriate CRATE_STATUS(n) bit in the Board Level Status Register #2. Board Level DAC Data Register W only Register Reg Address = 4 ----------------------------- The purpose of this register is to provide a legal VME target at which to write the Configuration Data. The register does not really exist as a register in the Board Control PAL hardware. Logic does exist in the Board Control PAL so that when TCC writes to this registers VME address the Board Control PAL will put OCB_DATA(0) on DATA_TO_FIRST_DAC_INPUT and send out a pulse on the DAC Serial Data Clock (assuming that the ENABLE_LOADING_DACS bit has been set). FPGA Configuration Section Registers ------------------------------------ Configuration Control Register RW Register Reg Address = 5 ------------------------------ Bit # Function ----- --------------------------------- 0 controls CNFG_PROG_B_REQ(0) 1 controls CNFG_PROG_B_REQ(1) 0: Request that CNFG_PROG_B(N) be set low (i.e. active) for reconfiguring FPGA#N Note that the ENABLE_FPGA_CONFIGURATION bit in Board Level Control Register #1 must be set to 1 before the Board Control PAL will actually negate the CNFG_PROG_B(N) signal going to FPGA#N 1: Normal operation 2 controls CNFG_CS_B(0) 3 controls CNFG_CS_B(1) 0: Set low (i.e. active) to select that FPGA#N be ingesting configuration data. 1: Normal operation 4 controls CNFG_RDWR_B 0: Set low (i.e. active) to specify that the configuration data is being written to the FPGA(s) currently targeted 1: Normal operation 5 unallocated 6 unallocated 7 unallocated Configuration Data Register W only Register Reg Address = 6 --------------------------- The purpose of this register is to provide a legal VME target at which to write the FPGA Configuration Data. The register does not really exist as a register in the Board Control PAL hardware. Logic does exist in the Board Control PAL so that when TCC writes to this registers VME address the Board Control PAL sends out a pulse on the FPGA Configuration Clock line (assuming that the ENABLE_FPGA_CONFIGURATION bit has been set). Configuration Status Register R only Register Reg Address = 7 ----------------------------- Bit # Function ----- ------------------------------ 0 reads CNFG_INIT_B(0) 1 reads CNFG_INIT_B(1) during configuration 0: FPGA#N configuration is being cleared 1: FPGA#N ready to receive new configuration after configuration these signals may be re-used as I/O pin (this option is not currently used) 2 reads CNFG_BUSY(0) 3 reads CNFG_BUSY(1) during configuration 0: FPGA#N ready for next configuration byte 1: FPGA#N still busy with previous byte after configuration these signals may be re-used as I/O pin (this option is not currently used) 4 reads CNFG_DONE(0) 5 reads CNFG_DONE(1) 0: FPGA#N not yet configured 1: FPGA#N successfully configured 6 unallocated 7 unallocated VME Interface Section Registers ------------------------------- none