FPGA BSPT FW v1                            Y.Ermoline, Current Rev. 10-Mar-2014
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FPGA_BSPT_FW_v1_20140310 ("safe")
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This version is based on the original code for CMM from Ian Brawn.
Project directory: "cmx_bspt_safe_20140310"
corresponding file "vme_map_20140310.txt"

It implements several VME registers:
- RO_0000 Module ID and SN
- RO_0002 Module HW/FW Revisions
- RW_0004 Module Control Register
- RW_0006 Module Resets Register
- RO_0008 Module Satus 1 Register
- RO_000A Module Satus 2 Register
For VME interface tests there are 2 registers and 2 register arrays:
- RW_000C temporary RW register 1
- RW_000E temporary RW register 2
- temporary array of 16-bit RW registers from 0060 to 007E
- temporary array of 16-bit RW registers from 00E0 to 00FE

It provides acces to the TTCrx chip on the TTCDEC card via registers:
- RW_0030 TTCrx Control Register
- RO_0032 TTCrx Status Register

The TTC_CLK_SEL and TTC_PD control bits are temporary set to fixed values
to bypass bits 5 and 6 in RW_0004 Module Control Register
- TTC_CLK_SEL <= '1';
- TTC_PD      <= '1';

The VME reseivers control temp set to fix the error with chip orientation
- VME_CTRL_RECVR_LE            <= '0'; -- 17.02.2014 temp set to '0'
- VME_ADRS_AND_CTRL_RECVR_OE_B <= '1'; -- 17.02.2014 temp set to '1'

For the LVDS lonks control the output control signals are set to static values
regardless of the input signals in such a way that:
- all LVDS transceivers (CTP and Backplane) are configured as inputs to the CMX,
- all level translators are configured as inputs to the BSPT/BF/TP FPGAs and are disabled.
In this way the BF and TP FPGAs may remain unconfigured after the BSPT configuration
from the BSPT PROM on power up.