CMX VME registers/memories map Y.Ermoline, Current Rev. 10-Mar-2014 ============================== "safe" version "cmx_bspt_safe_20140310" This documents is based on the following sources: [1] Common Merger Module, Version 1.8, 18-Jul-2008 [2] Missing Energy Significance Trigger, Version 2.1, 3-November-2011 [3] CMM schematics "pc3203m5_schems.pdf", last revision 20.09.06 [4] VHDL package "vme_cmm.vhd", last revision 05.01.11 [5] TTCrx Reference Manual, December 2005, version 3.11 (for para 4.4) [6] XILINX System ACE CompactFlash Solution, DS080(v2.0) October 1, 2008 (for para 4.5) [7] CMX Firmware Specifications (Wojtek, Pawel, Yuri) [8] inputs from Murrough, Wojtek, Pawel [9] CMX schematics and network lists Guidelines (from CMM_V1.8): --------------------------- The computer can read all registers; hence there are no ‘write only’ registers. The register bits generally have the same meaning for reads as for writes. - All Status Registers shall be Read-Only (RO) registers. - All Control Registers shall be Read/Write (RW) registers. - Reading back a register generally returns the last value written. - Attempts to write to RO registers or undefined portions of registers result in the non-modifiable fields being left unchanged It is illegal for the computer to read or write a value that the CMM module itself is able to modify at the same time. If the computer reads a register (e.g. a counter) which the CMM module is modifying, a well-defined value is returned. When the address space occupied by the CMM module is accessed, it always responds with a handshake to avoid a bus error. The power-up condition of all registers is all zeros, unless otherwise stated. Setting a bit-field means writing a 1 to it, clearing it means writing a 0. ------------------------------------------------------------------------------- 1. List of registers as now implemented in VAT test card (for reference) 1.1 VAT card list of registers 1.2 Detailed VAT test card registers description 1.3 CMX_VAT FPGA pins/signals 2. Proposal for the CMX Board Support FPGA (BSPT_FPGA) VME register map 2.1 BSPT_FPGA list of registers 2.2 Registers related to the whole CMX module 2.3 - 2.4 Registers related to the TTCrx chip on the TTCDec card 2.5 Registers related to the XILINX SystemACE chip ===================================================================================================================================== 1. List of registers as now implemented in VAT test card (for reference) ===================================================================================================================================== The VME-- base address ranges: CrateSlotNumber Module VME-- address 3 CMM0 0x00700000-0x0077FFFE 20 CMM1 0x00780000-0x007FFFFE 1.1 VAT card list of registers ------------------------------ Initial set of registers from Ian CMM specification and Uli ACE design Addr Re Name Size Description "vme_cmm" name FPGA Function Comments ----- -- ---- ---- ----------- -------------- ------- -------- -------- 00000 RO ModuleIdA 2 Module ID Register A ia_modulida Support VME CMX ModuleID 00002 RO ModuleIdB 2 Module ID Register B ia_modulidb Support VME CMX ModuleRew 00004 RW ControlModeReg 2 Control Mode Register ia_ctrlmode Support VME CMX ModuleControl 00006 RW ControlPulseReg 2 Control Pulse Register ia_ctrlpulse Support VME CMX ModuleResets 00008 RO StatusReg 2 Status Register ia_status Support VME CMX ModuleStatus 0000A RO FifoStatusReg 2 FIFO Status Register ia_fifostat Support VME CMX FIFOStatus 00040 RW TtcrxControl 2 TTCrx Control Register ia_ttc_c Support TTC CMX 00042 RO TtcrxStatus 2 TTCrx Status Register ia_ttc_s Support TTC CMX 00044 RO TtcNotReady 2 ->for test not in CMM spec ->not in "vme_cmm" Support TTC -> not implemented in CMX 00054 RO I2cId 2 I2C FPGA firmware version ia_i2cid Support TTC -> replaced by CMX ModuleRew 00056 RO VmeId 2 VME CPLD firmware version ia_vmeid Support VME -> replaced by CMX ModuleRew 00058 RO SystemAceVMEIf 2 System Ace VME Interface ia_sysace Support ACE -> replaced by CMX ModuleRew 0005C RW CanAccessA 2 CAN Access Register A ia_can_a Support CAN -> not implemented in CMX 0005E RW CanAccessB 2 CAN Access Register B ia_can_b Support CAN -> not implemented in CMX 001FA RW TtcI2Cid 2 TtcI2cId Register ia_ttc_id Support TTC -> not implemented in CMX 001FC RO TtcBrcst 2 TtcBrcst Register ia_ttc_brcst Support TTC CMX TTCDecBrcst 001FE RO TtcDq 2 TTC DQ Register ia_ttc_dqreg Support TTC CMX TTCDecDq 00200 RO TtcDump 32 TTC Dump RAM ia_ttc_dqram Support TTC CMX TTCDecDump 00300 RW 2 ->not in CMM spec ia_ace_ctrl -> Ian ACE replaced by Uli ACE 00302 RW 2 ->not in CMM spec ia_ace_d_msb -> Ian ACE replaced by Uli ACE 00304 RW 2 ->not in CMM spec ia_ace_rst -> Ian ACE replaced by Uli ACE 00306 RO 2 ->not in CMM spec ia_ace_out -> Ian ACE replaced by Uli ACE 00308 RO 2 ->not in CMM spec ia_ace_stats -> Ian ACE replaced by Uli ACE 04000 ->See SystemACE 96 ->See SystemACE ->not in "vme_cmm" Support ACE address from 04000 to 0405F 1.2 Detailed VAT test card registers description ------------------------------------------------ Addr Re Name Size Description "vme_cmm" name FPGA Function Comments ----- -- ---- ---- ----------- -------------- ------- -------- -------- 00000 RO ModuleIdA 2 Module ID Register A ia_modulida Support VME ---------------------------------------------------------------------------------------------- All bit fields are outputs from card. Bits 00-15: ModuleID A unique 16 bit number, set in firmware. vme_interface: module_id_a <= X"2417"; -- for CMM (RAL Number), for CMX - ?) CMM FPGA port: Internal Support FPGA signal, not connected to the FPGA port 00002 RO ModuleIdB 2 Module ID Register B ia_modulidb Support VME ---------------------------------------------------------------------------------------------- All bit fields are outputs from card. -> set in VAT to "095a" by jumpers Bits 00-07: Module Serial number A unique 8-bit number for each module, starting at 1 and set by solder jumpers CMM FPGA port: module_id_b : IN std_logic_vector (7 DOWNTO 0); Bits 08-11: Hardware Revision Number Four-bit revision number starting at 1 and set by solder jumpers CMM FPGA port: module_id_b : IN std_logic_vector (11 DOWNTO 8); Bits 12-15: null 00004 RW ControlModeReg 2 Control Mode Register ia_ctrlmode Support VME ---------------------------------------------------------------------------------------------- All bit fields are inputs to card. Bit 00 : Enable Playback Mode Writing a 1 to this bit causes the Input DPM to be used as a data playback memory. CMM FPGA port: plybk_en : OUT std_logic; -- to crate and system FPGAs Bits 01-04: GEOADD Bypass On power-up, these bits are set to the value obtained from the geographical addressing pins GEOADD and used to establish the module function. VME and TTC address decoding is performed using the VME GEOADD bits and so is not altered by changes made here. CMM FPGA port: Internal Support FPGA signal, not connected to the FPGA port Bit 05 : TTC Clock enable When this bit is set, the CMM uses the TTC clocks, otherwise - the on-board 40 MHz oscillator. Trying to set this bit when the TTC is not ready has no effect (TTC Ready - bit 7 in 00008 RO StatusReg). CMM FPGA port: ttc_clksel : OUT std_logic; -- to TTC card ClkSel (Clock Select) TTCS1-44 Bit 06 : TTC Protect This bit controls the TTC Decoder protection scheme described in the TTCDec specification CMM FPGA port: ttc_pd : OUT std_logic; -- to TTC card P/D (Mode Select) TTCS1-42 Bit 07 : LaserDisable_RoI When this bit is set, the laser used to drive the RoI G-Link is turned off to reduce power consumption. CMM FPGA port: laser_dis_daq : OUT std_logic; -- DAQ SFP cage Bit 08 : Laser_Disable_DAQ When this bit is set, the laser used to drive the DAQ G-Link is turned off to reduce power consumption. CMM FPGA port: laser_dis_roi : OUT std_logic; -- ROI SFP cage Bit 09 : Rate Counter Inhibit When this bit is set, incrementing of the rate meter counters and the normalization counter is inhibited. CMM FPGA port: sp_core : OUT std_logic_vector (1); -- Crate FPGA sp_service : OUT std_logic_vector (0); -- System FPGA Bits 10–15: null 00006 RW ControlPulseReg 2 Control Pulse Register ia_ctrlpulse Support VME ---------------------------------------------------------------------------------------------- All bit fields are inputs to card. All bits read back as zero, and writing a zero to a bit has no effect. Bit 00 : Reset Module Writing a 1 to this bit resets the module to the power-on state (includes restoring GEOADD and reloading the FPGAs). CMM FPGA port: n_board_reset : OUT std_logic; -- to crate and system FPGAs Bit 01 : Reset TTC Writing a 1 to this bit resets the TTC daughter board to the power on state. CMM FPGA port: n_ttc_reset : OUT std_logic; -- generates Reset_b for TTCDec card (TTCrx chip reset) TTCS1-29 Bit 02 : Reset RoI G-link Writing a 1 to this bit resets the RoI G-link to the power on state. CMM FPGA port: n_groi_reset : OUT std_logic; -- to GLink HDMP-1022 Bit 03 : Reset DAQ G-link Writing a 1 to this bit resets the DAQ G-link to the power on state. CMM FPGA port: n_gdaq_reset : OUT std_logic; -- to GLink HDMP-1022 Bit 04 : Reset CAN controller Writing a 1 to this bit resets the CAN microprocessor to the power on state. CMM FPGA port: n_can_reset : OUT std_logic; -- FUJITSU MB90F594 uC reset from VME Bit 05 : Reset I2C controller Writing a 1 to this bit resets the I2C interface controller to the power on state. CMM FPGA port: Internal Support FPGA signal, not connected to the FPGA port Bits 06-07: null Bit 08 : Reset DLL Writing a 1 to this bit resets to the power-on state the DLLs used for clock management within the Crate and System FPGAs. CMM FPGA port: n_dll_reset : OUT std_logic; -- to crate and system FPGAs Bit 09 : Clear Errors Writing a 1 to this bit resets to zero the Backplane Parity Error Register, the Cable Parity Error Register, the Parity Count Register, and the FIFO Overflow and Recorded FIFO Overflow bits. CMM FPGA port: clrpe : OUT std_logic; -- to crate and system FPGAs Bit 10 : Reload Crate-summing FPGA Writing a 1 to this bit reloads the Crate and System FPGAs with firmware corresponding to the module geographical address specified in the Geoadd Bypass field (Bits 01-04) in the Control Mode Register. CMM FPGA port: n_ace_reset : OUT std_logic; -- to ACE controller (from ACE CPLD in CMM) Bit 11 : Reset Rate Meter Counters Writing a 1 to this bit sets all rate meter counters and the normalisation counter to zero. CMM FPGA port: sp_core : OUT std_logic_vector (2); -- Crate FPGA sp_service : OUT std_logic_vector (1); -- System FPGA Bits 12–15: null 00008 RO StatusReg 2 Status Register ia_status Support VME ---------------------------------------------------------------------------------------------- All bit fields are outputs from card Connected to the status1_Bus : IN std_logic_vector (15 DOWNTO 0); Bit 00 : Combined Parity Error When this bit is set, a parity error has been detected on one or more of the incoming backplane or cable links since the last error reset. The bit is cleared by the error-reset bit (Bit 09) in the Control Pulse Register. CMM FPGA port: status1_Bus : IN std_logic_vector (0); -- CMM_PEC_NZERO from crate FPGA Bit 01 : FPGA Load Complete This bit is set if all FPGA configurations have loaded successfully -> Not used in CMM... Bit 02 : DAQ FIFO Overflow This bit is set if any of the readout FIFOs on the module have overflowed. It is cleared by the error-reset bit (Bit 09) in the Control Pulse Register. -> Not used in CMM...??? Bit 03 : null Bit 04 : I2C FPGA loaded This bit is set if the I2C controller FPGA has been configured correctly. CMM FPGA port: status1_Bus : IN std_logic_vector (4); -- I2C_DONE -> TTC FPGA merged now with VME CPLD and ACE CPLD in Spartan, -> use DONE from Spartan? OR set to '1' in FW? Bit 05 : Crate FPGA loaded This bit is set if the Crate FPGA has been configured correctly. -> Not used in CMM... (use cmm_done in ACE part) Bit 06 : System FPGA loaded This bit is set if the System FPGA has been configured correctly. -> Not used in CMM... (use cmms_done in ACE part) Bit 07 : TTC Ready This bit is set when the TTCrx is ready. CMM FPGA port: status1_Bus : IN std_logic_vector (7); -- TTC_READY from TTC card Bit 08 : Crate FPGA DLL locked This bit is set when the DLL in the Crate FPGA has successfully locked on to the 40 MHz clock. CMM FPGA port: status1_Bus : IN std_logic_vector (8); -- CMM_LOCKED_DLL Bit 09 : System FPGA DLL locked This bit is set when the DLL in the System FPGA has successfully locked on to the 40 MHz clock. CMM FPGA port: status1_Bus : IN std_logic_vector (9); -- CMMS_LOCKED_DLL Bit 10 : DAQ G-Link Ready This bit is set when the DAQ G-link is ready. CMM FPGA port: status1_Bus : IN std_logic_vector (10); -- GDAQ_LINKRDY Bit 11 : RoI G-Link Ready This bit is set when the RoI G-link is ready. CMM FPGA port: status1_Bus : IN std_logic_vector (11); -- GROI_LINKRDY Bit 12 : Recorded FIFO Overflow -> Not used in CMM... Bits 13–15: null 0000A RO FifoStatusReg 2 FIFO Status Register ia_fifostat Support VME ---------------------------------------------------------------------------------------------- All bit fields are outputs from card Connected to the status2_Bus : IN std_logic_vector (7 DOWNTO 0); Bits 00–07: Crate and system, DAQ and RoI Empty and full flags for all of the readout FIFOs on the module. CMM FPGA port: status2_Bus : IN std_logic_vector (7 DOWNTO 0); 00040 RW TtcrxControl 2 TTCrx Control Register ia_ttc_c Support TTC ---------------------------------------------------------------------------------------------- All bit fields are inputs to card. This register and the following TTCrx Status Register provide access to the 20 useraccessible internal registers of the TTCrx chip. Power-up condition initially sets all bits to 0. A TTCrx I/O operation takes place whenever this register is changed, unless the I2C bus is busy (see TTC Status register below). An I2C operation is aborted if the reset bit is set. Bits 00–07: Data to TTCrx This 8-bit field contains data to be written to the TTCrx chip. CMM FPGA port: Internal Support FPGA signal, not connected to the FPGA port Bits 08-12: TTC Register Number Specify the TTCrx register number to be read or written CMM FPGA port: Internal Support FPGA signal, not connected to the FPGA port Bit 13 : Write When set to 1, defines the operation as a write to TTCrx. When set to 0, the operation is a read. CMM FPGA port: Internal Support FPGA signal, not connected to the FPGA port Bit 14 : null Bit 15 : Reset TTCrx Controller When set to 1, resets the TTC controller logic and aborts any I2C operation in progress. CMM FPGA port: Internal Support FPGA signal, not connected to the FPGA port 00042 RO TtcrxStatus 2 TTCrx Status Register ia_ttc_s Support TTC ---------------------------------------------------------------------------------------------- All bit fields are outputs from card. Bits 00-07: Data from TTCrx This 8-bit field contains data read from the TTCrx chip. CMM FPGA port: Internal Support FPGA signal, not connected to the FPGA port Bits 08-12: null Bit 13 : I2C Busy When set to 1, indicates that an I2C transaction is underway CMM FPGA port: Internal Support FPGA signal, not connected to the FPGA port Bit 14 : I2C Error When set to 1, indicates that an I2C error has occurred CMM FPGA port: Internal Support FPGA signal, not connected to the FPGA port Bit 15 : unused 00044 RO TtcNotReady 2 ->not in CMM spec ->not in "vme_cmm" Support TTC -> for test ---------------------------------------------------------------------------------------------- All bit fields are outputs from card. Bit 00 : TtcNotReady For test? 00008 RO StatusReg Bit 07 TTC Ready ? 00054 RO I2cId 2 I2C FPGA firmware version ia_i2cid Support TTC -> replace 54, 56, 58 with one Reg. ---------------------------------------------------------------------------------------------- All bit fields are outputs from card. Bits 00-15: I2C FPFA irmware version This register contains the version number of the I2C FPGA controlling the TTCrx chip. This is a 16-bit value set in firmware. The first version is number 1. in i2c_ttc -> revision_id <= "0000000000000111"; -- 16#7# -> set to 7 CMM FPGA port: Internal Support FPGA signal, not connected to the FPGA port 00056 RO VmeId 2 VME CPLD firmware version ia_vmeid Support VME -> replace 54, 56, 58 with one Reg. ---------------------------------------------------------------------------------------------- All bit fields are outputs from card. Bits 00-15: VME CPLD firmware version This register contains the version number of the FPGA providing the interface to VME--. This is a 16-bit value set in firmware. The first version is number 1. vme_interface: fw_rev_big <= "00000000" & fw_rev; fw_rev <= X"0B"; -> initial IPB version CMM FPGA port: Internal Support FPGA signal, not connected to the FPGA port 00058 RO SystemAceVMEIf 2 System Ace VME Interface ia_sysace Support ACE -> replace 54, 56, 58 with one Reg. ---------------------------------------------------------------------------------------------- All bit fields are outputs from card. Bits 00-15: System Ace VME Interface firmware version vme_interface: ace_fw_rev <= "00000011"; -- set to 3 CMM FPGA port: Internal Support FPGA signal, not connected to the FPGA port 0005C RW CanAccessA 2 CAN Access Register A ia_can_a Support CAN ---------------------------------------------------------------------------------------------- All bit fields are inputs to card. No bits This register provide access to the microprocessor controlling the CAN bus. in vme_interface -> CMM_VMEdecoder generates n_can_reg1_en => CAN_BUF_EN* CMM FPGA port: n_can_reg1_en : OUT std_logic; -- CAN_BUF_EN* for FUJITSU MB90F594 uC 0005E RW CanAccessB 2 CAN Access Register B ia_can_b Support CAN ---------------------------------------------------------------------------------------------- All bit fields are inputs to card. Bits 00-03: Can Interrupt Request Writing a 1 to one of these bits causes an interrupt request to the CANBus processor at the corresponding priority. Writing a zero has no effect. --> These bits always read as zero. <-- Bits 04-15: null 001FA RW TtcI2Cid 2 TtcI2cId Register ia_ttc_id Support TTC ---------------------------------------------------------------------------------------------- All bit fields are outputs from card. Bits 00-05: TTCrx I2C ID This register contains the TTC base ID used by the I2C FPGA to communicate with the TTCrx, which is set up as the module resets. It matches the content of the TTCrx base address register I2C_ID (0:5), and should always contain the value 4. CMM FPGA port: Internal Support FPGA signal, not connected to the FPGA port Bits 06-15: null 001FC RO TtcBrcst 2 TtcBrcst Register ia_ttc_brcst Support TTC ---------------------------------------------------------------------------------------------- All bit fields are outputs from card. Bits 00-01: null Bits 02-05: TTC BRCST data (2:5) The most recent value of BRCST data bits (2:5) output from the TTCrx (that were qualified by the TTC strobe BRCSTSTR1). CMM FPGA port: brcst : IN std_logic_vector (5 DOWNTO 2); Bits 06-07: TTC BRCST data (6:7) The most recent value of BRCST data bits (6:7) output from the TTCrx (that were qualified by the TTC strobe BRCSTSTR2). CMM FPGA port: brcst : IN std_logic_vector (7 DOWNTO 6); Bits 08-15: null 001FE RO TtcDq 2 TTC DQ Register ia_ttc_dqreg Support TTC ---------------------------------------------------------------------------------------------- All bit fields are outputs from card. Bits 00-03: TTC DQ The most recent DQ value output from the TTCrx (that was qualified by the TTC strobe DOUTSTR). CMM FPGA port: dq : IN std_logic_vector (3 DOWNTO 0); Bits 04-15: null 00200 RO TtcDump 32 TTC Dump RAM ia_ttc_dqram Support TTC address from 00200 to 0021E ---------------------------------------------------------------------------------------------- All bit fields are outputs from card. Bits 00-07: TTC Dump Data A block of RAM 16 words deep that captures data from TTC Error and Configuration Dumps. Data from the TTC are mapped to the RAM using DQ as the address. CMM FPGA port: dout : IN std_logic_vector (7 DOWNTO 0); Bits 08-15: null 04000 ->See SystemACE 96 ->See SystemACE ->not in "vme_cmm" Support ACE address from 04000 to 0405F ---------------------------------------------------------------------------------------------- 1.3 CMX_VAT FPGA pins/signals ----------------------------- Initial set of pins from Ian CMM specification and Uli ACE design I/O Name So/De CMM FPGA port Register Address Bits Comment --- ---- ------ ------------- -------- ------- ----- ------- IN ModuleID Jumpers module_id_b ModuleIdB 00002 00-11 OUT TTC Clock enable TTC card ttc_clksel ControlModeReg 00004 05 <- BSPT_FPGA OUT TTC Protect TTC card ttc_pd ControlModeReg 00004 06 <- BSPT_FPGA OUT Reset TTC TTC card n_ttc_reset ControlPulseReg 00006 01 <- BSPT_FPGA OUT SCL TTC card scl - - - I2C clock IO SDA TTC card sda - - - I2C data IN TTC Ready TTC card status1_Bus(7) StatusReg 00008 07 <- BSPT_FPGA IN TtcBrcst TTC card brcst TtcBrcst Register 001FC 02-07 <- BSPT_FPGA IN TtcDq TTC card dq TTC DQ Register 001FE 00-03 <- BSPT_FPGA IN TtcDump TTC card dout TTC Dump RAM 00200 00-07 <- BSPT_FPGA OUT LaserDisable_RoI ROI SFP laser_dis_daq ControlModeReg 00004 07 <- OUT LaserDisable_DAQ DAQ SFP laser_dis_roi ControlModeReg 00004 08 <- OUT Reset RoI G-link HDMP-1022 n_groi_reset ControlPulseReg 00006 02 <- OUT Reset DAQ G-link HDMP-1022 n_gdaq_reset ControlPulseReg 00006 03 <- IN DAQ G-Link Ready HDMP-1022 status1_Bus(10) StatusReg 00008 10 <- IN RoI G-Link Ready HDMP-1022 status1_Bus(11) StatusReg 00008 11 <- OUT Reload FPGAs SystemACE n_ace_reset ControlPulseReg 00006 10 IN Crate FPGA loaded SystemACE cmm_done StatusReg 00008 05 <- BSPT_FPGA IN System FPGA loaded SystemACE cmms_done StatusReg 00008 06 <- BSPT_FPGA OUT Reset CAN controller MB90F594 n_can_reset ControlPulseReg 00006 04 <- BSPT_FPGA OUT CAN_BUF_EN* MB90F594 n_can_reg1_en CanAccessA 0005C - register enable signal OUT Can Interrupt Request MB90F594 can_reg2_bus CanAccessB 0005E 00-03 OUT Enable Playback Mode BaseFPGA plybk_en ControlModeReg 00004 00 OUT Rate Counter Inhibit BaseFPGA sp_core(1) ControlModeReg 00004 09 also sp_service(0) to System FPGA in CMM OUT Reset Module BaseFPGA n_board_reset ControlPulseReg 00006 00 OUT Reset DLL BaseFPGA n_dll_reset ControlPulseReg 00006 08 OUT Clear Errors BaseFPGA clrpe ControlPulseReg 00006 09 OUT Reset Rate Counters BaseFPGA sp_core(2) ControlPulseReg 00006 11 also sp_service(1) to System FPGA in CMM IN Combined Parity Error BaseFPGA status1_Bus(0) StatusReg 00008 00 IN Crate FPGA DLL locked BaseFPGA status1_Bus(8) StatusReg 00008 08 IN System FPGA DLL locked TopoFPGA status1_Bus(9) StatusReg 00008 09 IN Empty and full flags BaseFPGA status2_Bus FifoStatusReg 0000A 00-07 IN Empty and full flags TopoFPGA status2_Bus FifoStatusReg 0000A 00-07 ===================================================================================================================================== 2. Proposal for the CMX Board Support FPGA (BSPT_FPGA) VME register map ===================================================================================================================================== The VME-- base address ranges: CrateSlotNumber Module VME-- address 3 CMX0 0x00700000-0x0077FFFE 20 CMX1 0x00780000-0x007FFFFE BSPT_FPGA address range: 256 bytes 3 CMX0 0x00700000-0x007000FF 20 CMX1 0x00780000-0x007800FF 2.1 BSPT_FPGA list of registers implemented in "safe" version "cmx_bspt_safe_20140310" ====================================================================================== Addr Re Name Size Description VHDL name FPGA Function Comments ----- -- ---- ---- ----------- ---------- ---- ------- -------- 00000 RO ModuleIDSN 2 Module ID and SN module_idsn BSPT VME I/F 00002 RO ModuleRew 2 Module HW/FW Revisions module_rev BSPT VME I/F 00004 RW ModuleControl 2 Module Control Register module_cntrl BSPT VME I/F 00006 RW ModuleResets 2 Module Resets Register module_rsts BSPT VME I/F 00008 RO ModuleStatus1 2 Module Satus 1 module_stat1 BSPT VME I/F 0000A RO ModuleStatus2 2 Module Satus 2 module_stat2 BSPT Opto 0000C RW TempReg1 2 temporary RW register 1 vme_rw_reg1 BSPT test 0000E RW TempReg2 2 temporary RW register 2 vme_rw_reg2 BSPT test 00030 RW TTCrxControl 2 TTCrx Control Register ttc_control BSPT TTC 00032 RO TTCrxStatus 2 TTCrx Status Register ttc_status BSPT TTC 00034 RO TTCrxBrcst 2 TTCDec Brcst Register ttc_brcst BSPT TTC 00036 RO TTCrxDq 2 TTCDec DQ Register ttc_dq BSPT TTC 00040 RO TTCrxDump 32 TTCDec Dump RAM ttc_ram BSPT TTC addresses from 00040 to 0005E 00060 RW TemArrayReg2 32 temporary RW array 2 vme_rw_array2 BSPT test addresses from 00060 to 0007E 00080 ->See SystemACE 96 ->See SystemACE ->See SystemACE BSPT ACE addresses from 00080 to 000DF 000E0 RW TemArrayReg1 32 temporary RW array 1 vme_rw_array1 BSPT test addresses from 000E0 to 000FE Last BSPT_FPGAaddress: 000FF 2.2 Registers related to the whole CMX module ============================================= Addr Re Name Size Description VHDL name FPGA Function Comments ----- -- ---- ---- ----------- ---------- ---- ------- -------- 00000 RO ModuleIDSN 2 Module ID and SN module_idsn BSPT VME I/F -------------------------------------------------------------------------------------------------------------- All bit fields are outputs from the CMX This register replaces the CMM registers 00(00-15) and 02(00-07) Bits 00-07: Module_ID - a unique 8 bit Module Number (what is this number for CMX?), set in firmware BSPT_FPGA port: Internal BSPT_FPGA signal, not connected to the BSPT_FPGA port Bits 08-15: Module_SN - a 8-bit Serial Number for each module, starting at 1 and set by 5 jumpers + 3 upper bits in FW BSPT_FPGA port: MODULE_SN : in std_logic_vector (4 DOWNTO 0); -- 5 jumpers JMP101 through JMP105 00002 RO ModuleRew 2 Module HW/FW Revisions module_rev BSPT VME I/F -------------------------------------------------------------------------------------------------------------- All bit fields are outputs from the CMX This register replaces the CMM registers 02(08-11), 54(I2cId), 56(VmeId), 58(SystemAceVMEIf) Bits 00-07: CMX_HWR - 8 bit CMX Hardware Revision Number starting at 1 and set in firmware BSPT_FPGA port: Internal BSPT_FPGA signal, not connected to the BSPT_FPGA port Bits 08-15: BSPT_FWR - 8 bit Board Support FPGA Firmware Revision Number starting at 1 and set in firmware BSPT_FPGA port: Internal BSPT_FPGA signal, not connected to the BSPT_FPGA port 00004 RW ModuleControl 2 Module Control Register module_cntrl BSPT VME I/F -------------------------------------------------------------------------------------------------------------- All bit fields are inputs to the CMX Bit 00 : not used, defined as "null" Bits 01-04: GEOADD Bypass On power-up, these bits are set to the value obtained from the geographical addressing pins GEOAD and used to establish the module function (FW download). VME and TTC address decoding is performed using the VME GEOADD bits and so is not altered by changes made here. BSPT_FPGA port: xxx : in std_logic; -- U351-xx -- GEOADD0 BSPT_FPGA port: xxx : in std_logic_vector (6 DOWNTO 4); -- U351-xx -- GEOADD(6 DOWNTO 4) Bit 05 : TTCDec Clock Select - When this bit is set, the TTCDec uses the TTCrx clock, otherwise - XTAL clock Trying to set this bit when the TTC is not ready has no effect (TTC Ready - bit 00 in 000xx TTCDecStatus). BSPT_FPGA port: xxx : out std_logic; -- U351-xx -- to TTCDec card ClkSel (Clock Select) TTCS1-44 Bit 06 : TTCDec P/D Mode Select - This bit controls the TTCDec protection scheme described in the TTCDec specification BSPT_FPGA port: xxx : out std_logic; -- U351-xx -- to TTCDec card P/D (Mode Select) TTCS1-42 Bits 07–08: null Bit 09 : Rate Counter Inhibit When this bit is set, incrementing of the rate meter counters and the normalization counter is inhibited. BSPT_FPGA port: xxx : out std_logic; -- U351-xx -- to BASE_FPGA -> not used, defined as "null", will be inplemente in the Base FPGA Bit 10 : SFP1_TX_DISABLE - SFP1 Transmitter Disable (DAQ?) BSPT_FPGA port: SFP1_TX_DISABLE : out std_logic; -- U351-M1 Bit 11 : SFP2_TX_DISABLE - SFP2 Transmitter Disable (ROI?) BSPT_FPGA port: SFP2_TX_DISABLE : out std_logic; -- U351-L3 Bit 12 : SFP3_TX_DISABLE - SFP3 Transmitter Disable BSPT_FPGA port: SFP3_TX_DISABLE : out std_logic; -- U351-J1 Bit 13 : SFP4_TX_DISABLE - SFP4 Transmitter Disable BSPT_FPGA port: SFP4_TX_DISABLE : out std_logic; -- U351-H2 Bits 14-15: null 00006 RW ModuleResets 2 Module Resets Register module_rsts BSPT VME I/F -------------------------------------------------------------------------------------------------------------- All bit fields are inputs to the CMX. All bits read back as zero, and writing a zero to a bit has no effect. Bit 00 : Reset Module - Writing a 1 to this bit resets the module to the power-on state (includes restoring GEOADD and reloading the FPGAs) ???. BSPT_FPGA port: xxx : out std_logic; -- U351-xx -- ??? Bit 01 : Reset TTC - Writing a 1 to this bit resets the TTCDec card. Writing a 0 has no effect. Read back as zero. BSPT_FPGA port: xxx : out std_logic; -- U351-xx -- generates Reset_b for TTCDec card (TTCrx chip reset) TTCS1-29 Bit 02 : Reset MiniPods 1,2 - Writing a 1 to this bit generates Reset_B for MiniPods 1,2 BSPT_FPGA port: MP12_RESET_B : out std_logic; -- U351-R3 Bit 03 : Reset MiniPods 3,4,5 - Writing a 1 to this bit generates Reset_B for MiniPods 3,4,5 BSPT_FPGA port: MP345_RESET_B : out std_logic; -- U351-P4 Bit 04 : Reset CAN controller - Writing a 1 to this bit resets the CAN microprocessor to the power on state. BSPT_FPGA port: ??? : out std_logic; -- U351-xx -- FUJITSU MB90F594 uC reset from VME Bit 05 : Reset TTCrx I2C controller - Writing a 1 to this bit resets the I2C interface controller to the power on state. BSPT_FPGA port: Internal BSPT_FPGA signal, not connected to the BSPT_FPGA port Bit 06 : Upload IODELAY circuits - Writing a 1 to this bit will trigger adjustment of the IODELAY circuits to the tap values programmed in a dedicated registers (which ?) BSPT_FPGA port: xxx : out std_logic; -- U351-xx -- to BASE_FPGA (and TOPO_FPGA?) -> use trace from Bit 00 in ModuleControl register -> Pawel and Wojtek: bit 6 -> change to 'upload delays' Bit 07 : null Bit 08 : Reset DLL - Writing a 1 to this bit resets to the power-on state the DLLs used for clock management within the Crate and System FPGAs. BSPT_FPGA port: xxx : out std_logic; -- U351-xx -- to BASE_FPGA and TOPO_FPGA ??? Bit 09 : Clear Parity Errors - Writing a 1 to this bit resets to zero the Backplane Parity Error Register, the Cable Parity Error Register, the Parity Count Register, and the FIFO Overflow and Recorded FIFO Overflow bits. BSPT_FPGA port: xxx : out std_logic; -- U351-xx -- to BASE_FPGA ??? Bit 10 : Reset System ACE - Writing a 1 to this bit resets the Systen ACE controller and reloads the BASE_FPGA and TOPO_FPGA with firmware corresponding to the module geographical address specified in the GEOADD Bypass field (Bits 01-04) in the Module Control Register (00004). BSPT_FPGA port: ACE_RESET_B: out std_logic; -- U351-xx -- to System ACE controller (pin 33: RESET*) Bit 11 : Reset Rate Meter Counters - Writing a 1 to this bit sets all rate meter counters and the normalisation counter to zero. BSPT_FPGA port: xxx : out std_logic; -- U351-xx -- to BASE_FPGA and TOPO_FPGA ??? Bits 12–15: null 00008 RO ModuleStatus1 2 Module Satus 1 Register module_stat1 BSPT VME I/F -------------------------------------------------------------------------------------------------------------- All bit fields are outputs from the CMX Bit 00 : not used, defined as "null" Bit 01 : Lock Monitor VCXO_PLL DeScew-1 BSPT_FPGA port: BSPT_DEBUG_5 : in std_logic; -- U351-P16 Bit 02 : Lock Monitor VCXO_PLL DeScew-2 BSPT_FPGA port: BSPT_DEBUG_7 : in std_logic; -- U351-R18 Bit 03 : Lock Monitor VCXO_PLL 320 MHz BSPT_FPGA port: BSPT_DEBUG_6 : in std_logic; -- U351-U16 Bit 04 : System ACE Error - When this bit is set, an error occurred during FPGA configuration BSPT_FPGA port: ACE_ERRLED_B : in std_logic; -- U351-xx Bit 05 : BASE_FPGA loaded - This bit is set if the BASE_FPGA has been configured correctly. BSPT_FPGA port: BF_CONFIG_DONE : in std_logic; -- U351-xx -- DONE from BASE_FPGA Bit 06 : TOPO_FPGA loaded - This bit is set if the TOPO_FPGA has been configured correctly. BSPT_FPGA port: TP_CONFIG_DONE : in std_logic; -- U351-xx -- DONE from TOPO_FPGA Bit 07 : TTCrx Ready - This bit is set when the TTCrx on TTCDec card is ready. BSPT_FPGA port: BUF_TTC_READY : in std_logic; -- U351-xx -- TTC_READY from TTCDec card Bit 08 : BASE_FPGA DLL locked - This bit is set when the DLL in the BASE_FPGA has successfully locked on to the 40 MHz clock. BSPT_FPGA port: ??? : in std_logic; -- U351-xx -- ??? Bit 09 : TOPO_FPGA DLL locked - This bit is set when the DLL in the TOPO_FPGA has successfully locked on to the 40 MHz clock. BSPT_FPGA port: ??? : in std_logic; -- U351-xx -- ??? Bit 10 : MP1_INTRPT_B - MiniPOD 1 Interrupt_B BSPT_FPGA port: MP1_INTRPT_B : in std_logic; -- U351-R4 Bit 11 : MP2_INTRPT_B - MiniPOD 2 Interrupt_B BSPT_FPGA port: MP2_INTRPT_B : in std_logic; -- U351-R5 Bit 12 : MP3_INTRPT_B - MiniPOD 3 Interrupt_B BSPT_FPGA port: MP3_INTRPT_B : in std_logic; -- U351-N1 Bit 13 : MP4_INTRPT_B - MiniPOD 4 Interrupt_B BSPT_FPGA port: MP4_INTRPT_B : in std_logic; -- U351-N2 Bit 14 : MP5_INTRPT_B - MiniPOD 5 Interrupt_B BSPT_FPGA port: MP5_INTRPT_B : in std_logic; -- U351-N3 Bit 15 : Status2 - This bit is set when TTCrx is the clock source on the TTCDec card BSPT_FPGA port: BUF_TTC_STATUS_2 : in std_logic; -- U351-xx -- TTCDec card Status2 0000A RO ModuleStatus2 2 Module Satus 2 Register module_stat2 BSPT Opto -------------------------------------------------------------------------------------------------------------- All bit fields are outputs from the CMX SFP1 - BASE_FPGA DAQ SFP2 - BASE_FPGA ROI SFP3 - TOPO_FPGA DAQ SFP4 - TOPO_FPGA DAQ Bit 00: SFP1_TX_FAULT - SFP1 Transmitter Fault BSPT_FPGA port: SFP1_TX_FAULT : in std_logic; -- U351-N4 Bit 01: SFP1_MOD_PRESENT - SFP1 Module Present->Low BSPT_FPGA port: SFP1_MOD_PRESENT : in std_logic; -- U351-M5 Bit 02: SFP1_RX_LOS - SFP1 Receiver Signal Loss BSPT_FPGA port: SFP1_RX_LOST : in std_logic; -- U351-?? Bit 03: null Bit 04: SFP2_TX_FAULT - SFP2 Transmitter Fault BSPT_FPGA port: SFP2_TX_FAULT : in std_logic; -- U351-L1 Bit 05: SFP2_MOD_PRESENT - SFP2 Module Present->Low BSPT_FPGA port: SFP2_MOD_PRESENT : in std_logic; -- U351-K3 Bit 06: SFP2_RX_LOS - SFP2 Receiver Signal Loss BSPT_FPGA port: SFP2_RX_LOST : in std_logic; -- U351-?? Bit 07: null Bit 08: SFP3_TX_FAULT - SFP3 Transmitter Fault BSPT_FPGA port: SFP3_TX_FAULT : in std_logic; -- U351-K4 Bit 09: SFP3_MOD_PRESENT - SFP3 Module Present->Low BSPT_FPGA port: SFP3_MOD_PRESENT : in std_logic; -- U351-J4 Bit 10: SFP3_RX_LOS - SFP3 Receiver Signal Loss BSPT_FPGA port: SFP3_RX_LOST : in std_logic; -- U351-?? Bit 11: null Bit 12: SFP4_TX_FAULT - SFP4 Transmitter Fault BSPT_FPGA port: SFP4_TX_FAULT : in std_logic; -- U351-J5 Bit 13: SFP4_MOD_PRESENT - SFP4 Module Present->Low BSPT_FPGA port: SFP4_MOD_PRESENT : in std_logic; -- U351-G3 Bit 14: SFP4_RX_LOS - SFP4 Receiver Signal Loss BSPT_FPGA port: SFP4_RX_LOST : in std_logic; -- U351-?? Bit 15: null 0000C RO TempReg1 2 Temporary RW register 1 rw_reg1 BSPT test -------------------------------------------------------------------------------------------------------------- 0000E RO TempReg2 2 Temporary RW register 2 rw_reg2 BSPT test -------------------------------------------------------------------------------------------------------------- 2.4 Registers related to the TTCrx chip on the TTCDec card ========================================================== Addr Re Name Size Description VHDL name FPGA Function Comments ----- -- ---- ---- ----------- ---------- ---- ------- -------- 00030 RW TTCrxControl 2 TTCrx Control Register ttc_control BSPT TTC -------------------------------------------------------------------------------------------------------------- All bit fields are inputs to the CMX This register and the following TTCrx Status Register provide access to the 20 user accessible internal registers of the TTCrx chip (see also [5]). Power-up condition initially sets all bits to 0. A TTCrx I/O operation takes place whenever this register is changed, unless the I2C bus is busy (see TTC Status register below). An I2C operation is aborted if the reset bit is set. Bits 00–07: Data to TTCrx - This 8-bit field contains data to be written to the TTCrx chip. BSPT_FPGA port: Internal BSPT_FPGA signal, not connected to the BSPT_FPGA port Bits 08-12: TTCrx Register Number - Specify the TTCrx register number to be read or written BSPT_FPGA port: Internal BSPT_FPGA signal, not connected to the BSPT_FPGA port Bit 13 : Write - When set to 1, defines the operation as a write to TTCrx. When set to 0, the operation is a read. BSPT_FPGA port: Internal BSPT_FPGA signal, not connected to the BSPT_FPGA port Bit 14 : null Bit 15 : TTCrx Controller Abort When set to 1, resets the I2C interface logic in the BSPT FPGA and aborts any I2C operation in progress. (What the difference: Reset TTCrx I2C controller - bit 05 in the Module Resets Register 00006 ???) BSPT_FPGA port: Internal BSPT_FPGA signal, not connected to the BSPT_FPGA port 00032 RO TTCrxStatus 2 TTCrx Status Register ttc_status BSPT TTC -------------------------------------------------------------------------------------------------------------- All bit fields are outputs from the CMX Bits 00-07: Data from TTCrx - This 8-bit field contains data read from the TTCrx chip. BSPT_FPGA port: Internal BSPT_FPGA signal, not connected to the BSPT_FPGA port Bits 08-12: null Bit 13 : I2C Busy - When set to 1, indicates that an I2C transaction is underway BSPT_FPGA port: Internal BSPT_FPGA signal, not connected to the BSPT_FPGA port Bit 14 : I2C Error - When set to 1, indicates that an I2C error has occurred BSPT_FPGA port: Internal BSPT_FPGA signal, not connected to the BSPT_FPGA port Bit 15 : null 00034 RO TTCrxBrcst 2 TTCDec Brcst Register ttc_brcst BSPT TTC -------------------------------------------------------------------------------------------------------------- All bit fields are outputs from the CMX Bits 00-01: null Bits 02-05: TTCrx BRCST data (2:5) - The most recent value of BRCST data bits (2:5) output from the TTCrx (that were qualified by the TTC strobe BRCSTSTR1). BSPT_FPGA port: xxx : in std_logic_vector (5 DOWNTO 2); -- U351-xx -- Bits 06-07: TTCrx BRCST data (6:7) - The most recent value of BRCST data bits (6:7) output from the TTCrx (that were qualified by the TTC strobe BRCSTSTR2). BSPT_FPGA port: xxx : in std_logic_vector (7 DOWNTO 6); -- U351-xx -- Bits 08-15: null 00036 RO TTCrxDq 2 TTCDec DQ Register ttc_dq BSPT TTC -------------------------------------------------------------------------------------------------------------- All bit fields are outputs from card. Bits 00-03: TTCrx DQ - The most recent DQ value output from the TTCrx (that was qualified by the TTC strobe DOUTSTR). BSPT_FPGA port: xxx : in std_logic_vector (3 DOWNTO 0); -- U351-xx -- Bits 04-15: null 00040 RO TTCrxDump 32 TTCDec Dump RAM ttc_ram BSPT TTC addresses from 00040 to 0005E -------------------------------------------------------------------------------------------------------------- All bit fields are outputs from card. Bits 00-07: TTCrx Dump Data A block of RAM 16 words deep that captures data from TTC Error and Configuration Dumps. Data from the TTC are mapped to the RAM using DQ as the address. BSPT_FPGA port: xxx : in std_logic_vector (7 DOWNTO 0); -- U351-xx -- Bits 08-15: null 2.5 Registers related to the XILINX SystemACE chip ================================================== This is a block of XILINX SystemACE MPU registers (96 8-bit registers) mapped to the VME memory (see also [6]) Addr Re Name Size Description VHDL name FPGA Function Comments ----- -- ---- ---- ----------- ---------- ---- ------- -------- 00080 ->See SystemACE 96 ->See SystemACE ->See SystemACE BSPT ACE addresses from 00080 to 000DF --------------------------------------------------------------------------------------------------------------