FPGA BSPT FW v2                            Y.Ermoline, Current Rev. 17-Apr-2014
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FPGA_BSPT_FW_v2_20140417 - 17-Apr-2014
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Project directory: "cmx_bspt_v2_20140417", corresponding file "vme_map_v2_20140417.txt"

It implements VME registers, described in chapter 2.1 of "vme_map_v2_20140417.txt":
For VME interface tests there are 4 registers and 1 register array:
RW_0028 to RW_002E  Temporary RW registers
RW_0060 to RW_007F  Temporary RW array

It provides acces to the TTCrx chip on the TTCDEC card via registers:
- RW_0030 TTCrx Control Register
- RO_0032 TTCrx Status Register

The TTC_CLK_SEL and TTC_PD control bits are temporary set to fixed values
to bypass bits 5 and 6 in RW_0004 Module Control Register
- TTC_CLK_SEL <= '1';
- TTC_PD      <= '1';

The VME reseivers control temp set to fix the error with chip orientation
- VME_CTRL_RECVR_LE            <= '0'; -- 17.02.2014 temp set to '0'
- VME_ADRS_AND_CTRL_RECVR_OE_B <= '1'; -- 17.02.2014 temp set to '1'

For the LVDS links, the management of the control signals to the LVDS transceivers
comes from the BSPT FPGA. In turn the BSPT FPGA listens to signals from the BF and TP FPGAs
to learn how they want the various LVDS transceivers configured, i.e. as inputs or as outputs.
The status of all signals (coming from the BF and TP FPGAs and generated by the BSPT FPGA)
can be accessed via two status registers:
RO_000C   LVDS Link Satus 1
RO_000E   LVDS Link Satus 2

The XILINX System ACE controller internal registers are mapped to the VME adresses from
0080 to 00DF (See System ACE CompactFlash Solution, DS080 (v2.0) October 1, 2008)

Access to the internal registers of the optical components (SFP and MiniPOD) provided
via I2C interface usend to registers: Control/Status Reg and Data Register.
To WRITE the data into writable internal register of the optical component:
- write data to bits 15-8 of the Data Register
- write control data to the Control/Status Reg
To READ the data from the internal register of the optical component:
- write control data to the Control/Status Reg
- read the data from bits 7-0 of the Data Register