Board Support (BSPT) FPGA Firmware v4.0 Y.Ermoline, Current Rev. 06-Jul-2014 =============================================================================================== 1. Introduction 1.1. Presenting registers in VME-- space 1.2. Software to access VME registers 1.3. First look at BSPT registers 1.4. List of registers with expected values 2. Registers related to the whole CMX module 2.1. Module Resets Register RW_0006 2.2. Module Control Register RW_0004 2.3. Module Status 1 Register RO_0008 2.4. Module Status 2 Register RO_000A 3. Registers related to the CTP/BP LVDS Links Mngmnt 3.1. CTP LVDS Connectors Management signals 3.2. Backplane LVDS Cables Managements 3.3. Signal monitoring 3.4. Example 4. Registers related to the optical components access via I2C 5. Registers related to the LEDs control 5.1. LEDs Control register RW_0028 5.2. LEDs Requests Status register RO_002A 6. Registers related to debugging signals 7. Registers related to the TTCrx chip on the TTCDec card 7.1. TTCrx reset 7.2. I2C controller 7.3. TTCrx status 8. Registers related to the XILINX System ACE chip 9. Temporary registers for tests APENDIX 1 Opto_VME_I2C_access (access to optical components via I2C) APENDIX 2 TTCrx control APENDIX 3 CMX FPGA configuration APENDIX 4 FPGA BSPT FW versions APENDIX 5 CMX VME registers/memories map (pointer) 1. Introduction =============== Ancillary tasks which are not part of the real-time operation of the CMX card are implemented in a separate smaller FPGA called the Board Support FPGA (BSPT). The device chosen for the BSPT FPGA is a Xilinx Spartan-3A XC3S400A in the 400 pin FG400 package with attached serial configuration PROM XILINX xcf04s. The Board Control FPGA is responsible for: - presenting registers in VME-- space to access features, listed below, - controlling and monitoring LVDS Links - controlling all the front-panel LEDs except one (power). - controlling and monitoring the SFP optical modules, - controlling and monitoring the MiniPOD transmitters and receivers, - controlling and monitoring the operation of the TTCrx chip on the TTCDec, - controlling of the System ACE and configuration of the main FPGAs, On power up the BSPT FPGA configures itself using its attached serial configuration PROM. Updating the BSPT firmware requires using the Test JTAG Chain (accessible through the front-panel test connector): - to load the new firmware directly into the BSPT FPGA (.bit file) - to load the BSPT serial configuration PROM device (.mcs file) This is done via XILINX download cable using XILINX iMPACT software. The versions (last - v3) of the BSPT FPGA FW is located on the MSU web page: http://www.pa.msu.edu/hep/atlas/l1calo/cmx/firmware/fpga_bspt_fw/ Inside this directory there are following files and subdirectories: - File with the description of different FW versions: http://www.pa.msu.edu/hep/atlas/l1calo/cmx/firmware/fpga_bspt_fw/FPGA_BSPT_FW_versions.txt - File with the CMX VME registers/memories map v3 (vme_map_v3_20140617.txt): http://www.pa.msu.edu/hep/atlas/l1calo/cmx/firmware/fpga_bspt_fw/vme_map_v3_20140617.txt - Subdirectory with the zipped XILINX progect for v3: http://www.pa.msu.edu/hep/atlas/l1calo/cmx/firmware/fpga_bspt_fw/cmx_bspt_v3_20140617.zip Inside the project subdirectory there are all source files and project files, in particular: - "cmx_bspt.bit" file for download to BSPT FPGA, - "cmx_bspt.mcs" file for download to the serial configuration PROM. 1.1. Presenting registers in VME-- space ---------------------------------------- The BSPT FPGA VME memory map and detailed register description for the BSPT FPGA FW v3 is in the CMX VME registers/memories map v3 file "vme_map_v3_20140617.txt": The CMX VME-- memory map allocates 0x80000 bytes for each CMX (512k): CMX0 (slot 3): 0x700000 - 0x77FFFE CMX1 (slot 20): 0x780000 - 0x7FFFFE The first 256 bytes are allocated for the BSPT FPGA (0x0000 - 0x00FF). The BSPT FPGA address space is used as follow: - 0x00-0x0E – common module registers and LVDS Links management, - 0x10-0x26 – optical components access via I2C interface, - 0x28-0x2A - front panel LEDs control, - 0x2C-0x2E - debugging signals, - 0x30-0x5E – access to the TTCrx chip on the TTCDec card, - 0x60-0x7E - array of 16 16-bit RW test registers, not connected to the rest of BSPT FPGA, - 0x80-0xDE – access to the XILINX System ACE chip All unused addresses are reserved, some of them used to implement the test registers. RO - read-only register RW - read-write register Total list of BSPT_FPGA registers (from CMX VME registers/memories map v3): --------------------------------------------------------------------------- Addr Re Name Size Description VHDL name FPGA Function Comments ---- -- ---- ---- ----------- ---------- ---- ------- -------- 0000 RO ModuleIDSN 2 Module ID and SN module_idsn BSPT VME I/F 0002 RO ModuleRew 2 Module HW/FW Revisions module_rev BSPT VME I/F 0004 RW ModuleControl 2 Module Control Register module_cntrl BSPT VME I/F 0006 RW ModuleResets 2 Module Resets Register module_rsts BSPT VME I/F 0008 RO ModuleStatus1 2 Module Satus 1 module_stat1 BSPT VME I/F 000A RO ModuleStatus2 2 Module Satus 2 module_stat2 BSPT Opto 000C RO LinkStatus1 2 LVDS Link Satus 1 link_status1 BSPT LVDS 000E RO LinkStatus2 2 LVDS Link Satus 2 link_status2 BSPT LVDS 0010 RW SFP1_CSR 2 SFP1 Control/Status Reg sfp1_csr BSPT Opto_sfp 0012 RW SFP1_Data 2 SFP1 Data Register sfp1_data BSPT Opto_sfp 0014 RW SFP2_CSR 2 SFP2 Control/Status Reg sfp2_csr BSPT Opto_sfp 0016 RW SFP2_Data 2 SFP2 Data Register sfp2_data BSPT Opto_sfp 0018 RW SFP3_CSR 2 SFP3 Control/Status Reg sfp3_csr BSPT Opto_sfp 001A RW SFP3_Data 2 SFP3 Data Register sfp3_data BSPT Opto_sfp 001C RW SFP4_CSR 2 SFP4 Control/Status Reg sfp4_csr BSPT Opto_sfp 001E RW SFP4_Data 2 SFP4 Data Register sfp4_data BSPT Opto_sfp 0020 RW MP12_CSR 2 MP12 Control/Status Reg mp12_csr BSPT Opto_mp 0022 RW MP12_Data 2 MP12 Data Register mp12_data BSPT Opto_mp 0024 RW MP345_CSR 2 MP345 Control/Status Reg mp345_csr BSPT Opto_mp 0026 RW MP345_Data 2 MP345 Data Register mp345_data BSPT Opto_mp 0028 RW LEDsControl1 2 LEDs Control register 1 leds_cntr1 BSPT LEDs 002A RO LEDsRequests 2 LEDs Requests Status leds_req BSPT LEDs 002C RO BFTPDebug 2 BF and TP debug signals bftp_debug BSPT Debugging 002E RO BSPTDebug 2 BSPT debug signals bspt_debug BSPT Debugging 0030 RW TTCrxControl 2 TTCrx Control Register ttc_control BSPT TTC 0032 RO TTCrxStatus 2 TTCrx Status Register ttc_status BSPT TTC 0034 RO TTCrxBrcst 2 TTCDec Brcst Register ttc_brcst BSPT TTC 0036 RO TTCrxDq 2 TTCDec DQ Register ttc_dq BSPT TTC 0040 RO TTCrxDump 32 TTCDec Dump RAM ttc_ram BSPT TTC addresses from 0040 to 005E 0080 ->See SystemACE 96 ->See SystemACE ->See SystemACE BSPT ACE addresses from 0080 to 00DF 00E0 reserved addresses from 00E0 to 00FF (32 bytes) - DO NOT USE!!! (used by ACE VME address decoding!) 0038 RW TempReg1 2 Temporary RW register 1 vme_rw_reg1 BSPT reserved 003A RW TempReg2 2 Temporary RW register 2 vme_rw_reg2 BSPT reserved 003C RW TempReg3 2 Temporary RW register 3 vme_rw_reg3 BSPT reserved 003E RW TempReg4 2 Temporary RW register 4 vme_rw_reg4 BSPT reserved 0060 RW RegArray 32 Temporary RW array 1 vme_rw_array1 BSPT reserved addresses from 0060 to 007F Last BSPT_FPGAaddress: 00FF 1.2. Software to access VME registers ------------------------------------- After logging into the Single Board Computer (SBC) in the L1Calo crate and executing the configuration program, the folloing simple VME commands are available: Use PuTTY to connect to sbccmx-00.cern.ch source /afs/cern.ch/work/l/laughron/public/l1calo/scripts/login/.lxplus_bashrc Scan VME addresses: vme scan Read from VME address range: vme dump 0x7xxxxx 0x7xxxxx Write to VME from address: vme edit 0x7xxxxx To test the reliability of the access to the internal registers from VME a sophisticated program in Python was written by Philippe Laurens. It can be run, for example, on the array of 16 test registers Andrew Chegwidden is preparing a program to access VME registers in more convinient way. Philippe will write a simple CMX register dump program 1.3. First look at BSPT registers --------------------------------- For initial access via VME, 2 first BSPT registers can be read: RO_0000 CMX Module ID and Module SN : Bits 07-00: Module_ID - a unique 8 bit Module Number, set in firmware to 0x33 Bits 15-08: Module_SN - a 8-bit Serial Number for each module, starting at 1 bits 12-08 set by 5 jumpers on the CMX board, bits 15-13 set in FW to zero Therefore, data read from this register: 0x[xx]33 ([xx] = SN) RO_0002 CMX Module Hardware/Firmware Revisions : Bits 07-00: 8-bit CMX Hardware Revision Number, currently set to 0x01 Bits 15-08: BSPT_FWR - 8 bit Board Support FPGA Firmware Revision Number set in firmware in format X.x Bits 15-12 - major version Bits 11-08 - minor version set to 0x40 for BSPT_FW_v4.0 Therefore, data read from this register: 0x4001 In order to test read-write VME access to the BSPT FPGA, use Philippe's program. 4 RW test registers (0x38-0x3E) and array of 16 RW test registers (0x60-0x7E), not connected to the rest of BSPT FPGA, can be used for this test. 1.4. List of registers with expected values ------------------------------------------- The specific lists of registers to be reading or writing, with their expected values. Module Control Register RW_0004: -------------------------------- Bits 03-00: GEOADD0 Bypass (bit 0) and GEOADDR Bypass (bits 6-4) After BSPT FPGA configuration and after Reset Module(see 2.1) these bits are set to the value of the GEOADDR pins of the backplane. Bit 0 = '0' for the CMX in the left position in the crate Bit 0 = '1' for the CMX in the right position in the crate Bits 6-4 are set by the rotating switch on the rear side of the crate backplane. (e.g. - L1Calo crate in 104 - set to "000", L1Calo crate at MSU - set to "xxx"?) SFP1 optical component: ----------------------- The example is provided in the APPENDIX 1 Opto_VME_I2C_access, part 4: Reading byte 110 (0x6E) from the SFP1 second page - step 1: Write control data to the SFP1 Control/Status Register RW_0010: => control data to write to the SFP1 Control/Status Register: 0000_0001_0110_1110 (0x016E) This operation will start I2C operation to read from the SFP internal register - step 2: Read data from the SFP1 Data Register RW_0012: (look at page 6 of [4] in APPENDIX 1) => expected value to read from the SFP1 Data Register: 0x0012 => 0000_0000_0001_0010 MiniPOD optical component: -------------------------- The example is provided in the APPENDIX 1 Opto_VME_I2C_access, part 4: Reading byte 129 (0x81) from the MiniPOD1 Upper Memory Page 00h - step 1: Write control data to the MiniPOD12 Control/Status Register RW_0020: => control data to write to the MiniPOD12 Control/Status Register: 0000_0000_1000_0001 (0x0081) This operation will start I2C operation to read from the MiniPOD1 internal register - step 2: Read data from the MiniPOD12 Data Register RW_0022 (look at page 38 of [1]): => expected value to read from the MiniPOD12 Data Register: 0x0042 => 0000_0000_0100_0010 TTCrx chip ---------- The reset of the TTCrx chip may be needed after BSPT configuration. In order to reset the TTCrx chip, write '1' in bit 01 of the Module Resets Register RW_0006 (see 2.1). The access to the TTCrx chip internal registers is described in 6.1 and in APENDIX 2 TTCrx control. The interface to the I2C bus of the TTCrx chip consists of two registers: TTCrx Control Register RW_0030 TTCrx Status Register RO_0032 They provide access via I2C bus of the TTCrx chip to all the internal TTCrx registers. On page 15 of the the TTCrx manual ( [2] in APENDIX 2) there is a list of Default content (After reset) for internal registers of TTCrx, for example: - Control register (Address: 0x03) - data: 0x93 (1001_0011) - Config register 1 (Address: 0x13) - data: 0x1A (0001_1010) - Config register 2 (Address: 0x14) - data: 0x84 (1000_0100) - Config register 3 (Address: 0x15) - data: 0xA7 (1010_0111) - Status register (Address: 0x16) - data: 0xE0 (1110_0000) In order to access these 5 registers: - Write control data to the TTCrx Control Register RW_0030 this operation will start I2C operation to read from the TTCrx internal register - Read data from the TTCrx Status Register RO_0032: write 0x0002 to RW_0006 (Module Resets Register) to reset the TTCrx chip write 0x0300 to RW_0030 (Control Register) and read RO_0032 (TtcrxStatus), look at data (0x0093) write 0x1300 to RW_0030 (Control Register) and read RO_0032 (TtcrxStatus), look at data (0x001A) write 0x1400 to RW_0030 (Control Register) and read RO_0032 (TtcrxStatus), look at data (0x0084) write 0x1500 to RW_0030 (Control Register) and read RO_0032 (TtcrxStatus), look at data (0x00A7) write 0x1600 to RW_0030 (Control Register) and read RO_0032 (TtcrxStatus), look at data (0x00E0) XILINX System ACE controller ---------------------------- The System ACE MPU registers (96 8-bit registers) are mapped to the VME - addresses from 0x0080 to 0x00DF The access is word wide (16 bits), however due to even addressing scheme of VME bus one have to use the addresses as specified for byte wide access in the ACE manual (p. 20 in [4] in APENDIX 3, part 2) For correcr access to the internal System ACE registers, first need to set 16-bit WORD access mode: - write '1' to RW_0080 (BUSMODEREG) Then 32-bit RO STATUSREG at addresses 0x0084 and 0x0086 can be read (see p.22) and 16-bit RO VERSIONREG at address 0x0096 (see p.30 - value 0x100c) To test write operation, RW MPULBAREG can be used: 16-bits at address 0x0090 and 12-bits at address 0x0092 Summary: -------- - RO_0000 CMX Module ID and Module SN : expected value to read 0x[xx]33 ([xx] = SN) (after BSPT FPGA configuration) - RW_0012 SFP1 Data Register : expected value to read 0x0012 (after writing 0x016E to RW_0010 SFP1 Control/Status Register) - RW_0022 MiniPOD12 Data Register : expected value to read 0x0042 (after writing 0x0081 to RW_0020 MiniPOD12 Control/Status Register) - RO_0032 TtcrxStatus register : expected value to read 0x0093 (after TTCrx reset and writing 0x0300 to RW_0030 (TTCrx Control Register) - RO_0096 System ACE VERSIONREG : expected value to read 0x100c (after writing 0x0001 to RW_0080 BUSMODEREG) 2. Registers related to the whole CMX module ============================================ 2.1. Module Resets Register RW_0006 ----------------------------------- There is no power-on reset input to the BSPT FPGA from the CMX board. The input reset from the VME bus to BSPT FPGA - (OCB_SYS_RESET_B) - can be generated by software. In the cuttent version the OCB_SYS_RESET_B only reset the Module Resets Register (RW_0006). The output resets from the BSPT FPGA can be generated by writing a correspondent bit into RW_0006 Module Resets Register: Bit 01: Reset TTCrx - Writing a 1 to this bit resets TTCrx on the TTCDec card (500 ns pulse). Writing a 0 has no effect. Read back as zero. Generates Reset_b for TTCDec card (TTCrx chip reset). Bit 03: Reset System ACE - Writing a 1 to this bit resets the System ACE controller ( ns pulse) and reconfigure the BF and TP FPGAs with firmware corresponding to the module geographical address specified in the GEOADD Bypass field (Bits 03-00) in the Module Control Register (RW_0004). The Module Resets Register is also used to generate internal BSPT FPGA resets (500 ns pulse): Bit 00: Reset Module - Writing a 1 to this bit resets only Module Control Register RW_0004 Not connected to the BF or TP FPGAs Bit 02: Reset TTCrx I2C controller - Writing a 1 to this bit resets the I2C interface controller in the BSPT FPGA to the power on state. There are also resets for the optical componets and their I2C controllers in the BSPT FPGA (see x.x) Bit 08: Reset MiniPods 12 - Writing a 1 to this bit generates Reset_B for MiniPods 1,2 Bit 09: Reset MiniPods 12 I2C controller in the BSPT FPGA Bit 10: Reset MiniPods 345 - Writing a 1 to this bit generates Reset_B for MiniPods 3,4,5 Bit 11: Reset MiniPods 345 I2C controller in the BSPT FPGA Bit 12: Reset SFP1 I2C controller in the BSPT FPGA Bit 13: Reset SFP2 I2C controller in the BSPT FPGA Bit 14: Reset SFP3 I2C controller in the BSPT FPGA Bit 15: Reset SFP3 I2C controller in the BSPT FPGA 2.2. Module Control Register RW_0004 ------------------------------------ The Module Control Register (RW_0004) provides control on: - INT_GEOADD - TTCDec card with TTCrx chip - SFPs Transmitter INT_GEOADD ---------- Bits 03-00: INT_GEOADD_0 - (bit 00) and INT_GEOADD(2 downto 0) - bits (03-01) INT_GEOADD bits: these bits are set to the value of the OCB_GEO_ADRS_x pins of the backplane: bit 00 <- OCB_GEO_ADRS_0, bit 01 <- OCB_GEO_ADRS_4, bit 02 <- OCB_GEO_ADRS_5, bit 03 <- OCB_GEO_ADRS_6, - after BSPT FPGA configuration (by ACE reset internaly generated after configuration) - after Reset Module (writing '1' into bit 00 in RW_06 Module Resets Register (see 2.1) They are used then to define the CFGADDR bits for the XILINX System ACE controller in order to select appropriate CMX configuration from the CF card according to the CMX position in the L1Calo system (crate/slot) and to establish the module function. Bits 03-00 of RW_04 can be writted from VME and read back. This allow to define another CMX configuration on the CF card and reconfigure BF and TP FPGAs by Reset System ACE - writing 0x0008 to RW_0006 Module Resets Register. Note: VME and TTC address decoding is performed using the VME backplane geographical addressing pins OCB_GEO_ADRS_x (not INT_GEOADD bits) and so is not altered by changes made to the bits 03-00 of RW_04 from VME. TTCDec card control ------------------- Clock selection scheme on the TTCDec card: There are two input control bits (P/D Mode select and ClkSel clock select) and two output status bits (S1 - TTCReady and S2 - TTCrx clock is a clock source, see 2.3). The detailed function is as below. - P/D = 1: Protected Mode (Normal Running Mode) - ClkSel = 1: Select TTCrx as clock source, S1=TTCReady, S2 =1 - ClkSel = 0: Select XTAL as clock source, S1=TTCReady, S2 =0 - P/D = 0: Debug Mode - ClkSel = 1: Clock source automatic changeover - TTCReady = 1: Select TTCrx as clock source, S1 =1, S2 = 1 - TTCReady = 0: Select XTAL as clock source, S1 =0, S2 = 0 - ClkSel = 0: Select XTAL as clock source, S1=TTCReady, S2=0 S2 = '1' when TTCrx clock is a clock source The two control bits are set by 2 bits in Module Control Register RW_0004: Bit 04: TTCDec Clock Select When this bit is set, the TTCDec uses the TTCrx clock, otherwise - XTAL clock Trying to set this bit when the TTCrx is not ready has no effect (TTCrx Ready - bit 04 in RO_0008 ModuleStatus1, see 2.3) Bit 05: TTCDec P/D Mode Select This bit controls the TTCDec protection scheme described in the TTCDec specification After power-on the CMX card these two bits are set to zero. For the normal operationof the CMX card, both these bits have to be set to '1' bit 04 - TTCDec Clock Select -> '1' - TTCrx clock bit 05 - TTCDec P/D Mode Select -> '1' - Protected Mode (Normal Running Mode) SFP Transmitters ---------------- TX_DISABLE pin on the SFP transmitter allows the BSPT to turn off the laser in the transmitter. Bit 12: SFP1_TX_DISABLE - SFP1 Transmitter Disable (DAQ?) Bit 13: SFP2_TX_DISABLE - SFP2 Transmitter Disable (ROI?) Bit 14: SFP3_TX_DISABLE - SFP3 Transmitter Disable Bit 15: SFP4_TX_DISABLE - SFP4 Transmitter Disable 2.3. Module Status 1 Register RO_0008 ------------------------------------- This register allow monitoring the status information for: - XILINX System ACE controller - BF and TP FPGAs configuration - TTCDec card with TTCrx chip - PLL lock - MiniPODs interrupts Bit 00: System ACE Status - When on, the Status LED indicates that configuration is DONE. Bit 01: System ACE Error - When this bit is set, an error occurred during FPGA configuration Bit 02: BF_CONFIG_DONE - This bit is set if the BASE_FPGA has been configured correctly - DONE from BASE_FPGA Bit 03: TP_CONFIG_DONE - This bit is set if the TOPO_FPGA has been configured correctly - DONE from TOPO_FPGA Bit 04: TTCrx Ready - This bit is set when the TTCrx on TTCDec card is ready. Bit 05: Status2 - This bit is set when TTCrx is the clock source on the TTCDec card Bit 07-06: null Bit 08: Lock Monitor VCXO_PLL DeScew-1 (BSPT_DEBUG_5) Bit 09: Lock Monitor VCXO_PLL DeScew-2 (BSPT_DEBUG_7) Bit 10: Lock Monitor VCXO_PLL 320 MHz (BSPT_DEBUG_6)RO_R Bit 11: MP1_INTRPT_B - MiniPOD 1 Interrupt_B Bit 12: MP2_INTRPT_B - MiniPOD 2 Interrupt_B Bit 13: MP3_INTRPT_B - MiniPOD 3 Interrupt_B Bit 14: MP4_INTRPT_B - MiniPOD 4 Interrupt_B Bit 15: MP5_INTRPT_B - MiniPOD 5 Interrupt_B 2.4. Module Status 2 Register RO_000A ------------------------------------- This register allow monitoring the status of SFP transmitters: TX_FAULT signal allows the BSPT FPGA to know if there are problems with the laser transmitter. MOD_PRESENT signal tells the BSPT whether or not a component is plugged into the SFP socket. RX_LOS indicates that the optical input is absent or unusable. Bit 00: SFP1_TX_FAULT - SFP1 Transmitter Fault => def 0 (module operational) Bit 01: SFP1_MOD_PRESENT - SFP1 Module Present => def 1 (module installed) Bit 02: SFP1_RX_LOST - SFP1 Receiver Signal Loss => def 1 (no optical fibre connected) Bit 04: SFP2_TX_FAULT - SFP2 Transmitter Fault Bit 05: SFP2_MOD_PRESENT - SFP2 Module Present Bit 06: SFP2_RX_LOST - SFP2 Receiver Signal Loss Bit 08: SFP3_TX_FAULT - SFP3 Transmitter Fault Bit 09: SFP3_MOD_PRESENT - SFP3 Module Present Bit 10: SFP3_RX_LOST - SFP3 Receiver Signal Loss Bit 12: SFP4_TX_FAULT - SFP4 Transmitter Fault Bit 13: SFP4_MOD_PRESENT - SFP4 Module Present Bit 14: SFP4_RX_LOST - SFP4 Receiver Signal Loss 3. Registers related to the CTP/BP LVDS Links Mngmnt ==================================================== The CMX LVDS Connections are described in the note on the MSU web page: http://www.pa.msu.edu/hep/atlas/l1calo/cmx/hardware/details/cmx_ab_lvds_connections.txt 3.1. CTP LVDS Connectors Management signals ------------------------------------------- The control logic in the BSPT firmware listens to the following 8 input signals: BF_CONFIG_DONE - accessible for monitoring via RO_0008(02) TP_CONFIG_DONE - accessible for monitoring via RO_0008(03) TP_FPGA_INSTALLED_B - accessible for monitoring via RO_000C(00) ALLOW_BUSSED_IO - accessible for monitoring via RO_000C(01) BF_REQ_CTP_1_INPUT - accessible for monitoring via RO_000C(02) TP_REQ_CTP_1_INPUT - accessible for monitoring via RO_000C(03) BF_REQ_CTP_2_INPUT - accessible for monitoring via RO_000C(04) TP_REQ_CTP_2_INPUT - accessible for monitoring via RO_000C(05) The control logic in the BSPT firmware generates 10 output signals according to the Dan's proposal: CTP Connector Management Logic in the BSPT FPGA: http://www.pa.msu.edu/hep/atlas/l1calo/cmx/hardware/drawings/circuit_diagrams/22_ctp_connector_management.pdf http://www.pa.msu.edu/hep/atlas/l1calo/cmx/hardware/drawings/circuit_diagrams/23_ctp_connector_bstp_logic.pdf CTP_1_TRNCVR_DIR - accessible for monitoring via RO_000C(06) CTP_1_BF_TRNSLT_DIR - accessible for monitoring via RO_000C(07) BSPT_CTP_1_BF_TRNSLT_OE_B - accessible for monitoring via RO_000C(08) CTP_1_TP_TRNSLT_DIR - accessible for monitoring via RO_000C(09) BSPT_CTP_1_TP_TRNSLT_OE_B - accessible for monitoring via RO_000C(10) CTP_2_TRNCVR_DIR - accessible for monitoring via RO_000C(11) CTP_2_BF_TRNSLT_DIR - accessible for monitoring via RO_000C(12) BSPT_CTP_2_BF_TRNSLT_OE_B - accessible for monitoring via RO_000C(13) CTP_2_TP_TRNSLT_DIR - accessible for monitoring via RO_000C(14) BSPT_CTP_2_TP_TRNSLT_OE_B - accessible for monitoring via RO_000C(15) 3.2. Backplane LVDS Cables Managements -------------------------------------- The control logic in the BSPT firmware listens to the following 5 signals: BF_CONFIG_DONE - accessible for monitoring via RO_0008(02) ALLOW_BUSSED_IO - accessible for monitoring via RO_000C(01) BF_REQ_CABLE_1_INPUT - accessible for monitoring via RO_000E(00) BF_REQ_CABLE_2_INPUT - accessible for monitoring via RO_000E(04) BF_REQ_CABLE_3_INPUT - accessible for monitoring via RO_000E(08) The control logic in the BSPT firmware generates the 9 control signals according to the Dan's proposal: Backplane LVDS Cable Management in the BSPT FPGA: http://www.pa.msu.edu/hep/atlas/l1calo/cmx/hardware/drawings/circuit_diagrams/21_backplane_cable_management.pdf CABLE_1_TRNCVR_DIR - accessible for monitoring via RO_000E(01) CABLE_1_TRNSLT_DIR - accessible for monitoring via RO_000E(02) BSPT_CABLE_1_TRNSLT_OE_B - accessible for monitoring via RO_000E(03) CABLE_2_TRNCVR_DIR - accessible for monitoring via RO_000E(05) CABLE_2_TRNSLT_DIR - accessible for monitoring via RO_000E(06) BSPT_CABLE_2_TRNSLT_OE_B - accessible for monitoring via RO_000E(07) CABLE_3_TRNCVR_DIR - accessible for monitoring via RO_000E(09) CABLE_3_TRNSLT_DIR - accessible for monitoring via RO_000E(10) BSPT_CABLE_3_TRNSLT_OE_B - accessible for monitoring via RO_000E(11) 3.3. Signal monitoring ---------------------- All above signals (30 in total) are accessible for monitoring: Module Status 1 Register RO_0008 (see 2.3): Bit 02: BF_CONFIG_DONE - This bit is set if the BASE_FPGA has been configured correctly - DONE from BASE_FPGA Bit 03: TP_CONFIG_DONE - This bit is set if the TOPO_FPGA has been configured correctly - DONE from TOPO_FPGA CTP/BP LVDS Links Mngmnt register RO_000C: Bit 00: TP_FPGA_INSTALLED_B Bit 01: ALLOW_BUSSED_IO Bit 02: BF_REQ_CTP_1_INPUT Bit 03: TP_REQ_CTP_1_INPUT Bit 04: BF_REQ_CTP_2_INPUT Bit 05: TP_REQ_CTP_2_INPUT Bit 06: CTP_1_TRNCVR_DIR Bit 07: CTP_1_BF_TRNSLT_DIR Bit 08: BSPT_CTP_1_BF_TRNSLT_OE_B Bit 09: CTP_1_TP_TRNSLT_DIR Bit 10: BSPT_CTP_1_TP_TRNSLT_OE_B Bit 11: CTP_2_TRNCVR_DIR Bit 12: CTP_2_BF_TRNSLT_DIR Bit 13: BSPT_CTP_2_BF_TRNSLT_OE_B Bit 14: CTP_2_TP_TRNSLT_DIR Bit 15: BSPT_CTP_2_TP_TRNSLT_OE_B CTP/BP LVDS Links Mngmnt register RO_000E: Bit 00: BF_REQ_CABLE_1_INPUT Bit 01: CABLE_1_TRNCVR_DIR Bit 02: CABLE_1_TRNSLT_DIR Bit 03: BSPT_CABLE_1_TRNSLT_OE_B Bit 04: BF_REQ_CABLE_2_INPUT Bit 05: CABLE_2_TRNCVR_DIR Bit 06: CABLE_2_TRNSLT_DIR Bit 07: BSPT_CABLE_2_TRNSLT_OE_B Bit 08: BF_REQ_CABLE_3_INPUT Bit 09: CABLE_3_TRNCVR_DIR Bit 10: CABLE_3_TRNSLT_DIR Bit 11: BSPT_CABLE_3_TRNSLT_OE_B 3.4. Example ------------ CMX SN01 (left position in the L1Calo test rig in Bld.104) with BF and TP FPGAs After configuration BF FPGA doesn't request inputs: BF_REQ_CTP_1_INPUT <= '0'; RO_000C(02) - OK BF_REQ_CTP_2_INPUT <= '0'; RO_000C(04) - OK BF_REQ_CABLE_1_INPUT <= '0'; RO_000E(00) - OK BF_REQ_CABLE_2_INPUT <= '0'; RO_000E(04) - OK BF_REQ_CABLE_3_INPUT <= '0'; RO_000E(08) - OK Module Status 1 Register RO_0008: F814 -> 1111_1000_0001_0100 Bit 02: BF_CONFIG_DONE 1 OK (configured) Bit 03: TP_CONFIG_DONE 0 OK (not (configured) CTP/BP LVDS Links Mngmnt register RO_000C: DEEA -> 1101_1110_1110_1010 http://www.pa.msu.edu/hep/atlas/l1calo/cmx/hardware/drawings/circuit_diagrams/22_ctp_connector_management.pdf http://www.pa.msu.edu/hep/atlas/l1calo/cmx/hardware/drawings/circuit_diagrams/23_ctp_connector_bstp_logic.pdf Bit 00: TP_FPGA_INSTALLED_B 0 OK (TP FPGA installed) Bit 01: ALLOW_BUSSED_IO 1 OK (allowed) - Bit 02: BF_REQ_CTP_1_INPUT 0 OK (doesn't request) Bit 03: TP_REQ_CTP_1_INPUT 1 OK (request) Bit 04: BF_REQ_CTP_2_INPUT 0 OK (doesn't request) Bit 05: TP_REQ_CTP_2_INPUT 1 OK (request) - Bit 06: CTP_1_TRNCVR_DIR 1 DRV_ENB=1 (sending out) Bit 07: CTP_1_BF_TRNSLT_DIR 1 DIR=1 (sending out) Bit 08: BSPT_CTP_1_BF_TRNSLT_OE_B 0 OE_B=0 (enabled) Bit 09: CTP_1_TP_TRNSLT_DIR 1 DIR=1 (sending out) Bit 10: BSPT_CTP_1_TP_TRNSLT_OE_B 1 OE_B=1 (disabled) - Bit 11: CTP_2_TRNCVR_DIR 1 DRV_ENB=1 (sending out) Bit 12: CTP_2_BF_TRNSLT_DIR 1 DIR=1 (sending out) Bit 13: BSPT_CTP_2_BF_TRNSLT_OE_B 0 OE_B=0 (enabled) Bit 14: CTP_2_TP_TRNSLT_DIR 1 DIR=1 (sending out) Bit 15: BSPT_CTP_2_TP_TRNSLT_OE_B 1 OE_B=1 (disabled) CTP/BP LVDS Links Mngmnt register RO_000E: 0666 -> 0000_0110_0110_0110 http://www.pa.msu.edu/hep/atlas/l1calo/cmx/hardware/drawings/circuit_diagrams/21_backplane_cable_management.pdf Bit 00: BF_REQ_CABLE_1_INPUT 0 OK (doesn't request) Bit 01: CABLE_1_TRNCVR_DIR 1 DRV_ENB=1 (sending out) Bit 02: CABLE_1_TRNSLT_DIR 1 DIR=1 (sending out) Bit 03: BSPT_CABLE_1_TRNSLT_OE_B 0 OE_B=0 (enabled) - Bit 04: BF_REQ_CABLE_2_INPUT 0 OK (doesn't request) Bit 05: CABLE_2_TRNCVR_DIR 1 DRV_ENB=1 (sending out) Bit 06: CABLE_2_TRNSLT_DIR 1 DIR=1 (sending out) Bit 07: BSPT_CABLE_2_TRNSLT_OE_B 0 OE_B=0 (enabled) - Bit 08: BF_REQ_CABLE_3_INPUT 0 OK (doesn't request) Bit 09: CABLE_3_TRNCVR_DIR 1 DRV_ENB=1 (sending out) Bit 10: CABLE_3_TRNSLT_DIR 1 DIR=1 (sending out) Bit 11: BSPT_CABLE_3_TRNSLT_OE_B 0 OE_B=0 (enabled) 4. Registers related to the optical components access via I2C ============================================================= The CMX Low Speed Optical Components (SFP) are described in the note on the MSU web page: http://www.pa.msu.edu/hep/atlas/l1calo/cmx/hardware/details/cmx_ab_low_speed_optical.txt The CMX High Speed Optical Components (MiniPOD) are described in the note on the MSU web page: http://www.pa.msu.edu/hep/atlas/l1calo/cmx/hardware/details/cmx_ab_high_speed_optical.txt The I2C controllers, which control the access to the optical components via I2C buses, are accessible from VME via 2 registers: Control/Status Register and Data Register. Detailed description is provided in: APENDIX 1 Opto_VME_I2C_access (access to optical components via I2C) 5. Registers related to the LEDs control ======================================== The CMX LEDs on the Front Panel are described in the note on the MSU web page: http://www.pa.msu.edu/hep/atlas/l1calo/cmx/hardware/details/cmx_ab_leds_on_front_panel.txt The LEDs are driven by the BSPT FPGA, however traces have been provided on the CMX card to carry LED request signals from the Base Function FPGA (5 signals) and from the Topological FPGA (5 signals) to the BSPT FPGA. The mapping of which Front Panel LED is illuminated in response to one of these LED request signals is yet to be defined. The FPGA I/O pin must be set Low to cause the associated LED to illuminate. In the current version (v3) of the BSPT FPGA FW two registers are implemented: - a RW register to turn every LED on the front panel on/off. Bit(00) of this register is used to control the data source for LED: this register or internal BSPT FPGA signal. - a RO register to read a status of LED requests from Base Function and Topological FPGAs. (see 1.5 in the file CMX VME registers/memories map v3 "vme_map_v3_20140617.txt") 5.1. LEDs Control register RW_0028 ----------------------------------- Bit 00: LEDs Control - when '0', LEDs illuminated by internal BSPT FPGA signal Writing a '1' to this bit sets the LEDs control to this register (bits 15-01) Bit 01: LED_1R_GREEN - default value (bit 00 = '0') <= TTCrx Ready Bit 02: LED_2L_GREEN - default value (bit 00 = '0') <= BF FPGA configured Bit 03: LED_2R_GREEN - default value (bit 00 = '0') <= TP FPGA configured Bit 04: LED_3L_GREEN Bit 05: LED_3L_RED Bit 06: LED_3R_GREEN Bit 07: LED_3R_RED Bit 08: LED_4L_GREEN Bit 09: LED_4L_RED Bit 10: LED_4R_GREEN Bit 11: LED_4R_RED Bit 12: LED_5L_GREEN Bit 13: LED_5L_RED Bit 14: LED_5R_GREEN Bit 15: LED_5R_RED All internal signal currently set High - LEDs are NOT illuminated 5.2. LEDs Requests Status register RO_002A ------------------------------------------ Bit 00: BF_LED_REQ_0 Bit 01: BF_LED_REQ_1 Bit 02: BF_LED_REQ_2 Bit 03: BF_LED_REQ_3 Bit 04: BF_LED_REQ_4 Bit 08: TP_LED_REQ_0 Bit 09: TP_LED_REQ_1 Bit 10: TP_LED_REQ_2 Bit 11: TP_LED_REQ_3 Bit 12: TP_LED_REQ_4 6. Registers related to debugging signals ========================================= RO_002C BF and TP debug signals: Bit 00: BF_TO_FROM_BSPT_0 Bit 01: BF_TO_FROM_BSPT_1 Bit 02: BF_TO_FROM_BSPT_2 Bit 03: BF_TO_FROM_BSPT_3 Bit 04: BF_TO_FROM_BSPT_4 Bit 05: BF_TO_FROM_BSPT_5 Bit 06: BF_TO_FROM_BSPT_6 Bit 07: BF_TO_FROM_BSPT_7 Bit 08: TP_TO_FROM_BSPT_0 Bit 09: TP_TO_FROM_BSPT_1 Bit 10: TP_TO_FROM_BSPT_2 Bit 11: TP_TO_FROM_BSPT_3 Bit 12: TP_TO_FROM_BSPT_4 Bit 13: TP_TO_FROM_BSPT_5 Bit 14: TP_TO_FROM_BSPT_6 Bit 15: TP_TO_FROM_BSPT_7 RO_002E BSPT debug signals: Bit 00: BSPT_DEBUG_0 Bit 01: BSPT_DEBUG_1 Bit 02: BSPT_DEBUG_2 Bit 03: BSPT_DEBUG_3 Bit 04: BSPT_DEBUG_4 Bit 05: BSPT_DEBUG_8 Bit 06: BSPT_DEBUG_9 Bit 07: SPR_Conn_BSPT_Pin_A2 Bit 08: SPR_Conn_BSPT_Pin_B1 Bit 09: SPR_Conn_BSPT_Pin_J8 Bit 10: SPR_Conn_BSPT_Pin_K8 Bit 11: SPR_Conn_BSPT_Pin_M6 Bit 12: SPR_Conn_BSPT_Pin_M7 Bit 13: SPR_Conn_BSPT_Pin_M8 7. Registers related to the TTCrx chip on the TTCDec card ========================================================= 7.1. TTCrx reset ---------------- The reset of the TTCrx chip may be needed after BSPT configuration. In order to reset the TTCrx chip, write '1' in bit 01 of the Module Resets Register RW_0006 (see 2.1). Bit 01: Reset TTCrx - Writing a 1 to this bit resets TTCrx on the TTCDec card (500 ns pulse). Writing a 0 has no effect. Read back as zero. Generates Reset_b for TTCDec card (TTCrx chip reset). 7.2. I2C controller ------------------- The interface to the I2C bus of the TTCrx chip consists of two registers: TTCrx Control Register RW_0030 TTCrx Status Register RO_0032 They provide access via I2C bus of the TTCrx chip to all the internal TTCrx registers. - The TTCrx Control Register RW_0030 A TTCrx I/O operation takes place whenever this register is changed, unless the I2C bus is busy. An I2C operation is aborted if the reset bit is set. Bits 00–07: Data to TTCrx - This 8-bit field contains data to be written to the TTCrx chip. (the byte-values to be written into the I2C_data register of TTCrx). Bits 08-12: TTCrx Register Number - Specify the TTCrx register number to be read or written (the address of the internal register of the TTCrx chip to be written into the I2C_pointer register). Bit 13 : Write - When set to 1, defines the operation as a write to the TTCrx register. When set to 0, the operation is a read from the TTCrx internal register. Bit 14 : null Bit 15 : TTCrx Controller Abort When set to 1, resets the I2C interface logic in the BSPT FPGA and aborts any I2C operation in progress. - The TTCrx Status Register RO_0032 Bits 00-07: Data from TTCrx - This 8-bit field contains data read from the TTCrx chip (Bit 13 - Write - of TTCrx Control Register is set to 0). Bits 08-12: null Bit 13 : I2C Busy - When set to 1, indicates that an I2C transaction is underway Bit 14 : I2C Error - When set to 1, indicates that an I2C error has occurred Bit 15 : null Detailed description is provided in: APENDIX 2 TTCrx control 7.3. TTCrx status ----------------- TTCDec Brcst Register RO_0034 - The most recent value of BRCST data bits TTCDec DQ Register RO_0036 - The most recent DQ value output from the TTCrx TTCDec Dump RAM RO addresses from 0040 to 005E A block of RAM 16 words deep that captures data from TTC Error and Configuration Dumps. Data from the TTC are mapped to the RAM using DQ as the address. 8. Registers related to the XILINX System ACE chip ================================================== The System ACE controller can be reset via bit 3 in RW_0006 Module Resets Register Bit 03: Reset System ACE - Writing a 1 to this bit resets the System ACE controller (1500ns pulse) and reloads the BF and TP FPGAs with firmware corresponding to the module geographical address specified in the GEOADD Bypass field (Bits 03-00) in the Module Control Register (RW_0004). The System ACE MPU registers (96 8-bit registers) are mapped to the VME - addresses from 0x0080 to 0x00DF The access is word wide (16 bits), however due to even addressing scheme of VME bus one have to use the addresses as specified for byte wide access in the ACE manual (p. 20 in [4] in APENDIX 3, part 2) For correcr access to the internal System ACE registers, first need to set 16-bit WORD access mode: - write '1' to RW_0080 (BUSMODEREG) Then 32-bit RO STATUSREG at addresses 0x0084 and 0x0086 can be read (see p.22) and 16-bit RO VERSIONREG at address 0x0096 (see p.30 - value 0x100c) To test write operation, RW MPULBAREG can be used: 16-bits at address 0x0090 and 12-bits at address 0x0092 9. Temporary registers for tests ================================ To test the reliability of the access to the internal registers from VME a sophisticated program in Python was written by Philippe Laurens. It can be run, for example, on the array of 16 test registers ====================================================================================== ====================================================================================== APENDIX 1 Opto_VME_I2C_access =================== 1. Introduction 2. MiniPOD 2.1. Address inputs, Adr[2:0] 2.2. Interrupt output, IntL 2.3. Reset input, ResetL 2.4. Two-Wire Serial, TWS (I2C) 3. SFP Transceivers 3.1. Transmit Disable (Tx_Disable) input 3.2. Transmit Fault (Tx_Fault) output 3.3. Receiver Loss of Signal (Rx_LOS) output 3.4. Module Present output 4. Examples 4.1. Reading byte 110 (hex 6E) from the SFP1 second page 4.2. Write/read to byte 128 (hex 80) on the SFP1 second page 4.3. Reading byte 2 (0x02) from the MiniPOD1 Lower Memory Page 4.4. Reading byte 129 (0x81) from the MiniPOD1 Upper Memory Page 00h 4.5. Reading byte 128 (0x80) from the MiniPOD1 Upper Memory Page 01h - TBD 1. Introduction =============== This description is based on the following sources: [1] MiniPOD™ 10 Gbps/Channel Twelve Channel, Parallel Fiber Optics Modules (AFBR-81uVxyZ_miniPod_DS.pdf) upon request [2] Atmel Two-wire Serial EEPROM (Atmel AT24C01A _doc0180.pdf) http://www.pa.msu.edu/hep/atlas/l1calo/cmx/hardware/components/optical/sfp/atmel_serial_eeprom_at24c01a.pdf [3] AFBR-57M5APZ SFP Digital Diagnostic Optical Transceiver (AV02-3804EN+DS+AFBR-57M5APZ+23Jan2013.pdf) http://www.pa.msu.edu/hep/atlas/l1calo/cmx/hardware/components/optical/sfp/avago_afbr_57m5apz_sfp_optical_transceiver.pdf [4] Digital Diagnostic Monitoring Interface (DMI) on Avago Enterprise and Storage Fiber Optic Transceivers: Applications and Implementation, Application Note 5016 (AV01-0244EN+AN_5016+03Aug10.pdf http://www.pa.msu.edu/hep/atlas/l1calo/cmx/hardware/components/optical/transceivers/avago_note_5016_monitoring_interface_03Aug10.pdf [5] 14_high_speed_minipod_optical.pdf http://www.pa.msu.edu/hep/atlas/l1calo/cmx/hardware/drawings/circuit_diagrams/14_high_speed_minipod_optical.pdf [6] 13_low_speed_sfp_optical.pdf http://www.pa.msu.edu/hep/atlas/l1calo/cmx/hardware/drawings/circuit_diagrams/13_low_speed_sfp_optical.pdf [7] CMX VME registers/memories map v2 (vme_map_v2_20140417.txt) http://www.pa.msu.edu/hep/atlas/l1calo/cmx/firmware/fpga_bspt_fw/vme_map_v2_20140417.txt This note provide a short information from above sources, for the full information read originals. This note describes the access to the internal registers of the MiniPOD and SFP optical components on the CMX card: - 2 Avago MiniPOD AFBR-811VxyZ(Transmitter) chips on one I2C bus (MP12 I2C bus), - 3 Avago MiniPOD AFBR-821VxyZ (Receiver) chips on the second I2C bus (MP345 I2C bus), - 4 Avago SFP Transceivers on 4 individual I2C buses. The I2C controllers, which control the access to the optical components via I2C buses, are accessible from VME via 2 registers: Control/Status Register and Data Register. Illustration: BSPT FPGA |-------------------------| |--------| |--------| |-----| | I2C controller: | Adr1->|MiniPOD1| Adr2->|MiniPOD2| | SBC |<--->| Control/Status Register | |----|---| |----|---| |-----| VME | Data Register |<->----------|-----------------| |-------------------------| I2C The detailed desctiption of the CMX VME registers/memories map is in [7]: 2. Proposal for the CMX Board Support FPGA (BSPT_FPGA) VME register map The VME-- base address ranges for CMX modules: CrateSlotNumber Module VME-- address 3 CMX0 0x00700000-0x0077FFFE 20 CMX1 0x00780000-0x007FFFFE BSPT_FPGA address range: 256 bytes 3 CMX0 0x00700000-0x007000FF 20 CMX1 0x00780000-0x007800FF 2. MiniPOD ========== Control Interface and Memory Map of the MiniPOD is desribed in [1], p.26: The control interface combines dedicated signal lines for - address inputs, Adr[2:0], - interrupt output, IntL, - reset input, ResetL, - two-wire serial, TWS (I2C): interface clock, SCL, and data, SDA The TWS interface is implemented as a slave device and compatible with industry standard two-wire serial protocol. In general, TWS bus timing and protocols follow the implementation popularized in Atmel Two-wire Serial EEPROMs [2]. 2.1. Address inputs, Adr[2:0] ----------------------------- The address signals, Adr2, Adr1 and Adr0, provide the ability to program the TWS bus address of the module. On CMX, the Adr2, Adr1 and Adr0 oins of MiniPODs are hirdwired [5]: 2 Avago MiniPOD AFBR-811VxyZ(Transmitter) chips have addresses on MP12 I2C bus: MiniPOD 1 (MP1) = "000" MiniPOD 2 (MP2) = "001" 3 Avago MiniPOD AFBR-821VxyZ (Receiver) chips have addresses on MP345 I2C bus: MiniPOD 3 (MP3) = "000" MiniPOD 4 (MP4) = "001" MiniPOD 5 (MP5) = "010" 2.2. Interrupt output, IntL --------------------------- An interrupt signal, IntL, is used to alert the host of a loss of input signal (LOS), transmitter fault conditions and/ or assertion of any monitor flag. This reduces the need for dedicated status signal lines and polling the status and monitor registers while maintaining timely alerts to significant events. IntL can be programmed (page 01h byte 225 bit 0) to either pulse or static mode with static as the default mode. The status of MiniPOD interrupt outputs can be read from CMX Module Satus 1 Read Only (RO) Register at the VME address 0008 Bit 10: MP1_INTRPT_B - MiniPOD 1 Interrupt_B Bit 11: MP2_INTRPT_B - MiniPOD 2 Interrupt_B Bit 12: MP3_INTRPT_B - MiniPOD 3 Interrupt_B Bit 13: MP4_INTRPT_B - MiniPOD 4 Interrupt_B Bit 14: MP5_INTRPT_B - MiniPOD 5 Interrupt_B 2.3. Reset input, ResetL ------------------------ A dedicated module reset signal, ResetL, is provided in case the TWS interface becomes dysfunctional. When ResetL is asserted, the outputs are disabled, TWS interface commands are inhibited and the module returns to factory default settings except Non-volatile Read-Write (RW) registers which retain the last write. A module register (memory map except the non-volatile registers) reset can also be initiated over the TWS interface (TX page 5ih or RX page 6ih byte 91, bit 0). A TWS reset can be initiated by nine SCL clock cycles with SDA high in each cycle and creating a start condition. The reset signals for the MiniPODs can be generated by writing to the CMX Module Resets Register at the VME address 0006. Bit 08: Reset MiniPods 12 - Writing a 1 to this bit generates Reset_B for MiniPods 1,2 Bit 10: Reset MiniPods 345 - Writing a 1 to this bit generates Reset_B for MiniPods 3,4,5 All bits read back as zero, and writing a zero to a bit has no effect. 2.4. Two-Wire Serial, TWS (I2C) ------------------------------- The I2C interface used to access the 256 user accessible internal registers of the MiniPOD. Figure 34 on page 30 [1] presents an overview of the memory structure showing a lower page and two upper pages. Access to the internal registers provided via 2 VME registers for each I2C bus: Control/Status Register and Data Register [7]: Transmitters MP1 and MP2 on MP12 I2C bus: 0020 RW MP12 Control/Status Register 0022 RW MP12 Data Register Receivers MP3, MP4 and MP5 on MP345 I2C bus: 0024 RW MP345 Control/Status Register 0026 RW MP345 Data Register Control/Status Register for I2C bus controller ---------------------------------------------- Bits (13-00) are Read/Write (RW) inputs to the CMX, Bits (15-14) are RO outputs from CMX - MiniPOD I2C controller status Power-up condition initially sets all bits to 0. A MiniPOD I2C I/O operation takes place whenever this register is written unless the I2C bus is busy Bits 07–00: MiniPOD Register Number Specify the internal MiniPOD register number to be read or written. Bits 10-08: MiniPOD TWS Module Bus Address bits Adr[2:0] Specify the MiniPOD address: MiniPOD 1 (MP1) = "000" MiniPOD 2 (MP2) = "001" Bit 11: Write: When set to 1, defines the operation as a write to MiniPOD. When set to 0, the operation is a read. Bit 12: MP12 I2C controller Abort: When set to 1, resets the I2C interface logic and aborts any I2C operation in progress. Bit 13: null Bit(RO) 14: MP12 I2C controller Busy When set to 1, indicates that an I2C transaction is underway Bit(RO) 15: MP12 I2C controller Error When set to 1, indicates that an I2C error has occurred Data Register for I2C bus controller ------------------------------------ Bits(07-00) are RO outputs from CMX (data from MMiniPOD) Bits(15-08) are RW inputs to the CMX (data to MiniPOD) Bits 07-00: Data from MiniPOD This 8-bit field contains last data read from MiniPOD Writing to these bits has no effect Bits 15–08: Data to MiniPOD This 8-bit field contains data to be written to MiniPOD Read back the value written to these bits (not to MiniPOD) Read/Write access ----------------- To WRITE the data into writable internal register of the MiniPOD: - write data to bits 15-8 of the Data Register - write control data to the Control/Status Register (starts I2C operation) To READ the data from the internal register of the MiniPOD: - write control data to the Control/Status Register (starts I2C operation) - read the data from bits 7-0 of the Data Register I2C bus controller reset ------------------------ The MiniPOD I2C bus controllers can be reset by writing to the CMX Module Resets Register at the VME address 0006. Bit 09: Reset MiniPods 12 I2C controller Bit 11: Reset MiniPods 345 I2C controller 3. SFP Transceivers =================== Control Interface and Memory Map of the SFP is desribed in [3], p.3 and [4]. The control interface combines dedicated signal lines for - Transmit Disable (Tx_Disable) input, - Transmit Fault (Tx_Fault) output, - Receiver Loss of Signal (Rx_LOS) output, - Module Present output, - two-wire serial, TWS (I2C): interface clock, SCL, and data, SDA (similar to MiniPOD) 4 Avago SFP (SFP1 to SFP4) Transceivers are on on 4 individual I2C buses. 3.1. Transmit Disable (Tx_Disable) ---------------------------------- The AFBR-57M5APZ accepts a TTL and CMOS compatible transmit disable control signal input (pin 3) which shuts down the transmitter optical output. A high signal implements this function while a low signal allows normal transceiver operation. The Transmit Disable signals for the SFPs can be generated by writing to the CMX Module Control Register at the VME address 0004: Bit 12: SFP1_TX_DISABLE - SFP1 Transmitter Disable (DAQ?) Bit 13: SFP2_TX_DISABLE - SFP2 Transmitter Disable (ROI?) Bit 14: SFP3_TX_DISABLE - SFP3 Transmitter Disable Bit 15: SFP4_TX_DISABLE - SFP4 Transmitter Disable TX_DISABLE allows the BSPT to turn off the laser in the transmitter. 3.2. Transmit Fault (Tx_Fault) output ------------------------------------- A catastrophic laser fault will activate the transmitter signal, TX_FAULT, and disable the laser. This signal is an open collector output (pull-up required on the host board). A low signal indicates normal laser operation and a high signal indicates a fault. The TX_FAULT will be latched high when a laser fault occurs and is cleared by toggling the TX_DISABLE input or power cycling the transceiver. The transmitter fault condition can also be monitored via the two-wire serial interface (address A2, byte 110, bit 2). The status of SFP Transmit Fault outputs can be read from CMX Module Satus 2 Read Only (RO) Register at the VME address 000A: Bit 00: SFP1_TX_FAULT - SFP1 Transmitter Fault => def 0 (module operational) Bit 04: SFP2_TX_FAULT - SFP2 Transmitter Fault Bit 08: SFP3_TX_FAULT - SFP3 Transmitter Fault Bit 12: SFP4_TX_FAULT - SFP4 Transmitter Fault TX_FAULT signal allows the BSPT FPGA to know if there are problems with the laser transmitter. 3.3. Receiver Loss of Signal (Rx_LOS) output -------------------------------------------- The post-amplification IC also includes transition detection circuitry which monitors the ac level of incoming optical signals and provides a TTL/CMOS compatible status signal to the host (pin 8). An adequate optical input results in a low Rx_LOS output while a high Rx_LOS output indicates an unusable optical input. The Rx_LOS thresholds are factory set so that a high output indicates a definite optical fault has occurred. Rx_LOS can also be monitored via the two-wire serial interface (address A2h, byte 110, bit 1). The status of SFP Receiver Loss of Signal (Rx_LOS) output can be read from CMX Module Satus 2 Read Only (RO) Register at the VME address 000A: Bit 02: SFP1_RX_LOS - SFP1 Receiver Signal Loss => def 1 (no optical fibre connected) Bit 06: SFP2_RX_LOS - SFP2 Receiver Signal Loss Bit 10: SFP3_RX_LOS - SFP3 Receiver Signal Loss Bit 14: SFP4_RX_LOS - SFP4 Receiver Signal Loss 3.4. Module Present output -------------------------- The status of SFP Module Present output can be read from CMX Module Satus 2 Read Only (RO) Register at the VME address 000A: Bit 01: SFP1_MOD_PRESENT - SFP1 Module Present->Low => def 0 (module installed) Bit 05: SFP2_MOD_PRESENT - SFP2 Module Present->Low Bit 09: SFP3_MOD_PRESENT - SFP3 Module Present->Low Bit 13: SFP4_MOD_PRESENT - SFP4 Module Present->Low MOD_PRESENT signal tells the BSPT whether or not a component is plugged into the SFP socket. 3.5 Two-Wire Serial, TWS (I2C) ------------------------------ The I2C interface used to access the 2x256 user accessible internal registers of the SFP. Figure 1 on page 2 [4] presents an overview of the memory structure showing two pages. Access to the internal registers provided via 2 VME registers for each I2C bus: Control/Status Register and Data Register [7] (similar to MiniPOD): 0010 RW SFP1 Control/Status Register 0012 RW SFP1 Data Register 0014 RW SFP2 Control/Status Register 0016 RW SFP2 Data Register 0018 RW SFP3 Control/Status Register 001A RW SFP3 Data Register 001C RW SFP4 Control/Status Register 001E RW SFP4 Data Register Control/Status Register for I2C bus controller ---------------------------------------------- Bits (13-00) are Read/Write (RW) inputs to the CMX, Bits (15-14) are RO outputs from CMX - SFP I2C controller status Power-up condition initially sets all bits to 0. A SFP I2C I/O operation takes place whenever this register is written unless the I2C bus is busy. Bits 07–00: SFP1 Register Number Specify the internal SFP register number to be read or written (see [4]). Bit 08: SFP1 Page: 0 => SFP1 first page (256 bytes) 1010000X (0xA0) 1 => SFP1 second page 1010001X (0xA2) Bits 10-09: null Bit 11: Write: When set to 1, defines the operation as a write to SFP1. When set to 0, the operation is a read. Bit 12: SFP1 I2C controller Abort: When set to 1, resets the I2C interface logic and aborts any I2C operation in progress. Bit 13: null Bit 14: SFP1 I2C controller Busy: When set to 1, indicates that an I2C transaction is underway Bit 15: SFP1 I2C controller Error: When set to 1, indicates that an I2C error has occurred Data Register for I2C bus controller ------------------------------------ Bits(07-00) are RW inputs to the CMX (data to SFP1) Bits(15-08) are RO outputs from CMX (data from SFP1) Bits 07-00: Data from SFP1 - This 8-bit field contains last data read from SFP1 Writing to these bits has no effect Bits 15–08: Data to SFP1 - This 8-bit field contains data to be written to SFP1 Read back the value written to the RW_12 SFP1 Data Register (not to SFP) Read/Write access ----------------- To WRITE the data into writable internal register of the SFP: - write data to bits 15-8 of the Data Register - write control data to the Control/Status Register (starts I2C operation) To READ the data from the internal register of the SFP: - write control data to the Control/Status Register (starts I2C operation) - read the data from bits 7-0 of the Data Register I2C bus controller reset ------------------------ The I2C bus controllers can be reset by writing to the CMX Module Resets Register at the VME address 0006. Bit 12: Reset SFP1 I2C controller Bit 13: Reset SFP2 I2C controller Bit 14: Reset SFP3 I2C controller Bit 15: Reset SFP3 I2C controller 4. Examples =========== 4.1. Reading byte 110 (0x6E) from the SFP1 second page -------------------------------------------------------- - step 1: Write control data to the SFP1 Control/Status Register RW_0010: Bits 07–00: SFP1 Register Number = 0110_1110 (0x6E) Bit 08: SFP1 Page: = 1 Bits 10-09: null Bit 11: Write = 0 (the operation is a read) Bit 12: SFP1 I2C controller Abort: = 0 Bit 13: null Bit 14: null Bit 15: null => control data to write to the SFP1 Control/Status Register: 0000_0001_0110_1110 (0x016E) This operation will start I2C operation to read from the SFP internal register - step 2: Read data from the SFP1 Data Register RW_0012 (look at page 6 of [4]): => expected value to read from the SFP1 Data Register: 0x0012 => 0000_0000_0001_0010 4.2. Write/read to byte 128 (0x80) on the SFP1 second page ----------------------------------------------------------- This is User Writable EEPROM byte - step 1: Write data (to be written to the SFP) to the Data Register RW_0012 Bits 07-00: null Bits 15–08: 0101_0101 (0x55) => 0101_0101_0000_0000 (0x5500) - step 2: Write control data to the SFP1 Control/Status Register RW_0010: Bits 07–00: SFP1 Register Number = 1000_0000 (0x80) Bit 08: SFP1 Page: = 1 Bits 10-09: null Bit 11: Write: = 1 (the operation is a write) Bit 12: SFP1 I2C controller Abort: = 0 Bit 13: null Bit 14: null Bit 15: null => 0000_1001_1000_0000 (0x0980) This operation will start I2C operation to write to the SFP internal register - step 3: Write control data to the SFP1 Control/Status Register RW_0010: Bits 07–00: SFP1 Register Number = 1000_0000 (0x80) Bit 08: SFP1 Page: = 1 Bits 10-09: null Bit 11: Write: = 0 (the operation is a read) Bit 12: SFP1 I2C controller Abort: = 0 Bit 13: null Bit 14: null Bit 15: null => 0000_0001_1000_0000 (0x0180) This operation will start I2C operation to read from the SFP internal register - step 4: Read data from the SFP1 Data Register RW_0012: => 0x5555 => 0101_0101_0101_0101 First byte is the data from the SFP Second byte keeps the data written on the first step NB: Betwwen step 2 and 3 one can write other data to Bits 15–08 of the Data Register 0022 (e.g. - zero) to avoid misinterpreting... 4.3. Reading byte 2 (0x02) from the MiniPOD1 Lower Memory Page -------------------------------------------------------------- - step 1: Write control data to the MiniPOD12 Control/Status Register RW_0020: Bits 07–00: MiniPOD Register Number = 0000_0010 (0x02) Bits 10-08: MiniPOD Address = 000 (For MiniPOD 1) Bit 11: Write = 0 (the operation is a read) Bit 12: MP12 I2C controller Abort = 0 Bit 13: null Bit 14: MP12 I2C controller Busy = 0 Bit 15: MP12 I2C controller Error = 0 => control data to write to the MiniPOD12 Control/Status Register: 0000_0000_0000_0010 (0x0002) This operation will start I2C operation to read from the MiniPOD1 internal register - step 2: Read data from the MiniPOD12 Data Register RW_0022 (look at page 32 of [1]): => expected value to read from the MiniPOD12 Data Register: 0x0006 => 0000_0000_0000_0110 4.4. Reading byte 129 (0x81) from the MiniPOD1 Upper Memory Page 00h -------------------------------------------------------------------- - step 1: Write control data to the MiniPOD12 Control/Status Register RW_0020: Bits 07–00: MiniPOD Register Number = 1000_0001 (0x81) Bits 10-08: MiniPOD Address = 000 (For MiniPOD 1) Bit 11: Write = 0 (the operation is a read) Bit 12: MP12 I2C controller Abort = 0 Bit 13: null Bit 14: MP12 I2C controller Busy = 0 Bit 15: MP12 I2C controller Error = 0 => control data to write to the MiniPOD12 Control/Status Register: 0000_0000_1000_0001 (0x0081) This operation will start I2C operation to read from the MiniPOD1 internal register - step 2: Read data from the MiniPOD12 Data Register RW_0022 (look at page 38 of [1]): => expected value to read from the MiniPOD12 Data Register: 0x0042 => 0000_0000_0100_0010 4.5. Reading byte 128 (0x80) from the MiniPOD1 Upper Memory Page 01h -------------------------------------------------------------------- TBD ====================================================================================== ====================================================================================== APENDIX 2 TTCrx control ============= This note describes the control of the clock deskew in the TTCrx chip and how to issue the broadcast commands in the CMX module. This description is based on the following sources: [1] Use of TTC System, 25 August 2005, Version 1.0 (TTCBusy.pdf) [2] TTCrx Reference Manual, December 2005, Version 3.11 (TTCrx_manual3.11.pdf) [3] CMM Project Specification, Version 1.8, 18-Jul-2008(CMM_V1_8.pdf) [4] ... 1. TTCrx chip 1.1 TTCrx chip short description 1.2 TTCrx chip addressing 1.3 TTCrx internal timing registers 2. Control of the clock deskew in the TTCrx chip via the I2C bus 2.1 Access to the timing registers via the I2C bus 2.2 Access to the I2C bus via VME interface in the CMX 2.3 Software support for the clock deskew control 2.4. Examples TBD: 3. Control of the clock deskew in the TTCrx chip via TTC optical fibre 3.1 Access to the timing registers via TTC optical fibre 3.2 Access to the TTC optical fibre transmitter via VME 4. Issue the broadcast commands 4.1 1. TTCrx chip ============= 1.1 TTCrx chip short description -------------------------------- The Calorimeter Trigger contains of a number of different crates connected to the TTC system. In all of them, the TTC fibre from the TTC crate goes to a TCM which fans out the TTC signals electrically along a custom backplane. However in the present design, the TCM itself does not include a TTCrx chip, it is located on the TTCDec card in the CMX board. There are two path to access the TTCrx chip: - through the TTC optical link from the TTC crate ("write only" access), - via I2C bus of the TTCrx chip, controlled via VME interface in the CMX. The TTCrx delivers the clock together with control and synchronisation information - the 40.08 MHz LHC clock signal, the first level trigger decision signal, and its associated bunch and event numbers. The TTCrx can be programmed to compensate for propagation delays associated with the detectors and their electronics. In addition, it provides synchronised broadcast commands and individually-addressed commands and data. The TTC system provides two Time Division Multiplexed communication channels. - Channel A is exclusively dedicated to broadcast the first-level trigger-accept (L1A) decisions, delivering a one-bit decision for every bunch crossing. - Channel B delivers broadcast commands or individually-addressed commands/data. The TTC system is also used to distribute the LHC 40.08 MHz clock signal. This signal is recovered from the incoming data at each TTC system destination. The clock signal (Clock40) coming directly out of the clock and data recovery circuit is also fed into two independent high-resolution phase shifters, providing a programmable delay - deskew the clock signal in steps of 104ps. The two resulting de-skewed clocks are denoted Clock40Des1 and Clock40Des2. Broadcast commands are used to distribute messages to all TTC destinations. When detected, these commands are executed by all the TTC receivers. The individually-addressed commands/data are implemented in the system to transmit user-defined data and commands over the optical network. These commands have two distinct modes of operation: - in the first mode, they are aimed at the TTC receivers themselves and their user-defined content is used to control the receiver’s operation. - in the second mode, the data are intended for the external electronics. In this case, both the data and sub-address contents of the received commands are made externally available by the addressed TTC receiver. 1.2 TTCrx chip addressing ------------------------- Each TTCrx chip is identified by a unique 14-bit address - Identification (ID) number. This number ID<13:0> is read during the reset procedure by using the hard-wired ID mechanism from SubAddr<5:0> and Dout<7:0>. The TTCrx chip is accessible via the I2C bus. According to the I2C bus specification, each device on the bus is addressed by a 7-bit wide I2C device address. Each TTCrx chip occupies two consecutive positions in the 7-bit I2C address space. Hence, it is possible to address 64 devices in the system by ID_I2C<5:0> + 1bit. These top six bits of the two consecutive seven bit I2C addresses used by the TTCrx derived at reset from the lowest six bits of the 14 bit address ID<13:0> (ID_I2C<5:0> = Dout<5:0>). L1Calo in [1] proposed to use geographic addressing within VME crates to assign not only the VME address of a module, but also the TTC address of its TTCrx chip (hence the TTCrx I2C address). All the TTCrx chips on a given type of module have the same I2C bus addresses. An addressing scheme along these lines (from [1], page 3) allocates the following addresses to the CMM modules: TTCrx Address Module Type and Addresses ID_I2C 0ccc 000n 000100 CMM: module n=0–1 in crates ccc=0–5 4 n = GEOADD(0); ccc = GEOADD(6:4) According to the geographical addresses, allocated to the CMM module ([3], page 31) Three bussed address lines GEOADDR<6..4> with switches are needed to identify the system (CP/JEP) and crate number (up to 4 crates). Each module requires up to four additional pins GEOADDR<3..0> to uniquely identify its position within the crate. The geographic address pins are specified as active high. CMM: Crate GEOADD(6:4) GEOADD(0) Module Function 0-2 111,110,101 0 (Left) τ Crate-CMM 3 100 0 τ System-CMM 0-2 111,110,101 1 (Right) e/γ Crate-CMM 3 100 1 e/γ System-CMM 4 011 0 Energy Crate-CMM 4 011 1 Jet Crate-CMM 5 010 0 Energy System-CMM 5 010 1 Jet System-CMM 6-7 001,000 Any Reserved The VME-- base address ranges: CrateSlotNumber Module VME-- address 3 CMM0 0x00700000-0x0077FFFE 20 CMM1 0x00780000-0x007FFFFE 1.3 TTCrx internal timing registers ----------------------------------- The TTCrx contains several internal registers used for the control and monitoring of its operation. These registers, are described in detail in Chapter 3 of [2]. The Timing and Control registers can be written through the TTC optical link. In addition, all registers are accessible via the I2C bus. The Timing registers consist of: - two Fine Delay registers control the delay in the high-resolution phase-shifters. - the Coarse Delay register controls the pipeline delay the broadcast commands. The content of the Coarse Delay register in conjunction with that of the Fine Delay register affects the total amount of de-skewing. The Fine Delay register 1 and 2: Two deskewed clock outputs are provided by the high-resolution phase shifters: Clock40Des1 and Clock40Des2. The 25ns clock cycle is divided into 240 steps, equidistantly spaced by 104ps. The byte-values of a Fine Delay register for a corresponding phase delay are given in Appendix A. 2. Control of the clock deskew in the TTCrx chip via the I2C bus ================================================================ 2.1 Access to the timing registers via the I2C bus -------------------------------------------------- The fine delay registers can be also loaded via the I2C bus. Each TTCrx chip occupies two consecutive positions in the 7-bit I2C address space. All data transfer over the I2C bus is performed using only two I2C registers in the TTCrx chip: - The I2C_pointer register. I2C bus address: ID_I2C<5:0><0> = 40 hex This is five bits wide and contains the address of the internal register of the TTCrx chip. For the Fine Delay register 1 = "00000" For the Fine Delay register 2 = "00001" - The I2C_data register. I2C bus address: ID_I2C<5:0><1> = 41 hex This is byte wide register. - Writing a byte to the I2C_data register in fact writes to the TTCrx register addressed by the I2C_pointer register. - When reading the I2C_data register, the content of the TTCrx register being addressed by the pointer register is transferred. Therefore, each I2C access to the TTCrx internal register is performed in two steps: 1) Write the register address in the I2C_pointer register 2) Read or write the I2C_data register The byte-values to be written into the I2C_data register to set a phase delay of a Fine Delay register are given in Appendix A of [2]. 2.2 Access to the I2C bus via VME interface in the CMX ------------------------------------------------------ The interface to the I2C bus of the TTCrx chip consists of two registers: TTCrx Control Register RW_0030 TTCrx Status Register RW_0032 They provide access via I2C bus of the TTCrx chip to all the internal TTCrx registers. - The TTCrx Control Register RW_0030 A TTCrx I/O operation takes place whenever this register is changed, unless the I2C bus is busy. An I2C operation is aborted if the reset bit is set. Bits 00–07: Data to TTCrx - This 8-bit field contains data to be written to the TTCrx chip. (the byte-values to be written into the I2C_data register of TTCrx). Bits 08-12: TTCrx Register Number - Specify the TTCrx register number to be read or written (the address of the internal register of the TTCrx chip to be written into the I2C_pointer register). Bit 13 : Write - When set to 1, defines the operation as a write to the TTCrx register. When set to 0, the operation is a read from the TTCrx internal register. Bit 14 : null Bit 15 : TTCrx Controller Abort When set to 1, resets the I2C interface logic in the BSPT FPGA and aborts any I2C operation in progress. - The TTCrx Status Register RO_0032 Bits 00-07: Data from TTCrx - This 8-bit field contains data read from the TTCrx chip (Bit 13 - Write - of TTCrx Control Register is set to 0). Bits 08-12: null Bit 13 : I2C Busy - When set to 1, indicates that an I2C transaction is underway Bit 14 : I2C Error - When set to 1, indicates that an I2C error has occurred Bit 15 : null Therefore, in order to set a phase delay of 5*104ps for the Clock40Des1 (Fine Delay register 1) the following operation to be performed from the VME side: 1) Write to the VME address 0x00700030 the data "0_0_1_00000_1011001": this operation will write the specified delay into the TTCrx Fine Delay register 1 Bits 00–07: Data to TTCrx = "1011001" (89 decimal from conversion table in Appendix A of [2]) Bits 08-12: TTCrx Register Number = 00000 (TTCrx Fine Delay register 1 address) Bit 13 : set to 1 to define a write operation to the TTCrx internal register Bit 14 : null Bit 15 : TTCrx Controller Abort set to 0. The I2C controller in the BSPT FPGA will: - write the register address of the TTCrx Fine Delay register 1 in the I2C_pointer register - write the specified delay value in the I2C_data register - in fact internally in the TTCrx chip the specified delay value will be written into the TTCrx Fine Delay register 1 addressed by the I2C_pointer register. To check the specified delay value written into the TTCrx Fine Delay register 1: 2) Write to the VME address 0x00700030 the data "0_0_0_00000_xxxxxxx": this operation will read the value from the TTCrx Fine Delay register 1 to the TTCrx Status Register 3) Read from the VME address 0x00700032: this operation will read the value from the TTCrx Status Register Bits 00-07: Data from TTCrx - Fine Delay register 1 value Bit 13 : I2C Busy - check that = 0 Bit 14 : I2C Error - check that = 0 2.3 Software support for the clock deskew control ------------------------------------------------- Note from Duc: In the L1Calo software there is a special class ModuleI2CRegister that knows about the two registers TTCcontrol and TTCstatus which are used to talk to the TTC decode chip. When writing or reading values through this class, it automatically used the right procedure to write and set values. In the software this is even encapsuled into simple functions called setDeskew1 and setDeskew2 which use the ModuleI2CRegister class and wait 1 second. Note from Yuri: In CMM: TTCrx Control Register VME address was ..40 in CMX changed to ..30 TTCrx Status Register VME address was ..42 in CMX changed to ..32 These addresses in the CMX can be set the same as in the CMM to preserve the SW compatibility. TBD: 2.4. Examples ------------- 3. Control of the clock deskew in the TTCrx chip via TTC optical fibre ====================================================================== 3.1 Access to the timing registers via TTC optical fibre -------------------------------------------------------- The Fine Delay register 1 and 2 can be loaded over the optical link by sending individually-addressed commands to internal sub-addresses “0” and “1” of a given TTCrx. 3.2 Access to the TTC optical fibre transmitter via VME ------------------------------------------------------- 4. Issue the broadcast commands =============================== 4.1 ====================================================================================== ====================================================================================== APENDIX 3 CMX FPGA configuration ====================== 1. Virtex6 configuration using JTAG interface and iMPACT software 1.1 Programming file generation 1.2 Platform Cable USB II connection and jumpers setting 1.3 Programming Virtex6 FPGA via iMPACT Using JTAG 2. Virtex6 configuration on power-on from CF card by System ACE 2.1 CompactFlash card preparation 2.2 Programming file and ACE file generation 2.3 Writing System ACE files to CompactFlash card 2.4 FPGA configuration on the CMX board 2.5 Selecting the FPGA configuration 3. Open issues 1. Virtex6 configuration using JTAG interface and iMPACT software ================================================================= This description is based on the following sources: [1] Xilinx ISE In-Depth Tutorial UG695 (v13.4) January 18, 2012 (Xilinx ISE 13.4 tutorial.pdf) Chapter 8, Configuration Using iMPACT, p.131 [2] Virtex-6 FPGA Configuration User Guide UG360 (v3.2) November 1, 2010 (V6 Configuration ug360.pdf) Chapter 3, Boundary-Scan and JTAG Configuration, p.63 [3] Platform Cable USB II DS593 (v1.2.1) March 17, 2011 (Platform Cable USB II ds593.pdf) iMPACT is a file generation and device programming software tool. iMPACT enables to program through several parallel cables, including the Platform Cable USB. iMPACT can create bitstream files, System ACE™ solution files, PROM files, and SVF/XSVF files. Prior to launching iMPACT, set all jumpers on the CMX board, connect the Platform Cable USB II to your computer’s USB port and connect the cable to the JTAG port of the CMX board. Be sure that the board is powered. 1.1 Programming file generation ------------------------------- Create design in Xilinx ISE Project Navigator, synthesize and implement it. "Generate Programming File" - will generate .bit file in the design directory. Use default settings for the Process Properties 1.2 Platform Cable USB II connection and jumpers setting -------------------------------------------------------- Connect the Platform Cable USB II to your computer’s USB port. Connect the cable to the JTAG port of the CMX board. Be sure that the CMX board is powered. JTAFG chain - set the JTAG chain using jumpers on the CMX board -> SystemACE(Base+Topo) - BSPT(Spartan3) If the Virtex-6 device is configured via boundary-scan on power-up, it is recommended to tie the mode pins to the JTAG configuration mode settings, i.e., 101 (M2 = 1, M1 = 0, M0 = 1). This is not required because the JTAG configuration mode is available regardless of the mode pin settings; setting the mode pins to JTAG only removes potential conflicts on the configuration pins. --- in my email to Wojtek on Feb.19 2014: May be first exclude (by jumpers) all other devices from the TEST JTAG Chain (TTCDec, BSPT FPGA, Confog PROM) that only ACE is left. Then in the configuration JTAG Chain (from ACE) leave only Base FPGA. Set the mode pins of the Base FPGA to the JTAG configuration mode settings, i.e., 101 (M2 = 1, M1 = 0, M0 = 1) by jumpers. Look at the diagram on the p.56 (SystemACE) in the attached file and check that the INIT_B pin of the Base FPGA is connected to the ACE CFGINIT_B pin via JMP75. POR_BYPASS set to '0' (don’t install JMP81) -> Built-in POR circuit is used to reset the device. (On the ACE diagram – attached - there is a signal Board_Power_OK_B connected to the POR_RESET – I didn’t find where it’s coming from). The signal driven by the BSPT FPGA in this mode is RESET_B – it shall be HIGH – check it if it’s accessible, otherwise I will set it for the test permanently to ‘1’. Other signal - PROGRAM_B of the BASE FPGA is permanently driver HIGH from the BSPT FPGA. --- 1.3 Programming Virtex6 FPGA via iMPACT Using JTAG -------------------------------------------------- Opening iMPACT - to start iMPACT from Project Navigator, double-click in the Processes pane in the Design panel on "Configure Target Device" -> "Manage Configuration Project (iMPACT)" - Configure devices uses Boundary-Scan (JTAG) -> Automatically connect to a cable and identify Boundary-Scan chain (Initilize Chain) - Assign configuration files: -> XCCACE - bypass -> Virtex6 (BASE and TOPO) -> Spartan3 (BSPT) - Click on Virtex6 - Program -> program succeeded 2. Virtex6 configuration on power-on from CF card by System ACE =============================================================== This description is based on the following sources: [4] System ACE CompactFlash Solution, DS080 (v2.0) October 1, 2008 (SystemACE_DS.pdf) [5] Preparing System ACE collections for the CMM. Ian Brawn, 21.8.7 (CMM_SystemACE.pdf) [6] Multi-Card Reader/Writer MRW62E-S2, 2008 Sony Corporation (Sony MRW62E-S2.pdf) [7] CMM Project Specification, Version 1.8, 18-Jul-2008(CMM_V1_8.pdf) iMPACT is a file generation and device programming software tool. SONY USB multicard reader/writer MRW62E: http://www.sony.co.uk/support/en/product/MRW62E-S2/manuals (or any other CF card reader/writer) 2.1 CompactFlash card preparation --------------------------------- The XILINX System ACE controller can accommodate any standard CompactFlash (CF) module (up to 8 GB). Maximum CompactFlash (CF) partition capacity is 2 GB. http://www.xilinx.com/support/answers/14456.htm The System ACE CF partition must be formatted as DOS FAT12 or FAT16 The System ACE CF controller does not recognize the FAT32 file system. It was designed to recognize only the FAT12 and FAT16 formats. The CF card should always be formatted with a sectors-per-cluster size greater than 1. (UnitSize greater than 512) The System ACE CF controller can only read a CF card that is formatted with one reserved sector in the Partition Boot Record. Windows 2000, Windows NT, and Windows 98 default to one reserved sector when formatting. Therefore, formatting the CF card using these Windows operating systems is not problematical. This can be done using the format command with the /fs: and /a: options in this syntax: format [/fs:][/a:] For example: format D: /FS:FAT /A:1024 In Windows XP, however, an alternate disk formatting utility (such as mkdosfs, available from http://www1.mager.org/mkdosfs) must be used. http://www1.mager.org/mkdosfs/mkdosfs/mkdosfs.exe For example: C:\>mkdosfs -v E: (E: is the drive letter that matches the CF card) That was tested on 2GB CF card. 2.2 Programming file and ACE file generation -------------------------------------------- Create design in Xilinx ISE Project Navigator, synthesize and implement it. "Generate Programming File" - will generate .bit file in the design directory (this is one configuration file for one FPGA - e.g. BASE FPGA) "Manage Configuration Project (iMPACT)" in the Processes pane in the Design panel - select System ACE: -> Prepare System ACE files: -> Novice -> System ACE CF size: -> Generic -> System ACE Name and Location: directory name (e.g. "cmx") -> System ACE Configuration address and Design: Configuration address 0 (e.g. called "base") -> Finish -> Now start assigning device file to Config Address 0 -> cmx_alg_test.bit -> Would you like to add another divice file to Config Address 0 -> NO (if only BASE FPGA configured) -> Available operations -> Generate File... -> OK In the in the design directory there is a directory "cmx" and a file "xilinx.sys" File "xilinx.sys" will contain the following information: #Automatically generated. PLEASE DO NOT MODIFY. dir = cmx cfgaddr0 = base Directory "cmx" contain sub-dir "base" and a copy of file "xilinx.sys" Sub-directory "base" contain file "base.ace" - design file for the FPGA 2.3 Writing System ACE files to CompactFlash card ------------------------------------------------- Connect the CF card reader/writer to PC and insert CF card. Copy/paste from the design directory to the CF card file "xilinx.sys" and directory "cmx". Remove the CF card from the reader/writer. 2.4 FPGA configuration on the CMX board -------------------------------------- Insert CF card into CF socket on the CMX board, power the board. The System ACE CF controller has indicator pins to help monitor device status during operation. Table 1: System ACE CF Controller Status Indicators STATLED • When on, the Status LED indicates that configuration is DONE. • When blinking, this LED indicates that configuration is still in progress. • When off this LED indicates that configuration is in an IDLE state. ERRLED • When on, the ERROR LED indicates that an error occurred. • When blinking, this LED indicates that no CompactFlash device was found when the CompactFlash for the Configuration JTAG interface was enabled. • When off, this LED indicates that no errors are detected. 2.5 Selecting the FPGA configuration ------------------------------------ CFGMODEPIN pin of the System ACE CF Controller (pin 89): When 1, this pin instructs the System ACE CF controller to start the configuration process immediately following reset. -- MPU CFGMODE and CFGADDR generation CFGMODE <= '1'; -- System ACE CF controller starts the configuration immediately after reset In a case of multiple FPGA configurations (up to 8) - e.g. different CMX BASE FPGA functions for different CMX versions in CPM and JEM crates, different .bit files are generated in different projects. (e.g. - base_cpm.bit, base_jem.bit etc.) In the CMM ([3], page 31), all CMMs include a System-ACE device with a standard CF card holding the FPGA configuration versions for hit- and energy-summing functions. Appropriate FPGA configurations are selected and loaded automatically on power-up, based on backplane pin configuration as specified in Table 1, or by VME command. This scheme effectively assigns crate numbers 0-3 to the CP system and 4-5 to the JEP system, leaving crate numbers 6 and 7 unused. Table 1: CMMs (and CMXs) Crate GEOADD(6:4) GEOADD(0) Module Function 0-2 111,110,101 0 (Left) τ Crate-CMM 3 100 0 τ System-CMM 0-2 111,110,101 1 (Right) e/ Crate-CMM 3 100 1 e/γ System-CMM 4 011 0 Energy Crate-CMM 4 011 1 Jet Crate-CMM 5 010 0 Energy System-CMM 5 010 1 Jet System-CMM 6-7 001,000 Any Reserved The System ACE CF controller uses the three configuration address pins or MPU register bits (CFGADDR) to select the desired configuration. On the CMX board values of these 3 pins are derived from the geographical address of the CMX - GEOADD(6:4) and GEOADD(0): GEOADD <= INT_GEOADD_0 & INT_GEOADD; case (GEOADD) is -- CMM type Crate GEOADD(6:4) GEOADD(0) -- --------------------------------------------- when "1111" => CFGADDR <= "000"; -- e/γ Crate 0 111 1 (Right) when "1101" => CFGADDR <= "000"; -- e/γ Crate 1 110 1 when "1011" => CFGADDR <= "000"; -- e/γ Crate 2 101 1 when "1001" => CFGADDR <= "001"; -- e/γ System 3 100 1 -- when "1110" => CFGADDR <= "010"; -- τ Crate 0 111 0 (Left) when "1100" => CFGADDR <= "010"; -- τ Crate 1 110 0 when "1010" => CFGADDR <= "010"; -- τ Crate 2 101 0 when "1000" => CFGADDR <= "011"; -- τ System 3 100 0 -- when "0110" => CFGADDR <= "100"; -- Energy Crate 4 011 0 (Left) when "0100" => CFGADDR <= "101"; -- Energy System 5 010 0 -- when "0111" => CFGADDR <= "110"; -- Jet Crate 4 011 1 (Right) when "0101" => CFGADDR <= "111"; -- Jet System 5 010 1 -- when others => CFGADDR <= "000"; -- Reserved 6-7 001,000 Any --when others => null; end case; Module Control Register RW_0004 provides control on INT_GEOADD bits Bits 03-00: INT_GEOADD_0 - (bit 00) and INT_GEOADD(2 downto 0) - bits (03-01) INT_GEOADD bits: these bits are set to the value of the OCB_GEO_ADRS_x pins of the backplane: bit 00 <- OCB_GEO_ADRS_0, bit 01 <- OCB_GEO_ADRS_4, bit 02 <- OCB_GEO_ADRS_5, bit 03 <- OCB_GEO_ADRS_6, - after BSPT FPGA configuration (by ACE reset internaly generated after configuration) - after Reset Module (writing '1' into bit 00 in RW_06 Module Resets Register (see 2.1) They are used then to define the CFGADDR bits for the XILINX System ACE controller in order to select appropriate CMX configuration from the CF card according to the CMX position in the L1Calo system (crate/slot) and to establish the module function. Bits 03-00 of RW_04 can be writted from VME and read back. This allow to define another CMX configuration on the CF card and reconfigure BF and TP FPGAs by Reset System ACE - writing 0x0008 to RW_0006 Module Resets Register. In order to select appropriate configuration on the CF card, one have to load these 4 bits with corresponding GEOADD value fron Table 1. Note: VME and TTC address decoding is performed using the VME backplane geographical addressing pins OCB_GEO_ADRS_x (not INT_GEOADD bits) and so is not altered by changes made to the bits 03-00 of RW_04 from VME. 3. Open issues ============== The following features was not yet tested (on the VAT card): - Utilisation of the CF card with capasity of more than 2GB - selection of different FPGA configurations using CFGADDR pins - Configuration of a chain of FPGA devices ====================================================================================== ====================================================================================== APENDIX 4 FPGA BSPT FW versions ===================== 1. FPGA_BSPT_FW_v1_20140310 ("safe") - 10-Mar-2014 -------------------------------------------------- This version is based on the original code for CMM from Ian Brawn. Project directory: "cmx_bspt_safe_20140310" corresponding file "vme_map_20140310.txt" It implements several VME registers: - RO_0000 Module ID and SN - RO_0002 Module HW/FW Revisions - RW_0004 Module Control Register - RW_0006 Module Resets Register - RO_0008 Module Satus 1 Register - RO_000A Module Satus 2 Register For VME interface tests there are 2 registers and 2 register arrays: - RW_000C temporary RW register 1 - RW_000E temporary RW register 2 - temporary array of 16-bit RW registers from 0060 to 007E - temporary array of 16-bit RW registers from 00E0 to 00FE It provides acces to the TTCrx chip on the TTCDEC card via registers: - RW_0030 TTCrx Control Register - RO_0032 TTCrx Status Register The TTC_CLK_SEL and TTC_PD control bits are temporary set to fixed values to bypass bits 5 and 6 in RW_0004 Module Control Register - TTC_CLK_SEL <= '1'; - TTC_PD <= '1'; The VME reseivers control temp set to fix the error with chip orientation - VME_CTRL_RECVR_LE <= '0'; -- 17.02.2014 temp set to '0' - VME_ADRS_AND_CTRL_RECVR_OE_B <= '1'; -- 17.02.2014 temp set to '1' For the LVDS links control the output control signals are set to static values regardless of the input signals in such a way that: - all LVDS transceivers (CTP and Backplane) are configured as inputs to the CMX, - all level translators are configured as inputs to the BSPT/BF/TP FPGAs and are disabled. In this way the BF and TP FPGAs may remain unconfigured after the BSPT configuration from the BSPT PROM on power up. 2. FPGA_BSPT_FW_v2_20140417 - 17-Apr-2014 ----------------------------------------- Project directory: "cmx_bspt_v2_20140417", corresponding file "vme_map_v2_20140417.txt" It implements VME registers, described in chapter 2.1 of "vme_map_v2_20140417.txt": For VME interface tests there are 4 registers and 1 register array: RW_0028 to RW_002E Temporary RW registers RW_0060 to RW_007F Temporary RW array It provides acces to the TTCrx chip on the TTCDEC card via registers: - RW_0030 TTCrx Control Register - RO_0032 TTCrx Status Register The TTC_CLK_SEL and TTC_PD control bits are temporary set to fixed values to bypass bits 5 and 6 in RW_0004 Module Control Register - TTC_CLK_SEL <= '1'; - TTC_PD <= '1'; The VME reseivers control temp set to fix the error with chip orientation - VME_CTRL_RECVR_LE <= '0'; -- 17.02.2014 temp set to '0' - VME_ADRS_AND_CTRL_RECVR_OE_B <= '1'; -- 17.02.2014 temp set to '1' For the LVDS links, the management of the control signals to the LVDS transceivers comes from the BSPT FPGA. In turn the BSPT FPGA listens to signals from the BF and TP FPGAs to learn how they want the various LVDS transceivers configured, i.e. as inputs or as outputs. The status of all signals (coming from the BF and TP FPGAs and generated by the BSPT FPGA) can be accessed via two status registers: RO_000C LVDS Link Status 1 RO_000E LVDS Link Status 2 The XILINX System ACE controller internal registers are mapped to the VME adresses from 0080 to 00DF (See System ACE CompactFlash Solution, DS080 (v2.0) October 1, 2008) Access to the internal registers of the optical components (SFP and MiniPOD) is provided via I2C interface to registers: Control/Status Reg and Data Register. To WRITE the data into writable internal register of the optical component: - write data to bits 15-8 of the Data Register - write control data to the Control/Status Reg To READ the data from the internal register of the optical component: - write control data to the Control/Status Reg - read the data from bits 7-0 of the Data Register 3. FPGA_BSPT_FW_v3_20140704 - 04-Jul-2014 ----------------------------------------- Project directory: "cmx_bspt_v3_20140704.zip", corresponding file "vme_map_v3_20140704.txt" Layout of the Module Status 1 Register (RO_0008) is modified, System ACE Status added. Added registers, related to the LEDs control: - RW_0028 LEDs Control register (instead of temporary RW_0028) - RO_002A LEDs Requests Status (instead of temporary RW_002A) Added registers, related to the to debugging signals (RO_002C and RO_002E) 4 temporary RW registers are moved from addresses 0x0028-0x002E to 0x0038-0x003E The TTC_CLK_SEL and TTC_PD control bits are now controlled by bits 5 and 6 in RW_0004 Module Control Register. For the normal operation of the CMX card, both these bits have to be set to '1': bit 04 - TTCDec Clock Select -> '1' - TTCrx clock bit 05 - TTCDec P/D Mode Select -> '1' - Protected Mode (Normal Running Mode) After power-on the CMX card these two bits are set to '1'. LVDS logic - replace INTERNAL_TP_CONFIG_DONE by TP_CONFIG_DONE 4. FPGA_BSPT_FW_v4.0_20140706 - 06-Jul-2014 ----------------------------------------- Project directory: "cmx_bspt_v3_20140706.zip", corresponding file "vme_map_v4.0_20140706.txt" Change format of FW version to X.x in RO_0002 bits 15-08: Bits 15-08: BSPT_FWR - 8 bit Board Support FPGA Firmware Revision Number set in firmware in format X.x Bits 15-12 - major version Bits 11-08 - minor version LEDs allocation - default values when bit 00 in RW_0028 (LEDs Control register) is set to '0': LED_1R_GREEN <= TTCrx Ready LED_2L_GREEN <= BF FPGA configured LED_2R_GREEN <= TP FPGA configured Bits 03-00 in RW_0004 (Module Control Register) used to generate the CFGADDR bits for the XILINX System ACE controller Bits 03-00: INT_GEOADD_0 - (bit 00) and INT_GEOADD(2 downto 0) - bits (03-01) These bits are set to the value of the OCB_GEO_ADRS_x pins of the backplane: bit 00 <- OCB_GEO_ADRS_0, bit 01 <- OCB_GEO_ADRS_4, bit 02 <- OCB_GEO_ADRS_5, bit 03 <- OCB_GEO_ADRS_6, - after BSPT FPGA configuration (by ACE reset internaly generated after configuration) - after Reset Module (writing '1' into bit 00 in RW_06 Module Resets Register (see 2.1) These bits may be used to alter the value of the VME geographical addressing pins OCB_GEO_ADRS_x. INT_GEOADD is used to define the CFGADDR bits for the XILINX System ACE controller in order to select appropriate CMX configuration from the CF card according to the CMX position in the L1Calo system (crate/slot) and to establish the module function (FW download). VME and TTC address decoding is performed using the VME OCB_GEO_ADRS_x pins and so is not altered by changes made here. File "vme_map_version_date.txt" was renamed to "BSPT_vme_map_version_date.txt" ====================================================================================== ====================================================================================== APENDIX 5 CMX VME registers/memories map (pointer) ========================================= [1] CMX VME registers/memories map v3 (vme_map_v4.0_20140706.txt) http://www.pa.msu.edu/hep/atlas/l1calo/cmx/firmware/bspt_fpga_fw/BSPT_FPGA_FW_v4.0_20140706/