Board Support (BSPT) FPGA VME registers/memories map v4.0 Y.Ermoline, Current Rev. 06-Jul-2014 =============================================================================================== This documents is based on the following sources: [1] Common Merger Module, Version 1.8, 18-Jul-2008 [2] Missing Energy Significance Trigger, Version 2.1, 3-November-2011 [3] CMM schematics "pc3203m5_schems.pdf", last revision 20.09.06 [4] VHDL package "vme_cmm.vhd", last revision 05.01.11 [5] TTCrx Reference Manual, December 2005, version 3.11 (for para 4.4) [6] XILINX System ACE CompactFlash Solution, DS080(v2.0) October 1, 2008 (for para 4.5) [7] CMX Firmware Specifications (Wojtek, Pawel, Yuri) [8] inputs from Murrough, Wojtek, Pawel [9] CMX schematics and network lists Guidelines (from CMM_V1.8): --------------------------- The computer can read all registers; hence there are no ‘write only’ registers. The register bits generally have the same meaning for reads as for writes. - All Status Registers shall be Read-Only (RO) registers. - All Control Registers shall be Read/Write (RW) registers. - Reading back a register generally returns the last value written. - Attempts to write to RO registers or undefined portions of registers result in the non-modifiable fields being left unchanged It is illegal for the computer to read or write a value that the CMM module itself is able to modify at the same time. If the computer reads a register (e.g. a counter) which the CMM module is modifying, a well-defined value is returned. When the address space occupied by the CMM module is accessed, it always responds with a handshake to avoid a bus error. The power-up condition of all registers is all zeros, unless otherwise stated. Setting a bit-field means writing a 1 to it, clearing it means writing a 0. ------------------------------------------------------------------------------- 1. CMX Board Support FPGA (BSPT_FPGA) VME register map 1.1 BSPT_FPGA list of registers 1.2 Registers related to the whole CMX module 1.3 Registers related to the CTP/BP LVDS Links Mngmnt status 1.4 Registers related to the optical components access via I2C 1.5 Registers related to the LEDs control 1.6 Registers related to debugging signals 1.7 Registers related to the TTCrx chip on the TTCDec card 1.8 Registers related to the XILINX SystemACE chip 1.9 Temporary registers for tests =================================================================================================================================== 1. CMX Board Support FPGA (BSPT_FPGA) VME register map =================================================================================================================================== The VME-- base address ranges: CrateSlotNumber Module VME-- address 3 CMX0 0x00700000-0x0077FFFE 20 CMX1 0x00780000-0x007FFFFE BSPT_FPGA address range: 256 bytes 3 CMX0 0x00700000-0x007000FF 20 CMX1 0x00780000-0x007800FF 1.1 BSPT_FPGA list of registers =============================== Addr Re Name Size Description VHDL name FPGA Function Comments ---- -- ---- ---- ----------- ---------- ---- ------- -------- 0000 RO ModuleIDSN 2 Module ID and SN module_idsn BSPT VME I/F 0002 RO ModuleRew 2 Module HW/FW Revisions module_rev BSPT VME I/F 0004 RW ModuleControl 2 Module Control Register module_cntrl BSPT VME I/F 0006 RW ModuleResets 2 Module Resets Register module_rsts BSPT VME I/F 0008 RO ModuleStatus1 2 Module Satus 1 module_stat1 BSPT VME I/F 000A RO ModuleStatus2 2 Module Satus 2 module_stat2 BSPT Opto 000C RO LinkStatus1 2 LVDS Link Satus 1 link_status1 BSPT LVDS 000E RO LinkStatus2 2 LVDS Link Satus 2 link_status2 BSPT LVDS 0010 RW SFP1_CSR 2 SFP1 Control/Status Reg sfp1_csr BSPT Opto_sfp 0012 RW SFP1_Data 2 SFP1 Data Register sfp1_data BSPT Opto_sfp 0014 RW SFP2_CSR 2 SFP2 Control/Status Reg sfp2_csr BSPT Opto_sfp 0016 RW SFP2_Data 2 SFP2 Data Register sfp2_data BSPT Opto_sfp 0018 RW SFP3_CSR 2 SFP3 Control/Status Reg sfp3_csr BSPT Opto_sfp 001A RW SFP3_Data 2 SFP3 Data Register sfp3_data BSPT Opto_sfp 001C RW SFP4_CSR 2 SFP4 Control/Status Reg sfp4_csr BSPT Opto_sfp 001E RW SFP4_Data 2 SFP4 Data Register sfp4_data BSPT Opto_sfp 0020 RW MP12_CSR 2 MP12 Control/Status Reg mp12_csr BSPT Opto_mp 0022 RW MP12_Data 2 MP12 Data Register mp12_data BSPT Opto_mp 0024 RW MP345_CSR 2 MP345 Control/Status Reg mp345_csr BSPT Opto_mp 0026 RW MP345_Data 2 MP345 Data Register mp345_data BSPT Opto_mp 0028 RW LEDsControl1 2 LEDs Control register 1 leds_cntr1 BSPT LEDs 002A RO LEDsRequests 2 LEDs Requests Status leds_req BSPT LEDs 002C RO BFTPDebug 2 BF and TP debug signals bftp_debug BSPT Debugging 002E RO BSPTDebug 2 BSPT debug signals bspt_debug BSPT Debugging 0030 RW TTCrxControl 2 TTCrx Control Register ttc_control BSPT TTC 0032 RO TTCrxStatus 2 TTCrx Status Register ttc_status BSPT TTC 0034 RO TTCrxBrcst 2 TTCDec Brcst Register ttc_brcst BSPT TTC 0036 RO TTCrxDq 2 TTCDec DQ Register ttc_dq BSPT TTC 0040 RO TTCrxDump 32 TTCDec Dump RAM ttc_ram BSPT TTC addresses from 0040 to 005E 0080 ->See SystemACE 96 ->See SystemACE ->See SystemACE BSPT ACE addresses from 0080 to 00DF 00E0 reserved addresses from 00E0 to 00FF (32 bytes) - DO NOT USE!!! (used by ACE VME address decoding!) 0038 RW TempReg1 2 Temporary RW register 1 vme_rw_reg1 BSPT reserved 003A RW TempReg2 2 Temporary RW register 2 vme_rw_reg2 BSPT reserved 003C RW TempReg3 2 Temporary RW register 3 vme_rw_reg3 BSPT reserved 003E RW TempReg4 2 Temporary RW register 4 vme_rw_reg4 BSPT reserved 0060 RW RegArray 32 Temporary RW array 1 vme_rw_array1 BSPT reserved addresses from 0060 to 007F Last BSPT_FPGAaddress: 00FF 1.2 Registers related to the whole CMX module ============================================= Addr Re Name Size Description VHDL name FPGA Function Comments ---- -- ---- ---- ----------- ---------- ---- ------- -------- 0000 RO ModuleIDSN 2 Module ID and SN module_idsn BSPT VME I/F ------------------------------------------------------------------------------------------------------------ All bit fields are outputs from the CMX This register replaces the CMM registers 00(00-15) and 02(00-07) Bits 07-00: Module_ID - a unique 8 bit Module Number (what is this number for CMX?), set in firmware to X"33" Bits 15-08: Module_SN - a 8-bit Serial Number for each module, starting at 1 and set by 5 jumpers + 3 upper bits in FW 0002 RO ModuleRew 2 Module HW/FW Revisions module_rev BSPT VME I/F ------------------------------------------------------------------------------------------------------------- All bit fields are outputs from the CMX This register replaces the CMM registers 02(08-11), 54(I2cId), 56(VmeId), 58(SystemAceVMEIf) Bits 07-00: CMX_HWR - 8 bit CMX Hardware Revision Number starting at 1 and set in firmware Bits 15-08: BSPT_FWR - 8 bit Board Support FPGA Firmware Revision Number set in firmware in format X.x Bits 15-12 - major version Bits 11-08 - minor version 0004 RW ModuleControl 2 Module Control Register module_cntrl BSPT VME I/F ------------------------------------------------------------------------------------------------------------ All bit fields are inputs to the CMX Bits 03-00: INT_GEOADD_0 - (bit 00) and INT_GEOADD(2 downto 0) - bits (03-01) These bits are set to the value of the OCB_GEO_ADRS_x pins of the backplane: bit 00 <- OCB_GEO_ADRS_0, bit 01 <- OCB_GEO_ADRS_4, bit 02 <- OCB_GEO_ADRS_5, bit 03 <- OCB_GEO_ADRS_6, - after BSPT FPGA configuration (by ACE reset internaly generated after configuration) - after Reset Module (writing '1' into bit 00 in RW_06 Module Resets Register (see 2.1) These bits may be used to alter the value of the VME geographical addressing pins OCB_GEO_ADRS_x. INT_GEOADD is used to define the CFGADDR bits for the XILINX System ACE controller in order to select appropriate CMX configuration from the CF card according to the CMX position in the L1Calo system (crate/slot) and to establish the module function (FW download). VME and TTC address decoding is performed using the VME OCB_GEO_ADRS_x pins and so is not altered by changes made here. Bit 04: TTCDec Clock Select - When this bit is set, the TTCDec uses the TTCrx clock, otherwise - XTAL clock Trying to set this bit when the TTCrx is not ready has no effect (TTCrx Ready - bit 04 in RO_0008 ModuleStatus1). After power-on the CMX card this bit is set to '1'. Bit 05: TTCDec P/D Mode Select - This bit controls the TTCDec protection scheme described in the TTCDec specification After power-on the CMX card this bit is set to '1'. Bits 11–06: null, writing to these bits has no effect. Bit 12: SFP1_TX_DISABLE - SFP1 Transmitter Disable (DAQ?) Bit 13: SFP2_TX_DISABLE - SFP2 Transmitter Disable (ROI?) Bit 14: SFP3_TX_DISABLE - SFP3 Transmitter Disable Bit 15: SFP4_TX_DISABLE - SFP4 Transmitter Disable TX_DISABLE allows the BSPT to turn off the laser in the transmitter. 0006 RW ModuleResets 2 Module Resets Register module_rsts BSPT VME I/F ------------------------------------------------------------------------------------------------------------ All bit fields are inputs to the CMX. All bits read back as zero, and writing a zero to a bit has no effect. Bit 00: Reset Module - Writing a 1 to this bit resets only Module Control Register RW_0004 Not connected to the BF or TP FPGAs Bit 01: Reset TTCrx - Writing a 1 to this bit resets TTCrx on the TTCDec card (500 ns pulse). Writing a 0 has no effect. Read back as zero. Generates Reset_b for TTCDec card (TTCrx chip reset) TTCS1-29 Bit 02: Reset TTCrx I2C controller - Writing a 1 to this bit resets the I2C interface controller in the BSPT FPGA to the power on state. Bit 03: Reset System ACE - Writing a 1 to this bit resets the System ACE controller (1500ns pulse) and reloads the BF and TP FPGAs with firmware corresponding to the module geographical address specified in the GEOADD Bypass field (Bits 03-00) in the Module Control Register (RW_0004). Bits 07-04: null Bit 08: Reset MiniPods 12 - Writing a 1 to this bit generates Reset_B for MiniPods 1,2 Bit 09: Reset MiniPods 12 I2C controller in the BSPT FPGA Bit 10: Reset MiniPods 345 - Writing a 1 to this bit generates Reset_B for MiniPods 3,4,5 Bit 11: Reset MiniPods 345 I2C controller in the BSPT FPGA Bit 12: Reset SFP1 I2C controller in the BSPT FPGA Bit 13: Reset SFP2 I2C controller in the BSPT FPGA Bit 14: Reset SFP3 I2C controller in the BSPT FPGA Bit 15: Reset SFP3 I2C controller in the BSPT FPGA 0008 RO ModuleStatus1 2 Module Status 1 Register module_stat1 BSPT VME I/F ------------------------------------------------------------------------------------------------------------ All bit fields are outputs from the CMX Bit 00: System ACE Status - When this bit is set, indicates that configuration is DONE. Bit 01: System ACE Error - When this bit is set, an error occurred during FPGA configuration Bit 02: BF_CONFIG_DONE - This bit is set if the BASE_FPGA has been configured correctly - DONE from BASE_FPGA Bit 03: TP_CONFIG_DONE - This bit is set if the TOPO_FPGA has been configured correctly - DONE from TOPO_FPGA Bit 04: TTCrx Ready - This bit is set when the TTCrx on TTCDec card is ready. Bit 05: Status2 - This bit is set when TTCrx is the clock source on the TTCDec card Bit 07-06: null (may be used for temp status) Bit 08: Lock Monitor VCXO_PLL DeScew-1 (BSPT_DEBUG_5) Bit 09: Lock Monitor VCXO_PLL DeScew-2 (BSPT_DEBUG_7) Bit 10: Lock Monitor VCXO_PLL 320 MHz (BSPT_DEBUG_6)RO_R Bit 11: MP1_INTRPT_B - MiniPOD 1 Interrupt_B Bit 12: MP2_INTRPT_B - MiniPOD 2 Interrupt_B Bit 13: MP3_INTRPT_B - MiniPOD 3 Interrupt_B Bit 14: MP4_INTRPT_B - MiniPOD 4 Interrupt_B Bit 15: MP5_INTRPT_B - MiniPOD 5 Interrupt_B 000A RO ModuleStatus2 2 Module Status 2 Register module_stat2 BSPT Opto ------------------------------------------------------------------------------------------------------------- All bit fields are outputs from the CMX SFP1 - BASE_FPGA DAQ SFP2 - BASE_FPGA ROI SFP3 - TOPO_FPGA DAQ SFP4 - TOPO_FPGA ROI Bit 00: SFP1_TX_FAULT - SFP1 Transmitter Fault => def 0 (module operational) Bit 01: SFP1_MOD_PRESENT - SFP1 Module Present => def 1 (module installed) Bit 02: SFP1_RX_LOST - SFP1 Receiver Signal Loss => def 1 (no optical fibre connected) Bit 03: null Bit 04: SFP2_TX_FAULT - SFP2 Transmitter Fault Bit 05: SFP2_MOD_PRESENT - SFP2 Module Present Bit 06: SFP2_RX_LOST - SFP2 Receiver Signal Loss Bit 07: null Bit 08: SFP3_TX_FAULT - SFP3 Transmitter Fault Bit 09: SFP3_MOD_PRESENT - SFP3 Module Present Bit 10: SFP3_RX_LOST - SFP3 Receiver Signal Loss Bit 11: null Bit 12: SFP4_TX_FAULT - SFP4 Transmitter Fault Bit 13: SFP4_MOD_PRESENT - SFP4 Module Present- Bit 14: SFP4_RX_LOST - SFP4 Receiver Signal Loss Bit 15: null TX_FAULT signal allows the BSPT FPGA to know if there are problems with the laser transmitter. MOD_PRESENT signal tells the BSPT whether or not a component is plugged into the SFP socket. RX_LOS indicates that the optical input is absent or unusable. 1.3 Registers related to the CTP/BP LVDS Links Mngmnt status ============================================================ Addr Re Name Size Description VHDL name FPGA Function Comments ---- -- ---- ---- ----------- ---------- ---- ------- -------- 000C RO LinkStatus1 2 CTP/BP LVDS Links Mngmnt link_status1 BSPT LVDS ------------------------------------------------------------------------------------------------------------ All bit fields are outputs from the CMX Bit 00: TP_FPGA_INSTALLED_B Bit 01: ALLOW_BUSSED_IO Bit 02: BF_REQ_CTP_1_INPUT Bit 03: TP_REQ_CTP_1_INPUT Bit 04: BF_REQ_CTP_2_INPUT Bit 05: TP_REQ_CTP_2_INPUT Bit 06: CTP_1_TRNCVR_DIR Bit 07: CTP_1_BF_TRNSLT_DIR Bit 08: BSPT_CTP_1_BF_TRNSLT_OE_B Bit 09: CTP_1_TP_TRNSLT_DIR Bit 10: BSPT_CTP_1_TP_TRNSLT_OE_B Bit 11: CTP_2_TRNCVR_DIR Bit 12: CTP_2_BF_TRNSLT_DIR Bit 13: BSPT_CTP_2_BF_TRNSLT_OE_B Bit 14: CTP_2_TP_TRNSLT_DIR Bit 15: BSPT_CTP_2_TP_TRNSLT_OE_B 000E RO LinkStatus2 2 CTP/BP LVDS Links Mngmnt link_status2 BSPT LVDS ------------------------------------------------------------------------------------------------------------- All bit fields are outputs from the CMX Bit 00: BF_REQ_CABLE_1_INPUT Bit 01: CABLE_1_TRNCVR_DIR Bit 02: CABLE_1_TRNSLT_DIR Bit 03: BSPT_CABLE_1_TRNSLT_OE_B Bit 04: BF_REQ_CABLE_2_INPUT Bit 05: CABLE_2_TRNCVR_DIR Bit 06: CABLE_2_TRNSLT_DIR Bit 07: BSPT_CABLE_2_TRNSLT_OE_B Bit 08: BF_REQ_CABLE_3_INPUT Bit 09: CABLE_3_TRNCVR_DIR Bit 10: CABLE_3_TRNSLT_DIR Bit 11: BSPT_CABLE_3_TRNSLT_OE_B Bits 15-12: null 1.4 Registers related to the optical components access via I2C ============================================================== Addr Re Name Size Description VHDL name FPGA Function Comments ---- -- ---- ---- ----------- ---------- ---- ------- -------- 0010 RW SFP1_CSR 2 SFP1 Control/Status Reg sfp1_csr BSPT Opto_sfp ------------------------------------------------------------------------------------------------------------ Bit(13-00) are RW inputs to the CMX, bits (15-14) are RO outputs from CMX This register and the following SFP1 Data Register provide access to the 512 user accessible internal registers of the Avago AFBR-57M5APZ SFP chip. Power-up condition initially sets all bits to 0. A SFP I2C I/O operation takes place whenever this register is written unless the I2C bus is busy. Bits 07–00: SFP1 Register Number - Specify the register number to be read or written. Bit 08: SFP1 Page: 0 => SFP1 I2C address: 1010000X (0xA0); 1 => SFP1 I2C address: 1010001X (0xA2) Bits 10-09: null Bit 11: Write - When set to 1, defines the operation as a write to SFP1. When set to 0, the operation is a read. Bit 12: SFP1 I2C controller Abort - When set to 1, resets the I2C interface logic and aborts any I2C operation in progress. Bit 13: null Bit 14: SFP1 I2C controller Busy - When set to 1, indicates that an I2C transaction is underway Bit 15: SFP1 I2C controller Error - When set to 1, indicates that an I2C error has occurred 0012 RW SFP1_Data 2 SFP1 Data Register sfp1_data BSPT Opto_sfp ----------------------------------------------------------------------------------------------------------- Bits(07-00) are RW inputs to the CMX (data to SFP1); bits(15-08) are RO outputs from CMX (data from SFP1 Bits 07-00: Data from SFP1 - This 8-bit field contains last data read from SFP1 Writing to these bits has no effect Bits 15–08: Data to SFP1 - This 8-bit field contains data to be written to SFP1 Read back the value written to the RW_12 SFP1 Data Register (not to SFP) 0014 RW SFP2_CSR 2 SFP2 Control/Status Reg sfp2_csr BSPT Opto_sfp ------------------------------------------------------------------------------------------------------------ This register is similar to the SFP1 Control/Status Reg RW_00010 0016 RW SFP2_Data 2 SFP2 Data Register sfp2_data BSPT Opto_sfp ------------------------------------------------------------------------------------------------------------ This register is similar to the SFP1 Data Register RW_00012 0018 RW SFP3_CSR 2 SFP3 Control/Status Reg sfp3_csr BSPT Opto_sfp ------------------------------------------------------------------------------------------------------------ This register is similar to the SFP1 Control/Status Reg RW_00010 001A RW SFP3_Data 2 SFP3 Data Register sfp3_data BSPT Opto_sfp ------------------------------------------------------------------------------------------------------------ This register is similar to the SFP1 Data Register RW_00012 001C RW SFP4_CSR 2 SFP4 Control/Status Reg sfp4_csr BSPT Opto_sfp ------------------------------------------------------------------------------------------------------------ This register is similar to the SFP1 Control/Status Reg RW_00010 001E RW SFP4_Data 2 SFP4 Data Register sfp4_data BSPT Opto_sfp ------------------------------------------------------------------------------------------------------------ This register is similar to the SFP1 Data Register RW_00012 0020 RW MP12_CSR 2 MP12 Control/Status Reg mp12_csr BSPT Opto_mp ------------------------------------------------------------------------------------------------------------ Bits (13-00) are RW inputs to the CMX, bits (15-14) are RO outputs from CMX This register and the following MP12 Data Register provide access to the 256 user accessible internal registers of the Avago MiniPOD AFBR-811VxyZ(Transmitter) chips. Power-up condition initially sets all bits to 0. A MiniPOD I2C I/O operation takes place whenever this register is written unless the I2C bus is busy. Bits 07–00: MiniPOD Register Number - Specify the register number to be read or written. Bits 10-08: MiniPOD TWS Module Bus Address bits Adr[2:0] Address has the form 0101Adr[2:0](TX) or 0110Adr[2:0](RX) MiniPOD1 Adr[2:0]="000"; MiniPOD2 Adr[2:0]="001"; Bit 11: Write - When set to 1, defines the operation as a write to MiniPOD. When set to 0, the operation is a read. Bit 12: MP12 I2C controller Abort - When set to 1, resets the I2C interface logic and aborts any I2C operation in progress. Bit 13: null Bit 14: MP12 I2C controller Busy - When set to 1, indicates that an I2C transaction is underway Bit 15: MP12 I2C controller Error - When set to 1, indicates that an I2C error has occurred 0022 RW MP12_Data 2 MP12 Data Register mp12_data BSPT Opto_mp ------------------------------------------------------------------------------------------------------------ Bits(07-00) are RO outputs from CMX (data from MP12); bits(15-08) are RW inputs to the CMX (data to MP12); Bits 07-00: Data from MP12 - This 8-bit field contains last data read from MP12; Writing to these bits has no effect Bits 15–08: Data to MP12 - This 8-bit field contains data to be written to MP12 Read back the value written to the RW_22 SFP2_Dataregister (not to MiniPOD) 0024 RW MP345_CSR 2 MP345 Control/Status Reg mp345_csr BSPT Opto_mp ------------------------------------------------------------------------------------------------------------ This register is similar to the MP12 Control/Status Reg RW_00020 to access the Avago MiniPOD AFBR-821VxyZ (Receiver) chips MiniPOD3 Adr[2:0]="000"; MiniPOD4 Adr[2:0]="001"; MiniPOD5 Adr[2:0]="010"; 0026 RW MP345_Data 2 MP345 Data Register mp345_data BSPT Opto_mp ------------------------------------------------------------------------------------------------------------ This register is similar to the MP12 Data Register RW_00022 to access the Avago MiniPOD AFBR-821VxyZ (Receiver) chips 1.5 Registers related to the LEDs control ========================================= Addr Re Name Size Description VHDL name FPGA Function Comments ---- -- ---- ---- ----------- ---------- ---- ------- -------- 0028 RW LEDsControl 2 LEDs Control register leds_cntrl BSPT LEDs ------------------------------------------------------------------------------------------------------------ All bit fields are inputs to the CMX Bit 00: LEDs Control - when 0, LEDs illuminated by internal BSPT FPGA signal Writing a 1 to this bit sets the LEDs control to this register (bits 15-01) Bit 01: LED_1R_GREEN - default value (bit 00 = '0') <= TTCrx Ready Bit 02: LED_2L_GREEN - default value (bit 00 = '0') <= BF FPGA configured Bit 03: LED_2R_GREEN - default value (bit 00 = '0') <= TP FPGA configured Bit 04: LED_3L_GREEN Bit 05: LED_3L_RED Bit 06: LED_3R_GREEN Bit 07: LED_3R_RED Bit 08: LED_4L_GREEN Bit 09: LED_4L_RED Bit 10: LED_4R_GREEN Bit 11: LED_4R_RED Bit 12: LED_5L_GREEN Bit 13: LED_5L_RED Bit 14: LED_5R_GREEN Bit 15: LED_5R_RED 002A RO LEDsRequests 2 LEDs Requests Status leds_req BSPT LEDs ------------------------------------------------------------------------------------------------------------ All bit fields are outputs from the CMX Bit 00: BF_LED_REQ_0 Bit 01: BF_LED_REQ_1 Bit 02: BF_LED_REQ_2 Bit 03: BF_LED_REQ_3 Bit 04: BF_LED_REQ_4 Bits 07-05: null Bit 08: TP_LED_REQ_0 Bit 09: TP_LED_REQ_1 Bit 10: TP_LED_REQ_2 Bit 11: TP_LED_REQ_3 Bit 12: TP_LED_REQ_4 Bits 15-13: null 1.6 Registers related to debugging signals ========================================== 002C RO BFTPDebug 2 BF and TP debug signals bftp_debug BSPT Debugging ------------------------------------------------------------------------------------------------------------ All bit fields are outputs from the CMX Bit 00: BF_TO_FROM_BSPT_0 Bit 01: BF_TO_FROM_BSPT_1 Bit 02: BF_TO_FROM_BSPT_2 Bit 03: BF_TO_FROM_BSPT_3 Bit 04: BF_TO_FROM_BSPT_4 Bit 05: BF_TO_FROM_BSPT_5 Bit 06: BF_TO_FROM_BSPT_6 Bit 07: BF_TO_FROM_BSPT_7 Bit 08: TP_TO_FROM_BSPT_0 Bit 09: TP_TO_FROM_BSPT_1 Bit 10: TP_TO_FROM_BSPT_2 Bit 11: TP_TO_FROM_BSPT_3 Bit 12: TP_TO_FROM_BSPT_4 Bit 13: TP_TO_FROM_BSPT_5 Bit 14: TP_TO_FROM_BSPT_6 Bit 15: TP_TO_FROM_BSPT_7 002E RO BSPTDebug 2 BSPT debug signals bspt_debug BSPT Debugging ------------------------------------------------------------------------------------------------------------ All bit fields are outputs from the CMX Bit 00: BSPT_DEBUG_0 Bit 01: BSPT_DEBUG_1 Bit 02: BSPT_DEBUG_2 Bit 03: BSPT_DEBUG_3 Bit 04: BSPT_DEBUG_4 Bit 05: BSPT_DEBUG_8 Bit 06: BSPT_DEBUG_9 Bit 07: SPR_Conn_BSPT_Pin_A2 Bit 08: SPR_Conn_BSPT_Pin_B1 Bit 09: SPR_Conn_BSPT_Pin_J8 Bit 10: SPR_Conn_BSPT_Pin_K8 Bit 11: SPR_Conn_BSPT_Pin_M6 Bit 12: SPR_Conn_BSPT_Pin_M7 Bit 13: SPR_Conn_BSPT_Pin_M8 Bits 15-14: null 1.7 Registers related to the TTCrx chip on the TTCDec card ========================================================== Addr Re Name Size Description VHDL name FPGA Function Comments ---- -- ---- ---- ----------- ---------- ---- ------- -------- 0030 RW TTCrxControl 2 TTCrx Control Register ttc_control BSPT TTC ------------------------------------------------------------------------------------------------------------ All bit fields are inputs to the CMX This register and the following TTCrx Status Register provide access to the 20 user accessible internal registers of the TTCrx chip (see also [5]). Power-up condition initially sets all bits to 0. A TTCrx I/O operation takes place whenever this register is changed, unless the I2C bus is busy (see TTC Status register below). An I2C operation is aborted if the reset bit is set. Bits 00–07: Data to TTCrx - This 8-bit field contains data to be written to the TTCrx chip. Bits 12-08: TTCrx Register Number - Specify the TTCrx register number to be read or written Bit 13: Write - When set to 1, defines the operation as a write to TTCrx. When set to 0, the operation is a read. Bit 14: null Bit 15: TTCrx Controller Abort When set to 1, resets the I2C interface logic in the BSPT FPGA and aborts any I2C operation in progress. (What the difference: Reset TTCrx I2C controller - bit 05 in the Module Resets Register 00006 ???) 0032 RO TTCrxStatus 2 TTCrx Status Register ttc_status BSPT TTC -------------------------------------------------------------------------------------------------------------- All bit fields are outputs from the CMX Bits 07-00: Data from TTCrx - This 8-bit field contains data read from the TTCrx chip. Bits 12-08: null Bit 13: I2C Busy - When set to 1, indicates that an I2C transaction is underway Bit 14: I2C Error - When set to 1, indicates that an I2C error has occurred Bit 15: null 0034 RO TTCrxBrcst 2 TTCDec Brcst Register ttc_brcst BSPT TTC -------------------------------------------------------------------------------------------------------------- All bit fields are outputs from the CMX Bits 01-00: null Bits 05-02: TTCrx BRCST data (2:5) - The most recent value of BRCST data bits (2:5) output from the TTCrx (that were qualified by the TTC strobe BRCSTSTR1). Bits 07-06: TTCrx BRCST data (6:7) - The most recent value of BRCST data bits (6:7) output from the TTCrx (that were qualified by the TTC strobe BRCSTSTR2). Bits 15-08: null 0036 RO TTCrxDq 2 TTCDec DQ Register ttc_dq BSPT TTC -------------------------------------------------------------------------------------------------------------- All bit fields are outputs from card. Bits 03-00: TTCrx DQ - The most recent DQ value output from the TTCrx (that was qualified by the TTC strobe DOUTSTR). Bits 15-04: null 0040 RO TTCrxDump 32 TTCDec Dump RAM ttc_ram BSPT TTC addresses from 0040 to 005E -------------------------------------------------------------------------------------------------------------- All bit fields are outputs from card. Bits 07-00: TTCrx Dump Data A block of RAM 16 words deep that captures data from TTC Error and Configuration Dumps. Data from the TTC are mapped to the RAM using DQ as the address. Bits 15-08: null 1.8 Registers related to the XILINX SystemACE chip ================================================== This is a block of XILINX SystemACE MPU registers (96 8-bit registers) mapped to the VME memory (see also [6]) Addr Re Name Size Description VHDL name FPGA Function Comments ---- -- ---- ---- ----------- ---------- ---- ------- -------- 0080 ->See SystemACE 96 ->See SystemACE ->See SystemACE BSPT ACE addresses from 0080 to 00DF -------------------------------------------------------------------------------------------------------------- 1.9 Temporary registers for tests ================================= These are registers 0038 RW TempReg1 2 Temporary RW register 1 vme_rw_reg1 BSPT reserved 003A RW TempReg2 2 Temporary RW register 2 vme_rw_reg2 BSPT reserved 003C RW TempReg3 2 Temporary RW register 3 vme_rw_reg3 BSPT reserved 003E RW TempReg4 2 Temporary RW register 4 vme_rw_reg4 BSPT reserved 0060 RW RegArray 32 Temporary RW array 1 vme_rw_array1 BSPT reserved addresses from 0060 to 007F