CMX Board Jumpers ------------=======-- Original Rev. 5-Nov-2012 Current Rev. 3-Dec-2014 This file describes all of the jumpers that are on the CMX circuit board. These 114 jumpers are used to setup and control various functions of the CMX card. JMP1, JMP2, JMP3 Geographic Address Jumpers Geographic Address lines 0, 4, 5, 6 come from the backplane. Geographic Address lines 1, 2, 3 come from jumpers 1, 2, 3. When one of these 3 jumpers is installed the corresponding Geographic Address line is pulled LOW. E.G. if JMP2 is installed then Geographic_Address_2 is pulled LOW. notes: For the CMM slots, the value of GeoAddr 0 identifies the left-side slot number 3 with GA0 = 0 from the right-slide slot number 20 with GA0 = 1. GA4, GA5, GA6 identify the crate in the overall L1Calo system. Prototype build default: Set GA1, GA2, GA3 Low --> Install jumpers JMP1, JMP2, JMP3. Production build default: TBD JMP4 Board Support FPGA Configuration PROM CF_B signal to PROG_B Installing JMP4 allows the JTAG connection to the Configuration PROM for the Board Support FPGA to initiate the configuration of this FPGA. When installed, JMP4 connects the PROM's CF_B signal to the BSPT FPGA's PROG_B pin. Prototype build default: PROM cannot initiate configuration --> JMP4 NOT installed Production build default: TBD JMP5, JMP6, JMP7 Backplane LVDS Receiver Failsafe When installed the corresponding set of backplane LVDS receivers are in normal "Type 1" mode, i.e. symmetric voltage thresholds. When removed the corresponding set of LVDS receivers are in "Type 2" Failsafe mode with offset voltage thresholds. Normally we expect that all 3 of these jumpers will be installed. JMP5 controls the Upper Backplane Cable receivers. JMP6 the Middle and JMP7 the Lower cable receivers. Prototype build default: Symmetric voltage threshold --> JMP5, JMP6, JMP7 Installed Production build default: TBD R181, R182, R183 Backplane LVDS Transceiver Master_Enable These 3 "jumpers" are really 100 Ohm resistors. When they are installed they pull the Master Enable pin on the associated LVDS transceivers voltage HI there by enabling normal operation of these DS91M040 LVDS transceivers. We expect that normally all 3 of these "jumpers" will be installed. R181 controls the Upper Backplane Cable transceivers. R182 the Middle and R183 the Lower cable transceivers. Prototype build default: LVDS Transceivers enabled --> R181, R182, R183 Installed Production build default: TBD JMP8 and JMP9 Front Panel CTP LVDS Receiver Failsafe When installed the corresponding set of Front Panel CTP LVDS receivers are in normal "Type 1" mode, i.e. symmetric voltage thresholds. When removed the corresponding set of LVDS receivers are in "Type 2" Failsafe mode with offset voltage thresholds. Normally we expect that both of these jumpers will be installed. JMP8 controls the receivers for the Upper CTP connector J10. JMP9 controls the receivers for the Lower CTP connector J11. Prototype build default: Symmetric voltage threshold --> JMP8 and JMP9 Installed Production build default: TBD R184 and R185 Front Panel CTP LVDS Transceiver Master_Enable These 2 "jumpers" are really 100 Ohm resistors. When they are installed they pull the Master Enable pin on the associated set of LVDS transceivers voltage HI there by enabling normal operation of these DS91M040 LVDS transceivers. We expect that normally both of these "jumpers" will be installed. R184 controls the LVDS Transceivers for the Upper CTP connector J11. R185 controls the LVDS Transceivers for the Lower CTP connector J11. Prototype build default: LVDS Transceivers enabled --> R184 and R185 Installed Production build default: TBD JMP10 through JMP27 TTCDec Chip_ID and Master_Mode Bits These 18 jumpers are used to set 9 of the TTCDec CHIP_ID and MASTER_MODE bits when the TTCDec is Reset. Where installed, these "jumpers" are actually 4.7k Ohm 0603 resistors. They are setup as follows: Jumper to ------------- Pull Pull Low High ----- ----- JMP10 JMP11 ---> CHIP_ID(0) JMP12 JMP13 ---> CHIP_ID(1) JMP14 JMP15 ---> CHIP_ID(2) JMP16 JMP17 ---> CHIP_ID(3) JMP18 JMP19 ---> CHIP_ID(4) JMP20 JMP21 ---> CHIP_ID(5) JMP22 JMP23 ---> CHIP_ID(13) JMP24 JMP25 ---> MASTER_MODE(0) aka CHIP_ID(14) JMP26 JMP27 ---> MASTER_MODE(1) aka CHIP_ID(15) The remaining 7 bits of the CHIP_ID i.e. 12:6 are controlled by the 7 Geographic Address lines. Prototype build default: Set all of these TTCDec Chip ID signals LOW. --> Jumpers 10, 12, 14, 16, 18, 20, 22, 24, 26 Installed --> Jumpers 11, 13, 15, 17, 19, 21, 23, 25, 27 NOT installed After the prototype build it was learned that the TTCDec bit CHIP_ID(2) must be set HI. Thus for actual operation of the CMX cards these jumpers will be: Set all of these TTCDec Chip ID signals LOW except CHIP_ID(2) is set HI. --> Jumpers 10, 12, 15, 16, 18, 20, 22, 24, 26 Installed --> Jumpers 11, 13, 14, 17, 19, 21, 23, 25, 27 NOT installed R254, R255, R256 TTCDec CMX Clock Select Resistors R254 and R256 select whether the CLK_40_DES_1 or the CLK_40_DEC_1_PLL signal from TTCDec is used as the reference for the 40.08 MHz DeSkew-1 clock and thus also for the 320.64 MHz clock on the CMX card. Install R254 to select TCC_CLK_40_DES_1_PLL Install R256 to select TCC_CLK_40_DES_1 Note that resistor R255 is always installed to provide the CLK_40_DEC_2_PLL signal from TTCDec as the reference for the 40.08 MHz DeSkew-2 clock on the CMX card. These Jumper-Resistors also acts as a series back terminators on the traces that take the TTCDec output to the CMX Clock Generator. When installed, these "jumpers" are actually 47 Ohm 0603 resistors. Prototype build default: We will use the TTCDec signal CLK_40_DEC_1_PLL as the reference for the DeSkew-1 clocks on the CMX card. --> R254 Installed --> R256 NOT Installed Production build default: TBD JMP28 TTCDec Buffer Direction Control Jumper 28 sets the Direction of the Translator/Buffer chips U151:U154 (only 1/2 of U154) for the TTCDec Output Bus. The TTCDec output signals are converted to 2.5V and driven onto the TCCDec Output Bus to go to the Board Support FPGA and optionally to the Base Function and Topological Processor FPGA. The required Direction is "B"-->"A" so Direction control signal must be LOW. JMP28 is normally always installed, i.e. pull DIR Low. Prototype build default: Direction TTCdec -> BSPT --> JMP28 Installed Production build default: TBD JMP31 through JMP36 Base Function FPGA M2,M1,M0 These 6 jumpers control the M2, M1, and M0 Configuration signals to the Base Function Virtex FPGA. Normally the Base Function FPGA is Configured via JTAG which requires the M2, M1, M0 signals to be set to "101". Never install both the HI and LOW jumpers for a given signal. Install JMP31 to pull M2 LOW JMP32 to pull M2 HI Install JMP33 to pull M1 LOW JMP34 to pull M1 HI Install JMP35 to pull M0 LOW JMP36 to pull M0 HI Prototype build default: Select JTAG programming (101) --> JMP32, JMP33, JMP36 Installed --> JMP31, JMP34, JMP35 NOT installed Production build default: TBD JMP37 and JMP38 Base Function FPGA HSWAPEN Pin These 2 jumpers control the state of the HSWAPEN pin on the Base Function FPGA. Install only one of these jumpers - installing both will short the Bulk_2V5 bus. Install JMP37 to pull HSWAPEN Low Install JMP38 to pull HSWAPEN Hi Prototype build default: Enable the BF FPGA's weak pull-ups during configuration. --> JMP37 Installed --> JMP38 NOT installed Production build default: TBD JMP41 through JMP46 Topological FPGA M2,M1,M0 These 6 jumpers control the M2, M1, and M0 Configuration signals to the Topological Processor Virtex FPGA. Normally the Topological Processor FPGA is Configured via JTAG which requires the M2, M1, M0 signals to be set to "101". Never install both the HI and LOW jumpers for a given signal. Install JMP41 to pull M2 LOW JMP42 to pull M2 HI Install JMP43 to pull M1 LOW JMP44 to pull M1 HI Install JMP45 to pull M0 LOW JMP46 to pull M0 HI Prototype build default: Select JTAG programming (101) --> JMP42, JMP43, JMP46 Installed --> JMP41, JMP44, JMP45 NOT installed Production build default: TBD JMP47 and JMP48 Topological Processor FPGA HSWAPEN Pin These 2 jumpers control the state of the HSWAPEN pin on the Topological Processor FPGA. Install only one of these jumpers - installing both will short the Bulk_2V5 bus. Install JMP47 to pull HSWAPEN Low Install JMP48 to pull HSWAPEN Hi Prototype build default: Enable TP FPGA's weak pull-ups during configuration. --> JMP47 Installed --> JMP48 NOT installed Production build default: TBD JMP49 Topological Processor FPGA Installed This jumper unambiguously indicates to the Board Support FPGA whether or not the Topological Processor FPGA is installed on this card. This signal, TP_FPGA_INSTALLED_B, has a pull-up resistor to BULK_2V5 and the jumper JMP49 runs to Ground. Thus the TP_FPGA_INSTALLED_B signal is Low active. Low means that the TP FPGA is installed. Install JMP49 only on cards that have a Topological Processor FPGA installed on them Prototype build default: 3 of 4 prototypes can have it and easier to remove than add --> JMP49 Installed Production build default: TBD JMP51 through JMP56 Board Support FPGA M2,M1,M0 These 6 jumpers control the M2, M1, and M0 Configuration signals to the Board Support Spartan FPGA. Normally the Board Support FPGA is Configured via Master Serial mode from its dedicated Configuration "Platform FLASH" PROM which requires the M2, M1, M0 signals to be all set LOW. Never install both the HI and LOW jumpers for a given signal. Install JMP51 to pull M2 LOW JMP52 to pull M2 HI Install JMP53 to pull M1 LOW JMP54 to pull M1 HI Install JMP55 to pull M0 LOW JMP56 to pull M0 HI Prototype build default: Select serial EPROM configuration for the BSPT (000). --> JMP51, JMP53, JMP55 Installed --> JMP52, JMP54, JMP56 NOT installed Production build default: TBD JMP57 Board Support FPGA PUDC_B Pin JMP57 controls the state of the PUDC_B pin on the Board Support FPGA. The BSPT PUDC_B pin is like the HSWAPEN pin on the Virtex devices. When PUDC_B is LOW then before the initial configuration and during subsequent confirguration processes the I/O and Input pins have pull-up resistors to define a valid logic level on them JMP57 pulls BSPT PUDC_B LOW. R326 pulls PUDC_B HI. Install JMP57 to pull PUDC_B Low Remove JMP57 and PUDC_B will go Hi Prototype build default: Enable BSPT FPGA's weak pull-ups during configuration. --> JMP57 Installed Production build default: TBD JMP59 CMX Card Safe Jumper JMP59 indicates that it is safe to use buses on this CMX card. JMP59 is used to make the signal JUMPER_CMX_SAFE_B. This signal has a pull-up resistor to BULK_3V3 and the jumper JMP59 runs to Ground. Thus the JUMPER_CMX_SAFE_B signal is Low active. Low means that it is safe to use the buses on this CMX card. The signal JUMPER_CMX_SAFE_B is used by the Hardwired Oversight Logic. Install JMP59 only on card where it is safe to enable the VME-OCB drivers and the CTP and Cable Translator outputs. Prototype build default: Start in safe mode --> JMP59 NOT installed Production build default: TBD R257 Geographic Address Buffer Direction Control Jumper R257 is a 1k Ohm resistor that controls the Direction pin of the section of U154 that sends the Geographic Address lines to some of the TTCDec CHIP ID input pins when the TTCDec is being Reset. The Direction of just this section of U154 is always "A"-->"B" so the Direction control pin must be HI. R257 is normally always installed, i.e. pull DIR HI. Prototype build default: Direction GeoAddr -> TTCdec --> R257 Installed Production build default: TBD JMP61 through JMP68 TEST JTAG Chain Device Skip Jumpers JMP61 and JMP62 allow the front panel TEST JTAG chain to skip across the System-ACE device. Install either JMP61 or JMP62 - not both. Install JMP61 to include the System-ACE. Install JMP62 to skip the System-ACE. JMP63 and JMP64 allow the front panel TEST JTAG chain to skip across the TTCDec device. Install either JMP63 or JMP64 - not both. Install JMP63 to include the TTCDec. Install JMP64 to skip the TTCDec. JMP65 and JMP66 allow the front panel TEST JTAG chain to skip across the Configuration PROM for the BSPT FPGA. Install either JMP65 or JMP66 - not both. Install JMP65 to include the Configuration PROM. Install JMP66 to skip the Configuration PROM for the BSPT FPGA. JMP67 and JMP68 allow the front panel TEST JTAG chain to skip across the BSPT FPGA. Install either JMP67 or JMP68 - not both. Install JMP67 to include the BSPT FPGA. Install JMP68 to skip the BSPT FPGA. Note that to include the BSPT FPGA and provide back termination on the TDO data being sent to the JTAG interface pod that a resistor could be used in JMP67. Prototype build default: Include System-ACE, skip TTCdec, include BSPT EPROM, include BSPT --> JMP61, JMP64, JMP65, JMP67 Installed --> JMP62, JMP63, JMP66, JMP68 NOT installed Production build default: TBD JMP71 through JMP74 Configuration JTAG Chain Skip Jumpers JMP71 and JMP72 allow the System-ACE Configuration JTAG chain to skip across the Base Function FPGA U1. Install either JMP71 or JMP72 - not both. Install JMP71 to include the Base Function FPGA in the Configuration JTAG chain. Install JMP72 to skip the Base Function FPGA. JMP73 and JMP74 allow the System-ACE Configuration JTAG chain to skip across the Topological Processor FPGA U2. Install either JMP73 or JMP74 - not both. Install JMP73 to include the Topological Processor FPGA in the Configuration JTAG chain. Install JMP74 to skip the Topological Processor FPGA. Prototype build default: Include Base FPGA, skip TP FPGA --> JMP71, JMP74 Installed --> JMP72, JMP73 NOT installed Production build default: TBD JMP75 and JMP76 BF and TP INIT_B to System-ACE Select JMP75 and JMP76 allow selection of which Virtex FPGAs have their INIT_B Configuration signals connected to the System-ACE CFGINIT_B pin. This controls which subset of the two Virtex FPGAs the System-ACE will confirm is ready to receive a configuration before starting to send the bitstream to it via the Configuration JTAG. Installing JMP75 connects the Base Function FPGA's INIT_B signal to the System-ACE's CFGINIT_B pin. Installing JMP76 connects the Topological Processor FPGA's INIT_B signal to the System-ACE's CFGINIT_B pin. Note that the System ACE's CFGINIT_B pin is pulled up to 2.5 Volts with a 4.7k Ohm resistor. Prototype build default: Only listen to Base FPGA --> JMP75 Installed --> JMP76 NOT installed Production build default: TBD JMP78 and JMP79 TP_CORE DC/DC Converter Disable Jumpers Jumpers JMP78 and JMP79 are used to disable the TP_CORE DC/DC Converter on CMX cards that do not include a Topological Processor FPGA. JMP78 is associated with this converter's Inhibit pin. JMP79 is associated with this converter's Track pin. To disable the TP_Core DC/DC Converter install jumper JMP78 to pull this converter's Inhibit pin to Ground, and remove JMP79 to isolate this converter's Track pin from the Track bus that spans the other 6 converters. For operation of CMX cards with a Topological Processor FPGA remove JMP78 and install JMP79. Prototype build default: 3 of 4 prototypes can enable TP_CORE --> JMP78 Installed --> JMP79 NOT installed Production build default: TBD JMP81 System-ACE POR_BYPASS Pin Jumper JMP81 controls the state of the Xilinx System-ACE POR_BYPASS pin. When JMP81 is installed then the POR_BYPASS pin is held LOW and the System-ACE's internal power on reset circuits are used. With JMP81 removed the external POR_RESET signal can be used. The pull-up resistor for JMP81 is R308. Install JMP81 ACE uses internal Power On Reset circuit Remove JMP81 ACE uses external POR_RESET pin signal Prototype build default: Use External POR_RESET --> JMP81 NOT installed Production build default: TBD JMP85 CAN-Bus Monitoring Analog Multiplexer Control Jumper JMP85 determines whether the CAN-Bus uProcessor controls the External Analog Multiplexer or whether the External Analog Multiplexer is held in the state that sends the Voltage Monitoring signals to the ADCs in the CAN_Bus uProcessor. Install JMP85 CAN-Bus uProc controls the Analog Mux. Remove JMP85 Analog Mux sends Voltage Monitoring to ADCs. Prototype build default: Analog Mux sends only Voltage monitoring information --> JMP85 NOT Installed Production build default: TBD R481, R482, R483 PLL Lock-Detect to BSPT FPGA DEBUG Input These 3 jumpers are used to connect the Lock-Detect output signal from the 3 PLLs to Board Support FPGA DeBug signals input pins. These 3 jumpers are located near the J14 FPGA DeBug Connector. If these BSPT FPGA DeBug signals are needed for some other purpose then these jumpers must be removed. If these BSPT DeBug signals are not needed for some other purpose then they may be used to monitor the Lock Status of the 3 PLL circuits on the CMX card. When installed, these "jumpers" are actually 1.0k Ohm 0603 resistors. Installing R481 connects the Lock-Detect signal from the 320.6296 MHz PLL to the BSPT FPGA DEGUG_6 input. Installing R482 connects the Lock-Detect signal from the DeSkew-1 40.08 MHz PLL to the BSPT FPGA DEGUG_5 input. Installing R483 connects the Lock-Detect signal from the DeSkew-2 40.08 MHz PLL to the BSPT FPGA DEGUG_7 input. The default build option is to install these 3 jumpers. Prototype build default: Connect the Lock-Detect signals: --> R481, R482, R483 Installed Production build default: TBD R365 through R370 Select the Two Front Panel Access Signals The CMX card provides two Front Panel Access Signals. The jumper resistors R365 through R370 are used to select the source of the two FP Access Signals. Either the Base Function FPGA, the Topological Processor FPGA or the Board Support FPGA may be the source of a given FP Access Signal. When installed, these "jumpers" are actually 47 Ohm 0603 resistors. Select FP_Access_Signal_1: Installation of R365 selects BSPT FPGA DEBUG_8 as the source of the FP_Access_Signal_1 Installation of R366 selects Base Function FPGA DEBUG_8 as the source of the FP_Access_Signal_1 Installation of R369 selects Topological FPGA DEBUG_8 as the source of the FP_Access_Signal_1 Select FP_Access_Signal_2: Installation of R367 selects BSPT FPGA DEBUG_9 as the source of the FP_Access_Signal_2 Installation of R368 selects Base Function FPGA DEBUG_9 as the source of the FP_Access_Signal_2 Installation of R370 selects Topological FPGA DEBUG_9 as the source of the FP_Access_Signal_2 Install only R365, R366, or R369 - only one Install only R367, R368, or R370 - only one If the BF or BSPT DeBug signals are used for some other purpose then you may not want to install any of these jumper resistors. The default build option is to install R365 and R367 i.e. both FP Access Signals will come from the BSPT FPGA. Prototype build default: BSPT debug signal 8 and 9 sent to front panel --> R365, R367 Installed --> R366, R368, R369, R370 NOT installed Production build default: TBD JMP91A, JMP91B : JMP96A, JMP96B, JMP97, JMP98 Installing any of these 14 jumpers grounds the associated object to the CMX pcb ground planes. These jumpers may be left open, have a Zero Ohm jumper installed, or have any appropriate value resistor installed to optimize the ground loop and ground noise environment of the CMX card and the other cards in the L1Calo Processor Crate. JMP91A, JMP91B 2 jumpers to ground the SFP1 Cage JMP92A, JMP92B 2 jumpers to ground the SFP2 Cage JMP93A, JMP93B 2 jumpers to ground the SFP3 Cage JMP94A, JMP94B 2 jumpers to ground the SFP4 Cage JMP95A, JMP95B 2 jumpers to ground the bodies of front panel CTP connectors J10 and J11 JMP96A, JMP96B 2 jumpers to ground the 18 pins in the backplane connectors: J4, J5, J6 JMP97 jumper to ground pins 34 & 68 in CTP conn J10. JMP98 jumper to ground pins 34 & 68 in CTP conn J11. Note that in assembly of the CMX cards that the Front Panel, the SFP Cages, and the bodies of CTP connectors J10 and J11 may all be mechanically and electrically bonded together. The possible electrical connection of all (or just of some) of these objects will effect which of the above jumpers should be installed. Prototype build default: Hold the SFP Cages quiet with a semi weak connection to the CMX ground planes. Note that the SFP Cages will most likely make electrical contact with the front-panel. --> Install 4.7k Ohm 0603 resistors at JMP91A, JMP91B --> Install 4.7k Ohm 0603 resistors at JMP92A, JMP92B --> Install 4.7k Ohm 0603 resistors at JMP93A, JMP93B --> Install 4.7k Ohm 0603 resistors at JMP94A, JMP94B The Front Panel and Stiffener Bars will be tied to the CMX's ground planes via connection through the all metal CTP connector bodies. We want a strong enough connection to provide ESD protection. We want a weak enough connection to prevent ground loops. --> Install 4.7k Ohm 0603 resistors at JMP95A, JMP95B Hold the backplane pins quiet with a semi stiff connection to the CMX ground planes. --> Install 100 Ohm 0603 resistors at JMP96A, JMP96B Hold the CTP connector pins 34 & 68 quiet with a semi stiff connection to the CMX ground planes. --> Install 100 Ohm 0603 resistors at JMP97 & JMP98 Production build default: TBD R801 through R804 R801 and R802 control the grounding of the Base Function FPGA's Heat-Sink. R803 and R804 control the grounding of the Topological Processor FPGA's Heat-Sink. One may install either low value resistors, e.g. 10 to 100 Ohm, or Zero-Ohm jumpers in these locations. The FPGA's top surface heat spreader is at ground potential but it is not clear that this surface should be hard connected to the pcb's ground planes. Electro Static Discharge from people touching the heat-sink is another consideration in the grounding of the Virtex heat-sinks. R801 and R802 install jumper or resistor to ground the Base Function FPGA Heat-Sink R803 and R804 install jumper or resistor to ground the Topological Processor FPGA Heat-Sink Prototype build default: Semi stiff ground connection to both Virtex heat-sinks. --> Install 100 Ohm 0603 resistors at R801,R802, R803, R804. Production build default: TBD JMP101 through JMP105 Set a unique CMX Card Serial Number Jumpers JMP101 through JMP105 set a unique 5-bit CMX Card Serial Number. This 5-bit CMX Card Serial Number is used by the BSPT to make a unique 8-bit Module Serial Number. The 8-bit Module Serial Number together with the 4-bit Hardware Revision Number (which is common to all CMX cards and held in BSPT programming) make up the L1Calo 12-bit Module ID. Install JMP101:JMP105 - to set CMX Card Serial Num bit (1:5) Low Remove JMP101:JMP105 - to set CMX Card Serial Num bit (1:5) Hi Prototype build default: These jumpers must be set to give each CMX card a unique CMX Card Serial Number. They will be installed at MSU as we test each CMX card. --> JMP101 : JMP105 NOT Installed by assembly vendor Production build default: --> JMP101 : JMP105 NOT Installed by assembly vendor