CMX Glossary -------------------- Original Rev. 13-Dec-2012 Current Rev. 30-Apr-2014 A number of acronyms and abbreviations have been used in the design of the CMX card. This file contains the definitions of these terms. The net_names used in the design of the CMX have been written in all capital letters to prevent the chance of confusion by downstream tools. ACE System ACE (Advanced Configuration Environment) is a Xilinx product designed to configure Xilinx FPGAs from the content of a Compact Flash memory card. BF FPGA Base Function FPGA. The CMX FPGA which implements and extends the original CMM functions and additionnally sends data to the L1Topo or CMX-Topo. BSPT the Board Support FPGA CAN CAN bus (Controller Area Network) is a bus standard which originated in the automobile industry and designed to allow microcontrollers and devices to communicate with each other. It is used to report voltage and temperature monitoring on CMX CMM Common Merger Module CMX Common Merger Extended module CMX-Topo An optional mode of operation for a CMX card to act as a limited Topological Processor system in place of or parallel to the L1calo L1Topo system. CPM Cluster Processor Module. One of two types of modules sending real-time trigger information to the CMX through the backplane. CP Cluster Processor sub-system of the Calorimeter Trigger CTP Central Trigger Processor DAQ Data Acquisition. Used to identify one of the two types of G-link output ports on CMX by the information they send to a ROD DCS Distributed Control System. This is a generic term. CAN bus is a DCS DTACK_B Data Transmission Acknowledge (the "_B" postfix denotes that a logic low is used to assert the signal). One of the VME bus lines used by slave devices to convey their current status to the master during a bus cycle. FPGA Field Programmable Gate Array. An integrated circuit designed to be configured with specific firmware at run-time. G-link A 1Gbps protocol used by CMX to send out information to one or more RODs after every L1Accept. GTX (not an acronym) The MGT resource type available on the Virtex-6 FPGA used on CMX (XC6VLX550T), and capable of serial IO up to 6.6 Gbps. I2C Inter-Integrated Circuit (pronounced "eye-squared cee" or "eye-two-cee") is a "two-wire interface" multi-master serial single-ended computer bus used to attach low-speed peripherals. It is used to control the TTCrx chip of the TTCdec module. JEM Jet/Energy processor Module. One of two types of modules sending real-time trigger information to the CMX through the backplane. JEP Jet/Energy Processor sub-system of the Calorimeter Trigger JTAG Joint Test Action Group. A Standard for the Test Access Port and Boundary-Scan Architecture. L1A Level-1 Accept signal distributed via the TTC system. L1Calo Atlas Level 1 Calorimeter Trigger L1Topo Level 1 Trigger Topological Processor. This term generally refers to a standalone system being built for the Phase 0 upgrade of L1calo. The CMX platform is also designed to operate like a limited L1topo system using inputs from all CMX cards which is then called a CMX-Topo system. LVDS Low-Voltage Differential Signaling. A signaling standard used for the CMX to CMX Cable IO and for the output to CTP. MGT Multi-Gigabit Transceiver. A special type of IO pin on Virtex-6 for multi-gigabit serial IO (as opposed to Select IO pins). All MGT resources on the Virtex-6 FPGA used on CMX are GTX transceivers. MiniPOD The name of a family of optical transmitters and receivers manufactured by Avago (formerly Agilent, formerly HP). MMCM Mixed-Mode Clock Manager. A clock management resource on Virtex-6. MP MiniPOD the Avago optical transmitters and receivers used for the 6.4 Gb/s "high speed" optical links from the Base Function FPGA and to TP Function FPGA MPO/MTP Multiple-Fiber Push-On. A multi-fiber connector standard. ROD Read-Out Driver module. CMX sends information a every L1 Accept to a DAQ ROD and some CMX cards also send information to an ROI ROD. ROI Region of Interest. Used to identify one of the two types of G-link output ports on CMX by the information they send to a ROD RS-232 A serial communication standard commonly used for computer ports. RTM Rear Transition Module. A Card plugging in the back of CMX with connectors to plug up to 3 LVDS cables for Crate CMX to System CMX communication Select IO The standard type of IO pins on Virtex-6 (as opposed to MGT IO pins) S-LINK Simple Link Interface. The CERN specification for readout of front-end electronics used in ATLAS L1calo. SFP Small Form-factor Pluggable the optical transmitters that send out the 1 Gb/s "low speed" optical data from the BF and TP functions on the CMX to the ROI and DAQ systems TCM Timing and Control Module. One of the modules in the L1calo crates. TP FPGA Topological Processor FPGA on the CMX card TTC Timing, Trigger and Control. The centralized timing and control distribution system common to LHC experiments. It is distributed by a fibre distribution tree, with all information multiplexed onto a single optical signal. TTCDec TTC Decoder mezzanine card which recovers the 40.08 MHz LHC clock, the L1 Accept, the Bunch and Event identification information, as well as broadcast or targeted commands. It also includes a 40.00 MHz crystal for tests purposes. TTCrx The CERN custom IC used to receive the TTC signal. This chip provides is the core of the TTCDec. VAT The VAT card (VME/ACE/TTC) is a parallel prototype project to practice System ACE control and test Board Support FPGA firmware VME Versa Module Eurocard. A computer bus standard popular in HEP. VME-- A subset of the VME signals used for communication within L1calo crates. This bus is used on the custom backplane for the L1calo CP and JEP crates. VREF The name for the usage of some Virtex-6 Select IO pins with an external voltage reference. VREF can be used by an IO Bank as an input threshold voltage with a differential amplifier input buffer. Using an external VREF is a backup feature of CMX to recieve the 400 backplane inputs, as the nominal plan is to use the built-in 2.5V CMOS input standard. VRP,VRN The names of the two Virtex-6 Select IO pins used with a pair of external resistors to be optionally used with the Digitally Controlled Impedance technology to set the input impedance of the 400 backplane inputs. This is a backup feature of CMX as the nominal plan is to NOT terminate the 400 processor input signals.