CMX_0 Mentor Layout Details ------------------------------ Original Rev. 25-Aug-2011 Current Rev. 29-Apr-2014 This file collects the details of the Mentor layout of the CMX version 0 card. In the Mentor system we will always display the CMX-0 card in our "standard format", i.e. you are looking at the component side of the card, its front panel is to the left and its back plane connectors are to the right. CMX-0 is a "9U by 400mm" card, i.e. 366.70 mm +0 -0.3 tall by 400mm +0 -0.3 wide. The CMX-0 uses the fancy IEEE 1101.11 (or whatever it is) front panel hardware. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Layer Strategy and Usage in the CMX Card: ----------------------------------------- Be carefull - does "layer" mean: 1:10 Signal Layers or Mentor Logical Layers or Physical Stack Up Layers ? All information about layers in the CMX project is in the file: cmx_ab_routing_layer_strategy.txt =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Routing Vias used on the CMX Card: ---------------------------------- The following vias are used to route the CMX card. The numeric field in the via name should indicate the via's pad diameter aka land diameter. via_0mm60: finished hole diameter 0.30 mm land pad 0.60 mm plane relief 0.87 mm --> ring width 0.150 mm --> plane isolation Air Gap 0.135 mm from the pad Tented via_0mm65: finished hole diameter 0.30 mm land pad 0.65 mm plane relief 1.00 mm --> ring width 0.175 mm --> plane isolation Air Gap 0.175 mm from the pad Tented via_1mm1: finished hole diameter 0.60 mm land pad 1.10 mm plane relief 1.60 mm --> ring width 0.25 mm --> plane isolation Air Gap 0.25 mm from the pad Tented via_gtx_blind: finished hole diameter 0.25 mm land pad 0.56 mm plane relief 1.00 mm --> ring width 0.155 mm --> plane isolation Air Gap 0.220 mm from the pad This via connects only layers: Signal_1 - Signal_2 - Signal_3 Tented via_proc_in_blind and via_std_blind Currently these 2 types of blind vias have exactly the same dimensions as the via_gtx_blind. A difference is that in the current "Tech" files that via_gtx_blind has ground plane relief in the middle type of ground plane where as via_proc_in_blind and via_std_blind have the ground plane fill in in the middle type of ground plane. cf. section below for note about special versions of blind vias to generate the needed "donuts" for the L6 ground plane a the bottom of the blind via and pad stacks. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Blind Pin Padstacks: -------------------- Both the Virtex BGA and the MiniPOD Transmitter geometries will need Blind Pin Padstacks for their pins that carry the high-speed differential signals. These Blind Pin Padstack will connect only Signal Layers 1, 2, and 3. The dimensions of these Blind Pin Padstack are setup the similar to those of the via_gtx_blind via. That is: MiniPOD Transmitter Blind Pin Padstack: finished hole diameter 0.25 mm land pad 0.56 mm plane relief 1.00 mm --> ring width 0.155 mm --> plane isolation Air Gap 0.220 mm from the pad This via connects only layers: Signal_1 - Signal_2 - Signal_3 Tented Note that the MiniPOD Transmitter Blink Pin Padstack may use the "large" 1.00mm plane relief because the pins in the MAG-Array connector are spaced 1.27mm center to center. Virtex 1759 BGA Blind Pin Padstack: finished hole diameter 0.25 mm land pad 0.56 mm plane relief 0.85 mm --> ring width 0.155 mm --> plane isolation Air Gap 0.145 mm from the pad This via connects only layers: Signal_1 - Signal_2 - Signal_3 Tented Note that the Virtex 1759 BGA Blind Pin Padstack has the same plane relief diameter as is used for the rest of the pin vias in this geometry. This is as large of a plane relief as we can get and still have good connectivity of the ground plane into the center of the FPGA. We want as much plane relief from the high speed signals that used the Blind Pin Padstack as we can get (while still having a good ground plane). cf. section below for note about special versions of blind vias to generate the needed "donuts" for the L6 ground plane a the bottom of the blind via and pad stacks. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= L6 Ground plane issues : ----------------------- Generating pads on the bottom layer of the sub-lamination for blind vias and pins: ------------------------------------------- Mentor (at least our version) can create pads on signal layer but does not seem able to create the flashes appropriate for a negative data ground plane. The technology file defines the span of layers for blind vias stacks. If the bottom layer of the blind stack is a signal layer, the fablink artwork generation process creates all pads as expected. If the bottom layer is a power layer (e.g. our ground plane), fablink only generates round flashes in the negative data artwork, i.e. no pad for the blind vias. One would need to add another signal layer for this ground layer and generate a ground fill for this ground plane. For a negative data ground plane with blind via pads, we need a power relief with a pad in the middle of that relief and this would appear as a "donut" in the negative gerber data. There is a simple gerber definition to generate such donuts, but Mentor does not seem to know how to generate them. Furthermore the Mentor artwork viewer is not even able to simulate data including such donuts. The PCB manufacturer recommends an L1-L6 sub-lamination for the blind pins and vias for the CMX circuit board which would include our signal_1 = L1, signal_2 = L3, signal_3 = L5 with ground planes at L2, L4, and L6. The PCB house thus needs a L6 ground plane with pads for all blind vias. Trying to generate these pads by adding a circle to the via and pin geometries on some unused layer and including that layer in a separate dedicated layer for L6 does not work. This method adds concentric flashes, but a small flash on top of a big flash cannot make a donut. More generally, any method that will only *add* a donut on top of a relief flash will fail as well. The circular relief flashes need to be *replaced* with a donut. To replace the blind via and pin relief flashes we need to have just those vias and pins appear separately from the other power relief flashes in the gerber artwork file so that we can simply edit the gerber tool used. We thus need to force Mentor to use a different aperture for the ground "power" relief of all blind vias and pins. It needs to be different from the relief used for all other pins and vias. We could choose to make the blind via relief slightly different on all layers, but we instead make special versions of the geometries involved that will only be used to generate just the artwork for the L6 ground plane. Blind pin geometries: A special version of all blind pin geometries was created with 0.86 mm instead of 0.85 mm power relief so that these flashes can be forced to use a different aperture and thus receive a separate gerber D-code that we can edit to become "donuts". These geometries were only used to create the GND plane for Layer 6. minipod_transmitter.with_1mm01_short_pin_power_relief ffg1759_rev__bf19__geometry.with_0mm86_short_pin_power_relief.txt Blind via geometries: A special version of all blind via geometries was created with 1.01 mm instead of 1.00 mm power relief so that these flashes can be forced to use a different aperture and thus receive a separate gerber D-code that we can edit to become "donuts". These geometries were only used to create the GND plane for Layer 6. via_std_blind.with_1mm01_short_via_power_relief via_proc_in_blind.with_1mm01_short_via_power_relief via_gtx_blind.with_1mm01_short_via_power_relief We hand edited the versioned file aperture_table to add flash apertures 214 and 215 for D-codes 314 and 315 for flashes of 1.01 and 0.86mm. We then can edit the artwork_23 file for L6 to replace the D-codes %ADD314C,1.010000*% %ADD315C,0.860000*% with %ADD314C,1.000000X0.560000*% %ADD315C,0.850000X0.560000*% (the second parameter specifies the hole in the middle of the flash) Differential blind via pairs: ----------------------------- There is an additional difficulty to generate the correct ground plane cutouts under the differential blind via pairs. On all other ground layers, these cutouts are generated in the negative data gerber files by adding "ovals" as short wide paths under the via pairs. These short paths are included in the CMX board geometry on layer "DAM_1". DAM_1 is then included in the default artwork definition for all ground planes that need those cutouts. The problem is that such simple wide paths would overwrite the donuts created as described above. The solution is to replace each of these short wide paths on DAM_1 with a set of 3 shorter narrower paths forming a sideways "H" on DAM_3 and to include DAM_3 instead of DAM_1 for the artwork used to generate just the L6 Ground plane. The "H" combined with the two donuts then creates the intended overall "oval" relief plus one pad at each end. Use textpad to extract columns of coordinates of all the "ovals" on DAM_1 found from cmx_0_pcb_ground_plane_cuts.txt and paste into excel. Use Excel to compute the end points of the "H"s, i.e. for each pair of X-Y coord that was making a 1.0mm long X 1.0mm wide $$path from DAM_1 we derive 3 pairs of X-Y coords for the 3 segments of the corresponding "H". There are four orientations to compute: vertical, horizontal, +45 degree and -45 degree. The parallel bars of each "H" form the two outside edges of the oval. The line thickness matches the width of the gap between the pad and the relief (here is it 1/2 of 1.00 mm relief minus 0.56 mm pad, or 0.22 mm). The perpendicular cross bar of the "H" is in the middle with a thickness twice the airgap (here 0.44 mm). These three simple lines partially overlap the donuts (not a problem) and also completely fill out the gap between the pair of donuts to form the overall cutout, as desired. We hand edited the versioned file aperture_table to add path apertures 216 and 217 for D-codes 316 and 317 for paths of 0.22 mm and 0.44 mm. In hindsight: the 0.44mm path for the crossbar could have been replaced with two overlapping 0.22 mm paths. Furthermore it may not have been necessaryto use a special new 0.22 mm width as there is a significant overlap between the "H" and the "donuts". It may well have been possible to create the "H" using only our already existing 0.20 mm path width. The 0.22mm and 0.44mm "H" may still be the most straightforward method. Additional ground cutouts to blind vias: --------------------------------------- We also need cutouts under the DC block capacitors between the Avago receivers and the Virtex 6 GTX differential inputs. Including a set of paths on DAM_1 in the cap0201 component geometry for the DC block capacitor was not successful as the artwork output for the ground planes did not include those contributions to DAM_1. Maybe a different layer would be more successful or the DAM_1 layer may need to be declared with additional properties. The method used was to pull the coordinates x,y and angle from the comps file for all DC block capacitors (C1001-C1072) and use textpad and excel to recreate the same 3+2 $$path that was in the geometry, but now both on DAM_1 and DAM_3 under each cap and insert them in the board geometry. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Trace Widths Used for Routing the CMX Card: ------------------------------------------- The following trace widths are used for "Normal" applications: -------------------------------------------------------------- Normal CMOS signal routing where space permits: 0.20 mm traces on 0.6 mm centers To break out by 45 degrees they stager by 0.3 mm on the 0.6 mm center to center run. use via_0mm65 vias spaced 1.2mm center to center Normal CMOS signal routing where things are tight: In the BGA escape we need to use 0.13mm traces for the optimum layout. Details: the BGA Vias are 0.61mm diameter and are spaced 1mm center to center. This gives 0.39mm for the escape trace and its clearance on both sides. This 0.39mm is used as a 0.13mm escape trace and a 0.13mm clearance on both sides. Using 0.16 mm wide traces on 0.5 mm centers works out well for buses that come out of the FPGA and for the vertical busses for the TTC decoder signals and the on card bus signals. LVDS transceiver DS91M040: Signals - 0.20 mm trace Power & Ground - 0.20 mm trace to one via_0mm65 centered 0.8mm from pad edge Bypass Caps - 0.60 mm trace via_0mm65 Translator 74AVCAH164245 Signals - 0.20 mm trace straight IN 0.7mm to via_0mm65 OUT 0.4mm bend to 0.05mm grid via_0mm65 0.9mm from pad edge Power & Ground - 0.25 mm trace to via_0mm65 centered 0.7mm from pad edge Bypass Caps - 0.60 mm trace Bypass Capacitor 0603 size connections 0.60 mm trace to via_0mm65 centered 0.5mm from pad edge Normal Bypass Capacitor 0805 size connections 0.75 mm trace to via_0mm65 centered 0.7mm from pad edge In the power supply section may use 1.0mm trace width for the 0805 ceramic capacitors. Power Bypass Capacitor 0805 size connections 1.0 mm trace to via_1mm1 centered 1.0mm from pad edge or centered 0.9mm from pad edge Tant D pads 2x 1.20 mm 1mm1 via CL on pad edges 1.1mm or 1.2mm from pad edge to via center Tant B pads 1.20 mm trace 1mm1 via CL on pad edges 0.9mm from pad edge to via center or two 0.75 mm traces to two via_0mm65 Al Electrolytic F pads 2x 1.20 mm 1mm1 via edge on pad edges Transient Suppressor pads 1.20 mm 1mm1 via in center Fuse Holder pads 2x 4x 1.20 mm 1mm1 via 0.20mm width differential pair on 0.5mm center to center with a unit cell pitch of 1.5mm from one pair to the next. Thus you can fit 8 of these differential pairs in 12mm. 0.25mm width differential pair on 0.6mm center to center. 0.35mm width for the "analog" traces in the DC/DC converters. Special "Key" Trace Widths: --------------------------- 60 Ohm single ended on the Top layer: 0.12 mm width 60 Ohm single ended on a Mid layer: 0.12 mm width 6.4 GHz Differential on the Top layer: 6.4 GHz Differentail on a Mid layer: LVDS signals on the Top layer: LVDS signals on a Mid layer: Differentail Clocks on the Top layer: Differential Clocks on a Mid layer: For all of these 50 Ohm differential traces: 0.14mm width 0.4mm spacing center/center 0.5mm spacing cent/cent is an alternative Notes: We want the open space between a differential pair to be about twice the width of one of the traces in the differential pair. I.E. the center to center spacing is 3 times the width of one of the traces (or a little bit more - not less). We can not use 0.13mm width as a "Key" trace width because we need this for the BGA escape routing. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Differential Trace Layout: -------------------------- All 100 Ohm differential traces on the CMX will be layed out using a "key" trace width to indicate that they are a 100 Ohm differential pair. This key layout pattern is: Trace Width: 0.14 mm Trace Spacing Center to Center: 0.40 mm Open Space between Traces: 0.26 mm This is fine for horizontal and vertical traces. What about differential trace routing at an angle ? CMX could use: Starting from the Horz or Vert parallel traces, Stager by 0.20 mm to start the trace segments at an angle: Slope: 1 Center to Center Distance: 0.4243 mm Open Space between Traces: 0.2843 mm Extra Length at the Bend: 0.3414 mm Starting from the Horz or Vert parallel traces, Stager by 0.10 mm to start the trace segments at an angle: Slope: 1 Center to Center Distance: 0.3536 mm Open Space between Traces: 0.2136 mm <-- Too Small Extra Length at the Bend: 0.3121 mm Slope: 0.5 Center to Center Distance: 0.4025 mm Open Space between Traces: 0.2625 mm Extra Length at the Bend: 0.1894 mm Slope: 0.3333 Center to Center Distance: 0.4111 mm Open Space between Traces: 0.2711 mm Extra Length at the Bend: 0.1316 mm Slope: 0.25 Center to Center Distance: 0.4123 mm Open Space between Traces: 0.2723 mm Extra Length at the Bend: 0.1000 mm The pair of traces in a differential pair need to be the same length. This is especially important on the 6.4 Gbps GTX traces where: - the bit length is about 156 psec - a trace 1 mm long takes about 6.6 psec (assume 1/2 c) - the skew in a GTX transmitter output pair is 2 psec typical 8 psec maximum. - the 20%-80% rise and fall time is 120 psec typical We assume that the differential signals are isochronous at the component pins then there is a skew in getting these signals started into the differential trace pair. For example: - Coming out of the BF GTX pins, after the via pair, on the Red layer, in the now parallel traces, from points directly across from each other, the longer trace back to the FPGA is about 0.638 mm longer than the shorter trace. - Coming out of the BF GTX pins, on the Green layer, in the now parallel traces, from points directly across from each other, the longer trace back to the FPGA is about 1.206 mm longer than the shorter trace. - In the typical escape from the MiniPOD, to where the traces are parallel, from points directly across from each other, the longer trace back to the MiniPOD is about 1.7mm to 2.2mm longer than the shorter trace. - In a bend with a stager of 0.20mm going to a 45 degree trace, from points in the parallel traces that are directly across from each other the outer trace is about 0.34mm longer than the inner trace. - In a bend with a stager of 0.10mm going to a trace with a slope of 0.25 or less, from points in the parallel traces that are directly across from each other the outer trace is about 0.19mm to 0.10mm longer than the inner trace. From reading lots of application notes, and from looking at many examples of commercial cards with high speed differential traces, it is clear that we need to take some care with matching trace lengths on both sides of a differential signal. We used the following guide lines for adjusting the high speed differential trace lengths on the CMX card. These guide lines are: - First adjust the trace lengths by modifying the circuit at the net list level, e.g. change which GTX Translator is connected to which MiniPOD channel or add a polarity swap to get a better length match within a differential pair. In general this step appears to get the trace lengths within about 1.6 mm of being equal. - Next adjust the topology of how the traces enter the MiniPOD BGA to get a better length match, e.g. change which side of the BGA the traces enter from, enter on the other side of the MiniPOD BGA pins, add a loop to the shorter trace within the BGA foot print. - As the last step add a serpentine section to the shorter trace. We are using the following rules to make the serpentines: Add the serpentine at the MiniPOD end of the trace. On a vertical or horizontal trace the serpentine is: A perpendicular step out of 0.2 mm for a length of 0.5 mm. Return to the normal trace path for 0.5 mm before stepping out again. Round the 4 corners of each step out with an arc of 4 segments and a radius of 0.10 mm. Each of these step outs will add 0.234 mm of trace length. On a 45 degree diagonal trace the serpentine is: A perpendicular step out of 0.2121 mm for a length of 0.5657 mm. 0.2121 mm is 3 grid dots diagonally with a grid of 0.05 mm. 0.5657 mm is 4 grid dots diagonally with a grid of 0.10 mm. Return to the normal trace path for 0.5657 mm before stepping out again. Round the 4 corners of each step out with an arc of 4 segments and a radius of 0.10 mm. Each of these step outs will add 0.250 mm of trace length. Add serpentine until the short trace comes within about 0.3 mm of the longer trace. Do not make the short trace longer than the originally longer trace. Stopping the serpentine about 0.3 mm short of a match allows for the possibility that the added electrical delay of the serpentine is greater than its added geometric length. Note that all of the GTX traces have their 45 degree corners rounded with arcs of 2 segments at a radius of either: 0.40 mm, 0.30 mm or 0.16 mm. The 0.16 mm radius is needed only for corners adjacent to short segments, i.e. segments 0.3 mm in straight length or 0.2828 mm diagonally. When 0.16 mm radius needs to be used the other side of the differential line may use a 0.30 mm radius if that gives the best looking differential layout. The 0.40 mm radius is used only in open areas with long straight traces. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Differential Via Layout: ------------------------ - We will use a standardized via layout pattern for all of the 100 Ohm Differential traces. - All of the CMX's 100 Ohm differential traces are routed as 0.14 mm trace width on 0.4 mm centers. This is a "key trace width" to identify the 100 Ohm differential traces to the bare pcb house. - For the 6.4 GHz 100 Ohm Differential traces we will use a special blind via (via_gtx_blind) that only goes through the first 5 physical layers of the pcb (Signal_1, Signal_2, Signal_3, and the top 2 ground planes). - For the 100 Ohm Differential traces that are spaced 0.4mm we should use Differential Vias that are spaced 1.0mm center to center. - The ground plane is removed in an oval that is a line 1.0 mm wide and runs between the centers of the two via. - Also see the section above about the L6 ground plane. - The Area Fills are removed in a rectangle that is 1mm by 2mm, i.e. this rectangle has the same outer dimensions as the removed oval of ground plane. - We may let the ground plane fill in on the very bottom ground plane layer of the CMX card as this is far enough away from the differential blind via pair that it does not upset their transmission line characteristics. - It is good to put a pair (or a quad) of ground rivet vias near the Differential Via pair. In one pattern there are two ground rivets colinear with the two via and spaced at total of 3.4 mm center to center. The intent of the ground rivets in the differential via layout is to provide a local symmetric return path for any common mode current that is flowing with the differential signal. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Details from Looking at Examples of 6 GHz Routing -------------------------------------------------- Page 293 of the Xilinx GTX Transceiver User's Guide shows some examples of GTX signal routing. These traces and pads appear to be: BGA Pin Pad Array Land Dia 0.48mm BGA Via Array Land Dia 0.54mm BGA Via Array C to C 1.0 Routing Via Land Dia 0.42mm Routing Via C to C 1.0 Trace Width 0.11mm or 0.12mm Trace C to C 0.45 Traces to 10 GHz optical transceiver on PCI Express card 6 GHz PCI Express traces and vias Xilinx Demo 623 Board (was in mils - converted to mm) BGA Via Array Land Dia 0.51mm BGA Via Array C to C 1.0 Routing Via Land Dia 0.46mm Routing Via C to C 1.27 Drill Sizes: The only drill that they use that goes through only layers 1 through 6 (i.e. their blind vias) is 0.20mm diameter. Their smallest drill that goes through all layers is 0.25mm which by the hole counts must be used for all of their normal small vias. Summary: Blind Via Land 0.46mm Drill 0.20mm Through Via Land 0.51mm Drill 0.25mm Both of these vias appear to use a 0.76mm plane relief --> air gaps of 0.15mm and 0.125mm Trace Width Surface 0.10mm to 0.11mm Trace C to C 0.25mm to 0.26mm Trace Width Inner 0.13mm Trace C to C 0.43mm =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= At 6 Gbps What Size Imperfections Make a Difference ? ----------------------------------------------------- We have 6 G bits per second data flow to the MiniPODs. So this is basically a waveform like a 3 GHz sin wave but we need to include the 3rd and 5th harmonics. So we need transmission lines with good flat characteristics up through 15 GHz. In open space 15 GHz is 20 mm wave length. The transmission lines on the card are about 1/2 the speed of light so on these lines a wavelength is about 10 mm. To be a good flat line we must keep any imperfections down to a physical size of less then 1/20th of a wavelength or so. Thus we care about bumps that are 0.5mm in size. So for work on CMX lets wake up when we see bumps on the scale of 1/2 of that, i.e. 0.2mm in size. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Blind vias for 6 Gbps: ---------------------- We do need some vias in the 6 Gbps 100 Ohm differential traces. All of these signals are on layers: Signal_1, Signal_2, and Signal_3. Can we use just one type of bind via that can connect to any of these 3 signals layres or do we need two types of blind vias: one to connect Signal_1 with Signals_2 and another to connect Signal_1 wtih Signals_3 ? The issue is using a blind via that physically passes through layers Signal_1,2,3 to connect signals between Signal_1 and Signal_2, i.e. in this case will the stub running to Signal_3 cause trouble at 6 Gbps ? How long physically is this stub likely to be ? - Let's be generous in this length calculation because we are interested in the lowest frequency at which this stub may cause trouble. - The card will be about 2.8mm thick (110 mils). So each layer is about 0.13mm thick. - To this lets add the thcikness of the copper conductor. 1 oz copper is about 0.036mm thick. 1/2 oz copper is about 0.018mm thick. - The stub will go through a dielectric layer then a ground plane then another dielectric layer then layer signal_3. So physically the stub will be about 0.30mm long. - We know that at a frequency where 0.30mm is 1/4 of a wavelength that this stub will case a short circuit. - If the important Fourier components of our 6 Gbps GTX signals approach this frequency then this stub will cause us trouble. - In the pcb signals on these 100 Ohm differential traces will travel at about 1/2 the speed of light. - At 1/2 the speed of light, 125 GHz has a wavelength of 1.2mm (i.e. a 1/4 wavelength of 0.30mm). - 125 Ghz is a factor of 8 or so above the frequencies that we care about for our 6 Gbps signals. Thus it's not clear whether or not this stub will cause a significant transmission line effect in our application. - We clearly care about frequencies up through 15 GHz. 15 GHz on our transmission lines (at 1/2 half the speed of light) has a wavelength of 10 mm. So this 0.30 mm long stub is about 3% of a wavelength long. - In any case we still must consider the lumped capacitance effects of this stub with will drive down the Zo of the differential via pair. - As a final consideration of the via stub, think about the situation where you do not use a blind via. In this case the stub is the full thinkness of the card minus 2 layers. This is a stub about 2.5mm long. This is a 1/4 wavelength stub for our 15 GHz 10mm wavelength signals. ---> We must use blind vias. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Design Rules used for Routing the CMX Card: ------------------------------------------- We will start on 10-Apr-2013 with Net Rules for the Default Net_Type: Pin Via Trc Fill Pin 0.5 Via 0.1 0.3 Trc 0.22 0.25 0.25 Fill 0.4 0.4 0.5 0.7 =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Drill Holes: ------------ See also the file fill_generation_notes.txt for more information about drill holes for component pins and plain drill holes. The CMX circuit board has a significant number of drill holes in the area where traces are routed and components mounted. Many of these drill holes are for size 4-40 machine screws. 4-40 screws are used to mount: stiffener bars, head sinks, and front panel MDR connectors. Because of the limited clearance height on the back side of the pcb we will use button head allen type screws in most/all of these 4-40 screw applications. 4-40 Button Head Allen SS Machine Screw: diameter of the threaded section is about 2.8 mm head diamter is about 5.3 mm thickness of the head is about 1.5 mm 4-40 Hex SS Machine Nuts: about 6.3 mm across flats 6.35 mm = 1/4" across flats about 7.0 mm point to point 7.33 mm = 6.35 / cos 30 deg. Number 4 Flat Washer Plated: diameter is about 7.2 mm thickness is about - We will use 3.0 mm drill holes in the CMX for these screws. - We will relieve the power and ground planes from these 4-40 screws with a circle of diameter 4.0 mm that is from the edge of the drill hole to the closest metal in the plane is 0.5 mm - No routing trace should get closer than 1.0mm to the edge of the drill hole (i.e. closer than 0.5mm to the edge of the plane relief). High speed or critical signals should perhaps stay back further from the drill holes. - When a flat washer is not used all components should stay back at least 4.5 mm from the center of the drill holes for the 4-40 screws, i.e. there is a keepout circle of radius 4.5 mm. - Because of the very limited clearance height we do not have room to use a flat washer under the head of most of these 4-40 button head screws. VME reccommended back side stub height is 1.0 mm. Back side distance to the separation plane 4.07 mm But actually less than this because we mill off the back side of the card to fit into the card guides. - We will use a standard component pin pad-stack geometry for these 4-40 screws in CMX called STD_4_40_SCREW_PIN. - The STD_4_40_SCREW_PIN pad-stack is defined in only one place. It is in the Heat_Sink_BF_Geom.txt file. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Area Fill Generation: --------------------- The details of the Area Fill generation are given in a separate file named, "fill_generation_notes.txt". - CMX has 55 Area Fill Shapes. - These shapes are used to make 67 Fills. - The desigh net rules and the fill tool size must be adjusted while making these 67 Fills. - There are about 139 Excluder Shapes that are all used on 3 different layers. These Excluders are kept in the file, "exclude_fills_basic_setup.txt" and must be added to the Traces file before the Area Fills are made. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Gerber Plot Generation: Rev. 17-Oct-2013 ----------------------- --> Recall that the Aperture Table and the Artwork Format are Mentor Design Object type files and thus you must explicitly save them before exiting FabLink. --> Recall that the Gerber Artwork files in the .../mfg/ directory are written at the instant that you click "creat artwork" - any old files of this type are overwritten at that instant. Assume that the Gerber Format has been setup and saved. Gerber Data is in mm 3.3 format. If necessary use: Right Click --> Artwork --> Change Artwork Format Image Scale: 1 Units: mm Mode: Absolute Plot Offsets: Manual with X=0.0 Y=0.0 G_Code: Allow Zero Suppression: None Interpolation: Linear with 8 Segments Output Format: 3 Significant and 3 decimal Data Record Length: 80 Header String: none Sub-Header String: none Trailer String: none Machine Stop Code: M02 XY-Modal: not checked Open Shutter Modal: not checked View Artwork Format: not checked Command Block End Character: * Verify that you are using the proper version of the Drill_Holes section of the geometry for the CMX-0 pcb that has the copper for the ... Aperature Table: NOTE: Only delete and remake the Aperture Table if you need to. ----- Once we have the Aperture Table setup the way that we want it for the CMX then do NOT delte and remake it. Right Click --> Artwork --> Change Aperature Table --> Delete All Apertures Right Click --> Artwork --> Change Aperature Table --> Fill Aperature Table Select the Apertures for ALL Aizes Select NO ReSize and NO ReScale Flash Complex Padstacks: not checked Replace the table Report the Aperture Table (from Report Pull Down Menu) Include the ArtWork Format: yes Save and Display the Report Save Report to .../Work/Text/ Replace the existing Report Currently there are about 188 apertures. May/Will need to Edit the Power Apertures: After the Aperture Table is filled it is necessary to edit the 14 Power Apertures (aka thermal reliefs) to get the desired layout. To edit a Power Aperture Right Click --> Artwork --> Change Aperture Table --> Change Power Aperture For each Power Aperture select the Aperture Position and then set the: Tie Width, Air Gap, and Rotation and then click OK. Direct editing of the versioned aperture_table.apertt_x file is also possible. Note that the outer diameter of each Power Aperture is driven by its "power plane relief" diameter in its Geometry. We must set the Air Gap to get the desired pad size and set the Tie Width to get the desired amount of Copper connection. This version of Mentor lets us control the Tie Rotation. Before editing the Power Apertures are the following: Raw Power Apertures from the "Aperture Fill" aperture_table.apertt_20 27-Aug-2013 9:57 Pos Diameter Dcode This Must Be --- -------- ----- ------------------------ 102 1.00 202 via_0mm65 103 1.60 203 via_1mm1 104 0.87 204 GTX gnd rivet vias only by MiniPODs 111 1.85 211 front panel 2x8 conn ground pins 112 2.80 212 DC/DC Conv Gnd pins & CF_Socket screws 113 1.19 213 Gnds under LVDS trans & Clk 10x Fanout 114 2.00 214 SFP ground pin center back 117 1.05 217 MiniPOD larger pins 118 2.50 218 MiniPOD mounting screws 120 0.95 220 grounds NB6L611 clock buffer 122 0.85 222 grounds under FPGA BGAs 123 3.50 223 TTCDec mounting screws 124 3.00 224 power connector center pin grounds 125 1.65 225 backplane connector ground pins The remaining screw up on 27-Aug-2013 is that aperture 112 is used for two not compatable purposes. On 17-Oct-2013 needed to add the Power Aperture for the 3.80 mm basic diameter wrap_3mm0: 3.00 mm pad gives a 1.00 mm ring width (with a 1.00 mm drill) and a 0.40 mm Air Gap. On 17-Oct-2013 also needed to add the 0.45 mm and 0.55 mm Circular Flash for the new Virtex SMD Pad Lands and their Solder Mask. This is Aperture 212 & 213. On 29-Oct-2013 also needed to add the 0.86 mm and 1.01 mm circular flashes for the relief of blind vias and pins to generate the ground plane for stackup L6. This is Aperture 214 & 215. On 30-Oct-2013 also needed to add a 0.22 mm and 0.44 mm trace for the "H" relief underneath GTX differential via pairs to generate the ground plane for stackup L6. This is Aperture 216 & 217. After editing the Power Apertures are the following: aperture_table.apertt_21 30-Oct-2013 Hand Edited Power Apertures Desired for CMX-0 ----------------------------------- New-Current Outer Geom --------------------- Relief Air Air Tie Pos Diameter Gap Gap Width Rotate Function --- -------- ----- ----- ----- ------ ---------- 102 1.00 0.175 0.14 0.40 45 via_0mm65 103 1.60 0.25 0.20 0.64 45 via_1mm1 104 0.87 0.135 0.10 0.35 45 GTX ground rivet vias 111 1.85 0.175 0.14 0.75 45 front panel 2x8 conn 112 2.80 0.25 0.20 1.15 45 DC/DC Conv Gnd pins 113 1.19 0.24 0.20 0.50 45 Gnd LVDS trans & Clk 10x 114 2.00 0.25 0.20 0.80 45 SFP Gnd pin centr back 117 1.05 0.20 0.16 0.45 45 MiniPOD larger pins 118 2.50 -0.50 0.05 1.00 45 MiniPOD mountng screws 0.25 relief to drill 120 0.95 0.175 0.14 0.40 45 Gnd NB6L611 clock buff 122 0.85 0.120 0.10 0.35 45 gnds under FPGA BGAs 123 3.50 -0.70 0.05 1.40 45 TTCDec mounting screws 0.25 relief to drill 124 3.00 0.50 0.40 1.20 45 pwr conn centr Gnd pin 125 1.65 0.275 0.22 0.75 45 bckplane conn Gnd pins 210, 2.90 0.16 0.14 1.15 45 CompactFlash Screw Gnd 211, 3.80 0.40 0.40 1.00 45 Wrap_3mm0 In all cases this gives the same or slightly larger Land diameter than in the associated via's Signal/Pad layers and it gives generous Tie Width. The default sizes that I made are: Air Gap equals 80% of the geometries air gap. Tie Width equals 40% of the relief diameter. Gerber Data Generation: Use the geoms_421_for_all_other version of the geometries which uses the nominal power relief thus the standard aperture for all blind pins and vias Use the "Gerber_Ground_Upper" Technology file and then: Right Click --> Artwork --> Creat Artwork Data Gerber Data is Gerber 274X format Stroke the Area Fill, Flash the Polygon ASCII Data, for the BOARD, ALL ArtWork Numbers NO Tear Drops, REMOVE Unused Pins, REMOVE Unused Via's NO Output UnPlated Holes NO ReSize, NO ReScale Both the GTX and the non-GTX Blind pins and vias are set "Long" so all blind pins and vias will get ground plane relief. Right Click --> Artwork --> Creat Artwork Data All settings are the same except create Gerber Data for just ArtWork Numbers 1 i.e. just the Top pcb layer, and use the option: Output ALL Pins, Output ALL Via's Now use the "Gerber_Ground_Middle" Technology file and then: Right Click --> Artwork --> Creat Artwork Data All settings are set to how they were initially but now only the GTX Blind Vias and Pins are "long". Create just ArtWork Number 14 i.e. just the "Middle" type of Ground Plane that has relief for only the GTX type of Blind pins and vias. Now use the "Gerber_Ground_Lowest" Technology file and then: Right Click --> Artwork --> Creat Artwork Data All settings are set to how they were initially but now none of the Blind Vias and Pins are "long". The ground plane will fill in around all blind pins and vias. Create just ArtWork Number 15 i.e. just the lowest layer type of ground plane that does not have relief for any Blind Pins & Vias. Right Click --> Artwork --> Creat Artwork Data All settings are the same except create Gerber Data for just ArtWork Number 12 i.e. just the Bottom pcb layer, and use the option: Output ALL Pins, Output ALL Via's Switch to the geoms_420_for_artwork_23 version of the geometries which uses a different power relief thus a different aperture for all blind pins and vias Now return to the "Gerber_Ground_Upper" Technology file and then: Right Click --> Artwork --> Creat Artwork Data All settings are set to how they were initially but now only the GTX Blind Vias and Pins are "long". Create just ArtWork Number 23 i.e. just the "Layer 6" type of Ground Plane that has relief for all Blind pins and vias *AND* uses a separate D-code for all flashes blind pin and vias *AND* uses a modified style of "H" relief under the gtx differential vias. Edit artwork_23 to replace the D-code definitions for 314&315 %ADD314C,1.010000*% %ADD315C,0.860000*% with %ADD314C,1.000000X0.560000*% %ADD315C,0.850000X0.560000*% (the second parameter specifies the hole in the middle of the flash) and Save as artwork_23_edited Recall what is in each of thr Gerber artwork file: Gerber File 1 SIGNAL_1 Layer 1 in the PCB Stackup Top Gerber File 2 SIGNAL_2 Layer 3 in the PCB Stackup Gerber File 3 SIGNAL_3 Layer 5 in the PCB Stackup Gerber File 4 SIGNAL_4 Layer 7 in the PCB Stackup Gerber File 5 SIGNAL_5 Layer 9 in the PCB Stackup Gerber File 6 SIGNAL_11 Layer 11 in the PCB Stackup Bulk_2V5, GTX_AVTT,... Gerber File 7 SIGNAL_12 Layer 12 in the PCB Stackup Bulk_3V3, GTX_AVCC,... Gerber File 8 SIGNAL_8 Layer 14 in the PCB Stackup Gerber File 9 SIGNAL_6 Layer 16 in the PCB Stackup Gerber File 10 SIGNAL_7 Layer 18 in the PCB Stackup Gerber File 11 SIGNAL_9 Layer 20 in the PCB Stackup Gerber File 12 SIGNAL_10 Layer 22 in the PCB Stackup Bottom Gerber File 13 GROUND Plane Upper Relieve GTX and non-GTX blind pins and vias Layers: 2,4,8 in the PCB Stackup Gerber File 14 GROUND Plane Middle Relieve only GTX blind pins and vias Layers: 10,13,15,17,19 in PCB Stackup Gerber File 15 GROUND Plane Lowest Relieve none of the blind pins and vias Layer 21 in the PCB Stackup Gerber File 16 Board Dimensioned Fabrication Drawing BOARD_OUTLINE, SIGNAL_1, PAD_1, DRAWING_1, SILKSCREEN_1 Gerber Files 17 & 18 Silk Screens Top then Bottom Gerber Files 19 & 20 Solder Masks Top then Bottom Gerber Files 21 & 22 Solder Paste Stencils Top then Bottom (aka Solder Paste Masks) Gerber File 23 GROUND Plane just for Layer 6 Relieve GTX and non-GTX blind pins and vias Uses an "H" plane relief under the GTX deifferential via pairs Layers: 6 in PCB Stackup Release File Name Mentor File Name Content ----------------- ----------------- ------------------------- cmx_artwork_1 artwork_1 Layer 1 Trace Top Copper cmx_artwork_2 artwork_2 Layer 3 Trace cmx_artwork_3 artwork_3 Layer 5 Trace cmx_artwork_4 artwork_4 Layer 7 Trace cmx_artwork_5 artwork_5 Layer 9 Trace cmx_artwork_6 artwork_6 Layer 11 Power Fill cmx_artwork_7 artwork_7 Layer 12 Power Fill cmx_artwork_8 artwork_8 Layer 14 Power Fill cmx_artwork_9 artwork_9 Layer 16 Trace cmx_artwork_10 artwork_10 Layer 18 Trace cmx_artwork_11 artwork_11 Layer 20 Trace cmx_artwork_12 artwork_12 Layer 22 Trace Bottom Copper cmx_artwork_13 artwork_13 Layers 2,4,8 Gnd Plane cmx_artwork_14 (*) artwork_23_edited Layer 6 Gnd Plane cmx_artwork_15 artwork_14 Layers 10,13,15,17,19 Gnd Pln cmx_artwork_16 artwork_15 Layer 21 Gnd Plane cmx_artwork_17 artwork_16 Overall Assembly Drawing cmx_artwork_18 artwork_17 Silkscreen Top cmx_artwork_19 artwork_18 Silkscreen Bottom cmx_artwork_20 artwork_19 Solder Mask Top cmx_artwork_21 artwork_20 Solder Mask Bottom cmx_artwork_22 artwork_21 Solder Paste Stencil Top cmx_artwork_23 artwork_22 Solder Paste Stencil Bottom (*) note where we have inserted artwork_23 into a more natural location and shifted the numbering below that point Gerber Data Viewing: Right Click --> Artwork --> Simulate Artwork Data Note that currently the default FabLink grid is 0.005 mm and thus its hard to measure anything. This is clearly left over from an English project and needs to be changed. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Hand Edit the Final Gerbers: ---------------------------- Had to hand edit the GND plane for layer 6 to force pads on all blind pin and vias as the sub-lamination will be L1-L6. Edit artwork_23 to replace the D-code definitions for 314&315 %ADD314C,1.010000*% %ADD315C,0.860000*% with %ADD314C,1.000000X0.560000*% %ADD315C,0.850000X0.560000*% (the second parameter specifies the hole in the middle of the flash) and Save as artwork_23_edited =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Drill File Generation: Rev. 26-Aug-2013 ---------------------- --> Recall that the Drill Table and the Drill Format are Mentor Design Object type files and thus you must explicitly save them before exiting FabLink. --> Recall that the Excellon Drill files in the .../mfg/ directory are written at the instant that you click "creat drill file" - any old files of this type are overwritten at that instant. Assume that the Drill Format has been setup and saved. Drill Data is in mm 3.3 format. Drill Table: NOTE: Only delete and remake the Drill Table if you need to. ----- Once we have the Drill Table setup the way that we want it for the CMX then do NOT delte and remake it. Use the "Drill Generation" Technology file and then: Right Click --> Drill --> Change Drill Table --> Delete All Drills Right Click --> Drill --> Change Drill Table --> Fill Drill Table Select Replace the Drill Table Report the Drill Table (from Report Pull Down Menu) Currently there are about 22 drills. Right Click --> Drill --> Creat Drill Data This is now a lot more complicated menu because we have some drills that go only through the top 5 or 6 layers for the blind vias. It now also appears that this must be done in 2 steps, i.e. separate steps for "Plated Holes" and for "Unplated Thru-Holes" Note that from Mentor's point of view the mechanical mounting holes for the front panel and for the board stiffeners are Unplated. Generate the Plated Holes: Excellon, ASCII, NO Mirror, Board, Drill Hole Types: Plated_Holes, By Pin/Via Rules Physical_1 to Physical_3 YES Physical_1 to Physical_13 YES i.e. click Generate All Click "OK" at the bottom In the .../mfg/ directory this should make the files: drill_1_3 and drill_1_13 Generate the UnPlated Holes: Excellon, ASCII, NO Mirror, Board, Drill Hole Types: UnPlated Thru-Holes Click "OK" at the bottom In the .../mfg/ directory this should make the file: drill_unplt Report the Drill Table (from Report Pull Down Menu) Include the Drill Format Save and Display the Report Save Report to Design with .../Work/Text/ filename Replace the existing Report Look at the Simulation of the Drill Data and find: based on 16-Oct-2013 Drill_1_13 Drill Drill Position Size Count Plated Function ---------- ------ ----- ------ -------------------- 2 0.3 7137 yes small vias bga pins 3 0.6 1761 yes bigger vias backplane conn 4 0.7 136 yes mdr 68 pin front panel conn 5 0.9 16 yes 2x8 front panel connector 6 1.0 32 yes AWG22 WRAP vias & SFP Cage pin 8 1.1 36 yes SFP Cage pins 10 1.2 40 yes SFP Cage pins 11 1.3 95 yes DC/DC Converter pins 14 2.0 10 yes MiniPOD mounting screw pins 16 2.3 2 yes CF_Socket mountng screw pins 17 2.7 4 yes m2.5 mounting screw pins 18 3.0 38 yes 4-40 mounting screw pins Drill_1_3 Drill Drill Position Size Count Plated Function ---------- ------ ----- ------ -------------------- 1 0.25 967 yes blind vias Drill_Unplated Drill Drill Position Size Count Plated Function ---------- ------ ----- ------ -------------------- 7 1.0 10 no CF_Socket Header_2x20 TTCDec 9 1.1 10 no LED alignment 12 1.55 17 no SFP MiniPOD CANBus Proc Conn 13 1.75 2 no CF_Socket 15 2.0 3 no Power Conn alignment 19 3.18 2 no Backplane Pin Receptacle Viewing Drill Data: Right Click --> Drill --> Simulate Drill Data Note that currently the default FabLink grid is 0.005 mm and thus its hard to measure anything. This is clearly left over from an English project and needs to be changed. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= The actual PCB stackup that is used to manufacture the bare CMX PCBs is given in: http://www.pa.msu.edu/hep/atlas/l1calo/cmx/hardware/manufacturing/ for_production/cmx_stackup_fr4_14jan2014.pdf =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=