CMX LVDS Connections ------------------------- Original Rev. 13-Dec-2012 Current Rev. 28-Apr-2014 This file describes the LVDS connections to and from the CMX circuit board. - The backplane of the CMX card contains 3 "LVDS Cable Connections" of 27 bits each. All of these signals are routed to the Base Function FPGA. The backplane LVDS Cable connections on the CMX card are shown in the following circuit diagram on the web: 10_lvds_backplane_cables.pdf - The front panel of the CMX card contains 2 "CTP LVDS Cable Connections" of 33 bits each. All of these signals are routed to both the Base Function FPGA and to the Topological Processor FPGA. The front panel CTP LVDS connections to the CMX card are shown in the following circuit diagram on the web: 09_lvds_ctp_output.pdf Note that in some cases the connector pinout signal numbering scheme that is used in these LVDS connections is not continuous and skips around a bit. The CMX card implements both the backplane and the front panel LVDS connections in the same way. Specifically: - Each LVDS signal is received or transmitted by one channel of a quad National DS91M040 LVDS Transceiver. This is a high speed "M" type LVDS transceiver that provides double the normal drive current (for cables that are terminated at both ends) and has a receiver with wide common mode input range for use with cables. - The CMX circuit board provides a 100 Ohm differential termination resistor on each channel. In this way the LVDS circuits can be used as either transmitters or as receivers without making any changes to the card. - The DS91M040 LVDS transceivers have 3.3V CMOS single ended data and control signals. These 3.3V signals can not be used directly with the Virtex-6 BF and TP FPGAs. - Between the Virtex-6 FPGAs and the 3.3V CMOS data pins on the DS91M040 LVDS transceivers there are bi-directional 2.5V <-> 3.3V level translators. These parts are TI 74AVCAH164245. These translators include hold circuits to avoid the problem of floating CMOS inputs. - These 74AVCAH164245 translators are also used to provide the multiplexing function that allows either the Base Function FPGA or the Topological Processor FPGA to be connected to the front panel CTP LVDS signals. Note that this multiplexing of the front panel CTP LVDS signals is done on a per connector basis. Thus for example the BF FPGA can be sending or receiving LVDS signals on the upper front panel CTP LVDS connector while the TP FPGA is using the lower front panel CTP LVDS connector. Management of the National DS91M040 LVDS transceivers: - Management of the DRIVER_ENB and RECEIVER_ENB_B control signals to the LVDS transceivers comes from the BSPT FPGA. In turn the BSPT FPGA listens to signals from the BF and TP FPGAs to learn how they want the various LVDS transceivers configured, i.e. as inputs or as outputs. Once everything is running the BF and TP FPGAs have control over the direction of all of the LVDS transceivers with logic in the BSPT enforcing rules to prevent conflicts, e.g. aiming the transceiver and translator in different directions. - The National DS91M040 LVDS transceivers include control pins for their Failsafe and Master Enable functions. We do not anticipated that we will frequently need to change these control signals and thus their state is set in groups by jumpers which are described in detail in the file on the web: cmx_ab_board_jumpers.txt Management of the TI 74AVCAH164245 level translators: Management of the DIRECTION and OUTPUT_ENABLE_B control signals to the level translators comes from the BSPT FPGA and includes Hardwired Oversight Logic to prevent enabling the output of these translators before the BSPT FPGA is configured. In turn the BSPT listens to signals from the BF and TP FPGAs to learn how they want the level translators configured. Thus once everything is running the BF and TP FPGAs have control over these devices with logic in the BSPT enforcing rules to prevent conflicts, e.g. enabling two drivers on the same line at the same time. BSPT FPGA Firmware Management and Hardwired Oversight Logic Management of the LVDS Transceivers and Translators: - Management of the Backplane LVDS Cable Transceivers and Translators is shown in the following circuit diagram: 21_backplane_cable_management.pdf The Hardwired Oversight component of this management is shown in the upper left-hand corner of this drawing. The Hardwired Oversight Logic makes the ALLOW_BUSSED_IO signal which must be asserted Hi to enable the output buffers on any of the level translators in the Backplane LVDS Cable circuits. With all of the level translator outputs disabled there can not be any logic level conflicts at either the BF FPGA pins or at the LVDS transceiver pins of the Backplane LVDS Cable circuits. The BSPT FPGA Firmware component of this management is shown on the upper right-hand corner of the drawing noted above. This BSPT firmware generates the 9 control signals: CABLE_x_TRNCVR_DIR, CABLE_x_TRNSLT_DIR, and BSPT_CABLE_x_TRNSLT_OE_B where x is 1, 2, or 3 to manage the direction of the 3 Backplane LVDS Cables. The BSPT FPGA Firmware component of the management of the Backplane LVDS Cable Transceivers and Translators listens to the 3 BF_REQ_CABLE_x_INPUT signals that come from the Base Function FPGA to learn if the BF wants a given Backplane LVDS Cable to be an input or an output. This BSPT firmware then sets the control signals listed above to put the translator and LVDS transceiver circuits in the desired direction. Note that this needs to be coordinated with putting the BF FPGA pins that receive or send the Backplane LVDS Cable signals in the matching direction. - Management of the Front Panel CTP LVDS Transceivers and Translators is shown in the following circuit diagrams: 22_ctp_connector_management.pdf 23_ctp_connector_bstp_logic.pdf The Hardwired Oversight component of this management is shown in the top center of drawing 22. The Hardwired Oversight Logic makes the ALLOW_BUSSED_IO signal which must be asserted Hi to enable the output buffers on any of the level translators in the CTP LVDS circuits. With all of the level translator outputs disabled there can not be any logic level conflicts at either the BF or TP FPGA pins or at the LVDS transceiver pins of the CTP LVDS circuits. The BSPT FPGA Firmware component of this management is shown in drawing 23. This management firmware for the CTP Transceivers and Translators must separately manage the upper and lower CTP connectors and prevent conflicts between how the BF and TP FPGAs want to use these bi-directional LVDS circuits. This management firmware listens to the following signals: ALLOW_BUSSED_IO, BF_CONFIG_DONE, BF_REQ_CTP_x_INPUT, TP_FPGA_INSTALLED_B, TP_CONFIG_DONE, TP_REQ_CTP_x_INPUT, where x = 1 or 2 for the upper or lower CTP connectors. This firmware generates the 10 control signals to manage the transceivers and translators for the two CTP LVDS connectors. Note that this needs to be coordinated with putting the BF and TP FPGA pins that receive or send the CTP LVDS signals in the matching direction. - Overall Hardwired Oversight Logic: An overall drawing of the Hardwired Oversight Logic is given in circuit diagram: 24_hardwired_oversight_logic.pdf The main purpose of the Hardwired Oversight Logic is to prevent enable type signals from turning on various buffers, translators, and drivers before the BSPT FPGA that manages them is configured and running normally. The purpose of this is to prevent bus conflicts and to prevent problems like the CMX from asserting the VME_DTACK_B line before the BSPT FPGA is configured. The BSPT FPGA manages VME_DTACK_B once it is running. The Hardwired Oversight Logic consists of generating the ALLOW_BUSSED_IO signal and then using that signal to force the 12 control signal that pass through the Hardwired Oversight Logic to a benign state whenever ALLOW_BUSSED_IO is not asserted. The top of drawing 24 shows the signals that are used to generate the ALLOW_BUSSED_IO signal. The Hardwired Oversight Logic qualifies the following 12 enable type control signals with the ALLOW_BUSSED_IO signal: BSPT_CABLE_1_TRNSLT_OE_B Protect against Backplane BSPT_CABLE_2_TRNSLT_OE_B LVDS Cable conflicts BSPT_CABLE_3_TRNSLT_OE_B BSPT_CTP_1_BF_TRNSLT_OE_B Protect against Front BSPT_CTP_2_BF_TRNSLT_OE_B Panel CTP LVDS Connector BSPT_CTP_1_TP_TRNSLT_OE_B conflicts BSPT_CTP_2_TP_TRNSLT_OE_B BSPT_SEND_VME_DTACK_B Protect against BSPT_VME_BUS_TRNCVR_OE_B hanging the BSPT_OCB_ADRS_AND_CTRL_TRNSLT_OE_B crate's VME Bus BSPT_TTC_TRNSLT_OE_B Protect against TCCDec BSPT_TTC_RESET_TRNSLT_OE_B translator output conflicts