CMX Routing Layer Strategy ------------------------------- Current Rev. 25-April-2014 This file describes the pcb layer strategy that is used on the circuit board for the CMX. ------------------------------------------------------------ Notes added on 10-Jan-2014 Some details of this file have not been kept up to date and this whole topic has grown rather complicated. - I'm not going to touch anything in this file below this entry. Warning some stuff below here may have changed. - Recall different people mean different things by "layer" e.g. Mentor Logical Layer, PCB Physical Stackup Layer, Artwork File Number, Signal Routing Layers Only Numbering, - Recall that there were three major "layer" changes near the end of the design work on CMX: 1. We moved Mentor Signal Layer 8 which is all Area Fills to be Physically in the Stackup just under the Ground Plane that is immediately under the other Area Fill layers for power distribution. This was about 23-Aug-2013. 2. The pcb house changed their mind and wanted the blind vias to go 1-6 instead of the originally planned 1-5. This required pads for these vias on stackup layer 6 which is a ground plane. This required a special 4th type of ground plane. Adding this 4th new special ground plane was done at the end of the Default Artwork Order "geometry". To keep a rational order/numbering of the ArtWork files, they were renumbered, after they were generated. Specifically: The new 4th Ground Plane was re-numbered ArtWork_14 The existing ArtWork files 14:22 had their numbers incremented to become 15:23. The ArtWork files were only renumbers in the /Release_4_Final/ directory and in /for_production/ on the web. The ArtWork files were not renumbered in the /pcb/mfg/ directory where they were generated. This work was done about 25-Oct-2013 to 4-Nov-2013. 3. The pcb house had trouble balancing the 1-6 sub-stack with the rest of the card when trying to make controlled impedance traces on stackup layer 7. Instead we will have these controlled impedance traces on stackup layer 18. This involves just: Use the file cmx_artwork_4 for stackup Layer 18 Use the file cmx_artwork_10 for stackup Layer 7 This was done about 26-Nov-2013 - The description of the CMX stackup and the ArtWork files shown for the various Physical Stackup Layers in the cmx_pcb_description.txt file in /for_manufacturing/ on the web and in /Release_4_final/ on moto are correct. - The actual PCB stackup that is used to manufacture the bare CMX PCBs is given in: http://www.pa.msu.edu/hep/atlas/l1calo/cmx/hardware/manufacturing/ for_production/cmx_stackup_fr4_14jan2014.pdf ------------------------------------------------------------ Modification on 23-Aug-2013 - In the actual pcb stackup, the Mentor design layer Signal_8 i.e. an all Area Fill layer, has been moved so that it is just below the center power distribution layers for Bulk_2v5 and Bulk_3V3. Below Signal_8, Signals 6, 7, 9, and 10 will follow in order. New PCB Stackup PCB Stackup Layer Mentor Logical Design Layer ------- -------------------------------------------- 1 Signal_1 2 Ground Plane - Upper Type 3 Signal_2 4 Ground Plane - Upper Type 5 Signal_3 6 Ground Plane - Specific L6 Type 7 Signal_4 8 Ground Plane - Upper Type 9 Signal_5 10 Ground Plane - Middle Type 11 Signal_11: Bulk_2V5, GTX_AVTT, and other Fills 12 Signal_12: Bulk_3V3, GTX_AVCC, BF_Core, and other Fills 13 Ground Plane - Middle Type 14 Signal_8: BF VREF_P, TP_CORE, and other Fills 15 Ground Plane - Middle Type 16 Signal_6 17 Ground Plane - Middle Type 18 Signal_7 19 Ground Plane - Middle Type 20 Signal_9 21 Ground Plane - Lowest Type 22 Signal_10 - In all Area Fills there is relief around all GTX type blind vias and component pins. - In all Area Fills these is no relief for any non-GTX type blind vias or pins. - Upper and L6 type ground planes provide relief around all types of blind vias and component pins. - Middle type ground planes provide relief around only GTX type blind vias and pins. There is no relief around non-GTX type blind vias and pins. - Lowest type ground planes do not provide relief around any type of blind vias or pins. ------------------------------------------------------------ CMX Layer Strategy: ------------------- The word Layer means various things: - Physical layers in the actual pcb - Mentor design Logical layers - Thinking about just the Signal Trace layers - Recall that a Physical Layer may be used for example as a signal trace layer in one part of the CMX card and as a power plane in another area of the card. The design of the 400 backplane inputs and the backplane LVDS signals thinks in terms of "Signal Layers" (not in terms of Physical layers. - There are 10 signal layers used in the CMX design. - Signal layer number 1 is the top surface of the card. Signal layer number 10 is the bottom surface of the card. - Some of the 10 signal layers can have 65 Ohm traces and some can not reach above 50 Ohm Zo. - In our technical slang the 65 Ohm layers are called the "privileged layers". Use of the 10 Signal Layers in the 400 Backplane Processor Input to Base Function FPGA connections. Full Run --> Continuous traces on this layer the whole way from the backplane connector to the BF FPGA pin. Main Run --> Continuous traces on this layer from the backplane connector to the via array near the BF FPGA. Last Inch --> Continuous traces on this layer from the via array near the BF FPGA to a BF FPGA pin. Signal Use in the 400 Backplane Trace Layer Inputs Connecting to BF-FPGA Zo ------ ------------------------------- ----- 1 Last Inch only CMX Top Physical Layer 2 Full Run, Main Run or Last Inch 65 3 Full Run, Main Run or Last Inch 65 4 Full Run, Main Run or Last Inch 65 5 Full Run, Main Run or Last Inch 65 6 Last Inch only 50 7 Last Inch only 50 8 24 V_Ref, 8 DCI, 0-2 Last Inch 50 9 Full Run for 14 of the 16 Clks 65 & Full Run or Last Inch for some normal signals 10 none CMX Bottom Physical Layer Use of the 10 Signal Layers in the Backplane LVDS Cable IO connections to the Base Function. Conn-TX --> Traces on this layer from the backplane connector to the LVDS<-->3V3CMOS transceiver Transl-FPGA --> Traces on this layer from the 3V3CMOS<--<2V5CMOS translator to the BF FPGA. Signal Use in the Backplane LVDS Trace Layer Cable IO Connection to the BF-FPGA Zo ------ ----------------------------------- ----- 1 i.e. CMX Top Physical Layer Transceiver <--> Translator and the last ~2mm to pads for these parts and the ~1/2mm to pads under the BF FPGA 2 Conn-TX and Transl-FPGA 50 3 Conn-TX and Transl-FPGA 50 4 Conn-TX and Transl-FPGA 50 5 Conn-TX and Transl-FPGA 50 6 Conn-TX for the 3 "extra pairs" 50 7 - none - 8 - none - 9 Conn-TX and Transl-FPGA 50 10 i.e. CMX Bottom Physical Layer - none - Use of Signal Layers #6, #7, #8 in the area between the Base Function FPGA and the Backplane Connectors: - Signal Layers #6, #7 will carry the vertical mat of traces that involve many non principal signal flow signals (OCB, TTCdec, debug connector signals, BF to TP S-link back channel, one fabric clock) and the horizontal mat of traces in the nearby region south of the BF FPGA that involve the signals to the front panel LVDS CTP connectors. - Signal Layers #8 is so far still unallocated except near the BF FPGA for a VREF plane area fill and for the DCI control resistors to the IO banks used with the 400 backplane inputs. Physical Layer Rules: - Follow exactly the GTX layer rules. - All power planes must have an immediately adjacent ground plane on at least one side. Common Sense: - Ground planes should be contiguous Physical Layers. Physical Layer Design: ---------------------- There are 22 Physical Layers in the CMX circuit board. Stackup High Speed Ser IO PB 400 & LVDS & Layer FPGA and Optic TX Rest of BF FPGA TX and Translate -------- ----------------- ---------------- ---------------- 1 50 Ohm Microstrip Signal Layer #1 Signal Layer #1 2 Ground Plane Ground Plane Ground Plane 3 50 Ohm Stripline Signal Layer #2 Signal Layer #2 4 Ground Plane Ground Plane Ground Plane 5 50 Ohm Stripline Signal Layer #3 Signal Layer #3 6 Ground Plane Ground Plane Ground Plane 7 Diff FPGA Clocks Signal Layer #4 Signal Layer #4 8 Ground Plane Ground Plane Ground Plane 9 Diff FPGA Clocks Signal Layer #5 Signal Layer #5 10 Ground Plane Ground Plane Ground Plane 11 AVTT Fill Bulk_2V5 Fill Bulk_2V5 Fill 12 AVCC Fill BF_Core Fill Bulk_3V3 Fill 13 Ground Plane Ground Plane Ground Plane 14 Signal Layer #6 Signal Layer #6 15 Ground Plane Ground Plane Ground Plane 16 Signal Layer #7 Signal Layer #7 17 Ground Plane Ground Plane Ground Plane 18 Fill Sig Layer #8 Signal Layer #8 19 Ground Plane Ground Plane Ground Plane 20 Signal Layer #9 Signal Layer #9 21 Ground Plane Ground Plane Ground Plane 22 Signal Layer #10 Signal Layer #10 - The non high speed serial IO area under the TP FPGA is like the non high speed serial IO area under the BF FPGA except that it uses Physical Layer 12 for the TP_Core fill. - The area under the Board Support FPGA needs: Bulk_3V3, Bulk_2V5, and BSPT_Core 1.2V power. - The area under the 12 channel high speed optical parts needs Filtered 2.5V and 3.3V power. Each supply is filtered by a capacitor to Gnd, a series inductor, and a final capacitor to Gnd at the component power pin. - The area under the low speed SFP optical parts needs to have filtered 3.3V supplies, a separate filtered 3.3V supply for that SFP packages transmitter and for its receiver. Each supply is filtered by a capacitor to Gnd, a series inductor, and a final capacitor to Gnd at the component power pin. - These are all 1/2 oz copper layers except for the main power planes on layers 11 and 12 which are 1 oz. 1/2 oz copper is about 1 mOhm per square. The tolerance on the Virtex Core supply is 50 mV. The tolerance on the 12 channel optical part is 30 mV. The final design may require power fills on multiple layers. From the Mentor System: ----------------------- Setup on 12-Apr-2013 CMX PCB Philippe's Physical Mentor Physical & Signal CMX Signal Stack Up -------------------------------- ------------ ---------- PHYSICAL_1 SIGNAL_1 PAD_1 <-- CMX Signal 1 - Physical 1 PHYSICAL_2 SIGNAL_2 <-- CMX Signal 2 - Physical 3 PHYSICAL_3 SIGNAL_3 <-- CMX Signal 3 - Physical 5 PHYSICAL_4 SIGNAL_4 <-- CMX Signal 4 - Physical 7 PHYSICAL_5 SIGNAL_5 <-- CMX Signal 5 - Physical 9 PHYSICAL_6 SIGNAL_6 <-- CMX Signal 6 - Physical 14 PHYSICAL_7 SIGNAL_7 <-- CMX Signal 7 - Physical 16 PHYSICAL_8 SIGNAL_8 <-- CMX Signal 8 - Physical 18 PHYSICAL_9 SIGNAL_9 <-- CMX Signal 9 - Physical 20 PHYSICAL_10 POWER_1 <-- Ground on PCB Physical: 2, 4, 6, 8, 10 13, 15, 17, 19, 21 PHYSICAL_11 SIGNAL_11 <-- Area Fill on PCB Physical: 11 PHYSICAL_12 SIGNAL_12 <-- Area Fill on PCB Physical: 12 PHYSICAL_13 SIGNAL_10 PAD_2 <-- Phlp Signal 10 - PCB Physical 22 Notes During Routing About What Is On Which Layer: -------------------------------------------------- - In the Backplane Cable LVDS section we need two layers for some general signal traces a North-South layer and a East-West layer. For now I will use: signal layer 6 for North-South signal layer 7 for East-West - Under the Base Function FPGA there are a couple of choices about how to best use the 3 layers that are assigned for Area Fills. Under the Base Function FPGA these 3 layers must contain the area fills for the following supplies: BULK_2V5, BF_CORE, BF_GTX_AVCC, BF_GTX_AVTT, and VREF_P Recall that over most of the CMX pcb that BULK_2V5 is on layer 11 and that BULK_3v3 is on Layer 12. We do not need BULK_3V3 under the Base Function FPGA. We plan it use its layer 12 for the BF_CORE supply. 11 West of 219mm must be AVTT - East of 223mm must be Bulk_2V5 12 West of 221mm must be AVCC - East of 225mm must be BF_CORE 8 signal routing traces - East of 226mm must be VREF_P BF_CORE must go on the pcb physical layer that is normally used for BULK_3V3 in most places on the card. If 3 pcb physical layers are going to be used then a rational setup is: 11 - - - - - - - - - - - - Bulk_2V5 - - - - - - - - - - - - - 12 West of 219mm must be AVTT - East of 225mm must be BF_CORE 8 West of 221mm must be AVCC - East of 226mm must be VREF_P