CMX TTCDec Signal Connections -------------------------------- Current Rev. 27-Apr-2014 This file describes the connections to the TTCDec mezzanine card on the CMX circuit board. The TTCDec mezzanine card is located in the lower right-hand corner of the card where it is close to its input "clock" and were its outputs can run directly up on the right hand side of the 3 FPGAs that use the TTCDec output signals. The TTCDec "input clock" enters the CMX card via backplane pins and is immediately received by the differential buffer chip U155. The input to the U155 buffer is AC coupled with 10 nFd capacitors to help reduce out of band noise. This OnSemi NB6L611 buffer provides an internal input termination. From the output of this buffer there is a short direct connection to the clock input on the TTCDec mezzanine. The DeSkew_1 and DeSkew_2 clock outputs from the TTCDec provide the time-base for the CMX card. These TTCDec clock connections are shown in the following drawings: 26_clocks_overall_view.pdf 11a_clock_generation_and_distribution_a.pdf 11b_clock_generation_and_distribution_b.pdf Installation of either jumper R254 or R256 selects either the TTCDec: CLK_40_DES_1_PLL_2 or the CLK_40_DES_1 signal as the source of the DeSkew_1 timing on the CMX card. Jumper R255 is always installed to select the TTCDec signal CLK_40_DES_2_PLL_2 as the source of DeSkew_2 timing on the CMX circuit board. These TTCDec clock outputs are right next to the Clock Generation and Distribution section of the CMX card. With this close physical location of the TTCDec and the Clock Generation and Distribution components the interconnecting traces are kept short and direct and are located in a quiet section of the CMX circuit board. A drawing showing the output signals from the TTCDec mezzanine card and the reset signals to the TTCDec is on the web at: 12_ttcdec_data_distribution.pdf All of the non-clock type TTCDec output signals are buffered by 3.3V to 2.5V translators (74AVCAH164245s) and then back terminated by 47 Ohm resistor packs. These buffered TTCDec outputs run up the right-hand side of the 3 FPGAs on the CMX card. All of the TTCDec output signals are routed to both the BSPT FPGA and to the Topological Processor FPGA. Only the TTCDec signals: L1_ACCEPT and BNCH_CNT_RESET are routed to the Base Function FPGA. Routing only these two TTCDec output signals to the BF FPGA matches the functionality on the CMM card. Because of the high density of traces in the break-out region of the BF FPGA the intent is to not route TTCDec signals to the BF that will clearly never be used by it. The full list of TTCDec output signals is given for reference at the end of this note. The TTCDec can be reset by the BSPT FPGA. The TTCDec_Reset_B signal comes directly from a pin in the 3.3V I/O Bank of the BSPT FPGA. The process of resetting the TTCDec includes sending ID bits 13:0 and the 2 Master Mode bits to the TTCDec. In some ATLAS documents the 2 Master_Mode bits are referred to as ID bits 14 and 15 probably because this makes a nice round 16 bit quantity. CMX uses the same basic method of providing the ID and Master Mode bits to the TTCDec during its Reset process as the CMM card does. Considering the ID plus Master Mode information as one 16 bit quantity, bits 15, 14, 13, and bits 5:0 come from a set of resistor "jumpers": JMP27 through JMP10. During Reset the pins in the TTCDec that receive this information become inputs and their logic level is determined by which of these resistor jumpers have been installed. After the Reset process is complete these same pins are outputs with sufficient drive to over come the bias of the installed 4.7k Ohm resistor jumpers. ID bits 12:6 are handled in basically the same way except that during the Reset process these 7 ID bits come from the output of one half of U154 a 2.5V to 3.3V translator chip. The input to this translator is the 7 bit Geographic Address of the CMX card that comes from the 2.5V On-Card_Bus. During the TTCDec Reset process the BSPT FPGA coordinates enabling the output drivers on this half of the U154 translator in time with the TTCDec_Reset_B signal. After the Reset process the output of this half of the U154 translator is disabled and the TTCDec pins that received ID bits 12:6 return to being outputs. On the CMX card the BSPT FPGA provides connections to the SDA and SCL pins on the TTCDec. These signals come from the 3.3V I/O Bank on the BSPT FPGA and are back terminated by resistors R324 and R325. These signals are the I2C serial bus connection to the TTCDec mezzanine card. The 3.3V I/O bank on the BSPT FPGA also provides direct connections to the CLK_SEL and P/D pins on the TTCDec. These signals select either a 40.000 MHz crystal on the TTCDec mezzanine or the TTCrx ASIC Clk40Des1 and Clk40Des_2 signals in either a Normal mode or a Protected mode as the source of the clock outputs from the TTCDec. Recall that the CMX cards Clock Generation and Distribution circuits can only operate with a real LHC frequency clock reference, i.e. they will not operate correctly with a 40.000 Mhz reference clock. The CMX card also provides a JTAG connection to the TTCDec mezzanine on its 3.3V Test JTAG chain. No JTAG management of TTCDec is required that I know of. Jumpers are normally installed to jump the Test JTAG chain around the TTCDec. The only required management of the TTCDec that I know of is to Reset it. The 2.5V buffered TTCDec output signals that are available to the 3 FPGAs on the CMX card are the following: BRCST(7:2), BRCST_STR(2:1) from one section of U151 SIN_ERR_STR, DB_ERR_STR, CLK_40_L1A, from other BNCH_CNT_RES, EVT_CNT_RES, EVT_CNT_H_STR, section EVT_CNT_L_STR, BNCH_CNT_STR of U151 BNCH_CNT(11:0), DQ(3:0) from U152 L1_ACPT, SPARE_1_3, SPARE_2_3, from one SPARE_3_3, SER_B_CH, D_OUT_STR, section TTC_READY, STATUS_2 of U153 D_OUT(7:0) - ID(7:0) from other secion of U153 SUB_ADRS(7:0) - ID(15:8) from one section of U154 Note that if it ends up that only the TTCDec signals: L1_ACCEPT and BNCH_CNT_RESET are ever needed for the operation of the Base Function, Topological, and BSPT FPGAs then to reduce the amount of digital noise on the CMX card one could turn off the 2.5 V outputs on: one section of U151, both sections of U152, one section of U153, and the section of U154 that is used to drive the 2.5V TTCDec signals to the FPGAs.