CMX BF FPGA Virtex System Monitor ------------------------------------- Original Rev. 30-Dec-2013 Current Rev. 27-Apr-2014 This file describes the use of the Virtex System Monitor function in the Base Function and TP FPGAs on the CMX circuit board. A drawing of the reference supplies for the Virtex System Monitors and a general view of the inputs to the Base Function Virtex System Monitor are shown in the circuit diagrams: 06_reference_supplies.pdf 35_voltage_and_current_monitor_analog.pdf The Xilinx documentation about the Virtex-6 System Monitor is available on the MSU CMX web site in the file: virtex_6_system_monitor_ug370_v1_1.pdf As shown in figure 24 on page 46 of the Xilinx document listed above, the +2.5V AVDD power and the AVSS ground connection to the System Monitors on the CMX card are made through LC filter components as shown in the circuit diagram: 06_reference_supplies.pdf. Components: L1901, L1902, C1902, C1903, and C1906 together provide the LC filtering on the power and ground connections to the Base Function FPGA Virtex System Monitor. The traces for the FPGA AVDD and AVSS pins run from this LC filter and then under the FPGA on design layer Signal_7. Similar LC components provide the AVDD power and AVSS ground connections to the System Monitor in the Topological FPGA. The 1.250 Volt reference supply for the Base Function System Monitor is generated by IC U1901 starting from filtered power that is provided by the LC components listed above. IC U1901 is a TI Burr-Brown Part No. REF3140AIDBZT which has an initial accuracy of +- 0.2%, a temperature coefficient of 20 ppm/deg C, and a long term drift of 70 ppm. The 1.250 Volt reference is bypassed by C1905 and then VREFP and VREFN traces are run under the BF FPGA on design layer Signal_7. The direct inputs to the Base Function System Monitor VP and VN pins are not used on the CMX card - rather 12 of the 16 available auxiliary System Monitor input pin pairs are used on the BF FPGA. Neither the direct or auxiliary System Monitor inputs are used on the Topological Processor FPGA. In all uses on the CMX card the external inputs to the System Monitor are setup for unipolar ADC operation, that is the VAUXN(x) analog input pin is tied to ground via a differentially routed trace pair. The quantity to be measured is always positive wrt ground and is tied to the VAUXP(x) analog input pin through a voltage divider and/or an isolation current limiting resistor. All circuits include a 10 nFd anti-alias filter capacitor across the VAUXP(x) VAUXN(x) pin pair. In its basic form the ADC in the Virtex-6 System Monitor is a 10 bit device with a 1.000 Volt full scale input. Thus the basic calibration of this ADC is 0.9775 mV per LSB. The following connections have been made to the Auxiliary analog inputs to the Base Function FPGA System Monitor on the CMX circuit board: Base Func FPGA System Monitor Power Bus Voltage or Auxiliary Input Current Monitored by this Input --------------- ------------------------------- SYSMON_00 input not used for monitoring SYSMON_01 GTX_AVTT Voltage SYSMON_02 input not used for monitoring SYSMON_03 BF_CORE Current SYSMON_04 BF_CORE Voltage SYSMON_05 input not used for monitoring SYSMON_06 input not used for monitoring SYSMON_07 GTX_AVTT Current SYSMON_08 GTX_AVCC Current SYSMON_09 BULK_2V5 Voltage SYSMON_10 BULK_3V3 Current SYSMON_11 GTX_AVCC Voltage SYSMON_12 BULK_3V3 Voltage SYSMON_13 BULK_2V5 Current SYSMON_14 TP_CORE Current SYSMON_15 VREF_P Voltage Select I/O Ref This mapping of System Monitor inputs to the quantities to be measured is forced by routing constraints. The calibration of these various external inputs to the BF System Monitor, based on the resistor values specified in CMX Final Assembly document. As of December 2013 the following scale factors are in use: Refer Monitored SysMon LSB Desig Value Quantity Gain Input Scale ----- -------- ---------- ---- ------ -------- R1941 100k Ohm BF_Core V 0.50 4 1.955 mV R1942 100k Ohm R1943 100k Ohm BF_Core I 0.50 3 9.775 mA R1944 100k Ohm R1945 100k Ohm GTX_AVTT V 0.50 1 1.955 mV R1946 100k Ohm R1947 100k Ohm GTX_AVTT I 0.50 7 4.888 mA R1948 100k Ohm R1949 100k Ohm GTX_AVCC V 0.50 11 1.955 mV R1950 100k Ohm R1951 100k Ohm GTX_AVCC I 0.50 8 4.888 mA R1952 100k Ohm R1953 100k Ohm TP_Core I 0.50 14 9.775 mA R1954 100k Ohm R1955 300k Ohm BULK_3V3 V 0.25 12 3.910 mV R1956 100k Ohm R1957 100k Ohm BULK_3V3 I 0.50 10 9.775 mA R1958 100k Ohm R1959 300k Ohm BULK_2V5 V 0.25 9 3.910 mV R1960 100k Ohm R1961 100k Ohm BULK_2V5 I 0.50 13 9.775 mA R1962 100k Ohm R1963 100k Ohm Select I/O 0.50 15 1.955 mV R1964 100k Ohm VRef_P V This LSB Scale is based on assuming that the System Monitor ADC has a 1 Volt Full Scale Input and will be used to produce 10 bit outputs, i.e. the LBS of the raw converter is about 1 Volt / 1023 = 0.9775 mV per LSB. The one, currently unused, dedicated VP VN analog input pin pair to the Virtex System Monitor has an input current specification of 1 uAmp. The auxiliary analog inputs to the Virtex System Monitor, i.e. the VAUXP(x) VAUXN(x) pin pairs, have a maximum input current specification of 10 uAmps. This could be a problem working with the 50k Ohm source impedance of the voltage dividers as currently defined in the Final Assembly document. This source impedance can be lowered by a factor of 10 if this proves to be a problem.