/////////////////////////////////////////////////////////////////////////////// // // IO pin assignments for the CMX Base Function FPGA // -------------------------------==================== // /////////////////////////////////////////////////////////////////////////////// // // The pin assignments below correspond to the final version of the CMX netlist. // // This list matches the information automatically generated by // Match_Resource_to_Pin V3.1 on 10-Oct-2013. // Additional comments were added to the automatically generated file. // // The format of this file is suitable for (at least a starting point of) // a User Constraint File (UCF) for the Xilinx synthesis tools // /////////////////////////////////////////////////////////////////////////////// // // Rev: 27-Dec-2013 // /////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////// // // 400x Backplane Input Signals // /////////////////////////////////////////////////////////////////////////////// // // Px_y = backplane signals where // x=0:15 is the relative source processor module (JEM or CPM) in the crate, // y=0:24 is the signal index number within that processor source. // (These signal names match the CMM design) // // Every Px_24 signal carries the clock signal from source processor board number x. // All Px_24 signals are connected to one of the single ended regional clock resource pins // (i.e. connected to a signal named IO_L9P_MRCC_nn or IO_L10P_MRCC_nn, // with nn being the IO bank number) // // These signals are single-ended 60 Ohm source-series terminated 2.5V CMOS level input signals. // It may prove preferable to use the CMX external VREF voltage in which case the SSTL2 // IO standard may be appropriate. // // IO_L16N_VRP_35 NET "P0_0" LOC = "L11"; // IO_L18N_GC_35 NET "P0_1" LOC = "M12"; // IO_L10N_MRCC_35 NET "P0_2" LOC = "N13"; // IO_L9N_MRCC_35 NET "P0_3" LOC = "N14"; // IO_L13N_SM6N_35 NET "P0_4" LOC = "C14"; // IO_L18P_GC_35 NET "P0_5" LOC = "L12"; // IO_L12P_SM5P_35 NET "P0_6" LOC = "J13"; // IO_L17P_35 NET "P0_7" LOC = "D13"; // IO_L0N_35 NET "P0_8" LOC = "E12"; // IO_L4P_35 NET "P0_9" LOC = "H14"; // IO_L19N_GC_35 NET "P0_10" LOC = "F14"; // IO_L19P_36 NET "P0_11" LOC = "D17"; // IO_L1N_35 NET "P0_12" LOC = "B16"; // IO_L11N_SRCC_35 NET "P0_13" LOC = "F15"; // IO_L4P_36 NET "P0_14" LOC = "J16"; // IO_L6N_36 NET "P0_15" LOC = "J17"; // IO_L0P_36 NET "P0_16" LOC = "K18"; // IO_L15P_36 NET "P0_17" LOC = "B18"; // IO_L5N_36 NET "P0_18" LOC = "E18"; // IO_L1N_36 NET "P0_19" LOC = "G18"; // IO_L0N_36 NET "P0_20" LOC = "J18"; // IO_L3N_36 NET "P0_21" LOC = "F19"; // IO_L19N_36 NET "P0_22" LOC = "E17"; // IO_L9P_MRCC_36 NET "P0_23" LOC = "P18"; // IO_L10P_MRCC_35 NET "P0_24" LOC = "M13"; // IO_L14P_35 NET "P1_0" LOC = "K14"; // IO_L8N_SRCC_35 NET "P1_1" LOC = "J11"; // IO_L8P_SRCC_35 NET "P1_2" LOC = "J12"; // IO_L0P_35 NET "P1_3" LOC = "F12"; // IO_L13P_SM6P_35 NET "P1_4" LOC = "B14"; // IO_L5N_SM2N_35 NET "P1_5" LOC = "A14"; // IO_L12N_SM5N_35 NET "P1_6" LOC = "K13"; // IO_L16P_VRN_35 NET "P1_7" LOC = "K12"; // IO_L17N_35 NET "P1_8" LOC = "E13"; // IO_L2N_SM0N_35 NET "P1_9" LOC = "G14"; // IO_L14P_36 NET "P1_10" LOC = "J15"; // IO_L1P_35 NET "P1_11" LOC = "A16"; // IO_L5P_SM2P_35 NET "P1_12" LOC = "A15"; // IO_L19P_GC_35 NET "P1_13" LOC = "E14"; // IO_L2P_36 NET "P1_14" LOC = "G16"; // IO_L11N_SRCC_36 NET "P1_15" LOC = "G17"; // IO_L13P_36 NET "P1_16" LOC = "D18"; // IO_L2P_SM0P_35 NET "P1_17" LOC = "H15"; // IO_L11P_SRCC_35 NET "P1_18" LOC = "E15"; // IO_L2N_36 NET "P1_19" LOC = "F16"; // IO_L11P_SRCC_36 NET "P1_20" LOC = "F17"; // IO_L1P_36 NET "P1_21" LOC = "H18"; // IO_L15N_36 NET "P1_22" LOC = "A19"; // IO_L5P_36 NET "P1_23" LOC = "E19"; // IO_L9P_MRCC_35 NET "P1_24" LOC = "M14"; // IO_L16N_36 NET "P2_0" LOC = "L15"; // IO_L16P_36 NET "P2_1" LOC = "L16"; // IO_L17N_36 NET "P2_2" LOC = "B17"; // IO_L6P_36 NET "P2_3" LOC = "K17"; // IO_L8P_SRCC_36 NET "P2_4" LOC = "M18"; // IO_L18P_37 NET "P2_5" LOC = "K19"; // IO_L3P_36 NET "P2_6" LOC = "G19"; // IO_L12N_VRP_37 NET "P2_7" LOC = "F20"; // IO_L8N_SRCC_37 NET "P2_8" LOC = "G21"; // IO_L19P_37 NET "P2_9" LOC = "C20"; // IO_L15N_37 NET "P2_10" LOC = "A20"; // IO_L17P_37 NET "P2_11" LOC = "C21"; // IO_L6P_37 NET "P2_12" LOC = "H21"; // IO_L2P_37 NET "P2_13" LOC = "G22"; // IO_L7N_37 NET "P2_14" LOC = "E23"; // IO_L5N_37 NET "P2_15" LOC = "B22"; // IO_L1P_37 NET "P2_16" LOC = "B24"; // IO_L1N_37 NET "P2_17" LOC = "A24"; // IO_L5P_37 NET "P2_18" LOC = "B23"; // IO_L11P_SRCC_37 NET "P2_19" LOC = "D23"; // IO_L12P_VRN_37 NET "P2_20" LOC = "E20"; // IO_L4P_37 NET "P2_21" LOC = "F21"; // IO_L2N_37 NET "P2_22" LOC = "F22"; // IO_L11N_SRCC_37 NET "P2_23" LOC = "D22"; // IO_L10P_MRCC_37 NET "P2_24" LOC = "J22"; // IO_L18N_36 NET "P3_0" LOC = "N15"; // IO_L17P_36 NET "P3_1" LOC = "A17"; // IO_L18P_36 NET "P3_2" LOC = "M16"; // IO_L9N_MRCC_36 NET "P3_3" LOC = "P17"; // IO_L8N_SRCC_36 NET "P3_4" LOC = "N18"; // IO_L13N_36 NET "P3_5" LOC = "C18"; // IO_L18N_37 NET "P3_6" LOC = "L19"; // IO_L7N_36 NET "P3_7" LOC = "B19"; // IO_L7P_36 NET "P3_8" LOC = "C19"; // IO_L8P_SRCC_37 NET "P3_9" LOC = "H20"; // IO_L14P_37 NET "P3_10" LOC = "J20"; // IO_L17N_37 NET "P3_11" LOC = "D21"; // IO_L6N_37 NET "P3_12" LOC = "J21"; // IO_L13N_37 NET "P3_13" LOC = "A21"; // IO_L9P_MRCC_37 NET "P3_14" LOC = "L22"; // IO_L10N_MRCC_37 NET "P3_15" LOC = "K22"; // IO_L0P_37 NET "P3_16" LOC = "G23"; // IO_L3N_37 NET "P3_17" LOC = "C23"; // IO_L13P_37 NET "P3_18" LOC = "A22"; // IO_L15P_37 NET "P3_19" LOC = "B21"; // IO_L0N_37 NET "P3_20" LOC = "H23"; // IO_L3P_37 NET "P3_21" LOC = "C24"; // IO_L7P_37 NET "P3_22" LOC = "E24"; // IO_L19N_37 NET "P3_23" LOC = "D20"; // IO_L10P_MRCC_36 NET "P3_24" LOC = "N16"; // IO_L10N_MRCC_28 NET "P4_0" LOC = "N25"; // IO_L19P_28 NET "P4_1" LOC = "M26"; // IO_L18P_28 NET "P4_2" LOC = "L27"; // IO_L14P_28 NET "P4_3" LOC = "H28"; // IO_L15N_28 NET "P4_4" LOC = "C29"; // IO_L10N_MRCC_27 NET "P4_5" LOC = "M29"; // IO_L3P_28 NET "P4_6" LOC = "E30"; // IO_L5P_28 NET "P4_7" LOC = "C31"; // IO_L6P_27 NET "P4_8" LOC = "H31"; // IO_L8N_SRCC_27 NET "P4_9" LOC = "G32"; // IO_L3N_27 NET "P4_10" LOC = "C33"; // IO_L12P_VRN_27 NET "P4_11" LOC = "H33"; // IO_L9N_MRCC_28 NET "P4_12" LOC = "L25"; // IO_L0N_28 NET "P4_13" LOC = "J26"; // IO_L17N_28 NET "P4_14" LOC = "A30"; // IO_L15P_28 NET "P4_15" LOC = "B29"; // IO_L17P_28 NET "P4_16" LOC = "A29"; // IO_L11P_SRCC_28 NET "P4_17" LOC = "F27"; // IO_L1P_28 NET "P4_18" LOC = "D28"; // IO_L1N_28 NET "P4_19" LOC = "E29"; // IO_L7P_28 NET "P4_20" LOC = "C30"; // IO_L5N_28 NET "P4_21" LOC = "D31"; // IO_L0N_27 NET "P4_22" LOC = "D32"; // IO_L11P_SRCC_27 NET "P4_23" LOC = "D33"; // IO_L10P_MRCC_28 NET "P4_24" LOC = "N24"; // IO_L2P_28 NET "P5_0" LOC = "G28"; // IO_L6N_28 NET "P5_1" LOC = "P23"; // IO_L6P_28 NET "P5_2" LOC = "R23"; // IO_L8N_SRCC_28 NET "P5_3" LOC = "P25"; // IO_L13P_28 NET "P5_4" LOC = "A31"; // IO_L18N_28 NET "P5_5" LOC = "K27"; // IO_L0P_28 NET "P5_6" LOC = "J27"; // IO_L2N_28 NET "P5_7" LOC = "G27"; // IO_L11N_SRCC_28 NET "P5_8" LOC = "E28"; // IO_L13N_28 NET "P5_9" LOC = "B31"; // IO_L2P_27 NET "P5_10" LOC = "F32"; // IO_L6N_27 NET "P5_11" LOC = "G31"; // IO_L4P_28 NET "P5_12" LOC = "G29"; // IO_L7N_28 NET "P5_13" LOC = "D30"; // IO_L2N_27 NET "P5_14" LOC = "F31"; // IO_L13P_27 NET "P5_15" LOC = "A36"; // IO_L13N_27 NET "P5_16" LOC = "B36"; // IO_L5N_27 NET "P5_17" LOC = "A35"; // IO_L0P_27 NET "P5_18" LOC = "E32"; // IO_L11N_SRCC_27 NET "P5_19" LOC = "E33"; // IO_L17P_27 NET "P5_20" LOC = "E34"; // IO_L4P_27 NET "P5_21" LOC = "E35"; // IO_L19P_27 NET "P5_22" LOC = "D36"; // IO_L19N_27 NET "P5_23" LOC = "D37"; // IO_L9P_MRCC_28 NET "P5_24" LOC = "L26"; // IO_L1N_26 NET "P6_0" LOC = "A37"; // IO_L15P_27 NET "P6_1" LOC = "C35"; // IO_L10N_MRCC_26 NET "P6_2" LOC = "F36"; // IO_L3N_26 NET "P6_3" LOC = "A39"; // IO_L3P_26 NET "P6_4" LOC = "B38"; // IO_L1P_26 NET "P6_5" LOC = "B37"; // IO_L0N_26 NET "P6_6" LOC = "G36"; // IO_L4P_26 NET "P6_7" LOC = "F37"; // IO_L18N_26 NET "P6_8" LOC = "G42"; // IO_L19N_26 NET "P6_9" LOC = "F42"; // IO_L19P_26 NET "P6_10" LOC = "E42"; // IO_L7N_26 NET "P6_11" LOC = "A41"; // IO_L7P_26 NET "P6_12" LOC = "A40"; // IO_L6P_26 NET "P6_13" LOC = "D38"; // IO_L5P_26 NET "P6_14" LOC = "B39"; // IO_L5N_26 NET "P6_15" LOC = "C39"; // IO_L13P_26 NET "P6_16" LOC = "C40"; // IO_L11P_SRCC_26 NET "P6_17" LOC = "B41"; // IO_L13N_26 NET "P6_18" LOC = "C41"; // IO_L15N_26 NET "P6_19" LOC = "D41"; // IO_L17N_26 NET "P6_20" LOC = "E40"; // IO_L16P_26 NET "P6_21" LOC = "F40"; // IO_L16N_26 NET "P6_22" LOC = "F41"; // IO_L18P_26 NET "P6_23" LOC = "G41"; // IO_L9P_MRCC_26 NET "P6_24" LOC = "G34"; // IO_L18P_27 NET "P7_0" LOC = "K29"; // IO_L16P_27 NET "P7_1" LOC = "H30"; // IO_L3P_27 NET "P7_2" LOC = "B33"; // IO_L1N_27 NET "P7_3" LOC = "B32"; // IO_L1P_27 NET "P7_4" LOC = "A32"; // IO_L5P_27 NET "P7_5" LOC = "A34"; // IO_L7P_27 NET "P7_6" LOC = "B34"; // IO_L10P_MRCC_26 NET "P7_7" LOC = "F35"; // IO_L17N_27 NET "P7_8" LOC = "F34"; // IO_L8P_SRCC_27 NET "P7_9" LOC = "G33"; // IO_L7N_27 NET "P7_10" LOC = "C34"; // IO_L9N_MRCC_26 NET "P7_11" LOC = "H34"; // IO_L2N_26 NET "P7_12" LOC = "H35"; // IO_L15N_27 NET "P7_13" LOC = "C36"; // IO_L0P_26 NET "P7_14" LOC = "H36"; // IO_L14P_26 NET "P7_15" LOC = "G37"; // IO_L6N_26 NET "P7_16" LOC = "C38"; // IO_L8N_SRCC_26 NET "P7_17" LOC = "E38"; // IO_L17P_26 NET "P7_18" LOC = "D40"; // IO_L11N_SRCC_26 NET "P7_19" LOC = "B42"; // IO_L15P_26 NET "P7_20" LOC = "D42"; // IO_L8P_SRCC_26 NET "P7_21" LOC = "E39"; // IO_L12P_VRN_26 NET "P7_22" LOC = "F39"; // IO_L12N_VRP_26 NET "P7_23" LOC = "G39"; // IO_L9P_MRCC_27 NET "P7_24" LOC = "L29"; // IO_L6P_22 NET "P8_0" LOC = "BA32"; // IO_L14P_22 NET "P8_1" LOC = "BB33"; // IO_L16P_22 NET "P8_2" LOC = "BA31"; // IO_L19P_23 NET "P8_3" LOC = "AV33"; // IO_L19N_23 NET "P8_4" LOC = "AW33"; // IO_L3P_23 NET "P8_5" LOC = "AM33"; // IO_L3N_23 NET "P8_6" LOC = "AM32"; // IO_L12N_VRP_22 NET "P8_7" LOC = "BA29"; // IO_L4P_22 NET "P8_8" LOC = "AY32"; // IO_L1P_23 NET "P8_9" LOC = "AM31"; // IO_L2N_23 NET "P8_10" LOC = "AL30"; // IO_L8N_SRCC_22 NET "P8_11" LOC = "AY30"; // IO_L8N_SRCC_23 NET "P8_12" LOC = "AK29"; // IO_L12P_VRN_22 NET "P8_13" LOC = "AY29"; // IO_L6N_23 NET "P8_14" LOC = "AM28"; // IO_L16P_23 NET "P8_15" LOC = "AK27"; // IO_L5N_23 NET "P8_16" LOC = "AN34"; // IO_L17P_23 NET "P8_17" LOC = "AU33"; // IO_L17N_23 NET "P8_18" LOC = "AU32"; // IO_L13N_22 NET "P8_19" LOC = "AU31"; // IO_L7P_22 NET "P8_20" LOC = "AT30"; // IO_L5P_22 NET "P8_21" LOC = "AT29"; // IO_L10P_MRCC_22 NET "P8_22" LOC = "AN28"; // IO_L11P_SRCC_22 NET "P8_23" LOC = "AR27"; // IO_L9P_MRCC_22 NET "P8_24" LOC = "AM26"; // IO_L15P_23 NET "P9_0" LOC = "AR33"; // IO_L15N_23 NET "P9_1" LOC = "AT32"; // IO_L11P_SRCC_23 NET "P9_2" LOC = "AR34"; // IO_L5P_23 NET "P9_3" LOC = "AN33"; // IO_L13P_23 NET "P9_4" LOC = "AP32"; // IO_L2P_22 NET "P9_5" LOC = "AW31"; // IO_L16N_22 NET "P9_6" LOC = "BB31"; // IO_L8P_SRCC_22 NET "P9_7" LOC = "BA30"; // IO_L7N_23 NET "P9_8" LOC = "AN31"; // IO_L0N_23 NET "P9_9" LOC = "AN30"; // IO_L2P_23 NET "P9_10" LOC = "AL29"; // IO_L15N_22 NET "P9_11" LOC = "AV29"; // IO_L18N_22 NET "P9_12" LOC = "BB28"; // IO_L17N_22 NET "P9_13" LOC = "AV28"; // IO_L3N_22 NET "P9_14" LOC = "AP28"; // IO_L6P_23 NET "P9_15" LOC = "AL27"; // IO_L11N_SRCC_23 NET "P9_16" LOC = "AP33"; // IO_L13N_23 NET "P9_17" LOC = "AR32"; // IO_L0N_22 NET "P9_18" LOC = "AV30"; // IO_L0P_22 NET "P9_19" LOC = "AW30"; // IO_L7P_23 NET "P9_20" LOC = "AP31"; // IO_L0P_23 NET "P9_21" LOC = "AP30"; // IO_L4P_23 NET "P9_22" LOC = "AN29"; // IO_L3P_22 NET "P9_23" LOC = "AR28"; // IO_L9P_MRCC_23 NET "P9_24" LOC = "AJ25"; // IO_L6N_22 NET "P10_0" LOC = "AY33"; // IO_L2N_22 NET "P10_1" LOC = "AV31"; // IO_L13P_22 NET "P10_2" LOC = "AT31"; // IO_L7N_22 NET "P10_3" LOC = "AR30"; // IO_L5N_22 NET "P10_4" LOC = "AR29"; // IO_L15P_22 NET "P10_5" LOC = "AU29"; // IO_L17P_22 NET "P10_6" LOC = "AU28"; // IO_L1N_22 NET "P10_7" LOC = "AP27"; // IO_L11N_SRCC_22 NET "P10_8" LOC = "AT27"; // IO_L0N_21 NET "P10_9" LOC = "AU27"; // IO_L19P_22 NET "P10_10" LOC = "AW28"; // IO_L18P_22 NET "P10_11" LOC = "BB29"; // IO_L16P_21 NET "P10_12" LOC = "AV26"; // IO_L16N_21 NET "P10_13" LOC = "AU26"; // IO_L10N_MRCC_21 NET "P10_14" LOC = "AL25"; // IO_L18P_21 NET "P10_15" LOC = "AW25"; // IO_L2N_21 NET "P10_16" LOC = "AW27"; // IO_L6P_21 NET "P10_17" LOC = "BB26"; // IO_L12N_VRP_21 NET "P10_18" LOC = "AV25"; // IO_L8N_SRCC_21 NET "P10_19" LOC = "AU24"; // IO_L11N_SRCC_21 NET "P10_20" LOC = "AR23"; // IO_L12P_VRN_21 NET "P10_21" LOC = "AV24"; // IO_L8P_SRCC_21 NET "P10_22" LOC = "AU23"; // IO_L14P_21 NET "P10_23" LOC = "BA25"; // IO_L9P_MRCC_21 NET "P10_24" LOC = "AP25"; // IO_L2P_21 NET "P11_0" LOC = "AY27"; // IO_L1P_22 NET "P11_1" LOC = "AN26"; // IO_L13P_21 NET "P11_2" LOC = "AM24"; // IO_L5N_21 NET "P11_3" LOC = "AK23"; // IO_L7P_21 NET "P11_4" LOC = "AM23"; // IO_L1P_21 NET "P11_5" LOC = "AK22"; // IO_L1N_21 NET "P11_6" LOC = "AJ22"; // IO_L10N_MRCC_22 NET "P11_7" LOC = "AM27"; // IO_L0P_21 NET "P11_8" LOC = "AT26"; // IO_L18N_21 NET "P11_9" LOC = "AW26"; // IO_L4P_21 NET "P11_10" LOC = "BA26"; // IO_L19N_22 NET "P11_11" LOC = "AY28"; // IO_L19N_21 NET "P11_12" LOC = "AR25"; // IO_L19P_21 NET "P11_13" LOC = "AT25"; // IO_L17N_21 NET "P11_14" LOC = "AT24"; // IO_L11P_SRCC_21 NET "P11_15" LOC = "AP23"; // IO_L6N_21 NET "P11_16" LOC = "BB27"; // IO_L9N_MRCC_21 NET "P11_17" LOC = "AP26"; // IO_L15N_21 NET "P11_18" LOC = "AN25"; // IO_L17P_21 NET "P11_19" LOC = "AR24"; // IO_L15P_21 NET "P11_20" LOC = "AN24"; // IO_L7N_21 NET "P11_21" LOC = "AN23"; // IO_L3P_21 NET "P11_22" LOC = "AM22"; // IO_L3N_21 NET "P11_23" LOC = "AL22"; // IO_L10P_MRCC_21 NET "P11_24" LOC = "AK24"; // IO_L18P_32 NET "P12_0" LOC = "BB22"; // IO_L0N_32 NET "P12_1" LOC = "BA24"; // IO_L14P_32 NET "P12_2" LOC = "BA22"; // IO_L6N_32 NET "P12_3" LOC = "BB23"; // IO_L5N_32 NET "P12_4" LOC = "AL21"; // IO_L11P_SRCC_32 NET "P12_5" LOC = "AM21"; // IO_L3N_32 NET "P12_6" LOC = "AR20"; // IO_L8P_SRCC_32 NET "P12_7" LOC = "AY20"; // IO_L7N_32 NET "P12_8" LOC = "AP20"; // IO_L17N_33 NET "P12_9" LOC = "AY19"; // IO_L13P_33 NET "P12_10" LOC = "AV18"; // IO_L10N_MRCC_32 NET "P12_11" LOC = "AK19"; // IO_L18P_33 NET "P12_12" LOC = "AK18"; // IO_L6N_33 NET "P12_13" LOC = "AK17"; // IO_L14P_33 NET "P12_14" LOC = "AM17"; // IO_L8P_SRCC_33 NET "P12_15" LOC = "AN16"; // IO_L2P_33 NET "P12_16" LOC = "AN15"; // IO_L2N_33 NET "P12_17" LOC = "AM14"; // IO_L4P_32 NET "P12_18" LOC = "AW23"; // IO_L16N_32 NET "P12_19" LOC = "AY22"; // IO_L16P_32 NET "P12_20" LOC = "AW22"; // IO_L2P_32 NET "P12_21" LOC = "AV23"; // IO_L12N_VRP_32 NET "P12_22" LOC = "AW21"; // IO_L13N_32 NET "P12_23" LOC = "AW20"; // IO_L10P_MRCC_32 NET "P12_24" LOC = "AK20"; // IO_L17N_32 NET "P13_0" LOC = "AR22"; // IO_L19N_32 NET "P13_1" LOC = "AP22"; // IO_L15N_32 NET "P13_2" LOC = "AT21"; // IO_L6P_32 NET "P13_3" LOC = "BB24"; // IO_L2N_32 NET "P13_4" LOC = "AU22"; // IO_L17P_32 NET "P13_5" LOC = "AT22"; // IO_L15P_32 NET "P13_6" LOC = "AU21"; // IO_L12P_VRN_32 NET "P13_7" LOC = "AV21"; // IO_L13P_32 NET "P13_8" LOC = "AV20"; // IO_L11N_SRCC_33 NET "P13_9" LOC = "AR19"; // IO_L11N_SRCC_32 NET "P13_10" LOC = "AN21"; // IO_L19P_32 NET "P13_11" LOC = "AP21"; // IO_L18N_32 NET "P13_12" LOC = "BB21"; // IO_L15N_33 NET "P13_13" LOC = "BB19"; // IO_L8N_SRCC_32 NET "P13_14" LOC = "BA20"; // IO_L3P_32 NET "P13_15" LOC = "AT20"; // IO_L1N_32 NET "P13_16" LOC = "AM19"; // IO_L1P_32 NET "P13_17" LOC = "AL19"; // IO_L16P_33 NET "P13_18" LOC = "AN18"; // IO_L17P_33 NET "P13_19" LOC = "BA19"; // IO_L19N_33 NET "P13_20" LOC = "AT19"; // IO_L4P_33 NET "P13_21" LOC = "AL17"; // IO_L8N_SRCC_33 NET "P13_22" LOC = "AM16"; // IO_L12P_VRN_33 NET "P13_23" LOC = "AP16"; // IO_L9P_MRCC_33 NET "P13_24" LOC = "AK15"; // IO_L19P_33 NET "P14_0" LOC = "AU19"; // IO_L18P_A17_34 NET "P14_1" LOC = "AY17"; // IO_L7N_33 NET "P14_2" LOC = "AW18"; // IO_L7P_33 NET "P14_3" LOC = "AY18"; // IO_L13N_33 NET "P14_4" LOC = "AV19"; // IO_L16N_33 NET "P14_5" LOC = "AN19"; // IO_L15P_33 NET "P14_6" LOC = "BB18"; // IO_L8N_SRCC_34 NET "P14_7" LOC = "AW16"; // IO_L3N_33 NET "P14_8" LOC = "AU17"; // IO_L1N_33 NET "P14_9" LOC = "AR18"; // IO_L11P_SRCC_33 NET "P14_10" LOC = "AP18"; // IO_L10P_MRCC_33 NET "P14_11" LOC = "AJ16"; // IO_L8P_SRCC_34 NET "P14_12" LOC = "AV16"; // IO_L5P_33 NET "P14_13" LOC = "AT17"; // IO_L6P_A07_D23_34 NET "P14_14" LOC = "AY15"; // IO_L0P_33 NET "P14_15" LOC = "AL15"; // IO_L9N_MRCC_33 NET "P14_16" LOC = "AK14"; // IO_L10N_MRCC_34 NET "P14_17" LOC = "AN13"; // IO_L11P_SRCC_34 NET "P14_18" LOC = "AV13"; // IO_L14P_A25_34 NET "P14_19" LOC = "BA16"; // IO_L12N_A02_D18_34 NET "P14_20" LOC = "BB14"; // IO_L12P_A03_D19_34 NET "P14_21" LOC = "BB13"; // IO_L13N_A00_D16_34 NET "P14_22" LOC = "AW13"; // IO_L9N_MRCC_34 NET "P14_23" LOC = "AM12"; // IO_L10P_MRCC_34 NET "P14_24" LOC = "AN14"; // IO_L5N_33 NET "P15_0" LOC = "AU18"; // IO_L18N_A16_34 NET "P15_1" LOC = "AW17"; // IO_L6N_A06_D22_34 NET "P15_2" LOC = "AW15"; // IO_L12N_VRP_33 NET "P15_3" LOC = "AP17"; // IO_L1P_33 NET "P15_4" LOC = "AR17"; // IO_L3P_33 NET "P15_5" LOC = "AT16"; // IO_L4P_A11_D27_34 NET "P15_6" LOC = "AV15"; // IO_L15N_A22_34 NET "P15_7" LOC = "AT14"; // IO_L16N_A20_34 NET "P15_8" LOC = "BB17"; // IO_L16P_A21_34 NET "P15_9" LOC = "BB16"; // IO_L11N_SRCC_34 NET "P15_10" LOC = "AV14"; // IO_L17N_A18_34 NET "P15_11" LOC = "AR15"; // IO_L15P_A23_34 NET "P15_12" LOC = "AR14"; // IO_L2P_A15_D31_34 NET "P15_13" LOC = "BA15"; // IO_L2N_A14_D30_34 NET "P15_14" LOC = "BA14"; // IO_L7N_A04_D20_34 NET "P15_15" LOC = "AU13"; // IO_L7P_A05_D21_34 NET "P15_16" LOC = "AU12"; // IO_L5N_A08_D24_34 NET "P15_17" LOC = "AR13"; // IO_L3N_A12_D28_34 NET "P15_18" LOC = "AT12"; // IO_L17P_A19_34 NET "P15_19" LOC = "AP15"; // IO_L0N_33 NET "P15_20" LOC = "AL14"; // IO_L5P_A09_D25_34 NET "P15_21" LOC = "AP13"; // IO_L3P_A13_D29_34 NET "P15_22" LOC = "AR12"; // IO_L13P_A01_D17_34 NET "P15_23" LOC = "AW12"; // IO_L9P_MRCC_34 NET "P15_24" LOC = "AM13"; /////////////////////////////////////////////////////////////////////////////// // // External VREF for optional usage with backplane inputs // /////////////////////////////////////////////////////////////////////////////// // // These are the IO pins used to provide an external controlled VREF // to each IO bank instead of the default limited values of INTERNAL_VREF. // // Below are all the VREF pins from all IO banks involved // in receiving the 400x backplane inputs // // IO_L4N_VREF_21 NET "VREF_P" LOC = "BA27"; // IO_L14N_VREF_21 NET "VREF_P" LOC = "AY25"; // IO_L4N_VREF_22 NET "VREF_P" LOC = "AW32"; // IO_L14N_VREF_22 NET "VREF_P" LOC = "BB32"; // IO_L4N_VREF_23 NET "VREF_P" LOC = "AM29"; // IO_L14N_VREF_23 NET "VREF_P" LOC = "AG27"; // IO_L4N_VREF_26 NET "VREF_P" LOC = "E37"; // IO_L14N_VREF_26 NET "VREF_P" LOC = "G38"; // IO_L4N_VREF_27 NET "VREF_P" LOC = "D35"; // IO_L14N_VREF_27 NET "VREF_P" LOC = "J31"; // IO_L4N_VREF_28 NET "VREF_P" LOC = "F29"; // IO_L14N_VREF_28 NET "VREF_P" LOC = "H29"; // IO_L4N_VREF_32 NET "VREF_P" LOC = "AY23"; // IO_L14N_VREF_32 NET "VREF_P" LOC = "BA21"; // IO_L4N_VREF_33 NET "VREF_P" LOC = "AL16"; // IO_L14N_VREF_33 NET "VREF_P" LOC = "AM18"; // IO_L4N_VREF_A10_D26_34 NET "VREF_P" LOC = "AU14"; // IO_L14N_VREF_A24_34 NET "VREF_P" LOC = "BA17"; // IO_L4N_VREF_35 NET "VREF_P" LOC = "G13"; // IO_L14N_VREF_35 NET "VREF_P" LOC = "L14"; // IO_L4N_VREF_36 NET "VREF_P" LOC = "H16"; // IO_L14N_VREF_36 NET "VREF_P" LOC = "K15"; // IO_L4N_VREF_37 NET "VREF_P" LOC = "E22"; // IO_L14N_VREF_37 NET "VREF_P" LOC = "H19"; /////////////////////////////////////////////////////////////////////////////// // // Digitally Controlled Impedance (DCI) // /////////////////////////////////////////////////////////////////////////////// // // The l1calo recommendation based on the BLT tests is that the CMX card does not need // to terminate the 400x backplane input signals, but if termination were needed, the CMX // can provide an external reference resistor to set a 60 Ohm or other optimal termination. // // One pair of DCI reference pins is allocated and connected to reference resistors // for each set of 3 contiguous IO Banks used to receive a set of 4 processor input sources. // DCI Cascading is needed among the IO Banks in each set of 3 contiguous IO Banks in order // to share the reference resistors with the other 2 IO Banks from this set. // // IO_L12N_VRP_36 NET "P0TO3_DCI_P" LOC = "M17"; // IO_L12P_VRN_36 NET "P0TO3_DCI_N" LOC = "L17"; // IO_L12N_VRP_28 NET "P4TO7_DCI_P" LOC = "N26"; // IO_L12P_VRN_28 NET "P4TO7_DCI_N" LOC = "P26"; // IO_L12N_VRP_23 NET "P8TO11_DCI_P" LOC = "AJ28"; // IO_L12P_VRN_23 NET "P8TO11_DCI_N" LOC = "AH28"; // IO_L19N_VRP_34 NET "P12TO15_DCI_P" LOC = "AU16"; // IO_L19P_VRN_34 NET "P12TO15_DCI_N" LOC = "AT15"; /////////////////////////////////////////////////////////////////////////////// // // Crate CMX to System CMX Merger Cables // /////////////////////////////////////////////////////////////////////////////// // // These IO pins are connected to the 2.5V side of a set of bidirectional 2.5V to 3.3V // voltage level translators. The other side of these translators is connected // to bidirectional LVDS transceivers to drive or receive (via backplane pins) // the 27 LVDS signal pairs on each of the three Merger Cable connectors from // a Rear-Transition Module (RTM) plugged in the back of the l1calo crate. // // Up to 3 cables are used with a given CMX card. // A Crate CMX card uses only one cable and as an output, // while a System CMX card receives 2 or 3 cables as inputs. // // 'D_CBL_zz_B' are the cable IO signals available to the Base FPGA with zz=00 to 83. // The "_B" postfix is used to indicate that these signals are inverted with respect // to the LVDS signal polarity on the data cables. // (These signal names match the CMM design) // // The control signals used to enable and control the direction of the voltage // translators and LVDS transceivers are managed by the Board Support FPGA and // submitted to a final sanity check by going through the hardware oversight logic. // The Base Function FPGA thus sends three signals to the Board Support FPGA // to "request" the direction of each Merger IO Cable cf. BF_REQ_CABLE_n_INPUT below. // // A Rear Transition Module (RTM) card provides the interface to the three 34-signal // LVDS connectors where the IO cables can be connected. // Only 27 signals from each connector are routed on the current RTM cards. // zz=0 to 26 correspond to the first cable, // zz=27 to 53 correspond to the second cable, and // zz=54 to 80 correspond to the third cable. // // Additionally, 3 more differential pairs of signals are labelled on the backplane // but are not routed on the RTM: zz= 31 to 83 // The CMX card connects the currently unused M_81, M_82, and M_83 signals. // // The sets of cable signals are thus: // Cable #1 consists of signals M_00 to M_26 plus M_81 // Cable #2 consists of signals M_27 to M_53 plus M_82 // Cable #3 consists of signals M_54 to M_80 plus M_83 // // The CMX card could thus be able to use 28 LVDS signals per cable while the CMM was only able // to use 27 signals. Using 28 signals would however require a new version of the RTM card. // This 28th signal can be left unused and set to a fixed state by the FPGA of the source Crate CMX // while the LVDS transceiver of the receiving System CMX will default to receive a defined value // for all non-connected inputs. // // These signals are single-ended un-terminated 2.5V CMOS level input or output signals. // // IO_L1P_17 NET "D_CBL_00_B" LOC = "L39"; // IO_L3N_17 NET "D_CBL_01_B" LOC = "L42"; // IO_L0P_17 NET "D_CBL_02_B" LOC = "M36"; // IO_L7N_17 NET "D_CBL_03_B" LOC = "M42"; // IO_L6P_17 NET "D_CBL_04_B" LOC = "N36"; // IO_L6N_17 NET "D_CBL_05_B" LOC = "P37"; // IO_L15P_17 NET "D_CBL_06_B" LOC = "P42"; // IO_L14P_17 NET "D_CBL_07_B" LOC = "R35"; // IO_L15N_17 NET "D_CBL_08_B" LOC = "R42"; // IO_L18N_17 NET "D_CBL_09_B" LOC = "T35"; // IO_L19N_17 NET "D_CBL_10_B" LOC = "T42"; // IO_L16P_17 NET "D_CBL_11_B" LOC = "U36"; // IO_L3P_16 NET "D_CBL_12_B" LOC = "U42"; // IO_L2N_16 NET "D_CBL_13_B" LOC = "V36"; // IO_L6P_16 NET "D_CBL_14_B" LOC = "W35"; // IO_L15P_16 NET "D_CBL_15_B" LOC = "W42"; // IO_L14N_VREF_16 NET "D_CBL_16_B" LOC = "Y34"; // IO_L15N_16 NET "D_CBL_17_B" LOC = "Y42"; // IO_L8N_SRCC_16 NET "D_CBL_18_B" LOC = "Y35"; // IO_L14P_16 NET "D_CBL_19_B" LOC = "AA34"; // IO_L12P_VRN_16 NET "D_CBL_20_B" LOC = "AA32"; // IO_L1N_17 NET "D_CBL_21_B" LOC = "L40"; // IO_L0N_17 NET "D_CBL_22_B" LOC = "M37"; // IO_L7P_17 NET "D_CBL_23_B" LOC = "M41"; // IO_L11N_SRCC_17 NET "D_CBL_24_B" LOC = "N41"; // IO_L9P_MRCC_17 NET "D_CBL_25_B" LOC = "P36"; // IO_L17P_17 NET "D_CBL_26_B" LOC = "R40"; // IO_L5P_17 NET "D_CBL_81_B" LOC = "N38"; // IO_L8N_SRCC_17 NET "D_CBL_27_B" LOC = "P38"; // IO_L12P_VRN_17 NET "D_CBL_28_B" LOC = "R37"; // IO_L16N_17 NET "D_CBL_29_B" LOC = "T36"; // IO_L1P_16 NET "D_CBL_30_B" LOC = "U37"; // IO_L7P_16 NET "D_CBL_31_B" LOC = "V38"; // IO_L2P_16 NET "D_CBL_32_B" LOC = "W36"; // IO_L0P_16 NET "D_CBL_33_B" LOC = "W37"; // IO_L0N_16 NET "D_CBL_34_B" LOC = "Y37"; // IO_L4P_16 NET "D_CBL_35_B" LOC = "AA36"; // IO_L8P_SRCC_16 NET "D_CBL_36_B" LOC = "AA35"; // IO_L3P_17 NET "D_CBL_37_B" LOC = "L41"; // IO_L2P_17 NET "D_CBL_38_B" LOC = "M38"; // IO_L5N_17 NET "D_CBL_39_B" LOC = "N39"; // IO_L13P_17 NET "D_CBL_40_B" LOC = "P40"; // IO_L10N_MRCC_17 NET "D_CBL_41_B" LOC = "R38"; // IO_L12N_VRP_17 NET "D_CBL_42_B" LOC = "T37"; // IO_L1N_16 NET "D_CBL_43_B" LOC = "U38"; // IO_L5N_16 NET "D_CBL_44_B" LOC = "V39"; // IO_L11P_SRCC_16 NET "D_CBL_45_B" LOC = "V40"; // IO_L7N_16 NET "D_CBL_46_B" LOC = "W38"; // IO_L19P_16 NET "D_CBL_47_B" LOC = "Y38"; // IO_L10P_MRCC_17 NET "D_CBL_48_B" LOC = "T39"; // IO_L19P_17 NET "D_CBL_49_B" LOC = "T41"; // IO_L2N_17 NET "D_CBL_50_B" LOC = "M39"; // IO_L11P_SRCC_17 NET "D_CBL_51_B" LOC = "N40"; // IO_L13N_17 NET "D_CBL_52_B" LOC = "P41"; // IO_L8P_SRCC_17 NET "D_CBL_53_B" LOC = "R39"; // IO_L17N_17 NET "D_CBL_82_B" LOC = "T40"; // IO_L8P_SRCC_15 NET "D_CBL_54_B" LOC = "AC36"; // IO_L16P_VRN_15 NET "D_CBL_55_B" LOC = "AC35"; // IO_L10P_MRCC_15 NET "D_CBL_56_B" LOC = "AE37"; // IO_L17P_15 NET "D_CBL_57_B" LOC = "AF42"; // IO_L16N_VRP_15 NET "D_CBL_58_B" LOC = "AB34"; // IO_L8N_SRCC_15 NET "D_CBL_59_B" LOC = "AB36"; // IO_L4P_15 NET "D_CBL_60_B" LOC = "AC38"; // IO_L10N_MRCC_15 NET "D_CBL_61_B" LOC = "AD37"; // IO_L14P_15 NET "D_CBL_62_B" LOC = "AD36"; // IO_L19N_15 NET "D_CBL_63_B" LOC = "AE39"; // IO_L19N_16 NET "D_CBL_64_B" LOC = "AA39"; // IO_L4N_VREF_16 NET "D_CBL_65_B" LOC = "AA37"; // IO_L1P_15 NET "D_CBL_66_B" LOC = "AB37"; // IO_L1N_15 NET "D_CBL_67_B" LOC = "AB38"; // IO_L4N_VREF_15 NET "D_CBL_68_B" LOC = "AC39"; // IO_L5P_16 NET "D_CBL_69_B" LOC = "U39"; // IO_L3N_16 NET "D_CBL_70_B" LOC = "U41"; // IO_L13P_16 NET "D_CBL_71_B" LOC = "V41"; // IO_L11N_SRCC_16 NET "D_CBL_72_B" LOC = "W40"; // IO_L17N_16 NET "D_CBL_73_B" LOC = "Y39"; // IO_L11P_SRCC_15 NET "D_CBL_74_B" LOC = "AC41"; // IO_L11N_SRCC_15 NET "D_CBL_75_B" LOC = "AD41"; // IO_L19P_15 NET "D_CBL_76_B" LOC = "AE40"; // IO_L6N_16 NET "D_CBL_77_B" LOC = "V35"; // IO_L9P_MRCC_16 NET "D_CBL_78_B" LOC = "W32"; // IO_L13N_16 NET "D_CBL_79_B" LOC = "W41"; // IO_L17P_16 NET "D_CBL_80_B" LOC = "Y40"; // IO_L0N_15 NET "D_CBL_83_B" LOC = "AE35"; /////////////////////////////////////////////////////////////////////////////// // // CTP Output // /////////////////////////////////////////////////////////////////////////////// // // These IO pins are connected to the 2.5V side of a set of bidirectional 2.5V to 3.3V // voltage level translators. The other side of these translators is connected // to bidirectional LVDS transceivers to drive or receive the 33 LVDS signal pairs // from each of the two front panel CTP connectors. // // 0, 1 or 2 CTP cables can be connected to a given CMX card. // // - A Crate CMX with only Base CMX functionality (i.e. no Topo Functionality) // does not send any data to the CTP // - A System CMX in a CPM crate sends information to the CTP over one cable // - A System CMX in a JEM crate sends information to the CTP over two cables // // For reference: A Crate CMX with TP functionality would send information // to the CTP over 1 or 2 cables. Those signals would come // from the TP FPGA, not the BF FPGA. Two separate sets // of voltage translators provides the multiplexing. // // The control signals used to enable and control the direction of the voltage // translators and LVDS transceivers are managed by the Board Support FPGA and // submitted to a final sanity check by going through the hardware oversight logic. // The Base Function FPGA thus sends two signals to the Board Support FPGA // to "request" the direction of each of each CTP Cable cf. BF_REQ_CTP_n_INPUT below. // // 'BF_DOUT_CTP_xx' are the CTP output signals from the Base FPGA with xx=00 to 65. // Each CTP output cable carries 33 LVDS signals consisting of 31 data bits, one clock // and one parity bit. // // xx=0 to 30 carry data bits on cable #1 // xx=31 carry the clock on cable #1 // xx=64 carry the parity on cable #1 // // xx=32 to 62 carry data bits on cable #2 // xx=63 carry the clock on cable #2 // xx=65 carry the parity on cable #2 // // Note that regional clock signals are assigned to CTP output signals # 31 and 63 // for flexibility, so that the CTP output cables could be used as inputs. // // These signals are single-ended un-terminated 2.5V CMOS level ouput (or input) signals. // // IO_L8P_SRCC_12 NET "BF_DOUT_CTP_00" LOC = "AW37"; // IO_L5N_13 NET "BF_DOUT_CTP_01" LOC = "AU42"; // IO_L6N_12 NET "BF_DOUT_CTP_02" LOC = "AT36"; // IO_L2N_12 NET "BF_DOUT_CTP_03" LOC = "AR37"; // IO_L17N_12 NET "BF_DOUT_CTP_04" LOC = "AY35"; // IO_L10P_MRCC_12 NET "BF_DOUT_CTP_05" LOC = "AP36"; // IO_L7N_12 NET "BF_DOUT_CTP_06" LOC = "BB38"; // IO_L1N_12 NET "BF_DOUT_CTP_07" LOC = "AV38"; // IO_L4P_12 NET "BF_DOUT_CTP_08" LOC = "AU37"; // IO_L0P_12 NET "BF_DOUT_CTP_09" LOC = "AT37"; // IO_L13N_12 NET "BF_DOUT_CTP_10" LOC = "BA36"; // IO_L8P_SRCC_13 NET "BF_DOUT_CTP_11" LOC = "AR40"; // IO_L8N_SRCC_12 NET "BF_DOUT_CTP_12" LOC = "AW38"; // IO_L19N_13 NET "BF_DOUT_CTP_13" LOC = "AW40"; // IO_L7P_13 NET "BF_DOUT_CTP_14" LOC = "AW42"; // IO_L4N_VREF_12 NET "BF_DOUT_CTP_15" LOC = "AU38"; // IO_L8N_SRCC_13 NET "BF_DOUT_CTP_16" LOC = "AT41"; // IO_L5N_12 NET "BF_DOUT_CTP_17" LOC = "AY37"; // IO_L7P_12 NET "BF_DOUT_CTP_18" LOC = "BB39"; // IO_L17N_13 NET "BF_DOUT_CTP_19" LOC = "AY40"; // IO_L13P_13 NET "BF_DOUT_CTP_20" LOC = "AY42"; // IO_L1P_12 NET "BF_DOUT_CTP_21" LOC = "AV39"; // IO_L11N_SRCC_13 NET "BF_DOUT_CTP_22" LOC = "AU41"; // IO_L5P_12 NET "BF_DOUT_CTP_23" LOC = "AY38"; // IO_L3P_12 NET "BF_DOUT_CTP_24" LOC = "AY39"; // IO_L15P_13 NET "BF_DOUT_CTP_25" LOC = "BA41"; // IO_L13N_13 NET "BF_DOUT_CTP_26" LOC = "BA42"; // IO_L7N_13 NET "BF_DOUT_CTP_27" LOC = "AW41"; // IO_L11P_SRCC_13 NET "BF_DOUT_CTP_28" LOC = "AV41"; // IO_L3N_12 NET "BF_DOUT_CTP_29" LOC = "BA39"; // IO_L17P_13 NET "BF_DOUT_CTP_30" LOC = "BA40"; // IO_L10P_MRCC_13 NET "BF_DOUT_CTP_31" LOC = "AT40"; // IO_L15N_13 NET "BF_DOUT_CTP_64" LOC = "BB41"; // IO_L12P_VRN_13 NET "BF_DOUT_CTP_32" LOC = "AN38"; // IO_L15P_12 NET "BF_DOUT_CTP_33" LOC = "BB34"; // IO_L0P_13 NET "BF_DOUT_CTP_34" LOC = "AN40"; // IO_L16P_12 NET "BF_DOUT_CTP_35" LOC = "AU34"; // IO_L3P_13 NET "BF_DOUT_CTP_36" LOC = "AP42"; // IO_L0N_13 NET "BF_DOUT_CTP_37" LOC = "AP40"; // IO_L1P_13 NET "BF_DOUT_CTP_38" LOC = "AN41"; // IO_L18P_12 NET "BF_DOUT_CTP_39" LOC = "AV34"; // IO_L18N_12 NET "BF_DOUT_CTP_40" LOC = "AV35"; // IO_L12N_VRP_12 NET "BF_DOUT_CTP_41" LOC = "AT35"; // IO_L2P_12 NET "BF_DOUT_CTP_42" LOC = "AP37"; // IO_L0N_12 NET "BF_DOUT_CTP_43" LOC = "AR38"; // IO_L1N_13 NET "BF_DOUT_CTP_44" LOC = "AP41"; // IO_L19N_12 NET "BF_DOUT_CTP_45" LOC = "AW35"; // IO_L14N_VREF_12 NET "BF_DOUT_CTP_46" LOC = "AV36"; // IO_L13P_12 NET "BF_DOUT_CTP_47" LOC = "BB36"; // IO_L3N_13 NET "BF_DOUT_CTP_48" LOC = "AR42"; // IO_L14N_VREF_13 NET "BF_DOUT_CTP_49" LOC = "AT39"; // IO_L14P_13 NET "BF_DOUT_CTP_50" LOC = "AR39"; // IO_L14P_12 NET "BF_DOUT_CTP_51" LOC = "AW36"; // IO_L17P_12 NET "BF_DOUT_CTP_52" LOC = "BA35"; // IO_L6P_12 NET "BF_DOUT_CTP_53" LOC = "AU36"; // IO_L12P_VRN_12 NET "BF_DOUT_CTP_54" LOC = "AR35"; // IO_L10N_MRCC_13 NET "BF_DOUT_CTP_55" LOC = "AU39"; // IO_L2P_13 NET "BF_DOUT_CTP_56" LOC = "AN39"; // IO_L11P_SRCC_12 NET "BF_DOUT_CTP_57" LOC = "BA37"; // IO_L15N_12 NET "BF_DOUT_CTP_58" LOC = "BA34"; // IO_L11N_SRCC_12 NET "BF_DOUT_CTP_59" LOC = "BB37"; // IO_L5P_13 NET "BF_DOUT_CTP_60" LOC = "AT42"; // IO_L19P_13 NET "BF_DOUT_CTP_61" LOC = "AV40"; // IO_L12N_VRP_13 NET "BF_DOUT_CTP_62" LOC = "AP38"; // IO_L9P_MRCC_12 NET "BF_DOUT_CTP_63" LOC = "AN35"; // IO_L19P_12 NET "BF_DOUT_CTP_65" LOC = "AY34"; /////////////////////////////////////////////////////////////////////////////// // // GTX outputs to MiniPOD Transmitters // // // MPx_Fyy_QUAD_zzz_TRN_w_DIR = Direct signal // MPx_Fyy_QUAD_zzz_TRN_w_CMP = Complement signal // for GTX receiver number w (w=0:3) // from GTX quad number zzz (zzz=110:118) // corresponding to fiber number yy (yy=00:11) // from MiniPOD device number x (x=1:2) // // These signals are differential output signals, cf. GTX and MiniPOD docs. // /////////////////////////////////////////////////////////////////////////////// // // Transmitter 1 is MiniPOD device MP1 // // Note: To facilitate routing there is a criss-cross in the // Direct and Complement signals to the following // channels in Transmitter MiniPOD #1, i.e. MP1: // // F00, F01, F02, F03, F04, F05, F06, F07, F08, F09, F10, F11 // MGTTXP3_112 NET "MP1_F00_QUAD_112_TRN_3_DIR" LOC = "AL1"; // MGTTXN3_112 NET "MP1_F00_QUAD_112_TRN_3_CMP" LOC = "AL2"; // MGTTXP0_110 NET "MP1_F01_QUAD_110_TRN_0_DIR" LOC = "BB3"; // MGTTXN0_110 NET "MP1_F01_QUAD_110_TRN_0_CMP" LOC = "BB4"; // MGTTXP2_112 NET "MP1_F02_QUAD_112_TRN_2_DIR" LOC = "AM3"; // MGTTXN2_112 NET "MP1_F02_QUAD_112_TRN_2_CMP" LOC = "AM4"; // MGTTXP1_110 NET "MP1_F03_QUAD_110_TRN_1_DIR" LOC = "BA1"; // MGTTXN1_110 NET "MP1_F03_QUAD_110_TRN_1_CMP" LOC = "BA2"; // MGTTXP0_112 NET "MP1_F04_QUAD_112_TRN_0_DIR" LOC = "AP3"; // MGTTXN0_112 NET "MP1_F04_QUAD_112_TRN_0_CMP" LOC = "AP4"; // MGTTXP3_110 NET "MP1_F05_QUAD_110_TRN_3_DIR" LOC = "AW1"; // MGTTXN3_110 NET "MP1_F05_QUAD_110_TRN_3_CMP" LOC = "AW2"; // MGTTXP1_112 NET "MP1_F06_QUAD_112_TRN_1_DIR" LOC = "AN1"; // MGTTXN1_112 NET "MP1_F06_QUAD_112_TRN_1_CMP" LOC = "AN2"; // MGTTXP2_110 NET "MP1_F07_QUAD_110_TRN_2_DIR" LOC = "AY3"; // MGTTXN2_110 NET "MP1_F07_QUAD_110_TRN_2_CMP" LOC = "AY4"; // MGTTXP3_111 NET "MP1_F08_QUAD_111_TRN_3_DIR" LOC = "AR1"; // MGTTXN3_111 NET "MP1_F08_QUAD_111_TRN_3_CMP" LOC = "AR2"; // MGTTXP0_111 NET "MP1_F09_QUAD_111_TRN_0_DIR" LOC = "AV3"; // MGTTXN0_111 NET "MP1_F09_QUAD_111_TRN_0_CMP" LOC = "AV4"; // MGTTXP2_111 NET "MP1_F10_QUAD_111_TRN_2_DIR" LOC = "AT3"; // MGTTXN2_111 NET "MP1_F10_QUAD_111_TRN_2_CMP" LOC = "AT4"; // MGTTXP1_111 NET "MP1_F11_QUAD_111_TRN_1_DIR" LOC = "AU1"; // MGTTXN1_111 NET "MP1_F11_QUAD_111_TRN_1_CMP" LOC = "AU2"; // // Transmitter 2 is MiniPOD device MP2 // // Note: To facilitate routing there is a criss-cross in the // Direct and Complement signals to the following // channels in Transmitter MiniPOD #2, i.e. MP2: // // F00, F01, F02, F03, F04, F05, F06, F07, F10, F11 // // MGTTXP3_115 NET "MP2_F00_QUAD_115_TRN_3_DIR" LOC = "P3"; // MGTTXN3_115 NET "MP2_F00_QUAD_115_TRN_3_CMP" LOC = "P4"; // MGTTXP0_113 NET "MP2_F01_QUAD_113_TRN_0_DIR" LOC = "AK3"; // MGTTXN0_113 NET "MP2_F01_QUAD_113_TRN_0_CMP" LOC = "AK4"; // MGTTXP2_115 NET "MP2_F02_QUAD_115_TRN_2_DIR" LOC = "R1"; // MGTTXN2_115 NET "MP2_F02_QUAD_115_TRN_2_CMP" LOC = "R2"; // MGTTXP1_113 NET "MP2_F03_QUAD_113_TRN_1_DIR" LOC = "AJ1"; // MGTTXN1_113 NET "MP2_F03_QUAD_113_TRN_1_CMP" LOC = "AJ2"; // MGTTXP0_115 NET "MP2_F04_QUAD_115_TRN_0_DIR" LOC = "U1"; // MGTTXN0_115 NET "MP2_F04_QUAD_115_TRN_0_CMP" LOC = "U2"; // MGTTXP3_113 NET "MP2_F05_QUAD_113_TRN_3_DIR" LOC = "AG1"; // MGTTXN3_113 NET "MP2_F05_QUAD_113_TRN_3_CMP" LOC = "AG2"; // MGTTXP1_115 NET "MP2_F06_QUAD_115_TRN_1_DIR" LOC = "T3"; // MGTTXN1_115 NET "MP2_F06_QUAD_115_TRN_1_CMP" LOC = "T4"; // MGTTXP2_113 NET "MP2_F07_QUAD_113_TRN_2_DIR" LOC = "AH3"; // MGTTXN2_113 NET "MP2_F07_QUAD_113_TRN_2_CMP" LOC = "AH4"; // MGTTXP3_114 NET "MP2_F08_QUAD_114_TRN_3_DIR" LOC = "W1"; // MGTTXN3_114 NET "MP2_F08_QUAD_114_TRN_3_CMP" LOC = "W2"; // MGTTXP0_114 NET "MP2_F09_QUAD_114_TRN_0_DIR" LOC = "AE1"; // MGTTXN0_114 NET "MP2_F09_QUAD_114_TRN_0_CMP" LOC = "AE2"; // MGTTXP2_114 NET "MP2_F10_QUAD_114_TRN_2_DIR" LOC = "AA1"; // MGTTXN2_114 NET "MP2_F10_QUAD_114_TRN_2_CMP" LOC = "AA2"; // MGTTXP1_114 NET "MP2_F11_QUAD_114_TRN_1_DIR" LOC = "AC1"; // MGTTXN1_114 NET "MP2_F11_QUAD_114_TRN_1_CMP" LOC = "AC2"; /////////////////////////////////////////////////////////////////////////////// // // GTX Termination Calibration Resistor // /////////////////////////////////////////////////////////////////////////////// // // This is a precision 100 Ohm resistor. // See Chapter 5 page 274 of the // Virtex-6 GTX User Guide. // // // These are probably not needed in this UCF // // // MGTRREF_115 // NET "BF_MGTRREF" LOC = "B11"; // // // MGTAVTTRCAL_115 // NET "BF_GTX_AVTT" LOC = "A12"; /////////////////////////////////////////////////////////////////////////////// // // DAQ and ROI Data Outputs to SFP Optical Transmitters // /////////////////////////////////////////////////////////////////////////////// // // SFP1 Base Function DAQ SFP Optical Output // SFP2 Base Function RIO SFP Optical Output // // These signals are differential output signals, cf. GTX and SFP docs. // // MGTTXP3_118 NET "BF_DAQ_DATA_OUT_DIR" LOC = "B3"; // MGTTXN3_118 NET "BF_DAQ_DATA_OUT_CMP" LOC = "B4"; // MGTTXP2_118 NET "BF_ROI_DATA_OUT_DIR" LOC = "C1"; // MGTTXN2_118 NET "BF_ROI_DATA_OUT_CMP" LOC = "C2"; /////////////////////////////////////////////////////////////////////////////// // // Optional S-Link Control Signal // /////////////////////////////////////////////////////////////////////////////// // // These are inputs from Optical receivers from SFP1:SFP4 // Reminder: the BF FPGA needs to receieve the S-link control signal // associated with the TP DAQ/ROI SFP3:4 connections because // all of the TP FPGA GTX receivers are used for the 36x 6.4 Gb inputs. // // SFP1 Base Function DAQ SFP Optical Input // SFP2 Base Function RIO SFP Optical Input // SFP3 Topo Function DAQ SFP Optical Input // SFP4 Topo Function RIO SFP Optical Input // // NOTE: The receiver data pairs for SFP1 and SFP2 are flipped DIR<->CMP at the SFP device end // // These signals are differential input signals, cf. GTX and SFP docs. // // // MGTRXP3_117 NET "SFP1_RD_DIR" LOC = "E5"; // MGTRXN3_117 NET "SFP1_RD_CMP" LOC = "E6"; // MGTRXP2_117 NET "SFP2_RD_DIR" LOC = "F7"; // MGTRXN2_117 NET "SFP2_RD_CMP" LOC = "F8"; // MGTRXP1_117 NET "SFP3_RD_DIR" LOC = "G5"; // MGTRXN1_117 NET "SFP3_RD_CMP" LOC = "G6"; // MGTRXP0_117 NET "SFP4_RD_DIR" LOC = "H7"; // MGTRXN0_117 NET "SFP4_RD_CMP" LOC = "H8"; /////////////////////////////////////////////////////////////////////////////// // // Base Function System Monitor Auxiliary Analog Inputs // /////////////////////////////////////////////////////////////////////////////// // // Resistor Voltage Dividers are used to scale input // signals to the 0.0V to +1.0V range of the 12 // available Base-Function Auxiliary Analog Inputs // // We are using 12 of the Base Function System-Monitor // Auxiliary Analog Inputs to measure CMX Voltages and Currents. // // The 12 System Monitor Auxiliary Analog inputs reachable // for usage are: 01, 03, 04, 07, 08, 09, 10, 11, 12, 13, 14, 15 // and are used to monitor the following Voltages and Currents: // // BF_CORE Voltage and Current // GTX_AVTT Voltage and Current // GTX_AVCC Voltage and Current // TP_CORE Current // BULK_3V3 Voltage and Current // BULK_2V5 Voltage and Current // VREF_P Voltage // // Monitor BF_CORE Voltage // IO_L7P_SM4P_35 NET "BF_SYSMON_04_P" LOC = "C15"; // IO_L7N_SM4N_35 NET "BF_SYSMON_04_N" LOC = "D15"; // Monitor BF_CORE Current // IO_L6P_SM3P_35 NET "BF_SYSMON_03_P" LOC = "H13"; // IO_L6N_SM3N_35 NET "BF_SYSMON_03_N" LOC = "G12"; // Monitor GTX_AVTT Voltage // IO_L3P_SM1P_35 NET "BF_SYSMON_01_P" LOC = "D16"; // IO_L3N_SM1N_35 NET "BF_SYSMON_01_N" LOC = "C16"; // Monitor GTX_AVTT Current // IO_L15P_SM7P_35 NET "BF_SYSMON_07_P" LOC = "C13"; // IO_L15N_SM7N_35 NET "BF_SYSMON_07_N" LOC = "D12"; // Monitor GTX_AVCC Voltage // IO_L6N_SM11N_15 NET "BF_SYSMON_11_P" LOC = "AD38"; // IO_L6P_SM11P_15 NET "BF_SYSMON_11_N" LOC = "AE38"; // Monitor GTX_AVCC Current // IO_L2P_SM8P_15 NET "BF_SYSMON_08_P" LOC = "AE33"; // IO_L2N_SM8N_15 NET "BF_SYSMON_08_N" LOC = "AD33"; // Monitor TP_CORE Current // IO_L13P_SM14P_15 NET "BF_SYSMON_14_P" LOC = "AC40"; // IO_L13N_SM14N_15 NET "BF_SYSMON_14_N" LOC = "AD40"; // Monitor BULK_3V3 Voltage // IO_L7P_SM12P_15 NET "BF_SYSMON_12_P" LOC = "AA42"; // IO_L7N_SM12N_15 NET "BF_SYSMON_12_N" LOC = "AB42"; // Monitor BULK_3V3 Current // IO_L5P_SM10P_15 NET "BF_SYSMON_10_P" LOC = "AA41"; // IO_L5N_SM10N_15 NET "BF_SYSMON_10_N" LOC = "AB41"; // Monitor BULK_2V5 Voltage // IO_L3P_SM9P_15 NET "BF_SYSMON_09_P" LOC = "AB39"; // IO_L3N_SM9N_15 NET "BF_SYSMON_09_N" LOC = "AA40"; // Monitor BULK_2V5 Current // IO_L12P_SM13P_15 NET "BF_SYSMON_13_P" LOC = "AB32"; // IO_L12N_SM13N_15 NET "BF_SYSMON_13_N" LOC = "AB33"; // Monitor VREF_P Voltage // IO_L15P_SM15P_15 NET "BF_SYSMON_15_P" LOC = "AD42"; // IO_L15N_SM15N_15 NET "BF_SYSMON_15_N" LOC = "AE42"; /////////////////////////////////////////////////////////////////////////////// // // CMX On-Card Bus // /////////////////////////////////////////////////////////////////////////////// // // 'OCB_Axx' are the On-Card Bus Address lines with xx=01 to 23 // (note there is no "A00" signal) // // 'OCB_Dyy' are the On-Card Bus Data lines with yy=00 to 15 // // 'OCB_GEO_ADRS_z' are the On-Card Bus Geographic Section Address lines with z=0 to 6 // // // 'OCB_SYS_RESET_B' is the On-Card Bus VME SYS_RESET signal // The "_B" postfix is used to indicate that the reset request is active // when the electrical signal is low // // 'OCB_DS_B' is the On-Card Bus Data strobe. // The "_B" postfix is used to indicate that the data strobe signal is on the // falling edge of the electrical signal. // // 'OCB_WRITE_B' is the On-Card Bus Data Direction // The "_B" postfix is used to indicate that the Write direction is // requested when the electrical signal is low. // // These are un-terminated single ended 2.5V CMOS level input (or output) signals. // // IO_L15N_14 NET "OCB_A01" LOC = "AM41"; // IO_L13N_14 NET "OCB_A02" LOC = "AM42"; // IO_L15P_14 NET "OCB_A03" LOC = "AL41"; // IO_L13P_14 NET "OCB_A04" LOC = "AL42"; // IO_L17P_14 NET "OCB_A05" LOC = "AK40"; // IO_L7N_14 NET "OCB_A06" LOC = "AK42"; // IO_L5N_14 NET "OCB_A07" LOC = "AJ41"; // IO_L7P_14 NET "OCB_A08" LOC = "AJ42"; // IO_L5P_14 NET "OCB_A09" LOC = "AH40"; // IO_L3N_14 NET "OCB_A10" LOC = "AH41"; // IO_L3P_14 NET "OCB_A11" LOC = "AG42"; // IO_L4P_14 NET "OCB_A12" LOC = "AG38"; // IO_L12P_VRN_14 NET "OCB_A13" LOC = "AJ36"; // IO_L14N_VREF_14 NET "OCB_A14" LOC = "AH36"; // IO_L0P_14 NET "OCB_A15" LOC = "AG34"; // IO_L16P_14 NET "OCB_A16" LOC = "AF35"; // IO_L17N_14 NET "OCB_A17" LOC = "AL40"; // IO_L8P_SRCC_14 NET "OCB_A18" LOC = "AK38"; // IO_L11N_SRCC_14 NET "OCB_A19" LOC = "AJ40"; // IO_L11P_SRCC_14 NET "OCB_A20" LOC = "AH39"; // IO_L6P_13 NET "OCB_A21" LOC = "AM34"; // IO_L18N_13 NET "OCB_A22" LOC = "AL36"; // IO_L9N_MRCC_13 NET "OCB_A23" LOC = "AK34"; // IO_L0N_14 NET "OCB_D00" LOC = "AF34"; // IO_L18N_14 NET "OCB_D01" LOC = "AG33"; // IO_L12N_VRP_14 NET "OCB_D02" LOC = "AH35"; // IO_L9N_MRCC_14 NET "OCB_D03" LOC = "AJ35"; // IO_L16N_14 NET "OCB_D04" LOC = "AF36"; // IO_L14P_14 NET "OCB_D05" LOC = "AG36"; // IO_L4N_VREF_14 NET "OCB_D06" LOC = "AH38"; // IO_L8N_SRCC_14 NET "OCB_D07" LOC = "AJ38"; // IO_L10N_MRCC_14 NET "OCB_D08" LOC = "AK37"; // IO_L19N_14 NET "OCB_D09" LOC = "AL39"; // IO_L2P_14 NET "OCB_D10" LOC = "AF39"; // IO_L6P_14 NET "OCB_D11" LOC = "AF37"; // IO_L6N_14 NET "OCB_D12" LOC = "AG37"; // IO_L1P_14 NET "OCB_D13" LOC = "AF40"; // IO_L1N_14 NET "OCB_D14" LOC = "AG41"; // IO_L2N_14 NET "OCB_D15" LOC = "AG39"; // IO_L16P_13 NET "OCB_GEO_ADRS_0" LOC = "AM37"; // IO_L16N_13 NET "OCB_GEO_ADRS_1" LOC = "AM36"; // IO_L4P_13 NET "OCB_GEO_ADRS_2" LOC = "AL37"; // IO_L18P_13 NET "OCB_GEO_ADRS_3" LOC = "AK35"; // IO_L4N_VREF_13 NET "OCB_GEO_ADRS_4" LOC = "AM38"; // IO_L6N_13 NET "OCB_GEO_ADRS_5" LOC = "AL35"; // IO_L2N_13 NET "OCB_GEO_ADRS_6" LOC = "AM39"; // IO_L19P_14 NET "OCB_SYS_RESET_B" LOC = "AK39"; // IO_L10P_MRCC_14 NET "OCB_WRITE_B" LOC = "AJ37"; // IO_L9P_MRCC_14 NET "OCB_DS_B" LOC = "AH34"; /////////////////////////////////////////////////////////////////////////////// // // Logic Clocks: LHC Locked // /////////////////////////////////////////////////////////////////////////////// // // These are LHC locked LVDS clock signals to the Logic in the Base Function FPGA. // // A Global Clock input in I/O Bank 34 receives the DeSkew #1 40.08 MHz Logic clock. // // A Global Clock input in I/O Bank 25 receives the DeSkew #2 40.08 MHz Logic clock. // // A Global Clock input in I/O Bank 34 receives the 320.64 MHz Logic clock. // // These are LVDS input signals and the BF FPGA needs to provide the 100 Ohm termination. // // IO_L0P_GC_34 NET "CLK_40MHz08_DSKW_1_BF_LOGIC_DIR" LOC = "AY14"; // IO_L0N_GC_34 NET "CLK_40MHz08_DSKW_1_BF_LOGIC_CMP" LOC = "AY13"; // IO_L18P_GC_25 NET "CLK_40MHz08_DSKW_2_BF_LOGIC_DIR" LOC = "J42"; // IO_L18N_GC_25 NET "CLK_40MHz08_DSKW_2_BF_LOGIC_CMP" LOC = "K42"; // IO_L1N_GC_34 NET "CLK_320MHz64_LHC_BF_LOGIC_DIR" LOC = "AP12"; // IO_L1P_GC_34 NET "CLK_320MHz64_LHC_BF_LOGIC_CMP" LOC = "AP11"; /////////////////////////////////////////////////////////////////////////////// // // GTX Clock: CMX on-board Crystal Oscillator #1 // /////////////////////////////////////////////////////////////////////////////// // // 40.000 MHz Crystal Oscillator #1 // LVPECL clock to the clock "0" input of the GTX Transceiver Quad 118. // // This is the "G-Link" transciever for DAQ and RIO readout. // A crystal frequency other than 40MHz may be substituted // if necessary. // // These are differential LVPECL input signals, cf. GTX doc // // MGTREFCLK0P_118 NET "CLK_40MHz000_XTAL_1_BF_TRNCV_DIR" LOC = "C10"; // MGTREFCLK0N_118 NET "CLK_40MHz000_XTAL_1_BF_TRNCV_CMP" LOC = "C9"; /////////////////////////////////////////////////////////////////////////////// // // GTX Clock: CMX on-board Crystal Oscillator #2 // /////////////////////////////////////////////////////////////////////////////// // // 40.000 MHz or 100.000 Mhz Crystal Oscillator #2 // LVPECL clock to the clock "0" input of the GTX Transceiver Quad 117. // // This is the clock to the GTX Transcievers that receive // data from the 4 SFP optical components and thus may be // used to receive S-Link control information. // // These are differential LVPECL input signals, cf. GTX doc // // MGTREFCLK0P_117 NET "CLK_100MHz000_XTAL_2_BF_TRNCV_DIR" LOC = "G10"; // MGTREFCLK0N_117 NET "CLK_100MHz000_XTAL_2_BF_TRNCV_CMP" LOC = "G9"; /////////////////////////////////////////////////////////////////////////////// // // GTX Clocks: LHC Locked // /////////////////////////////////////////////////////////////////////////////// // // Individual copies of the 320.64 MHz LHC locked // LVPECL clocks to the clock "0" inputs for GTX Transceivers 111 and 114 // // These are the Base Function GTX Transceivers that // send out 6.4 Gbps data to the L1Topo system. // // These are differential LVPECL input signals, cf. GTX doc // // MGTREFCLK0P_111 NET "CLK_320MHz64_LHC_BF_QUAD_111_DIR" LOC = "AU10"; // MGTREFCLK0N_111 NET "CLK_320MHz64_LHC_BF_QUAD_111_CMP" LOC = "AU9"; // MGTREFCLK0P_114 NET "CLK_320MHz64_LHC_BF_QUAD_114_DIR" LOC = "AB8"; // MGTREFCLK0N_114 NET "CLK_320MHz64_LHC_BF_QUAD_114_CMP" LOC = "AB7"; /////////////////////////////////////////////////////////////////////////////// // // TTC signals // /////////////////////////////////////////////////////////////////////////////// // // These signals are buffered copies of the signals available at the TTCDec mezzanine // and are series terminated at the source. // // BUF_TTC_L1_ACCEPT L1 Accept signal // // BUF_TTC_BNCH_CNT_RES Bunch Count Reset signal // // These signals are single-ended 2.5V CMOS level input signals 47 Ohm series terminated at the TTCdec end. // // IO_L6P_25 NET "BUF_TTC_L1_ACCEPT" LOC = "H39"; // IO_L16N_VRP_25 NET "BUF_TTC_BNCH_CNT_RES" LOC = "K40"; /////////////////////////////////////////////////////////////////////////////// // // BF to TP connections for support of S-link return channels // /////////////////////////////////////////////////////////////////////////////// // // If the TP function needs to act as its own ROD and support S-link protocol // (rather than G-link if it is sending data to an external ROD) the CMX // will need to receive and handle the return channel of the Duplex S-link. // // The SFP optical receiver #3 and #4 from the 2x S-link connections (DAQ and ROI) // used to readout the Topological FPGA information cannot be received directly // on the TP FPGA because all 36x MGT receivers of the TP FPGA are already // used with the 3x12 Avago optical receivers. // // The SFP #3 and #4 optical receivers are instead routed to MGT receivers // located on the BF FPGA and the corresponding serial signal must be forwared // from the BF FPGA to the TP FPGA via two differential Select IO signals. // // BF_TO_TP_DAQ_SLINK_RETURN_DIR Direct signal // BF_TO_TP_DAQ_SLINK_RETURN_CMP Complement signal // for the return S-link channel for DAQ readout // // BF_TO_TP_ROI_SLINK_RETURN_DIR Direct signal // BF_TO_TP_ROI_SLINK_RETURN_CMP Complement signal // for the return S-link channel for ROI readout // // These signals are nominally defined as differential outputs by the BF // and differential inputs by the TP FPGAs but future requirements may change. // No termination is provided on the card. // // IO_L12P_25 NET "BF_TO_TP_DAQ_SLINK_RETURN_DIR" LOC = "H40"; // IO_L12N_25 NET "BF_TO_TP_DAQ_SLINK_RETURN_CMP" LOC = "H41"; // IO_L14P_25 NET "BF_TO_TP_ROI_SLINK_RETURN_DIR" LOC = "J40"; // IO_L14N_VREF_25 NET "BF_TO_TP_ROI_SLINK_RETURN_CMP" LOC = "J41"; /////////////////////////////////////////////////////////////////////////////// // // Base Function FPGA IO private connections to the Board Support FPGA // /////////////////////////////////////////////////////////////////////////////// // // BF_REQ_CTP_n_INPUT (n=1:2) 2x direction request signals // sent to the BSPT FPGA for control of CTP cable n // // BF_REQ_CABLE_n_INPUT (n=1:3) 3x direction request signals // sent to the BSPT FPGA for control of Merger Cable n // // BF_LED_REQ_n (n=0:4) 5x LED state request signals // sent to BSPT FPGA, with usage determined by the BSPT // // BF_TO_FROM_BSPT_n (n=0:7) 8x un-assigned Input or Ouput connections to BSPT FPGA // // These signals are nominally defined as outputs by the BF and inputs to the BSPT FPGAs // but future requirements may change. No termination is provided on the card. // // IO_L9N_MRCC_38 NET "BF_REQ_CTP_1_INPUT" LOC = "N19"; // IO_L19N_38 NET "BF_REQ_CTP_2_INPUT" LOC = "N20"; // IO_L18P_38 NET "BF_REQ_CABLE_1_INPUT" LOC = "P21"; // IO_L18N_38 NET "BF_REQ_CABLE_2_INPUT" LOC = "P22"; // IO_L8N_SRCC_38 NET "BF_REQ_CABLE_3_INPUT" LOC = "K23"; // IO_L0N_38 NET "BF_LED_REQ_0" LOC = "G24"; // IO_L2P_38 NET "BF_LED_REQ_1" LOC = "F25"; // IO_L11N_SRCC_38 NET "BF_LED_REQ_2" LOC = "A25"; // IO_L15N_38 NET "BF_LED_REQ_3" LOC = "C25"; // IO_L2N_38 NET "BF_LED_REQ_4" LOC = "F24"; // IO_L11P_SRCC_38 NET "BF_TO_FROM_BSPT_0" LOC = "A26"; // IO_L15P_38 NET "BF_TO_FROM_BSPT_1" LOC = "B26"; // IO_L17P_38 NET "BF_TO_FROM_BSPT_2" LOC = "D25"; // IO_L7N_38 NET "BF_TO_FROM_BSPT_3" LOC = "A27"; // IO_L5N_38 NET "BF_TO_FROM_BSPT_4" LOC = "F26"; // IO_L17N_38 NET "BF_TO_FROM_BSPT_5" LOC = "E25"; // IO_L13N_38 NET "BF_TO_FROM_BSPT_6" LOC = "D26"; // IO_L1P_38 NET "BF_TO_FROM_BSPT_7" LOC = "E27"; /////////////////////////////////////////////////////////////////////////////// // // Base Function FPGA private Connections to the Debug Connector // /////////////////////////////////////////////////////////////////////////////// // // BF_DEBUG_n (n=0:9) 10x spare Input or Ouput connections // between TP FPGA to debug connector J14 // // These signals are defined as inputs or outputs by the BF FPGA. // No termination is provided on the card. // // IO_L7P_38 NET "BF_DEBUG_0" LOC = "B27"; // IO_L10N_MRCC_38 NET "BF_DEBUG_1" LOC = "M21"; // IO_L13P_38 NET "BF_DEBUG_2" LOC = "C26"; // IO_L10P_MRCC_38 NET "BF_DEBUG_3" LOC = "N21"; // IO_L1N_38 NET "BF_DEBUG_4" LOC = "D27"; // IO_L9P_MRCC_38 NET "BF_DEBUG_5" LOC = "M19"; // IO_L3P_38 NET "BF_DEBUG_6" LOC = "C28"; // IO_L14P_38 NET "BF_DEBUG_7" LOC = "M22"; // IO_L3N_38 NET "BF_DEBUG_8" LOC = "B28"; // IO_L8P_SRCC_38 NET "BF_DEBUG_9" LOC = "J23"; /////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////// // // The following list assigns a unique net-name to // ALL UNUSED Select IO and GTX IO pins left on the BF FPGA. // /////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////// // MGTRXP0_110 NET "No_Conn_BF_MGTRXP0_110" LOC = "BB7"; // MGTRXN0_110 NET "No_Conn_BF_MGTRXN0_110" LOC = "BB8"; // MGTRXP1_110 NET "No_Conn_BF_MGTRXP1_110" LOC = "BA5"; // MGTRXN1_110 NET "No_Conn_BF_MGTRXN1_110" LOC = "BA6"; // MGTRXP2_110 NET "No_Conn_BF_MGTRXP2_110" LOC = "AY7"; // MGTRXN2_110 NET "No_Conn_BF_MGTRXN2_110" LOC = "AY8"; // MGTRXP3_110 NET "No_Conn_BF_MGTRXP3_110" LOC = "AW5"; // MGTRXN3_110 NET "No_Conn_BF_MGTRXN3_110" LOC = "AW6"; // MGTRXP0_111 NET "No_Conn_BF_MGTRXP0_111" LOC = "AV7"; // MGTRXN0_111 NET "No_Conn_BF_MGTRXN0_111" LOC = "AV8"; // MGTRXP1_111 NET "No_Conn_BF_MGTRXP1_111" LOC = "AU5"; // MGTRXN1_111 NET "No_Conn_BF_MGTRXN1_111" LOC = "AU6"; // MGTRXP2_111 NET "No_Conn_BF_MGTRXP2_111" LOC = "AR5"; // MGTRXN2_111 NET "No_Conn_BF_MGTRXN2_111" LOC = "AR6"; // MGTRXP3_111 NET "No_Conn_BF_MGTRXP3_111" LOC = "AP7"; // MGTRXN3_111 NET "No_Conn_BF_MGTRXN3_111" LOC = "AP8"; // MGTRXP0_112 NET "No_Conn_BF_MGTRXP0_112" LOC = "AN5"; // MGTRXN0_112 NET "No_Conn_BF_MGTRXN0_112" LOC = "AN6"; // MGTRXP1_112 NET "No_Conn_BF_MGTRXP1_112" LOC = "AM7"; // MGTRXN1_112 NET "No_Conn_BF_MGTRXN1_112" LOC = "AM8"; // MGTRXP2_112 NET "No_Conn_BF_MGTRXP2_112" LOC = "AL5"; // MGTRXN2_112 NET "No_Conn_BF_MGTRXN2_112" LOC = "AL6"; // MGTRXP3_112 NET "No_Conn_BF_MGTRXP3_112" LOC = "AJ5"; // MGTRXN3_112 NET "No_Conn_BF_MGTRXN3_112" LOC = "AJ6"; // MGTRXP0_113 NET "No_Conn_BF_MGTRXP0_113" LOC = "AG5"; // MGTRXN0_113 NET "No_Conn_BF_MGTRXN0_113" LOC = "AG6"; // MGTRXP1_113 NET "No_Conn_BF_MGTRXP1_113" LOC = "AF3"; // MGTRXN1_113 NET "No_Conn_BF_MGTRXN1_113" LOC = "AF4"; // MGTRXP2_113 NET "No_Conn_BF_MGTRXP2_113" LOC = "AE5"; // MGTRXN2_113 NET "No_Conn_BF_MGTRXN2_113" LOC = "AE6"; // MGTRXP3_113 NET "No_Conn_BF_MGTRXP3_113" LOC = "AD3"; // MGTRXN3_113 NET "No_Conn_BF_MGTRXN3_113" LOC = "AD4"; // MGTRXP0_114 NET "No_Conn_BF_MGTRXP0_114" LOC = "AC5"; // MGTRXN0_114 NET "No_Conn_BF_MGTRXN0_114" LOC = "AC6"; // MGTRXP1_114 NET "No_Conn_BF_MGTRXP1_114" LOC = "AB3"; // MGTRXN1_114 NET "No_Conn_BF_MGTRXN1_114" LOC = "AB4"; // MGTRXP2_114 NET "No_Conn_BF_MGTRXP2_114" LOC = "AA5"; // MGTRXN2_114 NET "No_Conn_BF_MGTRXN2_114" LOC = "AA6"; // MGTRXP3_114 NET "No_Conn_BF_MGTRXP3_114" LOC = "Y3"; // MGTRXN3_114 NET "No_Conn_BF_MGTRXN3_114" LOC = "Y4"; // MGTRXP0_115 NET "No_Conn_BF_MGTRXP0_115" LOC = "W5"; // MGTRXN0_115 NET "No_Conn_BF_MGTRXN0_115" LOC = "W6"; // MGTRXP1_115 NET "No_Conn_BF_MGTRXP1_115" LOC = "V3"; // MGTRXN1_115 NET "No_Conn_BF_MGTRXN1_115" LOC = "V4"; // MGTRXP2_115 NET "No_Conn_BF_MGTRXP2_115" LOC = "U5"; // MGTRXN2_115 NET "No_Conn_BF_MGTRXN2_115" LOC = "U6"; // MGTRXP3_115 NET "No_Conn_BF_MGTRXP3_115" LOC = "R5"; // MGTRXN3_115 NET "No_Conn_BF_MGTRXN3_115" LOC = "R6"; // MGTRXP0_116 NET "No_Conn_BF_MGTRXP0_116" LOC = "P7"; // MGTRXN0_116 NET "No_Conn_BF_MGTRXN0_116" LOC = "P8"; // MGTRXP1_116 NET "No_Conn_BF_MGTRXP1_116" LOC = "N5"; // MGTRXN1_116 NET "No_Conn_BF_MGTRXN1_116" LOC = "N6"; // MGTRXP2_116 NET "No_Conn_BF_MGTRXP2_116" LOC = "L5"; // MGTRXN2_116 NET "No_Conn_BF_MGTRXN2_116" LOC = "L6"; // MGTRXP3_116 NET "No_Conn_BF_MGTRXP3_116" LOC = "J5"; // MGTRXN3_116 NET "No_Conn_BF_MGTRXN3_116" LOC = "J6"; // MGTRXP0_118 NET "No_Conn_BF_MGTRXP0_118" LOC = "D7"; // MGTRXN0_118 NET "No_Conn_BF_MGTRXN0_118" LOC = "D8"; // MGTRXP1_118 NET "No_Conn_BF_MGTRXP1_118" LOC = "C5"; // MGTRXN1_118 NET "No_Conn_BF_MGTRXN1_118" LOC = "C6"; // MGTRXP2_118 NET "No_Conn_BF_MGTRXP2_118" LOC = "B7"; // MGTRXN2_118 NET "No_Conn_BF_MGTRXN2_118" LOC = "B8"; // MGTRXP3_118 NET "No_Conn_BF_MGTRXP3_118" LOC = "A5"; // MGTRXN3_118 NET "No_Conn_BF_MGTRXN3_118" LOC = "A6"; // MGTTXP0_116 NET "No_Conn_BF_MGTTXP0_116" LOC = "N1"; // MGTTXN0_116 NET "No_Conn_BF_MGTTXN0_116" LOC = "N2"; // MGTTXP1_116 NET "No_Conn_BF_MGTTXP1_116" LOC = "M3"; // MGTTXN1_116 NET "No_Conn_BF_MGTTXN1_116" LOC = "M4"; // MGTTXP2_116 NET "No_Conn_BF_MGTTXP2_116" LOC = "L1"; // MGTTXN2_116 NET "No_Conn_BF_MGTTXN2_116" LOC = "L2"; // MGTTXP3_116 NET "No_Conn_BF_MGTTXP3_116" LOC = "K3"; // MGTTXN3_116 NET "No_Conn_BF_MGTTXN3_116" LOC = "K4"; // MGTTXP0_117 NET "No_Conn_BF_MGTTXP0_117" LOC = "J1"; // MGTTXN0_117 NET "No_Conn_BF_MGTTXN0_117" LOC = "J2"; // MGTTXP1_117 NET "No_Conn_BF_MGTTXP1_117" LOC = "H3"; // MGTTXN1_117 NET "No_Conn_BF_MGTTXN1_117" LOC = "H4"; // MGTTXP2_117 NET "No_Conn_BF_MGTTXP2_117" LOC = "G1"; // MGTTXN2_117 NET "No_Conn_BF_MGTTXN2_117" LOC = "G2"; // MGTTXP3_117 NET "No_Conn_BF_MGTTXP3_117" LOC = "F3"; // MGTTXN3_117 NET "No_Conn_BF_MGTTXN3_117" LOC = "F4"; // MGTTXP0_118 NET "No_Conn_BF_MGTTXP0_118" LOC = "E1"; // MGTTXN0_118 NET "No_Conn_BF_MGTTXN0_118" LOC = "E2"; // MGTTXP1_118 NET "No_Conn_BF_MGTTXP1_118" LOC = "D3"; // MGTTXN1_118 NET "No_Conn_BF_MGTTXN1_118" LOC = "D4"; // IO_L9N_MRCC_12 NET "No_Conn_BF_IO_L9N_MRCC_12" LOC = "AN36"; // IO_L10N_MRCC_12 NET "No_Conn_BF_IO_L10N_MRCC_12" LOC = "AP35"; // IO_L16N_12 NET "No_Conn_BF_IO_L16N_12" LOC = "AT34"; // IO_L9P_MRCC_13 NET "No_Conn_BF_IO_L9P_MRCC_13" LOC = "AL34"; // IO_L18P_14 NET "No_Conn_BF_IO_L18P_14" LOC = "AF32"; // IO_L18N_15 NET "No_Conn_BF_IO_L18N_15" LOC = "AC33"; // IO_L18P_15 NET "No_Conn_BF_IO_L18P_15" LOC = "AC34"; // IO_L9P_MRCC_15 NET "No_Conn_BF_IO_L9P_MRCC_15" LOC = "AD32"; // IO_L14N_VREF_15 NET "No_Conn_BF_IO_L14N_VREF_15" LOC = "AD35"; // IO_L9N_MRCC_15 NET "No_Conn_BF_IO_L9N_MRCC_15" LOC = "AE32"; // IO_L0P_15 NET "No_Conn_BF_IO_L0P_15" LOC = "AE34"; // IO_L17N_15 NET "No_Conn_BF_IO_L17N_15" LOC = "AF41"; // IO_L16P_16 NET "No_Conn_BF_IO_L16P_16" LOC = "U32"; // IO_L16N_16 NET "No_Conn_BF_IO_L16N_16" LOC = "U33"; // IO_L10N_MRCC_16 NET "No_Conn_BF_IO_L10N_MRCC_16" LOC = "U34"; // IO_L18P_16 NET "No_Conn_BF_IO_L18P_16" LOC = "V33"; // IO_L10P_MRCC_16 NET "No_Conn_BF_IO_L10P_MRCC_16" LOC = "V34"; // IO_L18N_16 NET "No_Conn_BF_IO_L18N_16" LOC = "W33"; // IO_L12N_VRP_16 NET "No_Conn_BF_IO_L12N_VRP_16" LOC = "Y32"; // IO_L9N_MRCC_16 NET "No_Conn_BF_IO_L9N_MRCC_16" LOC = "Y33"; // IO_L4N_VREF_17 NET "No_Conn_BF_IO_L4N_VREF_17" LOC = "N34"; // IO_L4P_17 NET "No_Conn_BF_IO_L4P_17" LOC = "N35"; // IO_L9N_MRCC_17 NET "No_Conn_BF_IO_L9N_MRCC_17" LOC = "P35"; // IO_L14N_VREF_17 NET "No_Conn_BF_IO_L14N_VREF_17" LOC = "R34"; // IO_L18P_17 NET "No_Conn_BF_IO_L18P_17" LOC = "T34"; // IO_L5P_21 NET "No_Conn_BF_IO_L5P_21" LOC = "AJ23"; // IO_L13N_21 NET "No_Conn_BF_IO_L13N_21" LOC = "AL24"; // IO_L9N_MRCC_22 NET "No_Conn_BF_IO_L9N_MRCC_22" LOC = "AL26"; // IO_L14P_23 NET "No_Conn_BF_IO_L14P_23" LOC = "AG28"; // IO_L10P_MRCC_23 NET "No_Conn_BF_IO_L10P_MRCC_23" LOC = "AH24"; // IO_L10N_MRCC_23 NET "No_Conn_BF_IO_L10N_MRCC_23" LOC = "AH25"; // IO_L18N_23 NET "No_Conn_BF_IO_L18N_23" LOC = "AH26"; // IO_L18P_23 NET "No_Conn_BF_IO_L18P_23" LOC = "AJ26"; // IO_L16N_23 NET "No_Conn_BF_IO_L16N_23" LOC = "AJ27"; // IO_L9N_MRCC_23 NET "No_Conn_BF_IO_L9N_MRCC_23" LOC = "AK25"; // IO_L8P_SRCC_23 NET "No_Conn_BF_IO_L8P_SRCC_23" LOC = "AK28"; // IO_L1N_23 NET "No_Conn_BF_IO_L1N_23" LOC = "AL31"; // IO_L5P_D9_24 NET "No_Conn_BF_IO_L5P_D9_24" LOC = "N33"; // IO_L7P_D5_24 NET "No_Conn_BF_IO_L7P_D5_24" LOC = "P32"; // IO_L5N_D8_24 NET "No_Conn_BF_IO_L5N_D8_24" LOC = "P33"; // IO_L3N_D12_24 NET "No_Conn_BF_IO_L3N_D12_24" LOC = "R30"; // IO_L11P_SRCC_24 NET "No_Conn_BF_IO_L11P_SRCC_24" LOC = "R32"; // IO_L7N_D4_24 NET "No_Conn_BF_IO_L7N_D4_24" LOC = "R33"; // IO_L3P_D13_24 NET "No_Conn_BF_IO_L3P_D13_24" LOC = "T30"; // IO_L13P_D1_FS1_24 NET "No_Conn_BF_IO_L13P_D1_FS1_24" LOC = "T31"; // IO_L11N_SRCC_24 NET "No_Conn_BF_IO_L11N_SRCC_24" LOC = "T32"; // IO_L13N_D0_FS0_24 NET "No_Conn_BF_IO_L13N_D0_FS0_24" LOC = "U31"; // IO_L1N_GC_24 NET "No_Conn_BF_IO_L1N_GC_24" LOC = "V30"; // IO_L15P_FWE_B_24 NET "No_Conn_BF_IO_L15P_FWE_B_24" LOC = "V31"; // IO_L1P_GC_24 NET "No_Conn_BF_IO_L1P_GC_24" LOC = "W30"; // IO_L15N_RS1_24 NET "No_Conn_BF_IO_L15N_RS1_24" LOC = "W31"; // IO_L9P_MRCC_24 NET "No_Conn_BF_IO_L9P_MRCC_24" LOC = "Y30"; // IO_L9N_MRCC_24 NET "No_Conn_BF_IO_L9N_MRCC_24" LOC = "AA30"; // IO_L10P_MRCC_24 NET "No_Conn_BF_IO_L10P_MRCC_24" LOC = "AA31"; // IO_L10N_MRCC_24 NET "No_Conn_BF_IO_L10N_MRCC_24" LOC = "AB31"; // IO_L17N_VRP_24 NET "No_Conn_BF_IO_L17N_VRP_24" LOC = "AC30"; // IO_L17P_VRN_24 NET "No_Conn_BF_IO_L17P_VRN_24" LOC = "AC31"; // IO_L19N_24 NET "No_Conn_BF_IO_L19N_24" LOC = "AD30"; // IO_L19P_24 NET "No_Conn_BF_IO_L19P_24" LOC = "AD31"; // IO_L0P_GC_24 NET "No_Conn_BF_IO_L0P_GC_24" LOC = "AE30"; // IO_L0N_GC_24 NET "No_Conn_BF_IO_L0N_GC_24" LOC = "AF30"; // IO_L2N_D14_24 NET "No_Conn_BF_IO_L2N_D14_24" LOC = "AF31"; // IO_L18N_24 NET "No_Conn_BF_IO_L18N_24" LOC = "AG29"; // IO_L4N_VREF_D10_24 NET "No_Conn_BF_IO_L4N_VREF_D10_24" LOC = "AG31"; // IO_L2P_D15_24 NET "No_Conn_BF_IO_L2P_D15_24" LOC = "AG32"; // IO_L18P_24 NET "No_Conn_BF_IO_L18P_24" LOC = "AH29"; // IO_L14P_FCS_B_24 NET "No_Conn_BF_IO_L14P_FCS_B_24" LOC = "AH30"; // IO_L4P_D11_24 NET "No_Conn_BF_IO_L4P_D11_24" LOC = "AH31"; // IO_L6N_D6_24 NET "No_Conn_BF_IO_L6N_D6_24" LOC = "AH33"; // IO_L14N_VREF_FOE_B_MOSI_24 NET "No_Conn_BF_IO_L14N_VREF_FOE_B_MOSI_24" LOC = "AJ30"; // IO_L16P_RS0_24 NET "No_Conn_BF_IO_L16P_RS0_24" LOC = "AJ31"; // IO_L8N_SRCC_24 NET "No_Conn_BF_IO_L8N_SRCC_24" LOC = "AJ32"; // IO_L6P_D7_24 NET "No_Conn_BF_IO_L6P_D7_24" LOC = "AJ33"; // IO_L16N_CSO_B_24 NET "No_Conn_BF_IO_L16N_CSO_B_24" LOC = "AK30"; // IO_L12P_D3_24 NET "No_Conn_BF_IO_L12P_D3_24" LOC = "AK32"; // IO_L8P_SRCC_24 NET "No_Conn_BF_IO_L8P_SRCC_24" LOC = "AK33"; // IO_L12N_D2_FS2_24 NET "No_Conn_BF_IO_L12N_D2_FS2_24" LOC = "AL32"; // IO_L6N_25 NET "No_Conn_BF_IO_L6N_25" LOC = "H38"; // IO_L4N_VREF_25 NET "No_Conn_BF_IO_L4N_VREF_25" LOC = "J36"; // IO_L4P_25 NET "No_Conn_BF_IO_L4P_25" LOC = "J37"; // IO_L8N_SRCC_25 NET "No_Conn_BF_IO_L8N_SRCC_25" LOC = "J38"; // IO_L0N_25 NET "No_Conn_BF_IO_L0N_25" LOC = "K32"; // IO_L0P_25 NET "No_Conn_BF_IO_L0P_25" LOC = "K33"; // IO_L2N_25 NET "No_Conn_BF_IO_L2N_25" LOC = "K34"; // IO_L2P_25 NET "No_Conn_BF_IO_L2P_25" LOC = "K35"; // IO_L11P_SRCC_25 NET "No_Conn_BF_IO_L11P_SRCC_25" LOC = "K37"; // IO_L8P_SRCC_25 NET "No_Conn_BF_IO_L8P_SRCC_25" LOC = "K38"; // IO_L16P_VRN_25 NET "No_Conn_BF_IO_L16P_VRN_25" LOC = "K39"; // IO_L3P_25 NET "No_Conn_BF_IO_L3P_25" LOC = "L31"; // IO_L3N_25 NET "No_Conn_BF_IO_L3N_25" LOC = "L32"; // IO_L13P_25 NET "No_Conn_BF_IO_L13P_25" LOC = "L34"; // IO_L7P_25 NET "No_Conn_BF_IO_L7P_25" LOC = "L35"; // IO_L7N_25 NET "No_Conn_BF_IO_L7N_25" LOC = "L36"; // IO_L11N_SRCC_25 NET "No_Conn_BF_IO_L11N_SRCC_25" LOC = "L37"; // IO_L17P_25 NET "No_Conn_BF_IO_L17P_25" LOC = "M31"; // IO_L15N_25 NET "No_Conn_BF_IO_L15N_25" LOC = "M32"; // IO_L15P_25 NET "No_Conn_BF_IO_L15P_25" LOC = "M33"; // IO_L13N_25 NET "No_Conn_BF_IO_L13N_25" LOC = "M34"; // IO_L1P_25 NET "No_Conn_BF_IO_L1P_25" LOC = "N28"; // IO_L5P_25 NET "No_Conn_BF_IO_L5P_25" LOC = "N29"; // IO_L5N_25 NET "No_Conn_BF_IO_L5N_25" LOC = "N30"; // IO_L17N_25 NET "No_Conn_BF_IO_L17N_25" LOC = "N31"; // IO_L9P_MRCC_25 NET "No_Conn_BF_IO_L9P_MRCC_25" LOC = "P27"; // IO_L1N_25 NET "No_Conn_BF_IO_L1N_25" LOC = "P28"; // IO_L19P_GC_25 NET "No_Conn_BF_IO_L19P_GC_25" LOC = "P30"; // IO_L19N_GC_25 NET "No_Conn_BF_IO_L19N_GC_25" LOC = "P31"; // IO_L9N_MRCC_25 NET "No_Conn_BF_IO_L9N_MRCC_25" LOC = "R27"; // IO_L10P_MRCC_25 NET "No_Conn_BF_IO_L10P_MRCC_25" LOC = "R28"; // IO_L10N_MRCC_25 NET "No_Conn_BF_IO_L10N_MRCC_25" LOC = "R29"; // IO_L2P_26 NET "No_Conn_BF_IO_L2P_26" LOC = "J35"; // IO_L16N_27 NET "No_Conn_BF_IO_L16N_27" LOC = "J30"; // IO_L14P_27 NET "No_Conn_BF_IO_L14P_27" LOC = "J32"; // IO_L12N_VRP_27 NET "No_Conn_BF_IO_L12N_VRP_27" LOC = "J33"; // IO_L18N_27 NET "No_Conn_BF_IO_L18N_27" LOC = "K30"; // IO_L9N_MRCC_27 NET "No_Conn_BF_IO_L9N_MRCC_27" LOC = "L30"; // IO_L10P_MRCC_27 NET "No_Conn_BF_IO_L10P_MRCC_27" LOC = "M28"; // IO_L3N_28 NET "No_Conn_BF_IO_L3N_28" LOC = "F30"; // IO_L16P_28 NET "No_Conn_BF_IO_L16P_28" LOC = "J28"; // IO_L16N_28 NET "No_Conn_BF_IO_L16N_28" LOC = "K28"; // IO_L19N_28 NET "No_Conn_BF_IO_L19N_28" LOC = "M27"; // IO_L8P_SRCC_28 NET "No_Conn_BF_IO_L8P_SRCC_28" LOC = "R25"; // IO_L9N_MRCC_32 NET "No_Conn_BF_IO_L9N_MRCC_32" LOC = "AJ20"; // IO_L9P_MRCC_32 NET "No_Conn_BF_IO_L9P_MRCC_32" LOC = "AJ21"; // IO_L5P_32 NET "No_Conn_BF_IO_L5P_32" LOC = "AL20"; // IO_L7P_32 NET "No_Conn_BF_IO_L7P_32" LOC = "AN20"; // IO_L0P_32 NET "No_Conn_BF_IO_L0P_32" LOC = "AY24"; // IO_L10N_MRCC_33 NET "No_Conn_BF_IO_L10N_MRCC_33" LOC = "AJ15"; // IO_L6P_33 NET "No_Conn_BF_IO_L6P_33" LOC = "AJ17"; // IO_L18N_33 NET "No_Conn_BF_IO_L18N_33" LOC = "AJ18"; // IO_L10N_MRCC_36 NET "No_Conn_BF_IO_L10N_MRCC_36" LOC = "P16"; // IO_L16P_37 NET "No_Conn_BF_IO_L16P_37" LOC = "K20"; // IO_L16N_37 NET "No_Conn_BF_IO_L16N_37" LOC = "L20"; // IO_L9N_MRCC_37 NET "No_Conn_BF_IO_L9N_MRCC_37" LOC = "L21"; // IO_L5P_38 NET "No_Conn_BF_IO_L5P_38" LOC = "G26"; // IO_L0P_38 NET "No_Conn_BF_IO_L0P_38" LOC = "H24"; // IO_L4N_VREF_38 NET "No_Conn_BF_IO_L4N_VREF_38" LOC = "H25"; // IO_L4P_38 NET "No_Conn_BF_IO_L4P_38" LOC = "H26"; // IO_L6N_38 NET "No_Conn_BF_IO_L6N_38" LOC = "J25"; // IO_L12N_VRP_38 NET "No_Conn_BF_IO_L12N_VRP_38" LOC = "K24"; // IO_L6P_38 NET "No_Conn_BF_IO_L6P_38" LOC = "K25"; // IO_L12P_VRN_38 NET "No_Conn_BF_IO_L12P_VRN_38" LOC = "L24"; // IO_L14N_VREF_38 NET "No_Conn_BF_IO_L14N_VREF_38" LOC = "M23"; // IO_L16N_38 NET "No_Conn_BF_IO_L16N_38" LOC = "M24"; // IO_L16P_38 NET "No_Conn_BF_IO_L16P_38" LOC = "N23"; // IO_L19P_38 NET "No_Conn_BF_IO_L19P_38" LOC = "P20"; // // UN-Used Tranceiver Clock Inputs // // MGTREFCLK0P_110 NET "No_Conn_BF_GTX_CLK_0_110_DIR" LOC = "BA10"; // MGTREFCLK0N_110 NET "No_Conn_BF_GTX_CLK_0_110_CMP" LOC = "BA9"; // MGTREFCLK1P_110 NET "No_Conn_BF_GTX_CLK_1_110_DIR" LOC = "AW10"; // MGTREFCLK1N_110 NET "No_Conn_BF_GTX_CLK_1_110_CMP" LOC = "AW9"; // MGTREFCLK1P_111 NET "No_Conn_BF_GTX_CLK_1_111_DIR" LOC = "AT8"; // MGTREFCLK1N_111 NET "No_Conn_BF_GTX_CLK_1_111_CMP" LOC = "AT7"; // MGTREFCLK0P_112 NET "No_Conn_BF_GTX_CLK_0_112_DIR" LOC = "AK8"; // MGTREFCLK0N_112 NET "No_Conn_BF_GTX_CLK_0_112_CMP" LOC = "AK7"; // MGTREFCLK1P_112 NET "No_Conn_BF_GTX_CLK_1_112_DIR" LOC = "AH8"; // MGTREFCLK1N_112 NET "No_Conn_BF_GTX_CLK_1_112_CMP" LOC = "AH7"; // MGTREFCLK0P_113 NET "No_Conn_BF_GTX_CLK_0_113_DIR" LOC = "AF8"; // MGTREFCLK0N_113 NET "No_Conn_BF_GTX_CLK_0_113_CMP" LOC = "AF7"; // MGTREFCLK1P_113 NET "No_Conn_BF_GTX_CLK_1_113_DIR" LOC = "AD8"; // MGTREFCLK1N_113 NET "No_Conn_BF_GTX_CLK_1_113_CMP" LOC = "AD7"; // MGTREFCLK1P_114 NET "No_Conn_BF_GTX_CLK_1_114_DIR" LOC = "Y8"; // MGTREFCLK1N_114 NET "No_Conn_BF_GTX_CLK_1_114_CMP" LOC = "Y7"; // MGTREFCLK0P_115 NET "No_Conn_BF_GTX_CLK_0_115_DIR" LOC = "V8"; // MGTREFCLK0N_115 NET "No_Conn_BF_GTX_CLK_0_115_CMP" LOC = "V7"; // MGTREFCLK1P_115 NET "No_Conn_BF_GTX_CLK_1_115_DIR" LOC = "T8"; // MGTREFCLK1N_115 NET "No_Conn_BF_GTX_CLK_1_115_CMP" LOC = "T7"; // MGTREFCLK0P_116 NET "No_Conn_BF_GTX_CLK_0_116_DIR" LOC = "M8"; // MGTREFCLK0N_116 NET "No_Conn_BF_GTX_CLK_0_116_CMP" LOC = "M7"; // MGTREFCLK1P_116 NET "No_Conn_BF_GTX_CLK_1_116_DIR" LOC = "K8"; // MGTREFCLK1N_116 NET "No_Conn_BF_GTX_CLK_1_116_CMP" LOC = "K7"; // MGTREFCLK1P_117 NET "No_Conn_BF_GTX_CLK_1_117_DIR" LOC = "E10"; // MGTREFCLK1N_117 NET "No_Conn_BF_GTX_CLK_1_117_CMP" LOC = "E9"; // MGTREFCLK1P_118 NET "No_Conn_BF_GTX_CLK_1_118_DIR" LOC = "A10"; // MGTREFCLK1N_118 NET "No_Conn_BF_GTX_CLK_1_118_CMP" LOC = "A9";