/////////////////////////////////////////////////////////////////////////////// // // IO pin assignments for the CMX Board Support FPGA // -------------------------------==================== // /////////////////////////////////////////////////////////////////////////////// // // The assignments below correspond to the final version of the CMX netlist // // The format of this file is suitable for (at least a starting point of) // a User Constraint File (UCF) for the Xilinx synthesis tools // /////////////////////////////////////////////////////////////////////////////// // // Rev: 27-Dec-2013 Initial terse version // /////////////////////////////////////////////////////////////////////////////// // IO_L32P_2/D0/DIN/MISO # Config PROM Data to the FPGA NET "BSPT_CONFIG_DIN" LOC = "W18" // IO_L32N_2/CCLK # CCLK from the FPGA NET "BSPT_CONFIG_CCLK" LOC = "Y19" // IO_L24P_2/INIT_B # Config PROM OE/RESET_BAR pin is driven NET "BSPT_CONFIG_INIT_B" LOC = "Y14" // IO_L29P_0 # L29P-0 2.5V I/O NET "OCB_GEO_ADRS_1" LOC = "A4" // IO_L29N_0 # L29N-0 2.5V I/O NET "OCB_GEO_ADRS_2" LOC = "C4" // IO_L26P_0 # L26P-0 2.5V I/O NET "OCB_GEO_ADRS_3" LOC = "A5" // IO_L26N_0 # L26N-0 2.5V I/O NET "OCB_D00" LOC = "B5" // IO_L28P_0 # L28P-0 2.5V I/O NET "OCB_D01" LOC = "C5" // IO_L25P_0 # L25P-0 2.5V I/O NET "OCB_D02" LOC = "A6" // IO_L25N_0 # L25N-0 2.5V I/O NET "OCB_D03" LOC = "C6" // IO_L28N_0 # L28N-0 2.5V I/O NET "OCB_D04" LOC = "D6" // IO_L31P_0 # L31P-0 2.5V I/O NET "OCB_D05" LOC = "E6" // IO_L31N_0 # L31N-0 2.5V I/O NET "OCB_D06" LOC = "F6" // IO_L24N_0 # L24N-0 2.5V I/O NET "OCB_D07" LOC = "A7" // IO_L24P_0 # L24P-0 2.5V I/O NET "OCB_D08" LOC = "B7" // IO_L21P_0 # L21P-0 2.5V I/O NET "OCB_D09" LOC = "C7" // IO_L27P_0 # L27P-0 2.5V I/O NET "OCB_D10" LOC = "E7" // IO_L27N_0 # L27N-0 2.5V I/O NET "OCB_D11" LOC = "F7" // IO_L18N_0/GCLK11 # L18N-0 2.5V I/O NET "OCB_D12" LOC = "A8" // IO_L20P_0 # L20P-0 2.5V I/O NET "OCB_D13" LOC = "B8" // IO_L20N_0 # L20N-0 2.5V I/O NET "OCB_D14" LOC = "C8" // IO_L21N_0 # L21N-0 2.5V I/O NET "OCB_D15" LOC = "D8" // IO_L23P_0 # L23P-0 2.5V I/O NET "OCB_A23" LOC = "E8" // IO_L23N_0 # L23N-0 2.5V I/O NET "OCB_A22" LOC = "F8" // IO_L18P_0/GCLK10 # L18P-0 2.5V I/O NET "OCB_A21" LOC = "A9" // IO_L19P_0 # L19P-0 2.5V I/O NET "OCB_A20" LOC = "B9" // IO_L19N_0 # L19N-0 2.5V I/O NET "OCB_A19" LOC = "C9" // IO_L22P_0 # L22P-0 2.5V I/O NET "OCB_A18" LOC = "E9" // IO_L22N_0/VREF_0 # L22N-0 2.5V I/O NET "OCB_A17" LOC = "F9" // IO_L16P_0/GCLK6 # L16P-0 2.5V I/O NET "OCB_DS_B" LOC = "A10" // IO_L16N_0/GCLK7 # L16N-0 2.5V I/O NET "OCB_WRITE_B" LOC = "C10" // IO_L17P_0/GCLK8 # L17P-0 2.5V I/O NET "OCB_SYS_RESET_B" LOC = "D10" // IO_L17N_0/GCLK9 # L17N-0 2.5V I/O NET "OCB_GEO_ADRS_0" LOC = "E10" // IO_L15N_0/GCLK5 # L15N-0 2.5V I/O NET "OCB_GEO_ADRS_4" LOC = "E11" // IO_L15P_0/GCLK4 # L15P-0 2.5V I/O NET "OCB_GEO_ADRS_5" LOC = "D11" // IO_L14N_0 # L14N-0 2.5V I/O NET "OCB_GEO_ADRS_6" LOC = "C11" // IO_L14P_0 # L14P-0 2.5V I/O NET "OCB_A16" LOC = "B11" // IO_L12N_0 # L12N-0 2.5V I/O NET "OCB_A15" LOC = "F12" // IO_L12P_0 # L12P-0 2.5V I/O NET "OCB_A14" LOC = "D12" // IO_L11N_0 # L11N-0 2.5V I/O NET "OCB_A13" LOC = "C12" // IO_L13P_0 # L13P-0 2.5V I/O NET "OCB_A12" LOC = "B12" // IO_L13N_0 # L13N-0 2.5V I/O NET "OCB_A11" LOC = "A12" // IO_L09N_0 # L09N-0 2.5V I/O NET "OCB_A10" LOC = "F13" // IO_L09P_0 # L09P-0 2.5V I/O NET "OCB_A09" LOC = "E13" // IO_L10N_0/VREF_0 # L10N-0 2.5V I/O NET "OCB_A08" LOC = "C13" // IO_L11P_0 # L11P-0 2.5V I/O NET "OCB_A07" LOC = "B13" // IO_L10P_0 # L10P-0 2.5V I/O NET "OCB_A06" LOC = "D14" // IO_L07P_0 # L07P-0 2.5V I/O NET "OCB_A05" LOC = "C14" // IO_L07N_0 # L07N-0 2.5V I/O NET "OCB_A04" LOC = "A14" // IO_L06N_0 # L06N-0 2.5V I/O NET "OCB_A03" LOC = "C15" // IO_L08P_0 # L08P-0 2.5V I/O NET "OCB_A02" LOC = "B15" // IO_L08N_0 # L08N-0 2.5V I/O NET "OCB_A01" LOC = "A15" // IP_L04N_1/VREF_1 # Buffered TTC_BRCST_2 NET "BUF_TTC_BRCST_2" LOC = "P15" // IP_L04P_1 # Buffered TTC_BRCST_3 NET "BUF_TTC_BRCST_3" LOC = "P14" // IP_1/VREF_1 # Buffered TTC_BRCST_4 NET "BUF_TTC_BRCST_4" LOC = "N14" // IP_L11P_1 # Buffered TTC_BRCST_5 NET "BUF_TTC_BRCST_5" LOC = "M16" // IP_L11N_1/VREF_1 # Buffered TTC_BRCST_6 NET "BUF_TTC_BRCST_6" LOC = "M15" // IP_L15P_1/VREF_1 # Buffered TTC_BRCST_7 NET "BUF_TTC_BRCST_7" LOC = "M14" // IP_L15N_1 # Buffered TTC_BRCST_STR_1 NET "BUF_TTC_BRCST_STR_1" LOC = "M13" // IO_L16P_1/A8 # Buffered TTC_BRCST_STR_2 NET "BUF_TTC_BRCST_STR_2" LOC = "L15" // IP_L19P_1 # Buffered TTC_SIN_ERR_STR NET "BUF_TTC_SIN_ERR_STR" LOC = "L14" // IP_L19N_1 # Buffered TTC_DB_ERR_STR NET "BUF_TTC_DB_ERR_STR" LOC = "L13" // IP_L23N_1 # Buffered TTC_CLK_40_L1A NET "BUF_TTC_CLK_40_L1A" LOC = "K14" // IP_L23P_1/VREF_1 # Buffered TTC_BNCH_CNT_RES NET "BUF_TTC_BNCH_CNT_RES" LOC = "K15" // IO_L24N_1 # Buffered TTC_EV_CNT_RES NET "BUF_TTC_EV_CNT_RES" LOC = "K16" // IO_L20P_1/RHCLK4 # Buffered TTC_EV_CNT_H_STR NET "BUF_TTC_EV_CNT_H_STR" LOC = "K18" // IO_L21P_1/IRDY1/RHCLK6 # Buffered TTC_EV_CNT_L_STR NET "BUF_TTC_EV_CNT_L_STR" LOC = "K20" // IP_L31N_1 # Buffered TTC_BNCH_CNT_STR NET "BUF_TTC_BNCH_CNT_STR" LOC = "J13" // IP_L31P_1/VREF_1 # Buffered TTC_B_CNT_0 NET "BUF_TTC_B_CNT_0" LOC = "J14" // IP_L27N_1 # Buffered TTC_B_CNT_1 NET "BUF_TTC_B_CNT_1" LOC = "J15" // IP_L27P_1 # Buffered TTC_B_CNT_2 NET "BUF_TTC_B_CNT_2" LOC = "J16" // IO_L24P_1 # Buffered TTC_B_CNT_3 NET "BUF_TTC_B_CNT_3" LOC = "J17" // IO_L22N_1/A11 # Buffered TTC_B_CNT_4 NET "BUF_TTC_B_CNT_4" LOC = "J18" // IO_L22P_1/A10 # Buffered TTC_B_CNT_5 NET "BUF_TTC_B_CNT_5" LOC = "J19" // IO_L21N_1/RHCLK7 # Buffered TTC_B_CNT_6 NET "BUF_TTC_B_CNT_6" LOC = "J20" // IP_L35N_1 # Buffered TTC_B_CNT_7 NET "BUF_TTC_B_CNT_7" LOC = "H14" // IP_L35P_1 # Buffered TTC_B_CNT_8 NET "BUF_TTC_B_CNT_8" LOC = "H15" // IO_L28N_1 # Buffered TTC_B_CNT_9 NET "BUF_TTC_B_CNT_9" LOC = "H17" // IO_L25N_1/A13 # Buffered TTC_B_CNT_10 NET "BUF_TTC_B_CNT_10" LOC = "H18" // IO_L25P_1/A12 # Buffered TTC_B_CNT_11 NET "BUF_TTC_B_CNT_11" LOC = "H19" // IO_L26P_1/A14 # Buffered TTC_DQ_0 NET "BUF_TTC_DQ_0" LOC = "H20" // IP_L39N_1 # Buffered TTC_DQ_1 NET "BUF_TTC_DQ_1" LOC = "G14" // IP_L39P_1/VREF_1 # Buffered TTC_DQ_2 NET "BUF_TTC_DQ_2" LOC = "G15" // IO_L36P_1/A20 # Buffered TTC_DQ_3 NET "BUF_TTC_DQ_3" LOC = "G16" // IO_L30P_1/A18 # Buffered TTC_L1_ACCEPT NET "BUF_TTC_L1_ACCEPT" LOC = "G17" // IO_L28P_1 # Buffered TTC_SER_B_CH NET "BUF_TTC_SER_B_CH" LOC = "G18" // IO_L26N_1/A15 # Buffered TTC_D_OUT_STR NET "BUF_TTC_D_OUT_STR" LOC = "G20" // IO_L36N_1/A21 # Buffered TTC_READY (STATUS_1) NET "BUF_TTC_READY" LOC = "F16" // IO_L33N_1 # Buffered TTC_STATUS_2 NET "BUF_TTC_STATUS_2" LOC = "F17" // IO_L30N_1/A19 # Buffered TTC_D_OUT_0 NET "BUF_TTC_D_OUT_0" LOC = "F18" // IO_L29N_1/A17 # Buffered TTC_D_OUT_1 NET "BUF_TTC_D_OUT_1" LOC = "F19" // IO_L29P_1/A16 # Buffered TTC_D_OUT_2 NET "BUF_TTC_D_OUT_2" LOC = "F20" // IO_L33P_1 # Buffered TTC_D_OUT_3 NET "BUF_TTC_D_OUT_3" LOC = "E18" // IO_L32N_1 # Buffered TTC_D_OUT_4 NET "BUF_TTC_D_OUT_4" LOC = "E19" // IO_L32P_1 # Buffered TTC_D_OUT_5 NET "BUF_TTC_D_OUT_5" LOC = "E20" // IO_L34N_1 # Buffered TTC_D_OUT_6 NET "BUF_TTC_D_OUT_6" LOC = "D18" // IO_L34P_1 # Buffered TTC_D_OUT_7 NET "BUF_TTC_D_OUT_7" LOC = "D20" // IO_L37N_1/A23 # Buffered TTC_SUB_ADRS_0 NET "BUF_TTC_SUB_ADRS_0" LOC = "C19" // IO_L37P_1/A22 # Buffered TTC_SUB_ADRS_1 NET "BUF_TTC_SUB_ADRS_1" LOC = "C20" // IO_L38N_1/A25 # Buffered TTC_SUB_ADRS_2 NET "BUF_TTC_SUB_ADRS_2" LOC = "B19" // IO_L38P_1/A24 # Buffered TTC_SUB_ADRS_3 NET "BUF_TTC_SUB_ADRS_3" LOC = "B20" // IO_L01P_0 # Buffered TTC_SUB_ADRS_4 NET "BUF_TTC_SUB_ADRS_4" LOC = "B18" // IO_L01N_0 # Buffered TTC_SUB_ADRS_5 NET "BUF_TTC_SUB_ADRS_5" LOC = "A18" // IO_L02P_0/VREF_0 # Buffered TTC_SUB_ADRS_6 NET "BUF_TTC_SUB_ADRS_6" LOC = "D17" // IO_L02N_0 # Buffered TTC_SUB_ADRS_7 NET "BUF_TTC_SUB_ADRS_7" LOC = "C17" // IO_L36N_3 # Clock Changeover Mode: Protected or DeBug NET "TTC_PD" LOC = "T4" // IO_L34P_3 # Select 40 MHz rock or TTCrx clock source NET "TTC_CLK_SEL" LOC = "U1" // IO_L33P_3 # Reset the TTCrx ASIC NET "TTC_RESET_B" LOC = "T3" // IO_L37P_3 # I2C Serial Clock BSPT_FPGA --> Series Term NET "ST_TTC_SCL" LOC = "V1" // IO_L34N_3 # I2C Serail Data BSPT <-> Series Term NET "ST_TTC_SDA" LOC = "U3" // IO_L12P_3 # Control signal from the BSPT NET "BSPT_TTC_TRNSLT_OE_B" LOC = "G3" // IO_L13N_3/VREF_3 # Control signal from the BSPT NET "BSPT_TTC_RESET_TRNSLT_OE_B" LOC = "G1" // IO_L01N_1/LDC2 # BF PROG_B connection to the BSPT NET "BF_PROGRAM_B" LOC = "V20" // IO_L27N_2 # TP PROG_B connection to the BSPT NET "TP_PROGRAM_B" LOC = "T15" // IP_2/VREF_2 # BF FPGA INIT_B_0 to Input pin on BSPT NET "BF_INIT_B" LOC = "N12" // IP_2 # TP FPGA INIT_B_0 to Input pin on BSPT NET "TP_INIT_B" LOC = "R10" // IP_2 # BF DONE connection to a BSPT input NET "BF_CONFIG_DONE" LOC = "P12" // IP_2/VREF_2 # TP DONE connection to a BSPT input NET "TP_CONFIG_DONE" LOC = "P10" // IO_L25P_2 # 20 MHz Clock signal to the System-ACE NET "BSPT_ACE_CLK" LOC = "V14" // IO_L24N_2/D3 # System-ACE RESET input Vccl Int_PU NET "ACE_RESET_B" LOC = "W14" // IO_L04P_2 # System-ACE Status LED output pin open-drain NET "ACE_STATLED_B" LOC = "T6" // IO_L06N_2 # System-ACE Error LED output pin open-drain NET "ACE_ERRLED_B" LOC = "U6" // IO_L09N_2/VS0 # System-ACE MP Chip Enable _B input Vccl Int_PU NET "BSPT_ACE_MPCE_B" LOC = "W6" // IO_L04N_2 # System-ACE MP Write Enable _B input Vccl Int_PU NET "BSPT_ACE_MPWE_B" LOC = "R7" // IO_L12N_2/D6 # System-ACE MP Output Enable _B input Vccl Int_PU NET "BSPT_ACE_MPOE_B" LOC = "W8" // IP_2/VREF_2 # System-ACE MP Interrupt Request output Vccl In-Only NET "BSPT_ACE_MPIRQ" LOC = "N9" // IP_2 # System-ACE MP Data Buffer Ready output Vccl In-Only NET "BSPT_ACE_MPBRDY" LOC = "P9" // IO_L21P_2 # System-ACE MP Address 0 input Vccl NET "BSPT_ACE_MP_ADRS_0" LOC = "Y13" // IO_L25N_2 # System-ACE MP Address 1 input Vccl NET "BSPT_ACE_MP_ADRS_1" LOC = "T14" // IO_L21N_2 # System-ACE MP Address 2 input Vccl NET "BSPT_ACE_MP_ADRS_2" LOC = "W13" // IO_L13N_2 # System-ACE MP Address 3 input Vccl NET "BSPT_ACE_MP_ADRS_3" LOC = "V9" // IO_L15P_2/GCLK12 # System-ACE MP Address 4 input Vccl NET "BSPT_ACE_MP_ADRS_4" LOC = "W9" // IO_L15N_2/GCLK13 # System-ACE MP Address 5 input Vccl NET "BSPT_ACE_MP_ADRS_5" LOC = "Y9" // IO_L07P_2/RDWR_B # System-ACE MP Address 6 input Vccl NET "BSPT_ACE_MP_ADRS_6" LOC = "T8" // IO_L22N_2/DOUT # System-ACE MP Data 00 in/out Vccl NET "BSPT_ACE_MP_DATA_00" LOC = "V13" // IO_L22P_2/AWAKE # System-ACE MP Data 01 in/out Vccl NET "BSPT_ACE_MP_DATA_01" LOC = "U13" // IO_L23P_2 # System-ACE MP Data 02 in/out Vccl NET "BSPT_ACE_MP_DATA_02" LOC = "T13" // IO_L23N_2 # System-ACE MP Data 03 in/out Vccl NET "BSPT_ACE_MP_DATA_03" LOC = "R13" // IO_L20P_2 # System-ACE MP Data 04 in/out Vccl NET "BSPT_ACE_MP_DATA_04" LOC = "Y12" // IO_L20N_2/MOSI/CSI_B # System-ACE MP Data 05 in/out Vccl NET "BSPT_ACE_MP_DATA_05" LOC = "W12" // IO_L19P_2 # System-ACE MP Data 06 in/out Vccl NET "BSPT_ACE_MP_DATA_06" LOC = "T12" // IO_L19N_2 # System-ACE MP Data 07 in/out Vccl NET "BSPT_ACE_MP_DATA_07" LOC = "R12" // IO_L17P_2/GCLK0 # System-ACE MP Data 08 in/out Vccl NET "BSPT_ACE_MP_DATA_08" LOC = "Y11" // IO_L17N_2/GCLK1 # System-ACE MP Data 09 in/out Vccl NET "BSPT_ACE_MP_DATA_09" LOC = "V11" // IO_L14N_2/D4 # System-ACE MP Data 10 in/out Vccl NET "BSPT_ACE_MP_DATA_10" LOC = "T10" // IO_L14P_2/D5 # System-ACE MP Data 11 in/out Vccl NET "BSPT_ACE_MP_DATA_11" LOC = "U10" // IO_L16P_2/GCLK14 # System-ACE MP Data 12 in/out Vccl NET "BSPT_ACE_MP_DATA_12" LOC = "V10" // IO_L16N_2/GCLK15 # System-ACE MP Data 13 in/out Vccl NET "BSPT_ACE_MP_DATA_13" LOC = "W10" // IO_L11P_2 # System-ACE MP Data 14 in/out Vccl NET "BSPT_ACE_MP_DATA_14" LOC = "T9" // IO_L11N_2 # System-ACE MP Data 15 in/out Vccl NET "BSPT_ACE_MP_DATA_15" LOC = "U9" // IP_2/VREF_2 # Sys-ACE Configuration JTAG INIT input Vccl NET "ACE_CFG_INIT_B" LOC = "P8" // IO_L06P_2 # Sys-ACE Config Address Select 0 input Vccl Init_PD NET "ACE_CFG_ADRS_0" LOC = "T7" // IO_L10N_2 # Sys-ACE Config Address Select 1 input Vccl Init_PD NET "ACE_CFG_ADRS_1" LOC = "Y7" // IO_L12P_2/D7 # Sys-ACE Config Address Select 2 input Vccl Init_PD NET "ACE_CFG_ADRS_2" LOC = "V7" // IO_L07N_2/VS2 # Sys-ACE Config Mode Pin input Vccl Init_PU NET "ACE_CFG_MODE" LOC = "U7" // IP_L04N_3/VREF_3 # SFP1 Transmitter Fault 3.3V Input-Only NET "SFP1_TX_FAULT" LOC = "G6" // IO_L21P_3/TRDY2/LHCLK6 # SFP1 Transmitter Disable 3.3V Output NET "SFP1_TX_DISABLE" LOC = "L1" // IO_L24N_3 # SFP1 2 Wire Serial Data 3.3V I/O NET "SFP1_MOD_SER_DATA" LOC = "M5" // IO_L24P_3 # SFP1 2 Wire Serial Clock 3.3V Output NET "SFP1_MOD_SER_CLK" LOC = "M4" // IP_3 # SFP1 Module Present->Low 3.3V Input-Only NET "SFP1_MOD_PRESENT" LOC = "H7" // IP_L11N_3/VREF_3 # SFP2 Transmitter Fault 3.3V Input-Only NET "SFP2_TX_FAULT" LOC = "J7" // IO_L22N_3 # SFP2 Transmitter Disable 3.3V Output NET "SFP2_TX_DISABLE" LOC = "M3" // IO_L22P_3/VREF_3 # SFP2 2 Wire Serial Data 3.3V I/O NET "SFP2_MOD_SER_DATA" LOC = "M2" // IO_L21N_3/LHCLK7 # SFP2 2 Wire Serial Clock 3.3V Output NET "SFP2_MOD_SER_CLK" LOC = "M1" // IP_L15N_3 # SFP2 Module Present->Low 3.3V Input-Only NET "SFP2_MOD_PRESENT" LOC = "K7" // IP_L19P_3 # SFP3 Transmitter Fault 3.3V Input-Only NET "SFP3_TX_FAULT" LOC = "K6" // IO_L25N_3 # SFP3 Transmitter Disable 3.3V Output NET "SFP3_TX_DISABLE" LOC = "N2" // IO_L25P_3 # SFP3 2 Wire Serial Data 3.3V I/O NET "SFP3_MOD_SER_DATA" LOC = "N1" // IO_L29N_3 # SFP3 2 Wire Serial Clock 3.3V Output NET "SFP3_MOD_SER_CLK" LOC = "P4" // IP_L19N_3 # SFP3 Module Present->Low 3.3V Input-Only NET "SFP3_MOD_PRESENT" LOC = "K5" // IP_L23P_3 # SFP4 Transmitter Fault 3.3V Input-Only NET "SFP4_TX_FAULT" LOC = "L7" // IO_L29P_3 # SFP4 Transmitter Disable 3.3V Output NET "SFP4_TX_DISABLE" LOC = "P3" // IO_L28P_3 # SFP4 2 Wire Serial Data 3.3V I/O NET "SFP4_MOD_SER_DATA" LOC = "P1" // IO_L36P_3 # SFP4 2 Wire Serial Clock 3.3V Output NET "SFP4_MOD_SER_CLK" LOC = "R5" // IP_L23N_3 # SFP4 Module Present->Low 3.3V Input-Only NET "SFP4_MOD_PRESENT" LOC = "L6" // IO_L33N_3 # SDA connection to the BSPT 3.3V I/O NET "MP12_SDA" LOC = "R4" // IO_L32P_3/VREF_3 # SCL connection to the BSPT 3.3V Output NET "MP12_SCL" LOC = "T1" // IO_L32N_3 # MiniPods 1,2 Reset_B 3.3V Output NET "MP12_RESET_B" LOC = "T2" // IP_L39N_3/VREF_3 # MP1 Interrupt_B 3.3V In-Only pin NET "MP1_INTRPT_B" LOC = "P7" // IP_L39P_3 # MP2 Interrupt_B 3.3V In-Only pin NET "MP2_INTRPT_B" LOC = "P6" // IO_L28N_3 # SDA connection to the BSPT 3.3V I/O NET "MP345_SDA" LOC = "R1" // IO_L30P_3 # SCL connection to the BSPT 3.3V Output NET "MP345_SCL" LOC = "R2" // IO_L30N_3 # MiniPods 3,4,5 Reset_B 3.3V Output NET "MP345_RESET_B" LOC = "R3" // IP_L35P_3 # MP3 Interrupt_B 3.3V In-Only pin NET "MP3_INTRPT_B" LOC = "P5" // IP_L31N_3 # MP4 Interrupt_B 3.3V In-Only pin NET "MP4_INTRPT_B" LOC = "N7" // IP_L35N_3 # MP5 Interrupt_B 3.3V In-Only pin NET "MP5_INTRPT_B" LOC = "N6" // IO_L32N_0/PUDC_B # Control the IO_L32N_0/PUDC_B pin NET "BSPT_PUDC_B" LOC = "B2" // IO_L28P_2 # L28P-2 2.5V I/O used as Input NET "BF_LED_REQ_0" LOC = "Y16" // IO_L31P_2 # L31P-2 2.5V I/O used as Input NET "BF_LED_REQ_1" LOC = "V17" // IO_L30P_2 # L30P-2 2.5V I/O used as Input NET "BF_LED_REQ_2" LOC = "Y17" // IO_L30N_2 # L30N-2 2.5V I/O used as Input NET "BF_LED_REQ_3" LOC = "Y18" // IO_L01P_1/HDC # L01P-1 2.5V I/O used as Input NET "BF_LED_REQ_4" LOC = "W20" // IO_L10N_1/VREF_1 # L10N-1 2.5V I/O used as Input NET "TP_LED_REQ_0" LOC = "P20" // IO_L12P_1/A2 # L12P-1 2.5V I/O used as Input NET "TP_LED_REQ_1" LOC = "N15" // IO_L12N_1/A3 # L12N-1 2.5V I/O used as Input NET "TP_LED_REQ_2" LOC = "N17" // IO_L13P_1/A4 # L13P-1 2.5V I/O used as Input NET "TP_LED_REQ_3" LOC = "N18" // IO_L13N_1/A5 # L13N-1 2.5V I/O used as Input NET "TP_LED_REQ_4" LOC = "N19" // IO_L08P_3 # Drive signal to LED 1 Right Green NET "LED_1R_GREEN_DRV" LOC = "H6" // IO_L08N_3 # Drive signal to LED 2 Left Green NET "LED_2L_GREEN_DRV" LOC = "H4" // IO_L14N_3 # Drive signal to LED 2 Right Green NET "LED_2R_GREEN_DRV" LOC = "H3" // IO_L12N_3 # Drive signal to LED 3 Left Green NET "LED_3L_GREEN_DRV" LOC = "H2" // IO_L07P_3 # Drive signal to LED 3 Left Red NET "LED_3L_RED_DRV" LOC = "J6" // IO_L07N_3 # Drive signal to LED 3 Right Green NET "LED_3R_GREEN_DRV" LOC = "J5" // IO_L14P_3 # Drive signal to LED 3 Right Red NET "LED_3R_RED_DRV" LOC = "J4" // IO_L16P_3 # Drive signal to LED 4 Left Green NET "LED_4L_GREEN_DRV" LOC = "J3" // IO_L16N_3 # Drive signal to LED 4 Left Red NET "LED_4L_RED_DRV" LOC = "J2" // IO_L17P_3/LHCLK0 # Drive signal to LED 4 Right Green NET "LED_4R_GREEN_DRV" LOC = "J1" // IO_L20P_3/LHCLK4 # Drive signal to LED 4 Right Red NET "LED_4R_RED_DRV" LOC = "K4" // IO_L18P_3/LHCLK2 # Drive signal to LED 5 Left Green NET "LED_5L_GREEN_DRV" LOC = "K3" // IO_L17N_3/LHCLK1 # Drive signal to LED 5 Left Red NET "LED_5L_RED_DRV" LOC = "K2" // IO_L20N_3/LHCLK5 # Drive signal to LED 5 Right Green NET "LED_5R_GREEN_DRV" LOC = "L5" // IO_L18N_3/IRDY2/LHCLK3 # Drive signal to LED 5 Right Red NET "LED_5R_RED_DRV" LOC = "L3" // IO_L03N_3 # L03N-3 3.3V Output NET "BSPT_SEND_VME_DTACK_B" LOC = "D2" // IO_L01N_3 # L01N-3 3.3V Output NET "VME_D_BUS_TRNCVR_DIR" LOC = "D3" // IO_L05P_3 # L05P-3 3.3V Output NET "BSPT_VME_D_BUS_TRNCVR_OE_B" LOC = "D1" // IO_L05N_0 # L05N-0 2.5V Output NET "OCB_D_BUS_TRNSLT_DIR" LOC = "A16" // IO_L03N_0 # L03N-0 2.5V Output NET "OCB_D_BUS_TRNSLT_OE_B" LOC = "E15" // IO_L02N_3 # L02N-3 3.3V Output NET "VME_ADRS_RECVR_LE" LOC = "C2" // IO_L01P_3 # L01P-3 3.3V Output NET "VME_CTRL_RECVR_LE" LOC = "D4" // IO_L03P_3 # L03P-3 3.3V Output NET "VME_ADRS_AND_CTRL_RECVR_OE_B" LOC = "C1" // IO_L06P_0 # L06P-0 2.5V Output NET "OCB_ADRS_AND_CTRL_TRNSLT_DIR" LOC = "D15" // IO_L10P_3 # L10P-3 3.3V Output NET "BSPT_OCB_ADRS_AND_CTRL_TRNSLT_OE_B" LOC = "E3" // IO_L26N_2/D1 # 2.5V I/O input to the BSPT NET "BF_REQ_CABLE_1_INPUT" LOC = "V15" // IO_L38N_3 # 3.3V output from the BSPT NET "CABLE_1_TRNCVR_DIR" LOC = "W2" // IO_L04N_0 # 2.5V output from the BSPT NET "CABLE_1_TRNSLT_DIR" LOC = "A17" // IO_L05N_3 # 3.3V output from the BSPT NET "BSPT_CABLE_1_TRNSLT_OE_B" LOC = "E1" // IO_L26P_2/D2 # 2.5V I/O input to the BSPT NET "BF_REQ_CABLE_2_INPUT" LOC = "Y15" // IO_L38P_3 # 3.3V output from the BSPT NET "CABLE_2_TRNCVR_DIR" LOC = "W1" // IO_L03P_0 # 2.5V output from the BSPT NET "CABLE_2_TRNSLT_DIR" LOC = "D16" // IO_L06P_3 # 3.3V output from the BSPT NET "BSPT_CABLE_2_TRNSLT_OE_B" LOC = "F4" // IO_L28N_2 # 2.5V I/O input to the BSPT NET "BF_REQ_CABLE_3_INPUT" LOC = "W16" // IO_L37N_3 # 3.3V output from the BSPT NET "CABLE_3_TRNCVR_DIR" LOC = "V2" // IO_L05P_0 # 2.5V output from the BSPT NET "CABLE_3_TRNSLT_DIR" LOC = "C16" // IO_L09P_3 # 3.3V output from the BSPT NET "BSPT_CABLE_3_TRNSLT_OE_B" LOC = "F3" // IP_2/VREF_2 # 2.5V input only to the BSPT NET "BF_REQ_CTP_1_INPUT" LOC = "P11" // IP_2 # 2.5V input only to the BSPT NET "TP_REQ_CTP_1_INPUT" LOC = "P13" // IO_L26N_3 # 3.3V output from the BSPT NET "CTP_1_TRNCVR_DIR" LOC = "N4" // IO_L08N_2 # 2.5V output from the BSPT NET "CTP_1_BF_TRNSLT_DIR" LOC = "Y5" // IO_L10N_3 # 3.3V output from the BSPT NET "BSPT_CTP_1_BF_TRNSLT_OE_B" LOC = "F2" // IO_L05P_2 # 2.5V output from the BSPT NET "CTP_1_TP_TRNSLT_DIR" LOC = "V5" // IO_L13P_3 # 3.3V output from the BSPT NET "BSPT_CTP_1_TP_TRNSLT_OE_B" LOC = "F1" // IP_2 # 2.5V input only to the BSPT NET "BF_REQ_CTP_2_INPUT" LOC = "T11" // IP_2/VREF_2 # 2.5V input only to the BSPT NET "TP_REQ_CTP_2_INPUT" LOC = "R14" // IO_L26P_3 # 3.3V output from the BSPT NET "CTP_2_TRNCVR_DIR" LOC = "N3" // IO_L05N_2 # 2.5V output from the BSPT NET "CTP_2_BF_TRNSLT_DIR" LOC = "U5" // IO_L06N_3 # 3.3V output from the BSPT NET "BSPT_CTP_2_BF_TRNSLT_OE_B" LOC = "G5" // IO_L10P_2 # 2.5V output from the BSPT NET "CTP_2_TP_TRNSLT_DIR" LOC = "Y6" // IO_L09N_3 # 3.3V output from the BSPT NET "BSPT_CTP_2_TP_TRNSLT_OE_B" LOC = "G4" // IO_L30P_0 # L30P-0 2.5V I/O Output NET "BSPT_RUNNING_OK_B" LOC = "A3" // IP_0 # IP-0 2.5V In-Only NET "TP_FPGA_INSTALLED_B" LOC = "G8" // IP_L04P_3 # Receive the ALLOW_BUSSED_IO NET "ALLOW_BUSSED_IO" LOC = "G7" // IO_L03P_1/A0 # L03P-1 2.5V I/O DeBug Signal 0 NET "BSPT_DEBUG_0" LOC = "T17" // IO_L07N_1 # L07N-1 2.5V I/O DeBug Signal 1 NET "BSPT_DEBUG_1" LOC = "P17" // IO_L31N_2 # L31N-2 2.5V I/O DeBug Signal 2 NET "BSPT_DEBUG_2" LOC = "U17" // IO_L03N_1/A1 # L03N-1 2.5V I/O DeBug Signal 3 NET "BSPT_DEBUG_3" LOC = "R16" // IO_L29P_2 # L29P-2 2.5V I/O DeBug Signal 4 NET "BSPT_DEBUG_4" LOC = "V16" // IO_L07P_1 # L07P-1 2.5V I/O DeBug Signal 5 NET "BSPT_DEBUG_5" LOC = "P16" // IO_L29N_2 # L29N-2 2.5V I/O DeBug Signal 6 NET "BSPT_DEBUG_6" LOC = "U16" // IO_L08P_1 # L08P-1 2.5V I/O DeBug Signal 7 NET "BSPT_DEBUG_7" LOC = "R18" // IO_L27P_2 # L27P-2 2.5V I/O DeBug Signal 8 NET "BSPT_DEBUG_8" LOC = "U15" // IO_L08N_1 # L08N-1 2.5V I/O DeBug Signal 9 NET "BSPT_DEBUG_9" LOC = "R17" // IO_L02N_2/CSO_B # SFP1 Receiver Signal Lost BSPT Bank 2 2.5V I/O NET "SFP1_RX_LOST" LOC = "Y2" // IO_L03P_2 # SFP2 Receiver Signal Lost BSPT Bank 2 2.5V I/O NET "SFP2_RX_LOST" LOC = "Y3" // IO_L03N_2 # SFP3 Receiver Signal Lost BSPT Bank 2 2.5V I/O NET "SFP3_RX_LOST" LOC = "W4" // IO_L08P_2 # SFP4 Receiver Signal Lost BSPT Bank 2 2.5V I/O NET "SFP4_RX_LOST" LOC = "Y4" // IO_L18P_2/GCLK2 # Clock 40.08 MHz NET "CLK_40MHz08_DSKW_1_BSPT_LOGIC_DIR" LOC = "U11" // IO_L18N_2/GCLK3 # DeSkew #1 LHC Locked NET "CLK_40MHz08_DSKW_1_BSPT_LOGIC_CMP" LOC = "V12" // IO_L02P_1/LDC1 # L02P-1 2.5V I/O NET "BF_TO_FROM_BSPT_0" LOC = "V19" // IO_L06P_1 # L06P-1 2.5V I/O NET "BF_TO_FROM_BSPT_1" LOC = "U19" // IO_L06N_1 # L06N-1 2.5V I/O NET "BF_TO_FROM_BSPT_2" LOC = "U20" // IO_L05P_1 # L05P-1 2.5V I/O NET "BF_TO_FROM_BSPT_3" LOC = "T18" // IO_L05N_1 # L05N-1 2.5V I/O NET "BF_TO_FROM_BSPT_4" LOC = "T20" // IO_L09P_1 # L09P-1 2.5V I/O NET "BF_TO_FROM_BSPT_5" LOC = "R19" // IO_L09N_1 # L09N-1 2.5V I/O NET "BF_TO_FROM_BSPT_6" LOC = "R20" // IO_L10P_1 # L10P-1 2.5V I/O NET "BF_TO_FROM_BSPT_7" LOC = "P18" // IO_L17N_1/RHCLK1 # L17N-1 2.5V I/O NET "TP_TO_FROM_BSPT_0" LOC = "M20" // IO_L17P_1/RHCLK0 # L17P-1 2.5V I/O NET "TP_TO_FROM_BSPT_1" LOC = "M19" // IO_L14N_1/A7 # L14N-1 2.5V I/O NET "TP_TO_FROM_BSPT_2" LOC = "M18" // IO_L14P_1/A6 # L14P-1 2.5V I/O NET "TP_TO_FROM_BSPT_3" LOC = "M17" // IO_L18P_1/RHCLK2 # L18P-1 2.5V I/O NET "TP_TO_FROM_BSPT_4" LOC = "L19" // IO_L18N_1/TRDY1/RHCLK3 # L18N-1 2.5V I/O NET "TP_TO_FROM_BSPT_5" LOC = "L18" // IO_L20N_1/RHCLK5 # L20N-1 2.5V I/O NET "TP_TO_FROM_BSPT_6" LOC = "L17" // IO_L16N_1/A9 # L16N-1 2.5V I/O NET "TP_TO_FROM_BSPT_7" LOC = "L16" // IP_0 # Bit 1 of the CMX Card Seril Number NET "CMX_SERIAL_NUM_1" LOC = "G13" // IP_0 # Bit 2 of the CMX Card Seril Number NET "CMX_SERIAL_NUM_2" LOC = "G12" // IP_0/VREF_0 # Bit 3 of the CMX Card Seril Number NET "CMX_SERIAL_NUM_3" LOC = "G11" // IP_0 # Bit 4 of the CMX Card Seril Number NET "CMX_SERIAL_NUM_4" LOC = "G10" // IP_0 # Bit 5 of the CMX Card Seril Number NET "CMX_SERIAL_NUM_5" LOC = "G9" /////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////// // // The following list assigns a unique net-name to // ALL UNUSED Select IO and GTX IO pins left on the BF FPGA. // /////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////// // Note that a few of these pin have been routed to resistor-like // "SR" components (not installed) so that we can have access to these signals // by soldering wires if necessary. These spare pins have net names of the type // SPR_Conn_BSPT_Pin i.e. a spare connection. // // IO_L32P_0/VREF_0 # Spare Conn BSPT Pin A2 Bank 0 2.5V I/O NET "SPR_Conn_BSPT_Pin_A2" LOC = "A2" // IO_L30N_0 # No Connect BSPT Pin B3 Bank 0 2.5V I/O NET "No_Conn_BSPT_Pin_B3" LOC = "B3" // IO_L04P_0/VREF_0 # No Connect BSPT Pin B17 Bank 0 2.5V I/O NET "No_Conn_BSPT_Pin_B17" LOC = "B17" // IP_0 # No Connect BSPT Pin H9 Bank 0 2.5V In-Only NET "No_Conn_BSPT_Pin_H9" LOC = "H9" // IP_0 # No Connect BSPT Pin H10 Bank 0 2.5V In-Only NET "No_Conn_BSPT_Pin_H10" LOC = "H10" // IP_0 # No Connect BSPT Pin F11 Bank 0 2.5V In-Only NET "No_Conn_BSPT_Pin_F11" LOC = "F11" // IP_0 # No Connect BSPT Pin H11 Bank 0 2.5V In-Only NET "No_Conn_BSPT_Pin_H11" LOC = "H11" // IP_0 # No Connect BSPT Pin H12 Bank 0 2.5V In-Only NET "No_Conn_BSPT_Pin_H12" LOC = "H12" // IP_0 # No Connect BSPT Pin E14 Bank 0 2.5V In-Only NET "No_Conn_BSPT_Pin_E14" LOC = "E14" // IP_0 # No Connect BSPT Pin F14 Bank 0 2.5V In-Only NET "No_Conn_BSPT_Pin_F14" LOC = "F14" // IO_L02N_1/LDC0 # No Connect BSPT Pin U18 Bank 1 2.5V I/O NET "No_Conn_BSPT_Pin_U18" LOC = "U18" // IO_L09P_2/VS1 # No Connect BSPT Pin V6 Bank 2 2.5V I/O NET "No_Conn_BSPT_Pin_V6" LOC = "V6" // IO_L13P_2 # No Connect BSPT Pin V8 Bank 2 2.5V I/O NET "No_Conn_BSPT_Pin_V8" LOC = "V8" // IP_2 # No Connect BSPT Pin R8 Bank 2 2.5V In-Only NET "No_Conn_BSPT_Pin_R8" LOC = "R8" // IO_L02P_3 # Spare Conn BSPT Pin B1 Bank 3 3.3V I/O NET "SPR_Conn_BSPT_Pin_B1" LOC = "B1" // IP_L11P_3 # Spare Conn BSPT Pin J8 Bank 3 3.3V In-Only NET "SPR_Conn_BSPT_Pin_J8" LOC = "J8" // IP_L15P_3 # Spare Conn BSPT Pin K8 Bank 3 3.3V In-Only NET "SPR_Conn_BSPT_Pin_K8" LOC = "K8" // IP_L31P_3 # Spare Conn BSPT Pin M6 Bank 3 3.3V In-Only NET "SPR_Conn_BSPT_Pin_M6" LOC = "M6" // IP_L27N_3 # Spare Conn BSPT Pin M7 Bank 3 3.3V In-Only NET "SPR_Conn_BSPT_Pin_M7" LOC = "M7" // IP_L27P_3 # Spare Conn BSPT Pin M8 Bank 3 3.3V In-Only NET "SPR_Conn_BSPT_Pin_M8" LOC = "M8"