Date: Tue, 3 Dec 2013 16:44:05 -0500
To: Danny.Sekulovski@viasystems.com
Cc: cherrick@Debron-Electronics.com, Dennis.Hanley@viasystems.com,
    Todd.Henninger@viasystems.com, schell@Debron-Electronics.com,
    cracchiolo@Debron-Electronics.com, laurens@pa.msu.edu,
    Lynn.Majeed@viasystems.com, lsekulovski@ddiglobal.com,
    csingh@ddiglobal.com, kdpatel@ddiglobal.com, pariyana@ddiglobal.com
Subject: DEBRON  P/N: 40-00553-00LF, PO:63275, DDI Technical Query

Hello,

This note is our answers to the 8 points in the Technical
Query about manufacturing the bare CMX pcb.   This is
PO: 63275    Part: 40-00553-00LF    Sales Order: 173276-001

Thank you for your careful attention to the technical
details in manufacturing this pcb.

    Thanks,    Dan Edmunds  and  Philippe Laurens


Problem 1:  FYI

  Please note: Job has been set up using Green solder mask,
  White Idents and ENIG finish

Answer 1:

  The Green solder mask and White Idents are fine with us
  at MSU.

  We ask Debron to confirm that the ENIG finish is optimal
  for their SMD assembly process.


Problem 2:  Stackup

  Attacked stack-up for approval, changes made to facilitate
  balanced construction

Answer 2:

  We approve the stackup  Part Num: 40-00553-00LF
  that we received on  3-Dec-2013  from  Danny Sekulovski.

  We thank Danny Sekulovski at DDI for his work which
  appears to have substantially improved this stackup.


Problem 3:  Soldermask A/W Issues

  The 0.0236" vias (power connections not the connector) are
  covered by solder mask on both sides, these vias are too
  large to plug, request permission to add solder mask
  clearance of drill +.005" to prevent chemical entrapment
  during manufecturing

Answer 3:

  If exposing these vias through the Solder Mask is best
  for the pcb manufacturing process then please do so.

  While making this pcb design we covered all vias with
  Solder Mask because we thought  (evidently incorrectly)
  that this was the preferred setup for pcb manufacturing.
  Please advise us on the best way to handle the issue of
  exposing or not exposing the vias through the Solder Mask
  for our future designs.


Problem 4:  Netlist Problem

  No IPC netlist provided, please provide one or if
  not permission to generate one from supplied data

Answer 4:

  Please generate a netlist from the supplied data.


Problem 5:  Soldermask A/W Issues

  On comp side there is no mask clearances for SMT Pads
  see attached

Answer 5:

  Thank you for noting this.  This is how we want the pcb
  made.  This aspect of the CMX artwork is correct as is.


Problem 6:  Soldermask A/W Issues

  On solder side there is no mask clearances for SMT Pads
  see attached

Answer 6:

  Thank you for noting this.  This is how we want the pcb
  made.  This aspect of the CMX artwork is correct as is.


Problem 7: A/W Approval

  On both top and bottop layers there is isolated circuitry
  which will cause uneven plating distribution, request
  permission to add copper thieving in order to balance the
  copper, (thieving will be min 0.100" away from any feature
  and will be covered by mask)

Answer 7:

  Yes, please add the required thieving patterns.


Problem 8:

  Under the drill information section it stats all hole sizes
  are given as finished dia. yet drill table states Drill Size,
  we will consider "drill size" as finish size and apply a
  +/-.003" finished tolerance please advise

Answer 8:

  Yes, this tolerance sounds fine.  All diameters given in
  the   cmx_pcb_description.txt   file are finished size.
  It was my mistake to sometimes use the words "Drill Size"
  and at other times use the words "Hole Size".