# # CMX-0 Nets File # # Backplane LVDS Management Nets # --=========------------------------ # # # Original Rev. 1-Nov-2012 # Most Recent Rev. 4-Apr-2013 # # # # This file holds the nets involved in the management of the # Backplane LVDS Transceivers and Level Translators. # -------------- # # # The intent is to provide management of the backplane LVDS # connections so that the BF FPGA can independently choose # to Receive, Drive, or Ignore the 3 Backplane LVDS Cables. # # For each of the 3 Backplane LVDS Cables the intent is # that the BF_FPGA will have just 1 control signals, i.e. # a Direction signal signals. # # For each of the 3 Backplane LVDS Cables there will be # logic in the BSPT FPGA that take the direction request # signal from the BF FPGA and makes up the 3 control # signals that run to the Transceivers and Translators # for each Cable. The OE_B control signal to the # Translators goes through Hardwired Oversight Logic # that is between the BSPT and the Cable Translator # chips. # # The control to the OE_B pins to the Cable Translator # chips come from U363 in the Hardwired Oversight Logic. # # These OE_B signals to the Translator chips are named: # # CABLE_1_TRNSLT_OE_B # CABLE_2_TRNSLT_OE_B # CABLE_3_TRNSLT_OE_B # # These control signals originate in the BSPT FPGA but # pass through the Hardwired Oversight Logic on their # way to the OE_B pins on the Cable Translator chips. # As these signals come out of the BSPT FPGA that # are named: # # BSPT_CABLE_1_TRNSLT_OE_B # BSPT_CABLE_2_TRNSLT_OE_B # BSPT_CABLE_3_TRNSLT_OE_B # # # The UPPER set of Backplane LVDS management signals # ------- -------------- NET 'CABLE_1_TRNSLT_DIR' U42-1 U42-24 # Direction of 2V5<->3V3 Translators NET 'CABLE_1_TRNSLT_DIR' U43-1 U43-24 # Direction of 2V5<->3V3 Translators NET 'CABLE_1_TRNSLT_OE_B' U42-25 U42-48 # Output Enable Bar of Translators NET 'CABLE_1_TRNSLT_OE_B' U43-25 U43-48 # Output Enable Bar of Translators NET 'CABLE_1_TRNCVR_DIR' U21-13 U21-15 U21-26 U21-28 # Receiver Enb_B NET 'CABLE_1_TRNCVR_DIR' U22-13 U22-15 U22-26 U22-28 # Receiver Enb_B NET 'CABLE_1_TRNCVR_DIR' U23-13 U23-15 U23-26 U23-28 # Receiver Enb_B NET 'CABLE_1_TRNCVR_DIR' U24-13 U24-15 U24-26 U24-28 # Receiver Enb_B NET 'CABLE_1_TRNCVR_DIR' U25-13 U25-15 U25-26 U25-28 # Receiver Enb_B NET 'CABLE_1_TRNCVR_DIR' U26-13 U26-15 U26-26 U26-28 # Receiver Enb_B NET 'CABLE_1_TRNCVR_DIR' U27-13 U27-15 U27-26 U27-28 # Receiver Enb_B NET 'CABLE_1_TRNCVR_DIR' U21-14 U21-16 U21-25 U21-27 # Driver Enable NET 'CABLE_1_TRNCVR_DIR' U22-14 U22-16 U22-25 U22-27 # Driver Enable NET 'CABLE_1_TRNCVR_DIR' U23-14 U23-16 U23-25 U23-27 # Driver Enable NET 'CABLE_1_TRNCVR_DIR' U24-14 U24-16 U24-25 U24-27 # Driver Enable NET 'CABLE_1_TRNCVR_DIR' U25-14 U25-16 U25-25 U25-27 # Driver Enable NET 'CABLE_1_TRNCVR_DIR' U26-14 U26-16 U26-25 U26-27 # Driver Enable NET 'CABLE_1_TRNCVR_DIR' U27-14 U27-16 U27-25 U27-27 # Driver Enable NET 'BACK_UPPER_LVDS_FAILSAFE' U21-9 U21-32 U22-9 U22-32 # Receiver Failsafe NET 'BACK_UPPER_LVDS_FAILSAFE' U23-9 U23-32 U24-9 U24-32 # Receiver Failsafe NET 'BACK_UPPER_LVDS_FAILSAFE' U25-9 U25-32 U26-9 U26-32 # Receiver Failsafe NET 'BACK_UPPER_LVDS_FAILSAFE' U27-9 U27-32 # Receiver Failsafe NET 'BACK_UPPER_LVDS_MASTER_ENB' U21-10 U22-10 U23-10 U24-10 # Trncvr Master Enable NET 'BACK_UPPER_LVDS_MASTER_ENB' U25-10 U26-10 U27-10 # Trncvr Master Enable # The MIDDLE set of Backplane LVDS management signals # -------- -------------- NET 'CABLE_2_TRNSLT_DIR' U44-1 U44-24 # Direction of 2V5<->3V3 Translators NET 'CABLE_2_TRNSLT_DIR' U45-1 U45-24 # Direction of 2V5<->3V3 Translators NET 'CABLE_2_TRNSLT_OE_B' U44-25 U44-48 # Output Enable Bar of Translators NET 'CABLE_2_TRNSLT_OE_B' U45-25 U45-48 # Output Enable Bar of Translators NET 'CABLE_2_TRNCVR_DIR' U28-13 U28-15 U28-26 U28-28 # Receiver Enb_B NET 'CABLE_2_TRNCVR_DIR' U29-13 U29-15 U29-26 U29-28 # Receiver Enb_B NET 'CABLE_2_TRNCVR_DIR' U30-13 U30-15 U30-26 U30-28 # Receiver Enb_B NET 'CABLE_2_TRNCVR_DIR' U31-13 U31-15 U31-26 U31-28 # Receiver Enb_B NET 'CABLE_2_TRNCVR_DIR' U32-13 U32-15 U32-26 U32-28 # Receiver Enb_B NET 'CABLE_2_TRNCVR_DIR' U33-13 U33-15 U33-26 U33-28 # Receiver Enb_B NET 'CABLE_2_TRNCVR_DIR' U34-13 U34-15 U34-26 U34-28 # Receiver Enb_B NET 'CABLE_2_TRNCVR_DIR' U28-14 U28-16 U28-25 U28-27 # Driver Enable NET 'CABLE_2_TRNCVR_DIR' U29-14 U29-16 U29-25 U29-27 # Driver Enable NET 'CABLE_2_TRNCVR_DIR' U30-14 U30-16 U30-25 U30-27 # Driver Enable NET 'CABLE_2_TRNCVR_DIR' U31-14 U31-16 U31-25 U31-27 # Driver Enable NET 'CABLE_2_TRNCVR_DIR' U32-14 U32-16 U32-25 U32-27 # Driver Enable NET 'CABLE_2_TRNCVR_DIR' U33-14 U33-16 U33-25 U33-27 # Driver Enable NET 'CABLE_2_TRNCVR_DIR' U34-14 U34-16 U34-25 U34-27 # Driver Enable NET 'BACK_MIDDLE_LVDS_FAILSAFE' U28-9 U28-32 U29-9 U29-32 # Receiver Failsafe NET 'BACK_MIDDLE_LVDS_FAILSAFE' U30-9 U30-32 U31-9 U31-32 # Receiver Failsafe NET 'BACK_MIDDLE_LVDS_FAILSAFE' U32-9 U32-32 U33-9 U33-32 # Receiver Failsafe NET 'BACK_MIDDLE_LVDS_FAILSAFE' U34-9 U34-32 # Receiver Failsafe NET 'BACK_MIDDLE_LVDS_MASTER_ENB' U28-10 U29-10 U30-10 U31-10 # Trncvr Master Enable NET 'BACK_MIDDLE_LVDS_MASTER_ENB' U32-10 U33-10 U34-10 # Trncvr Master Enable # The LOWER set of Backplane LVDS management signals # ------- -------------- NET 'CABLE_3_TRNSLT_DIR' U46-1 U46-24 # Direction of 2V5<->3V3 Translators NET 'CABLE_3_TRNSLT_DIR' U47-1 U47-24 # Direction of 2V5<->3V3 Translators NET 'CABLE_3_TRNSLT_OE_B' U46-25 U46-48 # Output Enable Bar of Translators NET 'CABLE_3_TRNSLT_OE_B' U47-25 U47-48 # Output Enable Bar of Translators NET 'CABLE_3_TRNCVR_DIR' U35-13 U35-15 U35-26 U35-28 # Receiver Enb_B NET 'CABLE_3_TRNCVR_DIR' U36-13 U36-15 U36-26 U36-28 # Receiver Enb_B NET 'CABLE_3_TRNCVR_DIR' U37-13 U37-15 U37-26 U37-28 # Receiver Enb_B NET 'CABLE_3_TRNCVR_DIR' U38-13 U38-15 U38-26 U38-28 # Receiver Enb_B NET 'CABLE_3_TRNCVR_DIR' U39-13 U39-15 U39-26 U39-28 # Receiver Enb_B NET 'CABLE_3_TRNCVR_DIR' U40-13 U40-15 U40-26 U40-28 # Receiver Enb_B NET 'CABLE_3_TRNCVR_DIR' U41-13 U41-15 U41-26 U41-28 # Receiver Enb_B NET 'CABLE_3_TRNCVR_DIR' U35-14 U35-16 U35-25 U35-27 # Driver Enable NET 'CABLE_3_TRNCVR_DIR' U36-14 U36-16 U36-25 U36-27 # Driver Enable NET 'CABLE_3_TRNCVR_DIR' U37-14 U37-16 U37-25 U37-27 # Driver Enable NET 'CABLE_3_TRNCVR_DIR' U38-14 U38-16 U38-25 U38-27 # Driver Enable NET 'CABLE_3_TRNCVR_DIR' U39-14 U39-16 U39-25 U39-27 # Driver Enable NET 'CABLE_3_TRNCVR_DIR' U40-14 U40-16 U40-25 U40-27 # Driver Enable NET 'CABLE_3_TRNCVR_DIR' U41-14 U41-16 U41-25 U41-27 # Driver Enable NET 'BACK_LOWER_LVDS_FAILSAFE' U35-9 U35-32 U36-9 U36-32 # Receiver Failsafe NET 'BACK_LOWER_LVDS_FAILSAFE' U37-9 U37-32 U38-9 U38-32 # Receiver Failsafe NET 'BACK_LOWER_LVDS_FAILSAFE' U39-9 U39-32 U40-9 U40-32 # Receiver Failsafe NET 'BACK_LOWER_LVDS_FAILSAFE' U41-9 U41-32 # Receiver Failsafe NET 'BACK_LOWER_LVDS_MASTER_ENB' U35-10 U36-10 U37-10 U38-10 # Trncvr Master Enable NET 'BACK_LOWER_LVDS_MASTER_ENB' U39-10 U40-10 U41-10 # Trncvr Master Enable # # There are 2 functions of the DS91M040 LVDS Transceivers # that will be controlled only by the placement of # jumpers on the CMX card. These functions are: # Receiver Failsafe and Master_Enable # # Receiver Failsafe # # These are jumpers that pull the FSEN1 and FSEN2 pins # down to ground. There is a separate jumper for each # group of transceivers, i.e. the upper, middle, and # lower LVDS Cable transceivers. Normally we expect # all 3 of these jumpers to be installed so that all # 3 cables will have "Type 1" i.e. voltage symmetric # receivers. These 3 jumpers are reference designators # JMP 5, 6, and 7. JMP5 controlls the Upper Backplane # LVDS Cable receivers. JMP6 the Middle and JMP7 the # Lower LVDS Cable receivers. # NET 'BACK_UPPER_LVDS_FAILSAFE' JMP5-1 # Upper Cable Failsafe Jumper NET 'BACK_MIDDLE_LVDS_FAILSAFE' JMP6-1 # Middle Cable Failsafe Jumper NET 'BACK_LOWER_LVDS_FAILSAFE' JMP7-1 # Lower Cable Failsafe Jumper NET 'GROUND' JMP5-2 JMP6-2 JMP7-2 # Pull-Down to Ground # Master Enable # # When Master Enable is voltage HI then the DS91M040 # LVDS Transceiver will power up and operate. We expect # to always have these transceivers powered up. These # jumpers will actually be given resistor reference # designators on the CMX card because we never expect # to remove or change them. These will be nominal 1k # Ohm resistors from the Master Enable pin to BULK_3V3. # There will be a separate jumper (resistor) for each # group of tranceivers that services a cable, i.e. # upper, middle, or lower cables. R181 enables the # transceivers for the Upper Backplane LVDS Cable. # R182 the Middle and R183 the Lower Cable transceivers. NET 'BACK_UPPER_LVDS_MASTER_ENB' R181-1 # Lower Cable Trncvr Master Enable NET 'BACK_MIDDLE_LVDS_MASTER_ENB' R182-1 # Middle Cable Trncvr Master Enable NET 'BACK_LOWER_LVDS_MASTER_ENB' R183-1 # Upper Cable Trncvr Master Enable NET 'BULK_3V3' R181-2 R182-2 R183-2 # Pull-Up to 3.3 Volts