############################################################################################
#
#                            CMX Net-to-Resource File for the
#              Base Function FPGA IO signals used for the 400 Backplane Processor Inputs
#             -=============-------------------------------------------------------------
#
#
#     Original Rev. 26-Sep-2011 as separate PN files
#              Rev.  3-Nov-2011 merged and ordered into one file
#              Rev. 21-May-2012 rework assignment using paper and pencil
#              Rev. 22-Jun-2012 move P08-P11 and P12-P15 to inner column
#                               and reroute all while preserving all VREF and
#                               one set of VRP/VRN per group of 3 IO banks.
#              Rev. 25-Jun-2012 move P00-P03 from IO banks 36-37-38 to 35-36-37,
#                               move P4, P5, P6 clocks to remain at 2 clocks per H-row
#                              (and fix IO bank used for P5_21, P5_22, P7_00, P7_01)
#              Rev. 27-Jun-2012 fix typo from P12_17 BA29 <IO_L12N_VRP_22>
#                                          to P12_17 BA20 <IO_L8N_SRCC_32>
#              Rev. 29-Jun-2012 allow a few traces on top layer for P08-P11 group (banks 21-23)
#                               in order to only use 10 layers (top+9)
#              Rev. 10-Jul-2012 fix problem: a VREF signal had been assigned to P12_13
#              Rev. 12-Jul-2012 expunge information about "rank"
#              Rev. 20-Aug-2012 Assignment redone with corrected backplane pin order
#              Rev. 29-Aug-2012 switch P08-P11 to 11 layers, fixed P04-P07 template error
#              Rev. 07-Sep-2012 cosmetic changes to header comments
#              Rev. 12-Nov-2012 Complete re-think with a ring of vias and only 8 internal trace layers
#              Rev. 19-Nov-2012 Free up 4x SysMonit pairs on Bank 35 and 1x Global Clock pair on Bank 34
#              Rev. 28-Nov-2012 cross-check assignments and add via row and number
#              Rev: 11-Dec-2012 Cosmetic changes for uniformity and consistency between Base and TP files
#              Rev: 24-Jan-2013 Bug fix: Move P12_17 to bank 33 (was in 34) by swapping with P15_20
#              Rev: 28-Mar-2013 Move seven P14 and P15 signals to free the second Global Clock from Bank 34
#              Rev: 08-May-2013 Swap location of P8_0:2 to match the newly displaced vias
#              Rev: 17-May-2013 Rearrange P14_1,2,6:9 to solve layer 4 boundary conflict (P08:11 vs P12:14),
#                               swap P9_17 & _19 to better spread traces among via channels on layer 4
#                               and rearrange P12_18:21 to solve layer 9 boundary conflict (P08:11 vs P12:14)
#                               which also involved putting pin AV23 into use and dropping AY24
#  Most Recent Rev: 22-May-2013 Rearrange P6_8,9,10 to ease layer 3 trace density
#
#   Here we assign Base FPGA resources for the 400x Px_y backplane signals,
#   with x=0:15 corresponding to the relative source processor module (JEM or CPM) in the crate,
#   and y=0:24 corresponding to the signal index number from that processor source.
#   Each Px_24 signal carries the clock/parity signal from a given source processor board.
#   All Px_24 signals must be connected to a single ended regional clock resource pin
#   (i.e. a signal named IO_L9P_MRCC_nn or IO_L10P_MRCC_nn, nn being the IO block number)
#
#   Note: Trace layer information is appended as comments below.
#   -----
#
#   The Match Resource To Pin program will preserve this comment field, and append additional info.
#
#   NET   'P0_7'             U1-<IO_L17P_35>          #> F07 R1V3 #> T04 J1-A18  P00_07   D13
#
#                                  ^                   ^  ^   ^       ^   ^         ^      ^
#                                  |                   |  |   |       |   |         |      |
#   Virtex 6 Resource name --------+                   |  |   |       |   |         |      |
#   for Match_res2pin translation                      |  |   |       |   |         |      |
#                                                      |  |   |       |   |         |      |
#   Tailored comment flag to help with string searches +  |   |       |   |         |      |
#                                                         |   |       |   |         |      |
#   Target Trace Layer number to use for this net --------+   |       |   |         |      |
#   as it exits the FPGA (to a near via or the backplane)     |       |   |         |      |
#   F01 is top layer, F02 the first inner layer, etc          |       |   |         |      |
#                                                             |       |   |         |      |
#   When applicable: Via row (R1 is top row on sheet) --------+       |   |         |      |
#   and via number (V1 is leftmost) as determined in paper study      |   |         |      |
#                                                                     |   |         |      |
#   Target Trace Layer number to use for this net --------------------+   |         |      |
#   as it attaches to the backplane connector.                            |         |      |
#   T01 is top layer, T02 the first inner layer, etc                      |         |      |
#                                                                         |         |      |
#   Backplane Connector and Pin Number -----------------------------------+         |      |
#                                                                                   |      |
#   Net Name repeated to help manual entry of Pin Number ---------------------------+      |
#                                                                                          |
#   Target Pin Number read from paper drawing ---------------------------------------------+
#   and cross-checked after Match_Res2Pin
#
############################################################################################

#########################################################################################
#
# The Processor Inputs in P0-P1-P2-P3 use IO resources from banks 35-36-37
# P0_24  uses a regional clock in IO bank 35 on trace layer  9
# P1_24  uses a regional clock in IO bank 35 on trace layer  9
# P2_24  uses a regional clock in IO bank 37 on trace layer  4
# P3_24  uses a regional clock in IO bank 36 on trace layer  9
# The DCI master for this group is IO bank 36
#

NET   'P0_0'             U1-<IO_L16N_VRP_35>      #> F02      #> T02 J1-A11  P00_00   L11
NET   'P0_1'             U1-<IO_L18N_GC_35>       #> F02      #> T02 J1-A12  P00_01   M12
NET   'P0_2'             U1-<IO_L10N_MRCC_35>     #> F02      #> T02 J1-A13  P00_02   N13
NET   'P0_3'             U1-<IO_L9N_MRCC_35>      #> F02      #> T02 J1-A14  P00_03   N14
NET   'P0_4'             U1-<IO_L13N_SM6N_35>     #> F02      #> T02 J1-A15  P00_04   C14
NET   'P0_5'             U1-<IO_L18P_GC_35>       #> F04      #> T04 J1-A16  P00_05   L12
NET   'P0_6'             U1-<IO_L12P_SM5P_35>     #> F04      #> T04 J1-A17  P00_06   J13
NET   'P0_7'             U1-<IO_L17P_35>          #> F07 R1V3 #> T04 J1-A18  P00_07   D13
NET   'P0_8'             U1-<IO_L0N_35>           #> F07 R1V1 #> T04 J1-A19  P00_08   E12
NET   'P0_9'             U1-<IO_L4P_35>           #> F04      #> T04 J2-A1   P00_09   H14
NET   'P0_10'            U1-<IO_L19N_GC_35>       #> F04      #> T04 J2-A2   P00_10   F14
NET   'P0_11'            U1-<IO_L19P_36>          #> F06 R2V3 #> T04 J2-A3   P00_11   D17
NET   'P0_12'            U1-<IO_L1N_35>           #> F01 R2V4 #> T04 J2-A4   P00_12   B16
NET   'P0_13'            U1-<IO_L11N_SRCC_35>     #> F07 R2V1 #> T04 J2-A5   P00_13   F15
NET   'P0_14'            U1-<IO_L4P_36>           #> F04      #> T04 J2-A6   P00_14   J16
NET   'P0_15'            U1-<IO_L6N_36>           #> F04      #> T04 J2-A7   P00_15   J17
NET   'P0_16'            U1-<IO_L0P_36>           #> F04      #> T04 J2-A8   P00_16   K18
NET   'P0_17'            U1-<IO_L15P_36>          #> F01 R3V6 #> T04 J2-A9   P00_17   B18
NET   'P0_18'            U1-<IO_L5N_36>           #> F07 R3V3 #> T04 J2-A10  P00_18   E18
NET   'P0_19'            U1-<IO_L1N_36>           #> F07 R3V1 #> T04 J2-A11  P00_19   G18
NET   'P0_20'            U1-<IO_L0N_36>           #> F04      #> T04 J2-A12  P00_20   J18
NET   'P0_21'            U1-<IO_L3N_36>           #> F04      #> T04 J2-A13  P00_21   F19
NET   'P0_22'            U1-<IO_L19N_36>          #> F09 R4V4 #> T04 J2-A14  P00_22   E17
NET   'P0_23'            U1-<IO_L9P_MRCC_36>      #> F09 R4V2 #> T04 J2-A15  P00_23   P18
NET   'P0_24'            U1-<IO_L10P_MRCC_35>     #> F09      #> T09 J2-A16  P00_24   M13

NET   'P1_0'             U1-<IO_L14P_35>          #> F03      #> T03 J1-B15  P01_00   K14
NET   'P1_1'             U1-<IO_L8N_SRCC_35>      #> F09      #> T09 J1-C16  P01_01   J11
NET   'P1_2'             U1-<IO_L8P_SRCC_35>      #> F09      #> T09 J1-B17  P01_02   J12
NET   'P1_3'             U1-<IO_L0P_35>           #> F09      #> T09 J1-C18  P01_03   F12
NET   'P1_4'             U1-<IO_L13P_SM6P_35>     #> F01 R1V2 #> T05 J1-B19  P01_04   B14
NET   'P1_5'             U1-<IO_L5N_SM2N_35>      #> F01 R1V4 #> T05 J2-C1   P01_05   A14
NET   'P1_6'             U1-<IO_L12N_SM5N_35>     #> F03 R1V8 #> T05 J2-B2   P01_06   K13
NET   'P1_7'             U1-<IO_L16P_VRN_35>      #> F05      #> T05 J2-C3   P01_07   K12
NET   'P1_8'             U1-<IO_L17N_35>          #> F05      #> T05 J2-B4   P01_08   E13
NET   'P1_9'             U1-<IO_L2N_SM0N_35>      #> F05      #> T05 J2-C5   P01_09   G14
NET   'P1_10'            U1-<IO_L14P_36>          #> F05      #> T05 J2-B6   P01_10   J15
NET   'P1_11'            U1-<IO_L1P_35>           #> F01 R2V5 #> T05 J2-C7   P01_11   A16
NET   'P1_12'            U1-<IO_L5P_SM2P_35>      #> F01 R2V7 #> T05 J2-B8   P01_12   A15
NET   'P1_13'            U1-<IO_L19P_GC_35>       #> F07 R2V2 #> T05 J2-C9   P01_13   E14
NET   'P1_14'            U1-<IO_L2P_36>           #> F05      #> T05 J2-B10  P01_14   G16
NET   'P1_15'            U1-<IO_L11N_SRCC_36>     #> F05      #> T05 J2-C11  P01_15   G17
NET   'P1_16'            U1-<IO_L13P_36>          #> F06 R3V5 #> T05 J2-B12  P01_16   D18
NET   'P1_17'            U1-<IO_L2P_SM0P_35>      #> F09 R3V7 #> T05 J2-C13  P01_17   H15
NET   'P1_18'            U1-<IO_L11P_SRCC_35>     #> F07 R3V4 #> T05 J2-B14  P01_18   E15
NET   'P1_19'            U1-<IO_L2N_36>           #> F07 R3V2 #> T05 J2-C15  P01_19   F16
NET   'P1_20'            U1-<IO_L11P_SRCC_36>     #> F05      #> T05 J2-B16  P01_20   F17
NET   'P1_21'            U1-<IO_L1P_36>           #> F05      #> T05 J2-B17  P01_21   H18
NET   'P1_22'            U1-<IO_L15N_36>          #> F01 R4V6 #> T05 J2-B18  P01_22   A19
NET   'P1_23'            U1-<IO_L5P_36>           #> F05      #> T05 J2-C19  P01_23   E19
NET   'P1_24'            U1-<IO_L9P_MRCC_35>      #> F09      #> T09 J3-B1   P01_24   M14

NET   'P2_0'             U1-<IO_L16N_36>          #> F03      #> T03 J1-D15  P02_00   L15
NET   'P2_1'             U1-<IO_L16P_36>          #> F03      #> T03 J1-D16  P02_01   L16
NET   'P2_2'             U1-<IO_L17N_36>          #> F01 R2V6 #> T03 J1-C17  P02_02   B17
NET   'P2_3'             U1-<IO_L6P_36>           #> F03      #> T03 J1-D18  P02_03   K17
NET   'P2_4'             U1-<IO_L8P_SRCC_36>      #> F03      #> T03 J1-C19  P02_04   M18
NET   'P2_5'             U1-<IO_L18P_37>          #> F03      #> T03 J2-D1   P02_05   K19
NET   'P2_6'             U1-<IO_L3P_36>           #> F03      #> T03 J2-C2   P02_06   G19
NET   'P2_7'             U1-<IO_L12N_VRP_37>      #> F03      #> T03 J2-D3   P02_07   F20
NET   'P2_8'             U1-<IO_L8N_SRCC_37>      #> F03      #> T03 J2-C4   P02_08   G21
NET   'P2_9'             U1-<IO_L19P_37>          #> F09 R4V1 #> T03 J2-D5   P02_09   C20
NET   'P2_10'            U1-<IO_L15N_37>          #> F01 R4V3 #> T03 J2-C6   P02_10   A20
NET   'P2_11'            U1-<IO_L17P_37>          #> F01 R4V5 #> T03 J2-D7   P02_11   C21
NET   'P2_12'            U1-<IO_L6P_37>           #> F03      #> T03 J2-C8   P02_12   H21
NET   'P2_13'            U1-<IO_L2P_37>           #> F03      #> T03 J2-D9   P02_13   G22
NET   'P2_14'            U1-<IO_L7N_37>           #> F03      #> T03 J2-C10  P02_14   E23
NET   'P2_15'            U1-<IO_L5N_37>           #> F01 R5V2 #> T03 J2-D11  P02_15   B22
NET   'P2_16'            U1-<IO_L1P_37>           #> F01 R5V5 #> T03 J2-C12  P02_16   B24
NET   'P2_17'            U1-<IO_L1N_37>           #> F01 R5V3 #> T03 J2-D13  P02_17   A24
NET   'P2_18'            U1-<IO_L5P_37>           #> F01 R5V1 #> T03 J2-C14  P02_18   B23
NET   'P2_19'            U1-<IO_L11P_SRCC_37>     #> F03      #> T03 J2-D15  P02_19   D23
NET   'P2_20'            U1-<IO_L12P_VRN_37>      #> F04      #> T04 J2-C16  P02_20   E20
NET   'P2_21'            U1-<IO_L4P_37>           #> F04      #> T04 J2-D17  P02_21   F21
NET   'P2_22'            U1-<IO_L2N_37>           #> F04      #> T04 J2-C18  P02_22   F22
NET   'P2_23'            U1-<IO_L11N_SRCC_37>     #> F04      #> T04 J2-D19  P02_23   D22
NET   'P2_24'            U1-<IO_L10P_MRCC_37>     #> F04      #> T04 J3-C1   P02_24   J22

NET   'P3_0'             U1-<IO_L18N_36>          #> F02      #> T02 J1-E15  P03_00   N15
NET   'P3_1'             U1-<IO_L17P_36>          #> F01 R2V8 #> T02 J1-E16  P03_01   A17
NET   'P3_2'             U1-<IO_L18P_36>          #> F02      #> T02 J1-E17  P03_02   M16
NET   'P3_3'             U1-<IO_L9N_MRCC_36>      #> F02      #> T02 J1-E18  P03_03   P17
NET   'P3_4'             U1-<IO_L8N_SRCC_36>      #> F02      #> T02 J1-E19  P03_04   N18
NET   'P3_5'             U1-<IO_L13N_36>          #> F02      #> T02 J2-E1   P03_05   C18
NET   'P3_6'             U1-<IO_L18N_37>          #> F02      #> T02 J2-E2   P03_06   L19
NET   'P3_7'             U1-<IO_L7N_36>           #> F01 R3V8 #> T02 J2-E3   P03_07   B19
NET   'P3_8'             U1-<IO_L7P_36>           #> F02      #> T02 J2-E4   P03_08   C19
NET   'P3_9'             U1-<IO_L8P_SRCC_37>      #> F02      #> T02 J2-E5   P03_09   H20
NET   'P3_10'            U1-<IO_L14P_37>          #> F02      #> T02 J2-E6   P03_10   J20
NET   'P3_11'            U1-<IO_L17N_37>          #> F02      #> T02 J2-E7   P03_11   D21
NET   'P3_12'            U1-<IO_L6N_37>           #> F02      #> T02 J2-E8   P03_12   J21
NET   'P3_13'            U1-<IO_L13N_37>          #> F01 R4V8 #> T02 J2-E9   P03_13   A21
NET   'P3_14'            U1-<IO_L9P_MRCC_37>      #> F02      #> T02 J2-E10  P03_14   L22
NET   'P3_15'            U1-<IO_L10N_MRCC_37>     #> F02      #> T02 J2-E11  P03_15   K22
NET   'P3_16'            U1-<IO_L0P_37>           #> F02      #> T02 J2-E12  P03_16   G23
NET   'P3_17'            U1-<IO_L3N_37>           #> F02      #> T02 J2-E13  P03_17   C23
NET   'P3_18'            U1-<IO_L13P_37>          #> F01 R5V4 #> T02 J2-E14  P03_18   A22
NET   'P3_19'            U1-<IO_L15P_37>          #> F01 R5V8 #> T02 J2-E15  P03_19   B21
NET   'P3_20'            U1-<IO_L0N_37>           #> F02      #> T02 J2-E16  P03_20   H23
NET   'P3_21'            U1-<IO_L3P_37>           #> F02      #> T02 J2-E17  P03_21   C24
NET   'P3_22'            U1-<IO_L7P_37>           #> F02      #> T02 J2-E18  P03_22   E24
NET   'P3_23'            U1-<IO_L19N_37>          #> F05      #> T05 J2-E19  P03_23   D20
NET   'P3_24'            U1-<IO_L10P_MRCC_36>     #> F09      #> T09 J3-E1   P03_24   N16

NET   'P0TO3_DCI_P'      U1-<IO_L12N_VRP_36>                  #> T08                  M17
NET   'P0TO3_DCI_N'      U1-<IO_L12P_VRN_36>                  #> T08                  L17

NET   'VREF_P'           U1-<IO_L4N_VREF_35>                  #> T08                  G13
NET   'VREF_P'           U1-<IO_L14N_VREF_35>                 #> T08                  L14
NET   'VREF_P'           U1-<IO_L4N_VREF_36>                  #> T08                  H16
NET   'VREF_P'           U1-<IO_L14N_VREF_36>                 #> T08                  K15
NET   'VREF_P'           U1-<IO_L4N_VREF_37>                  #> T08                  E22
NET   'VREF_P'           U1-<IO_L14N_VREF_37>                 #> T08                  H19


#########################################################################################
#
# The Processor Inputs in P4-P5-P6-P7 use IO resources from banks 26-27-28
# P4_24  uses a regional clock in IO bank 28 on trace layer  9
# P5_24  uses a regional clock in IO bank 28 on trace layer  9
# P6_24  uses a regional clock in IO bank 26 on trace layer  5
# P7_24  uses a regional clock in IO bank 27 on trace layer  9
# The DCI master for this group is IO bank 28
#

NET   'P4_0'             U1-<IO_L10N_MRCC_28>     #> F02      #> T02 J3-A1   P04_00   N25
NET   'P4_1'             U1-<IO_L19P_28>          #> F02      #> T02 J3-A2   P04_01   M26
NET   'P4_2'             U1-<IO_L18P_28>          #> F02      #> T02 J3-A3   P04_02   L27
NET   'P4_3'             U1-<IO_L14P_28>          #> F02      #> T02 J3-A4   P04_03   H28
NET   'P4_4'             U1-<IO_L15N_28>          #> F02      #> T02 J3-A5   P04_04   C29
NET   'P4_5'             U1-<IO_L10N_MRCC_27>     #> F02      #> T02 J3-A6   P04_05   M29
NET   'P4_6'             U1-<IO_L3P_28>           #> F02      #> T02 J3-A7   P04_06   E30
NET   'P4_7'             U1-<IO_L5P_28>           #> F02      #> T02 J3-A8   P04_07   C31
NET   'P4_8'             U1-<IO_L6P_27>           #> F02      #> T02 J3-A9   P04_08   H31
NET   'P4_9'             U1-<IO_L8N_SRCC_27>      #> F02      #> T02 J3-A10  P04_09   G32
NET   'P4_10'            U1-<IO_L3N_27>           #> F02      #> T02 J3-A11  P04_10   C33
NET   'P4_11'            U1-<IO_L12P_VRN_27>      #> F02      #> T02 J3-A12  P04_11   H33
NET   'P4_12'            U1-<IO_L9N_MRCC_28>      #> F03 R1V2 #> T05 J3-A13  P04_12   L25
NET   'P4_13'            U1-<IO_L0N_28>           #> F03 R1V4 #> T05 J3-A14  P04_13   J26
NET   'P4_14'            U1-<IO_L17N_28>          #> F01 R1V5 #> T05 J3-A15  P04_14   A30
NET   'P4_15'            U1-<IO_L15P_28>          #> F01 R1V3 #> T05 J3-A16  P04_15   B29
NET   'P4_16'            U1-<IO_L17P_28>          #> F01 R1V1 #> T05 J3-A17  P04_16   A29
NET   'P4_17'            U1-<IO_L11P_SRCC_28>     #> F05      #> T05 J3-A18  P04_17   F27
NET   'P4_18'            U1-<IO_L1P_28>           #> F05      #> T05 J3-A19  P04_18   D28
NET   'P4_19'            U1-<IO_L1N_28>           #> F05      #> T05 J4-A1   P04_19   E29
NET   'P4_20'            U1-<IO_L7P_28>           #> F05      #> T05 J4-A2   P04_20   C30
NET   'P4_21'            U1-<IO_L5N_28>           #> F05      #> T05 J4-A3   P04_21   D31
NET   'P4_22'            U1-<IO_L0N_27>           #> F05      #> T05 J4-A4   P04_22   D32
NET   'P4_23'            U1-<IO_L11P_SRCC_27>     #> F05      #> T05 J4-A5   P04_23   D33
NET   'P4_24'            U1-<IO_L10P_MRCC_28>     #> F09      #> T09 J4-A6   P04_24   N24

NET   'P5_0'             U1-<IO_L2P_28>           #> F03      #> T03 J3-C2   P05_00   G28
NET   'P5_1'             U1-<IO_L6N_28>           #> F04      #> T04 J3-B3   P05_01   P23
NET   'P5_2'             U1-<IO_L6P_28>           #> F04      #> T04 J3-C4   P05_02   R23
NET   'P5_3'             U1-<IO_L8N_SRCC_28>      #> F04      #> T04 J3-B5   P05_03   P25
NET   'P5_4'             U1-<IO_L13P_28>          #> F01 R1V8 #> T04 J3-C6   P05_04   A31
NET   'P5_5'             U1-<IO_L18N_28>          #> F03 R1V6 #> T04 J3-B7   P05_05   K27
NET   'P5_6'             U1-<IO_L0P_28>           #> F04      #> T04 J3-C8   P05_06   J27
NET   'P5_7'             U1-<IO_L2N_28>           #> F04      #> T04 J3-B9   P05_07   G27
NET   'P5_8'             U1-<IO_L11N_SRCC_28>     #> F04      #> T04 J3-C10  P05_08   E28
NET   'P5_9'             U1-<IO_L13N_28>          #> F01 R2V7 #> T04 J3-B11  P05_09   B31
NET   'P5_10'            U1-<IO_L2P_27>           #> F03 R2V8 #> T04 J3-C12  P05_10   F32
NET   'P5_11'            U1-<IO_L6N_27>           #> F03 R2V6 #> T04 J3-B13  P05_11   G31
NET   'P5_12'            U1-<IO_L4P_28>           #> F04      #> T04 J3-C14  P05_12   G29
NET   'P5_13'            U1-<IO_L7N_28>           #> F04      #> T04 J3-B15  P05_13   D30
NET   'P5_14'            U1-<IO_L2N_27>           #> F04      #> T04 J3-C16  P05_14   F31
NET   'P5_15'            U1-<IO_L13P_27>          #> F01 R3V7 #> T04 J3-B17  P05_15   A36
NET   'P5_16'            U1-<IO_L13N_27>          #> F01 R3V8 #> T04 J3-C18  P05_16   B36
NET   'P5_17'            U1-<IO_L5N_27>           #> F01 R3V6 #> T04 J3-B19  P05_17   A35
NET   'P5_18'            U1-<IO_L0P_27>           #> F04      #> T04 J4-C1   P05_18   E32
NET   'P5_19'            U1-<IO_L11N_SRCC_27>     #> F04      #> T04 J4-B2   P05_19   E33
NET   'P5_20'            U1-<IO_L17P_27>          #> F04      #> T04 J4-C3   P05_20   E34
NET   'P5_21'            U1-<IO_L4P_27>           #> F04      #> T04 J4-B4   P05_21   E35
NET   'P5_22'            U1-<IO_L19P_27>          #> F04      #> T04 J4-C5   P05_22   D36
NET   'P5_23'            U1-<IO_L19N_27>          #> F04      #> T04 J4-B6   P05_23   D37
NET   'P5_24'            U1-<IO_L9P_MRCC_28>      #> F09      #> T09 J4-C7   P05_24   L26

NET   'P6_0'             U1-<IO_L1N_26>           #> F01 R4V1 #> T03 J3-D2   P06_00   A37
NET   'P6_1'             U1-<IO_L15P_27>          #> F05 R4V3 #> T03 J3-C3   P06_01   C35
NET   'P6_2'             U1-<IO_L10N_MRCC_26>     #> F05 R4V5 #> T03 J3-D4   P06_02   F36
NET   'P6_3'             U1-<IO_L3N_26>           #> F01 R4V6 #> T03 J3-C5   P06_03   A39
NET   'P6_4'             U1-<IO_L3P_26>           #> F01 R4V4 #> T03 J3-D6   P06_04   B38
NET   'P6_5'             U1-<IO_L1P_26>           #> F01 R4V2 #> T03 J3-C7   P06_05   B37
NET   'P6_6'             U1-<IO_L0N_26>           #> F03      #> T03 J3-D8   P06_06   G36
NET   'P6_7'             U1-<IO_L4P_26>           #> F03      #> T03 J3-C9   P06_07   F37
NET   'P6_8'             U1-<IO_L18N_26>          #> F01 R5V3 #> T03 J3-D10  P06_08   G42
NET   'P6_9'             U1-<IO_L19N_26>          #> F01 R5V5 #> T03 J3-C11  P06_09   F42
NET   'P6_10'            U1-<IO_L19P_26>          #> F01 R5V4 #> T03 J3-D12  P06_10   E42
NET   'P6_11'            U1-<IO_L7N_26>           #> F01 R5V2 #> T03 J3-C13  P06_11   A41
NET   'P6_12'            U1-<IO_L7P_26>           #> F01 R5V1 #> T03 J3-D14  P06_12   A40
NET   'P6_13'            U1-<IO_L6P_26>           #> F03      #> T03 J3-C15  P06_13   D38
NET   'P6_14'            U1-<IO_L5P_26>           #> F03      #> T03 J3-D16  P06_14   B39
NET   'P6_15'            U1-<IO_L5N_26>           #> F03      #> T03 J3-C17  P06_15   C39
NET   'P6_16'            U1-<IO_L13P_26>          #> F03      #> T03 J3-D18  P06_16   C40
NET   'P6_17'            U1-<IO_L11P_SRCC_26>     #> F03      #> T03 J3-C19  P06_17   B41
NET   'P6_18'            U1-<IO_L13N_26>          #> F03      #> T03 J4-D1   P06_18   C41
NET   'P6_19'            U1-<IO_L15N_26>          #> F03      #> T03 J4-C2   P06_19   D41
NET   'P6_20'            U1-<IO_L17N_26>          #> F03      #> T03 J4-D3   P06_20   E40
NET   'P6_21'            U1-<IO_L16P_26>          #> F03      #> T03 J4-C4   P06_21   F40
NET   'P6_22'            U1-<IO_L16N_26>          #> F03      #> T03 J4-D5   P06_22   F41
NET   'P6_23'            U1-<IO_L18P_26>          #> F03      #> T03 J4-C6   P06_23   G41
NET   'P6_24'            U1-<IO_L9P_MRCC_26>      #> F05      #> T05 J4-D7   P06_24   G34

NET   'P7_0'             U1-<IO_L18P_27>          #> F03 R2V2 #> T09 J3-E2   P07_00   K29
NET   'P7_1'             U1-<IO_L16P_27>          #> F03 R2V4 #> T09 J3-E3   P07_01   H30
NET   'P7_2'             U1-<IO_L3P_27>           #> F01 R2V5 #> T09 J3-E4   P07_02   B33
NET   'P7_3'             U1-<IO_L1N_27>           #> F01 R2V3 #> T09 J3-E5   P07_03   B32
NET   'P7_4'             U1-<IO_L1P_27>           #> F01 R2V1 #> T09 J3-E6   P07_04   A32
NET   'P7_5'             U1-<IO_L5P_27>           #> F01 R3V2 #> T09 J3-E7   P07_05   A34
NET   'P7_6'             U1-<IO_L7P_27>           #> F01 R3V4 #> T09 J3-E8   P07_06   B34
NET   'P7_7'             U1-<IO_L10P_MRCC_26>     #> F03 R3V5 #> T09 J3-E9   P07_07   F35
NET   'P7_8'             U1-<IO_L17N_27>          #> F03 R3V3 #> T09 J3-E10  P07_08   F34
NET   'P7_9'             U1-<IO_L8P_SRCC_27>      #> F03 R3V1 #> T09 J3-E11  P07_09   G33
NET   'P7_10'            U1-<IO_L7N_27>           #> F02      #> T02 J3-E12  P07_10   C34
NET   'P7_11'            U1-<IO_L9N_MRCC_26>      #> F02      #> T02 J3-E13  P07_11   H34
NET   'P7_12'            U1-<IO_L2N_26>           #> F02      #> T02 J3-E14  P07_12   H35
NET   'P7_13'            U1-<IO_L15N_27>          #> F02      #> T02 J3-E15  P07_13   C36
NET   'P7_14'            U1-<IO_L0P_26>           #> F02      #> T02 J3-E16  P07_14   H36
NET   'P7_15'            U1-<IO_L14P_26>          #> F02      #> T02 J3-E17  P07_15   G37
NET   'P7_16'            U1-<IO_L6N_26>           #> F02      #> T02 J3-E18  P07_16   C38
NET   'P7_17'            U1-<IO_L8N_SRCC_26>      #> F02      #> T02 J3-E19  P07_17   E38
NET   'P7_18'            U1-<IO_L17P_26>          #> F02      #> T02 J4-E1   P07_18   D40
NET   'P7_19'            U1-<IO_L11N_SRCC_26>     #> F02      #> T02 J4-E2   P07_19   B42
NET   'P7_20'            U1-<IO_L15P_26>          #> F02      #> T02 J4-E3   P07_20   D42
NET   'P7_21'            U1-<IO_L8P_SRCC_26>      #> F02      #> T02 J4-E4   P07_21   E39
NET   'P7_22'            U1-<IO_L12P_VRN_26>      #> F02      #> T02 J4-E5   P07_22   F39
NET   'P7_23'            U1-<IO_L12N_VRP_26>      #> F02      #> T02 J4-E6   P07_23   G39
NET   'P7_24'            U1-<IO_L9P_MRCC_27>      #> F09      #> T09 J4-E7   P07_24   L29

NET   'P4TO7_DCI_P'      U1-<IO_L12N_VRP_28>                  #> T08                  N26
NET   'P4TO7_DCI_N'      U1-<IO_L12P_VRN_28>                  #> T08                  P26

NET   'VREF_P'           U1-<IO_L4N_VREF_26>                  #> T08                  E37
NET   'VREF_P'           U1-<IO_L14N_VREF_26>                 #> T08                  G38
NET   'VREF_P'           U1-<IO_L4N_VREF_27>                  #> T08                  D35
NET   'VREF_P'           U1-<IO_L14N_VREF_27>                 #> T08                  J31
NET   'VREF_P'           U1-<IO_L4N_VREF_28>                  #> T08                  F29
NET   'VREF_P'           U1-<IO_L14N_VREF_28>                 #> T08                  H29


#########################################################################################
#
# The Processor Inputs in P8-P9-P10-P11 use IO resources from banks 21-22-23
# P8_24  uses a regional clock in IO bank 22 on trace layer  9
# P9_24  uses a regional clock in IO bank 23 on trace layer  9
# P10_24 uses a regional clock in IO bank 21 on trace layer  9
# P11_24 uses a regional clock in IO bank 21 on trace layer  9
# The DCI master for this group is IO bank 23
#

NET   'P8_0'             U1-<IO_L6P_22>           #> F01 R1V5 #> T02 J5-A14  P08_00  BA32
NET   'P8_1'             U1-<IO_L14P_22>          #> F01 R1V8 #> T02 J5-A15  P08_01  BB33
NET   'P8_2'             U1-<IO_L16P_22>          #> F01 R1V6 #> T02 J5-A16  P08_02  BA31
NET   'P8_3'             U1-<IO_L19P_23>          #> F06 R1V3 #> T02 J5-A17  P08_03  AV33
NET   'P8_4'             U1-<IO_L19N_23>          #> F06 R1V1 #> T02 J5-A18  P08_04  AW33
NET   'P8_5'             U1-<IO_L3P_23>           #> F02      #> T02 J5-A19  P08_05  AM33
NET   'P8_6'             U1-<IO_L3N_23>           #> F02      #> T02 J5-A20  P08_06  AM32
NET   'P8_7'             U1-<IO_L12N_VRP_22>      #> F01 R2V8 #> T02 J5-A21  P08_07  BA29
NET   'P8_8'             U1-<IO_L4P_22>           #> F02      #> T02 J5-A22  P08_08  AY32
NET   'P8_9'             U1-<IO_L1P_23>           #> F02      #> T02 J5-A23  P08_09  AM31
NET   'P8_10'            U1-<IO_L2N_23>           #> F02      #> T02 J5-A24  P08_10  AL30
NET   'P8_11'            U1-<IO_L8N_SRCC_22>      #> F02      #> T02 J5-A25  P08_11  AY30
NET   'P8_12'            U1-<IO_L8N_SRCC_23>      #> F02      #> T02 J6-A1   P08_12  AK29
NET   'P8_13'            U1-<IO_L12P_VRN_22>      #> F02      #> T02 J6-A2   P08_13  AY29
NET   'P8_14'            U1-<IO_L6N_23>           #> F02      #> T02 J6-A3   P08_14  AM28
NET   'P8_15'            U1-<IO_L16P_23>          #> F02      #> T02 J6-A4   P08_15  AK27
NET   'P8_16'            U1-<IO_L5N_23>           #> F09      #> T09 J6-A5   P08_16  AN34
NET   'P8_17'            U1-<IO_L17P_23>          #> F09      #> T09 J6-A6   P08_17  AU33
NET   'P8_18'            U1-<IO_L17N_23>          #> F09      #> T09 J6-A7   P08_18  AU32
NET   'P8_19'            U1-<IO_L13N_22>          #> F09      #> T09 J6-A8   P08_19  AU31
NET   'P8_20'            U1-<IO_L7P_22>           #> F09      #> T09 J6-A9   P08_20  AT30
NET   'P8_21'            U1-<IO_L5P_22>           #> F09      #> T09 J6-A10  P08_21  AT29
NET   'P8_22'            U1-<IO_L10P_MRCC_22>     #> F09      #> T09 J6-A11  P08_22  AN28
NET   'P8_23'            U1-<IO_L11P_SRCC_22>     #> F09      #> T09 J6-A12  P08_23  AR27
NET   'P8_24'            U1-<IO_L9P_MRCC_22>      #> F09      #> T09 J6-A13  P08_24  AM26

NET   'P9_0'             U1-<IO_L15P_23>          #> F05      #> T05 J5-B23  P09_00  AR33
NET   'P9_1'             U1-<IO_L15N_23>          #> F05      #> T05 J5-B24  P09_01  AT32
NET   'P9_2'             U1-<IO_L11P_SRCC_23>     #> F03      #> T03 J5-B25  P09_02  AR34
NET   'P9_3'             U1-<IO_L5P_23>           #> F03      #> T03 J6-C1   P09_03  AN33
NET   'P9_4'             U1-<IO_L13P_23>          #> F03      #> T03 J6-B2   P09_04  AP32
NET   'P9_5'             U1-<IO_L2P_22>           #> F07 R2V5 #> T03 J6-C3   P09_05  AW31
NET   'P9_6'             U1-<IO_L16N_22>          #> F01 R2V7 #> T03 J6-B4   P09_06  BB31
NET   'P9_7'             U1-<IO_L8P_SRCC_22>      #> F01 R2V6 #> T03 J6-C5   P09_07  BA30
NET   'P9_8'             U1-<IO_L7N_23>           #> F03      #> T03 J6-B6   P09_08  AN31
NET   'P9_9'             U1-<IO_L0N_23>           #> F03      #> T03 J6-C7   P09_09  AN30
NET   'P9_10'            U1-<IO_L2P_23>           #> F03      #> T03 J6-B8   P09_10  AL29
NET   'P9_11'            U1-<IO_L15N_22>          #> F07 R3V4 #> T03 J6-C9   P09_11  AV29
NET   'P9_12'            U1-<IO_L18N_22>          #> F01 R3V6 #> T03 J6-B10  P09_12  BB28
NET   'P9_13'            U1-<IO_L17N_22>          #> F06 R3V2 #> T03 J6-C11  P09_13  AV28
NET   'P9_14'            U1-<IO_L3N_22>           #> F03      #> T03 J6-B12  P09_14  AP28
NET   'P9_15'            U1-<IO_L6P_23>           #> F03      #> T03 J6-C13  P09_15  AL27
NET   'P9_16'            U1-<IO_L11N_SRCC_23>     #> F04      #> T04 J6-B14  P09_16  AP33
NET   'P9_17'            U1-<IO_L13N_23>          #> F07 R2V4 #> T04 J6-C15  P09_17  AR32
NET   'P9_18'            U1-<IO_L0N_22>           #> F06 R2V2 #> T04 J6-B16  P09_18  AV30
NET   'P9_19'            U1-<IO_L0P_22>           #> F04      #> T04 J6-C17  P09_19  AW30
NET   'P9_20'            U1-<IO_L7P_23>           #> F04      #> T04 J6-B18  P09_20  AP31
NET   'P9_21'            U1-<IO_L0P_23>           #> F04      #> T04 J6-C19  P09_21  AP30
NET   'P9_22'            U1-<IO_L4P_23>           #> F04      #> T04 J7-B1   P09_22  AN29
NET   'P9_23'            U1-<IO_L3P_22>           #> F04      #> T04 J7-B2   P09_23  AR28
NET   'P9_24'            U1-<IO_L9P_MRCC_23>      #> F09      #> T09 J7-B3   P09_24  AJ25

NET   'P10_0'            U1-<IO_L6N_22>           #> F07 R1V4 #> T05 J6-D6   P10_00  AY33
NET   'P10_1'            U1-<IO_L2N_22>           #> F06 R1V2 #> T05 J6-D7   P10_01  AV31
NET   'P10_2'            U1-<IO_L13P_22>          #> F05      #> T05 J6-D8   P10_02  AT31
NET   'P10_3'            U1-<IO_L7N_22>           #> F05      #> T05 J6-D9   P10_03  AR30
NET   'P10_4'            U1-<IO_L5N_22>           #> F05      #> T05 J6-C10  P10_04  AR29
NET   'P10_5'            U1-<IO_L15P_22>          #> F06 R2V3 #> T05 J6-D11  P10_05  AU29
NET   'P10_6'            U1-<IO_L17P_22>          #> F05      #> T05 J6-C12  P10_06  AU28
NET   'P10_7'            U1-<IO_L1N_22>           #> F05      #> T05 J6-D13  P10_07  AP27
NET   'P10_8'            U1-<IO_L11N_SRCC_22>     #> F06 R3V1 #> T05 J6-C14  P10_08  AT27
NET   'P10_9'            U1-<IO_L0N_21>           #> F06 R3V3 #> T05 J6-D15  P10_09  AU27
NET   'P10_10'           U1-<IO_L19P_22>          #> F07 R3V5 #> T05 J6-C16  P10_10  AW28
NET   'P10_11'           U1-<IO_L18P_22>          #> F01 R3V8 #> T05 J6-D17  P10_11  BB29
NET   'P10_12'           U1-<IO_L16P_21>          #> F05      #> T05 J6-C18  P10_12  AV26
NET   'P10_13'           U1-<IO_L16N_21>          #> F05      #> T05 J6-D19  P10_13  AU26
NET   'P10_14'           U1-<IO_L10N_MRCC_21>     #> F02 R4V1 #> T05 J7-D1   P10_14  AL25
NET   'P10_15'           U1-<IO_L18P_21>          #> F06 R4V3 #> T05 J7-C2   P10_15  AW25
NET   'P10_16'           U1-<IO_L2N_21>           #> F07 R4V5 #> T05 J7-D3   P10_16  AW27
NET   'P10_17'           U1-<IO_L6P_21>           #> F01 R4V8 #> T05 J7-C4   P10_17  BB26
NET   'P10_18'           U1-<IO_L12N_VRP_21>      #> F05      #> T05 J7-D5   P10_18  AV25
NET   'P10_19'           U1-<IO_L8N_SRCC_21>      #> F05      #> T05 J7-C6   P10_19  AU24
NET   'P10_20'           U1-<IO_L11N_SRCC_21>     #> F05      #> T05 J7-D7   P10_20  AR23
NET   'P10_21'           U1-<IO_L12P_VRN_21>      #> F07 R5V1 #> T05 J7-C8   P10_21  AV24
NET   'P10_22'           U1-<IO_L8P_SRCC_21>      #> F06 R5V2 #> T05 J7-D9   P10_22  AU23
NET   'P10_23'           U1-<IO_L14P_21>          #> F01 R5V8 #> T05 J7-C10  P10_23  BA25
NET   'P10_24'           U1-<IO_L9P_MRCC_21>      #> F09      #> T09 J7-D11  P10_24  AP25

NET   'P11_0'            U1-<IO_L2P_21>           #> F02      #> T02 J6-E14  P11_00  AY27
NET   'P11_1'            U1-<IO_L1P_22>           #> F02      #> T02 J6-E15  P11_01  AN26
NET   'P11_2'            U1-<IO_L13P_21>          #> F02      #> T02 J6-E16  P11_02  AM24
NET   'P11_3'            U1-<IO_L5N_21>           #> F02      #> T02 J6-E17  P11_03  AK23
NET   'P11_4'            U1-<IO_L7P_21>           #> F02      #> T02 J6-E18  P11_04  AM23
NET   'P11_5'            U1-<IO_L1P_21>           #> F02      #> T02 J6-E19  P11_05  AK22
NET   'P11_6'            U1-<IO_L1N_21>           #> F02      #> T02 J7-E1   P11_06  AJ22
NET   'P11_7'            U1-<IO_L10N_MRCC_22>     #> F04      #> T04 J7-E2   P11_07  AM27
NET   'P11_8'            U1-<IO_L0P_21>           #> F04      #> T04 J7-E3   P11_08  AT26
NET   'P11_9'            U1-<IO_L18N_21>          #> F06 R4V2 #> T04 J7-E4   P11_09  AW26
NET   'P11_10'           U1-<IO_L4P_21>           #> F01 R4V6 #> T04 J7-E5   P11_10  BA26
NET   'P11_11'           U1-<IO_L19N_22>          #> F07 R4V4 #> T04 J7-E6   P11_11  AY28
NET   'P11_12'           U1-<IO_L19N_21>          #> F04      #> T04 J7-E7   P11_12  AR25
NET   'P11_13'           U1-<IO_L19P_21>          #> F04      #> T04 J7-E8   P11_13  AT25
NET   'P11_14'           U1-<IO_L17N_21>          #> F04      #> T04 J7-E9   P11_14  AT24
NET   'P11_15'           U1-<IO_L11P_SRCC_21>     #> F04      #> T04 J7-E10  P11_15  AP23
NET   'P11_16'           U1-<IO_L6N_21>           #> F01 R4V7 #> T03 J7-E11  P11_16  BB27
NET   'P11_17'           U1-<IO_L9N_MRCC_21>      #> F03      #> T03 J7-E12  P11_17  AP26
NET   'P11_18'           U1-<IO_L15N_21>          #> F03      #> T03 J7-E13  P11_18  AN25
NET   'P11_19'           U1-<IO_L17P_21>          #> F03      #> T03 J7-E14  P11_19  AR24
NET   'P11_20'           U1-<IO_L15P_21>          #> F03      #> T03 J7-E15  P11_20  AN24
NET   'P11_21'           U1-<IO_L7N_21>           #> F03      #> T03 J7-E16  P11_21  AN23
NET   'P11_22'           U1-<IO_L3P_21>           #> F03      #> T03 J7-E17  P11_22  AM22
NET   'P11_23'           U1-<IO_L3N_21>           #> F03      #> T03 J7-E18  P11_23  AL22
NET   'P11_24'           U1-<IO_L10P_MRCC_21>     #> F09      #> T09 J7-E19  P11_24  AK24

NET   'P8TO11_DCI_P'     U1-<IO_L12N_VRP_23>                  #> T08                 AJ28
NET   'P8TO11_DCI_N'     U1-<IO_L12P_VRN_23>                  #> T08                 AH28

NET   'VREF_P'           U1-<IO_L4N_VREF_21>                  #> T08                 BA27
NET   'VREF_P'           U1-<IO_L14N_VREF_21>                 #> T08                 AY25
NET   'VREF_P'           U1-<IO_L4N_VREF_22>                  #> T08                 AW32
NET   'VREF_P'           U1-<IO_L14N_VREF_22>                 #> T08                 BB32
NET   'VREF_P'           U1-<IO_L4N_VREF_23>                  #> T08                 AM29
NET   'VREF_P'           U1-<IO_L14N_VREF_23>                 #> T08                 AG27


#########################################################################################
#
# The Processor Inputs in P12-P13-P14-P15 use IO resources from banks 32-33-34
# P12_24 uses a regional clock in IO bank 32 on trace layer  9
# P13_24 uses a regional clock in IO bank 33 on trace layer  9
# P14_24 uses a regional clock in IO bank 34 on trace layer  9
# P15_24 uses a regional clock in IO bank 34 on trace layer  9
# The DCI master for this group is IO bank 34
#

NET   'P12_0'            U1-<IO_L18P_32>          #> F01 R1V7 #> T02 J7-A10  P12_00  BB22
NET   'P12_1'            U1-<IO_L0N_32>           #> F01 R1V6 #> T02 J7-A11  P12_01  BA24
NET   'P12_2'            U1-<IO_L14P_32>          #> F01 R1V5 #> T02 J7-A12  P12_02  BA22
NET   'P12_3'            U1-<IO_L6N_32>           #> F01 R1V3 #> T02 J7-A13  P12_03  BB23
NET   'P12_4'            U1-<IO_L5N_32>           #> F02      #> T02 J7-A14  P12_04  AL21
NET   'P12_5'            U1-<IO_L11P_SRCC_32>     #> F02      #> T02 J7-A15  P12_05  AM21
NET   'P12_6'            U1-<IO_L3N_32>           #> F02      #> T02 J7-A16  P12_06  AR20
NET   'P12_7'            U1-<IO_L8P_SRCC_32>      #> F02      #> T02 J7-A17  P12_07  AY20
NET   'P12_8'            U1-<IO_L7N_32>           #> F02      #> T02 J7-A18  P12_08  AP20
NET   'P12_9'            U1-<IO_L17N_33>          #> F02      #> T02 J7-A19  P12_09  AY19
NET   'P12_10'           U1-<IO_L13P_33>          #> F09 R3V8 #> T02 J8-A1   P12_10  AV18
NET   'P12_11'           U1-<IO_L10N_MRCC_32>     #> F02      #> T02 J8-A2   P12_11  AK19
NET   'P12_12'           U1-<IO_L18P_33>          #> F02      #> T02 J8-A3   P12_12  AK18
NET   'P12_13'           U1-<IO_L6N_33>           #> F02      #> T02 J8-A4   P12_13  AK17
NET   'P12_14'           U1-<IO_L14P_33>          #> F04      #> T04 J8-A5   P12_14  AM17
NET   'P12_15'           U1-<IO_L8P_SRCC_33>      #> F04      #> T04 J8-A6   P12_15  AN16
NET   'P12_16'           U1-<IO_L2P_33>           #> F04      #> T04 J8-A7   P12_16  AN15
NET   'P12_17'           U1-<IO_L2N_33>           #> F04      #> T04 J8-A8   P12_17  AM14
NET   'P12_18'           U1-<IO_L4P_32>           #> F09      #> T09 J8-A9   P12_18  AW23
NET   'P12_19'           U1-<IO_L16N_32>          #> F09      #> T09 J8-A10  P12_19  AY22
NET   'P12_20'           U1-<IO_L16P_32>          #> F09      #> T09 J8-A11  P12_20  AW22
NET   'P12_21'           U1-<IO_L2P_32>           #> F09      #> T09 J8-A12  P12_21  AV23
NET   'P12_22'           U1-<IO_L12N_VRP_32>      #> F09      #> T09 J8-A13  P12_22  AW21
NET   'P12_23'           U1-<IO_L13N_32>          #> F09      #> T09 J8-A14  P12_23  AW20
NET   'P12_24'           U1-<IO_L10P_MRCC_32>     #> F09      #> T09 J8-A15  P12_24  AK20

NET   'P13_0'            U1-<IO_L17N_32>          #> F04      #> T04 J7-B10  P13_00  AR22
NET   'P13_1'            U1-<IO_L19N_32>          #> F04      #> T04 J7-C11  P13_01  AP22
NET   'P13_2'            U1-<IO_L15N_32>          #> F04      #> T04 J7-B12  P13_02  AT21
NET   'P13_3'            U1-<IO_L6P_32>           #> F01 R1V4 #> T05 J7-C13  P13_03  BB24
NET   'P13_4'            U1-<IO_L2N_32>           #> F05      #> T05 J7-B14  P13_04  AU22
NET   'P13_5'            U1-<IO_L17P_32>          #> F05      #> T05 J7-C15  P13_05  AT22
NET   'P13_6'            U1-<IO_L15P_32>          #> F05      #> T05 J7-B16  P13_06  AU21
NET   'P13_7'            U1-<IO_L12P_VRN_32>      #> F05      #> T05 J7-C17  P13_07  AV21
NET   'P13_8'            U1-<IO_L13P_32>          #> F05      #> T05 J7-B18  P13_08  AV20
NET   'P13_9'            U1-<IO_L11N_SRCC_33>     #> F05      #> T05 J7-C19  P13_09  AR19
NET   'P13_10'           U1-<IO_L11N_SRCC_32>     #> F03      #> T03 J8-B1   P13_10  AN21
NET   'P13_11'           U1-<IO_L19P_32>          #> F03      #> T03 J8-C2   P13_11  AP21
NET   'P13_12'           U1-<IO_L18N_32>          #> F01 R2V7 #> T03 J8-B3   P13_12  BB21
NET   'P13_13'           U1-<IO_L15N_33>          #> F01 R2V8 #> T03 J8-C4   P13_13  BB19
NET   'P13_14'           U1-<IO_L8N_SRCC_32>      #> F01 R2V6 #> T03 J8-B5   P13_14  BA20
NET   'P13_15'           U1-<IO_L3P_32>           #> F03      #> T03 J8-C6   P13_15  AT20
NET   'P13_16'           U1-<IO_L1N_32>           #> F03      #> T03 J8-B7   P13_16  AM19
NET   'P13_17'           U1-<IO_L1P_32>           #> F03      #> T03 J8-C8   P13_17  AL19
NET   'P13_18'           U1-<IO_L16P_33>          #> F03      #> T03 J8-B9   P13_18  AN18
NET   'P13_19'           U1-<IO_L17P_33>          #> F01 R3V7 #> T03 J8-C10  P13_19  BA19
NET   'P13_20'           U1-<IO_L19N_33>          #> F09 R3V6 #> T03 J8-B11  P13_20  AT19
NET   'P13_21'           U1-<IO_L4P_33>           #> F03      #> T03 J8-C12  P13_21  AL17
NET   'P13_22'           U1-<IO_L8N_SRCC_33>      #> F03      #> T03 J8-B13  P13_22  AM16
NET   'P13_23'           U1-<IO_L12P_VRN_33>      #> F09 R4V6 #> T03 J8-C14  P13_23  AP16
NET   'P13_24'           U1-<IO_L9P_MRCC_33>      #> F09      #> T09 J8-B15  P13_24  AK15

NET   'P14_0'            U1-<IO_L19P_33>          #> F06 R2V2 #> T04 J7-C12  P14_00  AU19
NET   'P14_1'            U1-<IO_L18P_A17_34>      #> F06 R2V4 #> T04 J7-D13  P14_01  AY17
NET   'P14_2'            U1-<IO_L7N_33>           #> F07 R2V5 #> T04 J7-C14  P14_02  AW18
NET   'P14_3'            U1-<IO_L7P_33>           #> F07 R2V3 #> T04 J7-D15  P14_03  AY18
NET   'P14_4'            U1-<IO_L13N_33>          #> F07 R2V1 #> T04 J7-C16  P14_04  AV19
NET   'P14_5'            U1-<IO_L16N_33>          #> F04      #> T04 J7-D17  P14_05  AN19
NET   'P14_6'            U1-<IO_L15P_33>          #> F04      #> T04 J7-C18  P14_06  BB18
NET   'P14_7'            U1-<IO_L8N_SRCC_34>      #> F01 R3V5 #> T04 J7-D19  P14_07  AW16
NET   'P14_8'            U1-<IO_L3N_33>           #> F06 R3V3 #> T04 J8-C1   P14_08  AU17
NET   'P14_9'            U1-<IO_L1N_33>           #> F06 R3V1 #> T04 J8-D2   P14_09  AR18
NET   'P14_10'           U1-<IO_L11P_SRCC_33>     #> F04      #> T04 J8-C3   P14_10  AP18
NET   'P14_11'           U1-<IO_L10P_MRCC_33>     #> F02      #> T02 J8-D4   P14_11  AJ16
NET   'P14_12'           U1-<IO_L8P_SRCC_34>      #> F06 R4V3 #> T02 J8-C5   P14_12  AV16
NET   'P14_13'           U1-<IO_L5P_33>           #> F09 R4V8 #> T02 J8-D6   P14_13  AT17
NET   'P14_14'           U1-<IO_L6P_A07_D23_34>   #> F02      #> T02 J8-C7   P14_14  AY15
NET   'P14_15'           U1-<IO_L0P_33>           #> F02      #> T02 J8-D8   P14_15  AL15
NET   'P14_16'           U1-<IO_L9N_MRCC_33>      #> F02      #> T02 J8-C9   P14_16  AK14
NET   'P14_17'           U1-<IO_L10N_MRCC_34>     #> F02      #> T02 J8-D10  P14_17  AN13
NET   'P14_18'           U1-<IO_L11P_SRCC_34>     #> F06 R5V2 #> T02 J8-C11  P14_18  AV13
NET   'P14_19'           U1-<IO_L14P_A25_34>      #> F01 R5V8 #> T02 J8-D12  P14_19  BA16
NET   'P14_20'           U1-<IO_L12N_A02_D18_34>  #> F01 R5V6 #> T02 J8-C13  P14_20  BB14
NET   'P14_21'           U1-<IO_L12P_A03_D19_34>  #> F01 R5V4 #> T02 J8-D14  P14_21  BB13
NET   'P14_22'           U1-<IO_L13N_A00_D16_34>  #> F07 R5V1 #> T02 J8-C15  P14_22  AW13
NET   'P14_23'           U1-<IO_L9N_MRCC_34>      #> F02      #> T02 J8-D16  P14_23  AM12
NET   'P14_24'           U1-<IO_L10P_MRCC_34>     #> F09      #> T09 J8-C17  P14_24  AN14

NET   'P15_0'            U1-<IO_L5N_33>           #> F05      #> T05 J8-E1   P15_00  AU18
NET   'P15_1'            U1-<IO_L18N_A16_34>      #> F07 R3V2 #> T05 J8-E2   P15_01  AW17
NET   'P15_2'            U1-<IO_L6N_A06_D22_34>   #> F07 R3V4 #> T05 J8-E3   P15_02  AW15
NET   'P15_3'            U1-<IO_L12N_VRP_33>      #> F05      #> T05 J8-E4   P15_03  AP17
NET   'P15_4'            U1-<IO_L1P_33>           #> F05      #> T05 J8-E5   P15_04  AR17
NET   'P15_5'            U1-<IO_L3P_33>           #> F05      #> T05 J8-E6   P15_05  AT16
NET   'P15_6'            U1-<IO_L4P_A11_D27_34>   #> F07 R4V1 #> T05 J8-E7   P15_06  AV15
NET   'P15_7'            U1-<IO_L15N_A22_34>      #> F07 R4V4 #> T05 J8-E8   P15_07  AT14
NET   'P15_8'            U1-<IO_L16N_A20_34>      #> F01 R4V7 #> T05 J8-E9   P15_08  BB17
NET   'P15_9'            U1-<IO_L16P_A21_34>      #> F01 R4V5 #> T05 J8-E10  P15_09  BB16
NET   'P15_10'           U1-<IO_L11N_SRCC_34>     #> F06 R4V2 #> T05 J8-E11  P15_10  AV14
NET   'P15_11'           U1-<IO_L17N_A18_34>      #> F05      #> T05 J8-E12  P15_11  AR15
NET   'P15_12'           U1-<IO_L15P_A23_34>      #> F05      #> T05 J8-E13  P15_12  AR14
NET   'P15_13'           U1-<IO_L2P_A15_D31_34>   #> F01 R5V7 #> T05 J8-E14  P15_13  BA15
NET   'P15_14'           U1-<IO_L2N_A14_D30_34>   #> F01 R5V5 #> T05 J8-E15  P15_14  BA14
NET   'P15_15'           U1-<IO_L7N_A04_D20_34>   #> F05      #> T05 J8-E16  P15_15  AU13
NET   'P15_16'           U1-<IO_L7P_A05_D21_34>   #> F05      #> T05 J8-E17  P15_16  AU12
NET   'P15_17'           U1-<IO_L5N_A08_D24_34>   #> F04      #> T04 J8-E18  P15_17  AR13
NET   'P15_18'           U1-<IO_L3N_A12_D28_34>   #> F04      #> T04 J8-E19  P15_18  AT12
NET   'P15_19'           U1-<IO_L17P_A19_34>      #> F03      #> T03 J8-E20  P15_19  AP15
NET   'P15_20'           U1-<IO_L0N_33>           #> F03      #> T03 J8-E21  P15_20  AL14
NET   'P15_21'           U1-<IO_L5P_A09_D25_34>   #> F03      #> T03 J8-E22  P15_21  AP13
NET   'P15_22'           U1-<IO_L3P_A13_D29_34>   #> F03      #> T03 J8-E23  P15_22  AR12
NET   'P15_23'           U1-<IO_L13P_A01_D17_34>  #> F09 R5V3 #> T03 J8-E24  P15_23  AW12
NET   'P15_24'           U1-<IO_L9P_MRCC_34>      #> F09      #> T09 J8-E25  P15_24  AM13

NET   'P12TO15_DCI_P'    U1-<IO_L19N_VRP_34>                  #> T08                 AU16
NET   'P12TO15_DCI_N'    U1-<IO_L19P_VRN_34>                  #> T08                 AT15

NET   'VREF_P'           U1-<IO_L4N_VREF_32>                  #> T08                 AY23
NET   'VREF_P'           U1-<IO_L14N_VREF_32>                 #> T08                 BA21
NET   'VREF_P'           U1-<IO_L4N_VREF_33>                  #> T08                 AL16
NET   'VREF_P'           U1-<IO_L14N_VREF_33>                 #> T08                 AM18
NET   'VREF_P'           U1-<IO_L4N_VREF_A10_D26_34>          #> T08                 AU14
NET   'VREF_P'           U1-<IO_L14N_VREF_A24_34>             #> T08                 BA17