############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for the LVDS cable IO # -=============---------------------------------------------- # # # Original Rev. 18-Nov-2011 # Rev. 22-Jun-2012 comment all out because processor inputs have moved to banks 22&23 # Rev. 31-Aug-2012 Now on IO banks 15,16,17 and layer assigned # Rev: 07-Sep-2012 Add header comments # Rev: 19-Nov-2012 Re-do breakout strategy which frees up layers 6 and 7 now unused # Skip the 8 System Monitor pin pairs from IO Bank 15 # Rev. 30-Nov-2012 Studying the set of unused pins generated 2 allocation improvements here # Most Recent Rev: 03-Jun-2013 swap pin used for cable IO signal 83 (AE35 is now used; AF41 now unused) # # Signal Nets referenced in this file: # ------------------------------------ # # 'D_CBL_zz_B' are the cable IO signals available to the Base FPGA with zz=00 to 83. # The "_B" postfix is used to indicate that these signals are inverted with respect # to the LVDS signal polarity on the data cables. # # There are up to 3 cables used for a given CMX card. # A Crate CMX card uses one cable as output only, # while a System CMX card receives 2 or 3 cables as input. # # A Rear Transition Module (RTM) card provides the interface to the three 34-signal # LVDS connectors where the IO cables can be connected. # Only 27 signals from each connector are routed on the current RTM cards. # zz=0 to 26 correspond to the first cable, # zz=27 to 53 correspond to the second cable, and # zz=54 to 80 correspond to the third cable. # # Additionally, 3 more differential pairs of signals are labelled on the backplane # but are not routed on the RTM: zz= 31 to 83 # The CMX card will route the currently unused M_81, M_82, and M_83 signals # to become usable as cable IO signals. The sets of cable signals thus are: # Cable #1 consists of signals M_00 to M_26 plus M_81 # Cable #2 consists of signals M_27 to M_53 plus M_82 # Cable #3 consists of signals M_54 to M_80 plus M_83 # The CMX card could thus be able to use 28 LVDS signals per cable while the CMM was only able # to use 27 signals. Using 28 signals would however require a new version of the RTM card. # This 28th signal can be left unused and set to a fixed state by the FPGA of the source Crate CMX # while the LVDS transceiver of the receiving System CMX will default to a defined value # for all non-connected inputs. # # The path to the LVDS transceivers D_CBL_zz signals are in the file backplane_cable_tx_n2p.txt # in the Net_Lists/Components_Backplane_Tx directory # # Note: Trace layer information is appended as comments below. # ----- # # NET 'D_CBL_00' U1- #> T02 00 L12 # # ^ ^ ^ ^ # | | | | # Tailored comment flag to help with string searches -------------------+ | | | # | | | # Target Trace Layer number to use for this net ----------------------------+ | | # T01 is top layer, T02 the first inner layer, etc | | # | | # Signal number is repeated to help manual entry of Pin Number ----------------+ | # | # Target Pin Number read from paper drawing ----------------------------------------+ # and cross-checked after Match_Res2Pin # ############################################################################################ # # IO Cable #1 # # This group uses signals from IO banks 16 and 17 and a regional clock from bank 17 NET 'D_CBL_00_B' U1- #> T02 00 L39 NET 'D_CBL_01_B' U1- #> T02 01 L42 NET 'D_CBL_02_B' U1- #> T02 02 M36 NET 'D_CBL_03_B' U1- #> T02 03 M42 NET 'D_CBL_04_B' U1- #> T02 04 N36 NET 'D_CBL_05_B' U1- #> T02 05 P37 NET 'D_CBL_06_B' U1- #> T02 06 P42 NET 'D_CBL_07_B' U1- #> T02 07 R35 NET 'D_CBL_08_B' U1- #> T02 08 R42 NET 'D_CBL_09_B' U1- #> T02 09 T35 NET 'D_CBL_10_B' U1- #> T02 10 T42 NET 'D_CBL_11_B' U1- #> T02 11 U36 NET 'D_CBL_12_B' U1- #> T02 12 U42 NET 'D_CBL_13_B' U1- #> T02 13 V36 NET 'D_CBL_14_B' U1- #> T02 14 W35 NET 'D_CBL_15_B' U1- #> T02 15 W42 NET 'D_CBL_16_B' U1- #> T02 16 Y34 NET 'D_CBL_17_B' U1- #> T02 17 Y42 NET 'D_CBL_18_B' U1- #> T02 18 Y35 NET 'D_CBL_19_B' U1- #> T02 19 AA34 NET 'D_CBL_20_B' U1- #> T02 20 AA32 NET 'D_CBL_21_B' U1- #> T03 21 L40 NET 'D_CBL_22_B' U1- #> T03 22 M37 NET 'D_CBL_23_B' U1- #> T09 23 M41 NET 'D_CBL_24_B' U1- #> T09 24 N41 NET 'D_CBL_25_B' U1- # Clock #> T09 25 P36 NET 'D_CBL_26_B' U1- # Parity #> T09 26 R40 NET 'D_CBL_81_B' U1- #> T03 81 N38 # # IO Cable #2 # # This group uses signals from IO banks 16 and 17 and a regional clock from bank 17 NET 'D_CBL_27_B' U1- #> T03 27 P38 NET 'D_CBL_28_B' U1- #> T03 28 R37 NET 'D_CBL_29_B' U1- #> T03 29 T36 NET 'D_CBL_30_B' U1- #> T03 30 U37 NET 'D_CBL_31_B' U1- #> T03 31 V38 NET 'D_CBL_32_B' U1- #> T03 32 W36 NET 'D_CBL_33_B' U1- #> T03 33 W37 NET 'D_CBL_34_B' U1- #> T03 34 Y37 NET 'D_CBL_35_B' U1- #> T03 35 AA36 NET 'D_CBL_36_B' U1- #> T03 36 AA35 NET 'D_CBL_37_B' U1- #> T04 37 L41 NET 'D_CBL_38_B' U1- #> T04 38 M38 NET 'D_CBL_39_B' U1- #> T04 39 N39 NET 'D_CBL_40_B' U1- #> T04 40 P40 NET 'D_CBL_41_B' U1- #> T04 41 R38 NET 'D_CBL_42_B' U1- #> T04 42 T37 NET 'D_CBL_43_B' U1- #> T04 43 U38 NET 'D_CBL_44_B' U1- #> T04 44 V39 NET 'D_CBL_45_B' U1- #> T04 45 V40 NET 'D_CBL_46_B' U1- #> T04 46 W38 NET 'D_CBL_47_B' U1- #> T04 47 Y38 NET 'D_CBL_48_B' U1- # Clock #> T09 48 T39 NET 'D_CBL_49_B' U1- # Parity #> T09 49 T41 NET 'D_CBL_50_B' U1- #> T05 50 M39 NET 'D_CBL_51_B' U1- #> T05 51 N40 NET 'D_CBL_52_B' U1- #> T05 52 P41 NET 'D_CBL_53_B' U1- #> T05 53 R39 NET 'D_CBL_82_B' U1- #> T05 82 T40 # # IO Cable #3 # # This group uses signals from IO banks 15 and 16 and a regional clock from bank 16 NET 'D_CBL_54_B' U1- #> T02 54 AC36 NET 'D_CBL_55_B' U1- #> T02 55 AC35 NET 'D_CBL_56_B' U1- #> T02 56 AE37 NET 'D_CBL_57_B' U1- #> T02 57 AF42 NET 'D_CBL_58_B' U1- #> T03 58 AB34 NET 'D_CBL_59_B' U1- #> T03 59 AB36 NET 'D_CBL_60_B' U1- #> T03 60 AC38 NET 'D_CBL_61_B' U1- #> T03 61 AD37 NET 'D_CBL_62_B' U1- #> T03 62 AD36 NET 'D_CBL_63_B' U1- #> T03 63 AE39 NET 'D_CBL_64_B' U1- #> T04 64 AA39 NET 'D_CBL_65_B' U1- #> T04 65 AA37 NET 'D_CBL_66_B' U1- #> T04 66 AB37 NET 'D_CBL_67_B' U1- #> T04 67 AB38 NET 'D_CBL_68_B' U1- #> T04 68 AC39 NET 'D_CBL_69_B' U1- #> T05 69 U39 NET 'D_CBL_70_B' U1- #> T05 70 U41 NET 'D_CBL_71_B' U1- #> T05 71 V41 NET 'D_CBL_72_B' U1- #> T05 72 W40 NET 'D_CBL_73_B' U1- #> T05 73 Y39 NET 'D_CBL_74_B' U1- #> T05 74 AC41 NET 'D_CBL_75_B' U1- #> T05 75 AD41 NET 'D_CBL_76_B' U1- #> T05 76 AE40 NET 'D_CBL_77_B' U1- #> T09 77 V35 NET 'D_CBL_78_B' U1- # Clock #> T09 78 W32 NET 'D_CBL_79_B' U1- # Parity #> T09 79 W41 NET 'D_CBL_80_B' U1- #> T09 80 Y40 NET 'D_CBL_83_B' U1- #> T09 83 AE35