############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for Front Panel CTP Output # -=============--------------------------------------------- # # # Original Rev. 15-Nov-2011 assign to banks 33 & 34 # Rev. 22-Jun-2012 comment everything out as 33&34 taken by Processor inputs # Rev. 10-Sep-2012 Reassign to IO Banks 12 & part of 13 # Rev: 19-Nov-2012 Re-do breakout strategy # and plan for "a matrix of vias" near FPGA South East corner # The long haul is temporarily recoreded as layer 1 (T01), to be determined. # Rename nets to make Base Function a prefix (DOUT_CTP_xx_BF -> BF_DOUT_CTP_xx) # Rev: 11-Dec-2012 File name changed for uniformity and consistency between Base and TP files # Rev: 14-Jan-2013 Edit header comments # Rev: 05-Apr-2013 Tentatively flag these signals to belong to layer 7 # Rev: 20-May-2013 Swap BF_DOUT_CTP_51 and BF_DOUT_CTP_57 to solve problem with backplane IO # Most Recent Rev: 06-Jun-2013 Update position of signal #65 and rotate position of upper half signals # after final location of 5th translator # # # Signal Nets referenced in this file: # ------------------------------------ # # There are 0, 1 or 2 CTP cables connected to a given CMX card. # A Crate CMX with only Base CMX functionality does not send any data to the CTP # A System CMX in a CPM crate sends information to the CTP over one cable # A System CMX in a JEM crate sends information to the CTP over two cables # A Crate CMX with TP functionality would probably send information to the CTP over two cables # # 'BF_DOUT_CTP_xx' are the CTP output signals from the Base FPGA with xx=00 to 65. # Each CTP output cable carries 33 LVDS signals consisting of 31 data bits, one clock # and one parity bit. # xx=0 to 30 carry data bits on cable #1 # xx=31 carry the clock on cable #1 # xx=64 carry the parity on cable #1 # xx=32 to 62 carry data bits on cable #2 # xx=63 carry the clock on cable #2 # xx=65 carry the parity on cable #2 # Note that regional clock signals are assigned to CTP output signals # 31 and 63 # for flexibility, so that the CTP output cables could be used as inputs instead. # # These CTP output signals are assigned here to resources in IO banks 12 and 13. # Only part of IO bank 13 is used here, namely only the pins in rows AN to BB # while 11 io pins in rows AK, AL and AM are used for the on-card bus. # # The rest of the circuitry used to drive the LVDS cables is in the file front_panel_ctp_driver_n2p.txt # in the Net_Lists/Front_Panel_CTP_IO_Nets directory # # # Note: Trace layer information is appended as comments below. # ----- # # NET 'BF_DOUT_CTP_00' U1- #> F02 #> T01 00 AW37 # # ^ ^ ^ ^ ^ # | | | | | # Tailored comment flag to help with string searches -----------------+ | | | | # | | | | # Target Trace Layer number to use for this net --------------------------+ | | | # as it exits the FPGA (to reach a via in the via matrix) | | | # F01 is top layer, F02 the first inner layer, etc | | | # | | | # Target Trace Layer number to use for this net ---------------------------------+ | | # as it reaches the level translator near the front of the card | | # T01 is top layer, T02 the first inner layer, etc | | # | | # Signal number is repeated to help manual entry of Pin Number ---------------------+ | # | # Target Pin Number read from paper study -----------------------------------------------+ # and cross-checked after Match_Res2Pin # ############################################################################################ # # CTP Cable #1 # # This group uses signals from IO banks 12 and 13 and a regional clock from bank 13 NET 'BF_DOUT_CTP_00' U1- #> F02 #> T07 00 AW37 NET 'BF_DOUT_CTP_01' U1- #> F02 #> T07 01 AU42 NET 'BF_DOUT_CTP_02' U1- #> F02 #> T07 02 AT36 NET 'BF_DOUT_CTP_03' U1- #> F03 #> T07 03 AR37 NET 'BF_DOUT_CTP_04' U1- #> F05 #> T07 04 AY35 NET 'BF_DOUT_CTP_05' U1- #> F09 #> T07 05 AP36 NET 'BF_DOUT_CTP_06' U1- #> F02 #> T07 06 BB38 NET 'BF_DOUT_CTP_07' U1- #> F02 #> T07 07 AV38 NET 'BF_DOUT_CTP_08' U1- #> F02 #> T07 08 AU37 NET 'BF_DOUT_CTP_09' U1- #> F03 #> T07 09 AT37 NET 'BF_DOUT_CTP_10' U1- #> F05 #> T07 10 BA36 NET 'BF_DOUT_CTP_11' U1- #> F09 #> T07 11 AR40 NET 'BF_DOUT_CTP_12' U1- #> F02 #> T07 12 AW38 NET 'BF_DOUT_CTP_13' U1- #> F02 #> T07 13 AW40 NET 'BF_DOUT_CTP_14' U1- #> F02 #> T07 14 AW42 NET 'BF_DOUT_CTP_15' U1- #> F03 #> T07 15 AU38 NET 'BF_DOUT_CTP_16' U1- #> F05 #> T07 16 AT41 NET 'BF_DOUT_CTP_17' U1- #> F03 #> T07 17 AY37 NET 'BF_DOUT_CTP_18' U1- #> F02 #> T07 18 BB39 NET 'BF_DOUT_CTP_19' U1- #> F02 #> T07 19 AY40 NET 'BF_DOUT_CTP_20' U1- #> F02 #> T07 20 AY42 NET 'BF_DOUT_CTP_21' U1- #> F03 #> T07 21 AV39 NET 'BF_DOUT_CTP_22' U1- #> F05 #> T07 22 AU41 NET 'BF_DOUT_CTP_23' U1- #> F03 #> T07 23 AY38 NET 'BF_DOUT_CTP_24' U1- #> F02 #> T07 24 AY39 NET 'BF_DOUT_CTP_25' U1- #> F02 #> T07 25 BA41 NET 'BF_DOUT_CTP_26' U1- #> F02 #> T07 26 BA42 NET 'BF_DOUT_CTP_27' U1- #> F03 #> T07 27 AW41 NET 'BF_DOUT_CTP_28' U1- #> F05 #> T07 28 AV41 NET 'BF_DOUT_CTP_29' U1- #> F03 #> T07 29 BA39 NET 'BF_DOUT_CTP_30' U1- #> F02 #> T07 30 BA40 NET 'BF_DOUT_CTP_31' U1- #> F09 #> T07 31 AT40 NET 'BF_DOUT_CTP_64' U1- #> F02 #> T07 64 BB41 # # CTP Cable #2 # # This group uses signals from IO banks 12 and 13 and a regional clock from bank 12 NET 'BF_DOUT_CTP_32' U1- #> F02 #> T07 32 AN38 NET 'BF_DOUT_CTP_33' U1- #> F04 #> T07 33 BB34 NET 'BF_DOUT_CTP_34' U1- #> F02 #> T07 34 AN40 NET 'BF_DOUT_CTP_35' U1- #> F02 #> T07 35 AU34 NET 'BF_DOUT_CTP_36' U1- #> F04 #> T07 36 AP42 NET 'BF_DOUT_CTP_37' U1- #> F05 #> T07 37 AP40 NET 'BF_DOUT_CTP_38' U1- #> F04 #> T07 38 AN41 NET 'BF_DOUT_CTP_39' U1- #> F03 #> T07 39 AV34 NET 'BF_DOUT_CTP_40' U1- #> F02 #> T07 40 AV35 NET 'BF_DOUT_CTP_41' U1- #> F02 #> T07 41 AT35 NET 'BF_DOUT_CTP_42' U1- #> F04 #> T07 42 AP37 NET 'BF_DOUT_CTP_43' U1- #> F05 #> T07 43 AR38 NET 'BF_DOUT_CTP_44' U1- #> F04 #> T07 44 AP41 NET 'BF_DOUT_CTP_45' U1- #> F03 #> T07 45 AW35 NET 'BF_DOUT_CTP_46' U1- #> F02 #> T07 46 AV36 NET 'BF_DOUT_CTP_47' U1- #> F02 #> T07 47 BB36 NET 'BF_DOUT_CTP_48' U1- #> F04 #> T07 48 AR42 NET 'BF_DOUT_CTP_49' U1- #> F05 #> T07 49 AT39 NET 'BF_DOUT_CTP_50' U1- #> F04 #> T07 50 AR39 NET 'BF_DOUT_CTP_51' U1- #> F09 #> T07 51 AW36 NET 'BF_DOUT_CTP_52' U1- #> F02 #> T07 52 BA35 NET 'BF_DOUT_CTP_53' U1- #> F02 #> T07 53 AU36 NET 'BF_DOUT_CTP_54' U1- #> F04 #> T07 54 AR35 NET 'BF_DOUT_CTP_55' U1- #> F03 #> T07 55 AU39 NET 'BF_DOUT_CTP_56' U1- #> F04 #> T07 56 AN39 NET 'BF_DOUT_CTP_57' U1- #> F09 #> T07 57 BA37 NET 'BF_DOUT_CTP_58' U1- #> F02 #> T07 58 BA34 NET 'BF_DOUT_CTP_59' U1- #> F02 #> T07 59 BB37 NET 'BF_DOUT_CTP_60' U1- #> F04 #> T07 60 AT42 NET 'BF_DOUT_CTP_61' U1- #> F03 #> T07 61 AV40 NET 'BF_DOUT_CTP_62' U1- #> F05 #> T07 62 AP38 NET 'BF_DOUT_CTP_63' U1- #> F09 #> T07 63 AN35 NET 'BF_DOUT_CTP_65' U1- #> F02 #> T07 65 AY34