############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for the highspeed GTX Transmitters # -=============--------------------------------------------------------- # # # Base Function FPGA # ---------------------- # # # Original Rev. 16-Mar-2012 # Rev. 19-Nov-2012 Add termination resistors # Rev: 11-Dec-2012 File name changed for uniformity and consistency between Base and TP files # Rev: 31-Dec-2012 Change the net-name on the MGTAVTTRCAL_115 Calibration Resistor pin. # Rev. 16-Jan-2013 Add unused MGT transceiver pins and rename file # base_function_gtx_transceivers_n2r.txt # Rev. 14-May-2013 Rearrange the GTX Quad to MiniPOD connections to facilitate trace routing. # Most Recent Rev. 2-Oct-2013 Swap 4 Transceiver vs MiniPOD Fiber to equalize differential trace lengths. # # # Signal Nets referenced in this file: # ------------------------------------ # # 'MPn_Fpp_QUAD_qqq_TRN_r_xxx' are the net names assigned to the MGT Transmitter IO signals with: # "n" is the miniPOD device number (n=1:2 for transmitter 1:2) # "pp" is the fiber number on the minipod device (pp = 0:11) # "qqq" is the FPGA Quad number (qqq = 110:118, but only 110:115 used here) # "r" is the transmitter number on that Quad (r = 0:3) # "xxx" is the signal polarity (xxx = "DIR" for Direct aka Positive or Non-Inverted # or "CMP" for Complement aka Negative or Inverted) # ############################################################################################ # Transmitter 1 is MiniPOD device MP1 NET 'MP1_F01_QUAD_110_TRN_0_DIR' U1- NET 'MP1_F01_QUAD_110_TRN_0_CMP' U1- NET 'MP1_F03_QUAD_110_TRN_1_DIR' U1- NET 'MP1_F03_QUAD_110_TRN_1_CMP' U1- NET 'MP1_F07_QUAD_110_TRN_2_DIR' U1- NET 'MP1_F07_QUAD_110_TRN_2_CMP' U1- NET 'MP1_F05_QUAD_110_TRN_3_DIR' U1- NET 'MP1_F05_QUAD_110_TRN_3_CMP' U1- NET 'MP1_F09_QUAD_111_TRN_0_DIR' U1- NET 'MP1_F09_QUAD_111_TRN_0_CMP' U1- NET 'MP1_F11_QUAD_111_TRN_1_DIR' U1- NET 'MP1_F11_QUAD_111_TRN_1_CMP' U1- NET 'MP1_F10_QUAD_111_TRN_2_DIR' U1- NET 'MP1_F10_QUAD_111_TRN_2_CMP' U1- NET 'MP1_F08_QUAD_111_TRN_3_DIR' U1- NET 'MP1_F08_QUAD_111_TRN_3_CMP' U1- NET 'MP1_F04_QUAD_112_TRN_0_DIR' U1- NET 'MP1_F04_QUAD_112_TRN_0_CMP' U1- NET 'MP1_F06_QUAD_112_TRN_1_DIR' U1- NET 'MP1_F06_QUAD_112_TRN_1_CMP' U1- NET 'MP1_F02_QUAD_112_TRN_2_DIR' U1- NET 'MP1_F02_QUAD_112_TRN_2_CMP' U1- NET 'MP1_F00_QUAD_112_TRN_3_DIR' U1- NET 'MP1_F00_QUAD_112_TRN_3_CMP' U1- # Transmitter 2 is MiniPOD device MP2 NET 'MP2_F01_QUAD_113_TRN_0_DIR' U1- NET 'MP2_F01_QUAD_113_TRN_0_CMP' U1- NET 'MP2_F03_QUAD_113_TRN_1_DIR' U1- NET 'MP2_F03_QUAD_113_TRN_1_CMP' U1- NET 'MP2_F07_QUAD_113_TRN_2_DIR' U1- NET 'MP2_F07_QUAD_113_TRN_2_CMP' U1- NET 'MP2_F05_QUAD_113_TRN_3_DIR' U1- NET 'MP2_F05_QUAD_113_TRN_3_CMP' U1- NET 'MP2_F09_QUAD_114_TRN_0_DIR' U1- NET 'MP2_F09_QUAD_114_TRN_0_CMP' U1- NET 'MP2_F11_QUAD_114_TRN_1_DIR' U1- NET 'MP2_F11_QUAD_114_TRN_1_CMP' U1- NET 'MP2_F10_QUAD_114_TRN_2_DIR' U1- NET 'MP2_F10_QUAD_114_TRN_2_CMP' U1- NET 'MP2_F08_QUAD_114_TRN_3_DIR' U1- NET 'MP2_F08_QUAD_114_TRN_3_CMP' U1- NET 'MP2_F04_QUAD_115_TRN_0_DIR' U1- NET 'MP2_F04_QUAD_115_TRN_0_CMP' U1- NET 'MP2_F06_QUAD_115_TRN_1_DIR' U1- NET 'MP2_F06_QUAD_115_TRN_1_CMP' U1- NET 'MP2_F02_QUAD_115_TRN_2_DIR' U1- NET 'MP2_F02_QUAD_115_TRN_2_CMP' U1- NET 'MP2_F00_QUAD_115_TRN_3_DIR' U1- NET 'MP2_F00_QUAD_115_TRN_3_CMP' U1- # Now connect the GTX Termination Calibration Resistor # This is a precision 100 Ohm resistor. # See Chapter 5 page 274 of the # Virtex-6 GTX User Guide. # # The other half of these connections is in: # # ..../Everything_Else/dci_gtx_res_nets_n2p.txt # NET 'BF_MGTRREF' U1- # B11 Base Function MGTRREF pin NET 'BF_GTX_AVTT' U1- # A12 Base Function MGTAVTTRCAL # connected to the BF_GTX_AVTT bus # as indicated in the User Guide