############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for the On-Card VME bus signals # -=============------------------------------------------------------ # # # Original Rev. 13-Sep-2012 # Rev: 17-Sep-2012 Arbitrary temporary assignement # Rev: 19-Nov-2012 Re-do breakout strategy and Add Goeographic Address signals. # Pick the quietest lines to share IO bank 13 with CTP output # Rev. 30-Nov-2012 Studying the set of unused pins generated 1 allocation improvement here # Rev: 11-Dec-2012 File name changed for uniformity and consistency between Base and TP files # Rev: 14-Jan-2013 Edit header comments and tentatively set comments to specify layer 7 for vertical run # Rev: 30-May-2013 Fix order of geographic address lines # Most Recent Rev: 03-Jun-2013 swap pins for OCB_GEO_ADRS_1 and _3 to avoid additional via # # # # Signal Nets referenced in this file: # ------------------------------------ # # 'OCB_Axx' are the On-Card Bus Address lines to the Base FPGA with xx=01 to 23 # (note there is no "A00" signal) # # 'OCB_Dyy' are the On-Card Bus Data lines to the Base FPGA with yy=00 to 15 # # 'OCB_GEO_ADRS_z' are the On-Card Bus Geographic Section Address lines with z=0 to 6 # # # 'OCB_SYS_RESET_B' is the On-Card Bus VME SYS_RESET signal # The "_B" postfix is used to indicate that the reset request is active # when the electrical signal is low # # 'OCB_DS_B' is the On-Card Bus Data strobe. # The "_B" postfix is used to indicate that the data strobe signal is on the # falling edge of the electrical signal. # # 'OCB_WRITE_B' is the On-Card Bus Data Direction # The "_B" postfix is used to indicate that the Write direction is # requested when the electrical signal is low. # # # IO Banks used # ------------- # # Most signal nets are assigned to IO Bank 14 and a few to Io Bank 13 # - All address line nets are in IO Bank 14 # - All data line nets are in IO Bank 14 # - The Data Strobe net is assigned to a regional clock pin in IO Bank 14 # - The Board Select net is assigned to a regional clock pin in IO Bank 13 # - The Write Net is assigned to an IO input pin in Bank 13 # - The Sys_Reset net is assigned to an IO input pin in Bank 13 # # The bulk of IO Bank 13 is used for the CTP output signals # # Note: Trace layer information is appended as comments below. # ----- # # NET 'OCB_A01' U1- #> F06 #> T07 A01 AM41 # # ^ ^ ^ ^ ^ # | | | | | # Tailored comment flag to help with string searches ------------------+ | | | | # | | | | # Target Trace Layer number to use for this net --------------------------+ | | | # as it exits the FPGA (to reach a nearby via) | | | # F01 is top layer, F02 the first inner layer, etc | | | # | | | # Target Trace Layer number to use for this net ---------------------------------+ | | # as it connects the VME bus transceiver section to the two FPGAs | | # T01 is top layer, T02 the first inner layer, etc | | # | | # Signal number is repeated to help manual entry of Pin Number ---------------------+ | # | # Target Pin Number read from paper drawing ---------------------------------------------+ # and cross-checked after Match_Res2Pin # ############################################################################################ # The lower Address (1:20), all Data, the Data Strobe, Direction and SysReset signals are in IO Bank 14 # The data strobe is assigned to a regional clock input pin (but probably not used as a clock) NET 'OCB_A01' U1- #> F06 #> T07 A01 AM41 NET 'OCB_A02' U1- #> F06 #> T07 A02 AM42 NET 'OCB_A03' U1- #> F06 #> T07 A03 AL41 NET 'OCB_A04' U1- #> F06 #> T07 A04 AL42 NET 'OCB_A05' U1- #> F06 #> T07 A05 AK40 NET 'OCB_A06' U1- #> F06 #> T07 A06 AK42 NET 'OCB_A07' U1- #> F06 #> T07 A07 AJ41 NET 'OCB_A08' U1- #> F06 #> T07 A08 AJ42 NET 'OCB_A09' U1- #> F06 #> T07 A09 AH40 NET 'OCB_A10' U1- #> F06 #> T07 A10 AH41 NET 'OCB_A11' U1- #> F06 #> T07 A11 AG42 NET 'OCB_A12' U1- #> F06 #> T07 A12 AG38 NET 'OCB_A13' U1- #> F03 #> T07 A13 AJ36 NET 'OCB_A14' U1- #> F03 #> T07 A14 AH36 NET 'OCB_A15' U1- #> F03 #> T07 A15 AG34 NET 'OCB_A16' U1- #> F03 #> T07 A16 AF35 NET 'OCB_A17' U1- #> F05 #> T07 A17 AL40 NET 'OCB_A18' U1- #> F05 #> T07 A18 AK38 NET 'OCB_A19' U1- #> F05 #> T07 A19 AJ40 NET 'OCB_A20' U1- #> F05 #> T07 A20 AH39 NET 'OCB_D00' U1- #> F02 #> T07 D00 AF34 NET 'OCB_D01' U1- #> F02 #> T07 D01 AG33 NET 'OCB_D02' U1- #> F02 #> T07 D02 AH35 NET 'OCB_D03' U1- #> F02 #> T07 D03 AJ35 NET 'OCB_D04' U1- #> F04 #> T07 D04 AF36 NET 'OCB_D05' U1- #> F04 #> T07 D05 AG36 NET 'OCB_D06' U1- #> F04 #> T07 D06 AH38 NET 'OCB_D07' U1- #> F04 #> T07 D07 AJ38 NET 'OCB_D08' U1- #> F04 #> T07 D08 AK37 NET 'OCB_D09' U1- #> F04 #> T07 D09 AL39 NET 'OCB_D10' U1- #> F05 #> T07 D10 AF39 NET 'OCB_D11' U1- #> F05 #> T07 D11 AF37 NET 'OCB_D12' U1- #> F05 #> T07 D12 AG37 NET 'OCB_D13' U1- #> F09 #> T07 D13 AF40 NET 'OCB_D14' U1- #> F09 #> T07 D14 AG41 NET 'OCB_D15' U1- #> F09 #> T07 D15 AG39 NET 'OCB_SYS_RESET_B' U1- #> F09 #> T07 RES AK39 NET 'OCB_WRITE_B' U1- #> F09 #> T07 WRI AJ37 NET 'OCB_DS_B' U1- #> F09 #> T07 DS AH34 # The upper Address (21:23), and all Geographic Address signals are in IO Bank 13 # as these signals are static or thought to change less often and will probably # minimize interaction with the CTP output also using Bank 13. NET 'OCB_A21' U1- #> F02 #> T07 A21 AM34 NET 'OCB_A22' U1- #> F02 #> T07 A22 AL36 NET 'OCB_A23' U1- #> F02 #> T07 A23 AK34 NET 'OCB_GEO_ADRS_0' U1- #> F03 #> T07 GA0 AM37 NET 'OCB_GEO_ADRS_1' U1- #> F03 #> T07 GA1 AM36 NET 'OCB_GEO_ADRS_2' U1- #> F03 #> T07 GA2 AL37 NET 'OCB_GEO_ADRS_3' U1- #> F04 #> T07 GA3 AK35 NET 'OCB_GEO_ADRS_4' U1- #> F05 #> T07 GA4 AM38 NET 'OCB_GEO_ADRS_5' U1- #> F09 #> T07 GA5 AL35 NET 'OCB_GEO_ADRS_6' U1- #> F09 #> T07 GA6 AM39