############################################################################################ # # CMX Net-to-Resource File # -------------------------- # # # Clock Connections to the Base Function FPGA # ----------------------------=============------- # # # # Original Rev. 24-AUG-2012 # Rev. 26-Nov-2012 # Rev: 11-Dec-2012 File name changed for uniformity and consistency between Base and TP files # Rev: 26-Dec-2012 Change "Clk" in net_names to "CLK". # Rev: 29-Dec-2012 Remove the JTAG nets from this file. Remove "jtag" from the filename. # Rev: 16-Jan-2013 Change "Not_Used_" to "No_Conn_". # Rev: 28-Mar-2013 Add third logic global clock # Most Recent Rev: 2-May-2013 Change Logic and GTX clock net names to # reflect the 40.08 or 320.64 MHz LHC clocks # and the 40.000 or 100.000 MHz Crystal clocks # # # Base Function FPGA Clocks for Logic and Transceivers # ---------------------======---------------------------- # # # LHC Locked Logic Clocks # # Connect the 40.08 MHz and 320.64 MHz Logic Clocks to # the Base Function FPGA. These are LHC locked LVDS clock # signals to the Logic in the Base Function FPGA. # # A Global Clock input in I/O Bank 34 receives the DeSkew #1 40.08 MHz Logic clock. # # A Global Clock input in I/O Bank 25 receives the DeSkew #2 40.08 MHz Logic clock. # # A Global Clock input in I/O Bank 34 receives the 320.64 MHz Logic clock. # NET 'CLK_40MHz08_DSKW_1_BF_LOGIC_DIR' U1- # AY14 40.08 MHz DeSkew-1 LHC Logic NET 'CLK_40MHz08_DSKW_1_BF_LOGIC_CMP' U1- # AY13 Clk to the Base Function FPGA NET 'CLK_40MHz08_DSKW_2_BF_LOGIC_DIR' U1- # J42 40.08 MHz DeSkew-2 LHC Logic NET 'CLK_40MHz08_DSKW_2_BF_LOGIC_CMP' U1- # K42 Clk to the Base Function FPGA NET 'CLK_320MHz64_LHC_BF_LOGIC_DIR' U1- # AP12 320.64 MHz LHC Logic Clock NET 'CLK_320MHz64_LHC_BF_LOGIC_CMP' U1- # AP11 to the Base Function FPGA # # Crystal Oscillator #1 GTX Clock # # Now to the Base Function FPGA connect the 40.000 MHz # Crystal Oscillator #1 LVPECL clock to the clock "0" # input of the GTX Transceiver Quad 118. # # This is the "G-Link" transciever for DAQ and RIO readout. # NET 'CLK_40MHz000_XTAL_1_BF_TRNCV_DIR' U1- # C10 40.000 MHz Crystal Osc #1 NET 'CLK_40MHz000_XTAL_1_BF_TRNCV_CMP' U1- # C9 GTX Clk to the BF FPGA # # Crystal Oscillator #2 GTX Clock # # Now to the Base Function FPGA connect the 40.000 MHz # or 100.000 Mhz Crystal Oscillator #2 LVPECL clock to # the clock "0" input of the GTX Transceiver Quad 117. # # This is the clock to the GTX Transcievers that receive # data from the 4 SFP optical components and thus may be # used to receive S-Link control information. # NET 'CLK_100MHz000_XTAL_2_BF_TRNCV_DIR' U1- # G10 100.000 MHz Crystal Osc #2 NET 'CLK_100MHz000_XTAL_2_BF_TRNCV_CMP' U1- # G9 GTX Clk to the BF FPGA # This could also be 40.000 MHz # # LHC Locked GTX Clocks # # Now on the Base Function FPGA connect the 320.64 MHz # LHC locked LVPECL clocks to the clock inputs for # the GTX Transceivers. # # We will use the "0" clock inputs to the Quad Banks # 111 and 114 to receive these Transceiver clocks. # These are the Base Function GTX Transceivers that # send out 6.4 Gbps data to the L1Topo system. # NET 'CLK_320MHz64_LHC_BF_QUAD_111_DIR' U1- # AU10 320.64 MHz LHC GTX Clk #1 NET 'CLK_320MHz64_LHC_BF_QUAD_111_CMP' U1- # AU9 to the Base Function FPGA NET 'CLK_320MHz64_LHC_BF_QUAD_114_DIR' U1- # AB8 320.64 MHz LHC GTX Clk #2 NET 'CLK_320MHz64_LHC_BF_QUAD_114_CMP' U1- # AB7 to the Base Function FPGA # # Now on the Base Function FPGA connect ALL of the # UN-Used Tranceiver Clock Inputs to single point nets. # # Not Used Bank 110 Clock Inputs NET 'No_Conn_BF_GTX_CLK_0_110_DIR' U1- # pin BA10 NET 'No_Conn_BF_GTX_CLK_0_110_CMP' U1- # pin BA9 NET 'No_Conn_BF_GTX_CLK_1_110_DIR' U1- # pin AW10 NET 'No_Conn_BF_GTX_CLK_1_110_CMP' U1- # pin AW9 # Not Used Bank 111 Clock Input NET 'No_Conn_BF_GTX_CLK_1_111_DIR' U1- # pin AT8 NET 'No_Conn_BF_GTX_CLK_1_111_CMP' U1- # pin AT7 # Not Used Bank 112 Clock Inputs NET 'No_Conn_BF_GTX_CLK_0_112_DIR' U1- # pin AK8 NET 'No_Conn_BF_GTX_CLK_0_112_CMP' U1- # pin AK7 NET 'No_Conn_BF_GTX_CLK_1_112_DIR' U1- # pin AH8 NET 'No_Conn_BF_GTX_CLK_1_112_CMP' U1- # pin AH7 # Not Used Bank 113 Clock Inputs NET 'No_Conn_BF_GTX_CLK_0_113_DIR' U1- # pin AF8 NET 'No_Conn_BF_GTX_CLK_0_113_CMP' U1- # pin AF7 NET 'No_Conn_BF_GTX_CLK_1_113_DIR' U1- # pin AD8 NET 'No_Conn_BF_GTX_CLK_1_113_CMP' U1- # pin AD7 # Not Used Bank 114 Clock Input NET 'No_Conn_BF_GTX_CLK_1_114_DIR' U1- # pin Y8 NET 'No_Conn_BF_GTX_CLK_1_114_CMP' U1- # pin Y7 # Not Used Bank 115 Clock Inputs NET 'No_Conn_BF_GTX_CLK_0_115_DIR' U1- # pin V8 NET 'No_Conn_BF_GTX_CLK_0_115_CMP' U1- # pin V7 NET 'No_Conn_BF_GTX_CLK_1_115_DIR' U1- # pin T8 NET 'No_Conn_BF_GTX_CLK_1_115_CMP' U1- # pin T7 # Not Used Bank 116 Clock Inputs NET 'No_Conn_BF_GTX_CLK_0_116_DIR' U1- # pin M8 NET 'No_Conn_BF_GTX_CLK_0_116_CMP' U1- # pin M7 NET 'No_Conn_BF_GTX_CLK_1_116_DIR' U1- # pin K8 NET 'No_Conn_BF_GTX_CLK_1_116_CMP' U1- # pin K7 # Not Used Bank 117 Clock Input NET 'No_Conn_BF_GTX_CLK_1_117_DIR' U1- # pin E10 NET 'No_Conn_BF_GTX_CLK_1_117_CMP' U1- # pin E9 # Not Used Bank 118 Clock Input NET 'No_Conn_BF_GTX_CLK_1_118_DIR' U1- # pin A10 NET 'No_Conn_BF_GTX_CLK_1_118_CMP' U1- # pin A9