############################################################################################
#
#                            CMX Net-to-Resource File for the
#              Base Function FPGA IO signals used for the connections to the Debug Connector
#             -=============------------------------------------------======================
#
#
#     Original Rev. 28-Mar-2012
#              Rev. 28-Mar-2013 find location for these 10x signals without interfering with backplane inputs
#              Rev: 30-May-2013 BF debug connections were re-arranged after the layout of the backplane inputs
#  Most Recent Rev: 10-Jul-2013 Reorder pin assignment for straight route near debug connector
#
#  Signal Nets referenced in this file:
#  ------------------------------------
#
#   BF_DEBUG_n            (n=0:9)  10x spare connections from the BF FPGA to debug connector J14
#
############################################################################################


# 10x signals are going to the Debug Connector on layer 6
# These signals are listed in west to east order as they come out of the FPGA on layer 6
# The order of the BF_DEBUG_n nets may be adjusted to optimize access near J14

NET  'BF_DEBUG_0'                      U1-<IO_L7P_38>            #> F06 #> T06        B27
NET  'BF_DEBUG_1'                      U1-<IO_L10N_MRCC_38>      #> F06 #> T06        M21
NET  'BF_DEBUG_2'                      U1-<IO_L13P_38>           #> F06 #> T06        C26
NET  'BF_DEBUG_3'                      U1-<IO_L10P_MRCC_38>      #> F06 #> T06        N21
NET  'BF_DEBUG_4'                      U1-<IO_L1N_38>            #> F06 #> T06        D27
NET  'BF_DEBUG_5'                      U1-<IO_L9P_MRCC_38>       #> F06 #> T06        M19
NET  'BF_DEBUG_6'                      U1-<IO_L3P_38>            #> F06 #> T06        C28
NET  'BF_DEBUG_7'                      U1-<IO_L14P_38>           #> F06 #> T06        M22
NET  'BF_DEBUG_8'                      U1-<IO_L3N_38>            #> F06 #> T06        B28
NET  'BF_DEBUG_9'                      U1-<IO_L8P_SRCC_38>       #> F06 #> T06        J23

# note: other Select IO pins on IO Bank 38 are used for connections to the BSPT FPGA
#       cf. base_function_25_bspt_connections_n2r.txt