#
#                     CMX FF1759 Package NET-to-Pin File
#                   --------------------------------------
#
#
#                         Bank 0  and  Special  Pins
#                       ------===---------------------
#
#
#
#                                                 Original Rev. 29-Dec-2012
#                                              Most Recent Rev. 18-Mar-2012
#
#
#
#  This is the N2P file for  Virtex-6  "Bank 0"  and  Special
#  Nets for the CMX Base Function FPGA.
#
#  Pins with many and completely different functions are
#  included in what Xilinx calls "Bank 0".   These are not
#  Select I/O pins.   Rather these pins include those that
#  are involved with thinks like  Configuration, System
#  Monitor, JTAG,  Power Management,  Si temperature
#  measurement, ...
#
#  These are all  special one of a kind fixed location pins.
#
#  Other "special" pins, besides those in "Bank 0"  should
#  be included in this  Net to Pin  file.  Recall, we want
#  to assign a net to every one of the 1760 pins on this
#  component.
#
#
#  This file is for the Base Function FPGA on the CMX card.
#                       -------------
#


#
#  JTAG connections to the Base Function FPGA
#
#    On the CMX's Virtex-6 FPGAs the JTAG connections
#    are pins in "Bank 0"


NET  'CFG_TMS_from_ACE'       U1-AN11     #  TMS_0  CFG JTAG TMS from ACE pin 85

NET  'CFG_TCK_from_ACE'       U1-AN10     #  TCK_0  CFG JTAG TCK from ACE pin 80

NET  'CFG_ACE_TDO_to_BF_TDI'  U1-AP10     #  TDI_0  CFG JTAG Data from ACE to BF

NET  'CFG_BF_TDO'             U1-AR10     #  TDO_0  CFG JTAG Data from BF to TP




#
#  Configuration Nets

NET  'BF_PROGRAM_B'           U1-M11      #  PROGRAM_B_0

NET  'BF_INIT_B'              U1-N11      #  INIT_B_0

NET  'BF_CONFIG_DONE'         U1-N10      #  DONE_0

NET  'BF_M0'                  U1-AL11     #  M0_0

NET  'BF_M1'                  U1-AM11     #  M1_0

NET  'BF_M2'                  U1-AL10     #  M2_0

NET  'BF_CCLK'                U1-K10      #  CCLK_0

NET  'BF_DIN'                 U1-L10      #  DIN_0

NET  'BF_DOUT_BUSY'           U1-AK10     #  DOUT_BUSY_0

NET  'BF_CSI_B'               U1-T10      #  CSI_B_0

NET  'BF_RDWR_B'              U1-J10      #  RDWR_B_0



#
#  System Monitor Nets

NET  'BF_SM_AVDD'             U1-Y22      #  AVDD_0

NET  'BF_SM_AVSS'             U1-Y21      #  AVSS_0

NET  'BF_SM_VP'               U1-AA22     #  VP_0

NET  'BF_SM_VN'               U1-AB21     #  VN_0

NET  'BF_SM_VREFP'            U1-AB22     #  VREFP_0

NET  'BF_SM_AVSS'             U1-AA21     #  VREFN_0



#
#  Silicon Temperature Nets

NET  'BF_SI_TEMP_DXP'         U1-AC22     #  DXP_0

NET  'BF_SI_TEMP_DXN'         U1-AC21     #  DXN_0





#
#  Other Special "Bank 0" Nets

NET  'BF_HSWAPEN'             U1-P10      #  HSWAPEN_0



#  VBATT is a power supply pin for the Decryptor Key memory.
#  The book says that when VBATT is not used to connect
#  this pin to either VccAUX or to GROUND.  CMX will not
#  use the Decryptor Key VBATT supply.  CMX will
#  permanently and irrevocably Ground this pin.
#
## NET  'BF_VBATT'            U1-R10      #  VBATT_0

NET     'GROUND'              U1-R10      #  VBATT_0



#  VFS is a power supply pin for programming the EFUSE.
#  The book says to Ground the VFS pin when it is not
#  being used.  CMX will not use the EFUSE.  Thus CMX
#  will permanently and irrevocably Ground this pin.
#
## NET  'BF_VFS'              U1-AH10     #  VFS_0

NET     'GROUND'              U1-AH10     #  VFS_0





#
#  Special Non-Bank 0 Nets