# # CMX Backplane LVDS Cable IO Net-to-Pin File # ------------------------------------------------- # # # Original Rev. 13-Oct-2011 # Rev. 14-Aug-2012 comment all out for change of IC # Rev. 22-Aug-2012 switch to using DS91M040 and 2.5-3.3V translators # Rev. 31-Aug-2012 Add layer assignment in comment # Rev: 07-Sep-2012 Add header comments # Rev: 2-Nov-2012 Edit what channels are used in the 74AVCAH164245 translators # to use the channels closest to the center of the pcb, i.e. # give as much space as possible to the 400 Processor Inputs # Most Recent Rev: 19-Nov-2012 Move layer assignment to match re-work of backplane inputs # Note: signals 81,82,83 were moved to layer 10 (bottom) to be determined. # # # ICs referenced in this file: # ---------------------------- # # U21 to U41 are National Semiconductor DS91M040 LVDS transceivers # # U42 to U47 are Texas Instrument 74AVCAH164245 level translators to interface between # the 2.5V CMOS logic level of the FPGA IO banks # and the 3.3V CMOS level side of the LVDS transceivers # # Signal Nets referenced in this file: # ------------------------------------ # # 'M_zz_POS' and 'M_zz_NEG' are the LVDS signal used for Cable IO # from a Crate CMX card to a System CMX card. 'M_zz_POS' is the # non-inverted signal and 'M_zz_NEG' is the inverted signal. # # There are up to 3 cables used for a given CMX card. # A Crate CMX card uses one cable as output only, # while a System CMX card receives 2 or 3 cables as input. # # A Rear Transition Module (RTM) card provides the interface to the three 34-signal # LVDS connectors where the IO cables can be connected. # Only 27 signals from each connector are routed on the current RTM cards. # zz=0 to 26 correspond to the first cable, # zz=27 to 53 correspond to the second cable, and # zz=54 to 80 correspond to the third cable. # # Additionally, 3 more differential pairs of signals are labelled on the backplane # but are not routed on the RTM: zz= 31 to 83 # The CMX card will route the currently unused M_81, M_82, and M_83 signals # to become usable as cable IO signals. The sets of cable signals thus are: # Cable #1 consists of signals M_00 to M_26 plus M_81 # Cable #2 consists of signals M_27 to M_53 plus M_82 # Cable #3 consists of signals M_54 to M_80 plus M_83 # The CMX card could thus be able to use 28 LVDS signals per cable while the CMM was only able # to use 27 signals. Using 28 signals would however require a new version of the RTM card. # This 28th signal can be left unused and set to a fixed state by the FPGA of the source Crate CMX # while the LVDS transceiver of the receiving System CMX will default to a defined value # for all non-connected inputs. # # The backplane connections for these M_zz signals are in files # backplane_connector_4_n2p.txt, backplane_connector_5_n2p.txt, and backplane_connector_6_n2p.txt # located in the the Net_Lists/Connectors_Backplane directory # # Each differential M_zz signal is connected to a DS91M040 transceiver channel. # Note that we connect *all* these signals backwards from the normal DS91M040 polarity. # This is to avoid needing to systematically crossing the traces from the two halves # of the signal at the transceiver end. # We thus connect the 'M_zz_POS' to a pin from the transceiver coresponding # to the inverted half of the differential signal and we connect the 'M_zz_NEG' # to a pin from the transceiver coresponding to the non-inverted half # of the differential signal. The signal on the single ended side # of the transceiver will thus be the inverse of the conventional # LVDS polarity on the cable. This can either be ignored since a CMX card # with this inversion is used at both the source and receiving end of the # connection which inverts the signal twice, OR the signal can also easily # be inverted at the FPGA IO block. # # The three LVDS cables will be able to operate as input or output independently # of each other (this feature is not necessary in normal operation, but useful for testing). # For each set of 28 cable signal we thus use two 16-wide 74AVCAH164245 level translator # chips and seven 4-channel DS91M040 LVDS transceivers. The direction for each set # of 38 cable signal is controlled independently. # # 'D_CBL_zz_B' are the cable IO signals available to the Base FPGA with zz=00 to 83. # The "_B" postfix is used to indicate that these signals are inverted with respect # to the LVDS signal polarity on the data cables. # These signals are connected here to the 2.5V side of the 74AVCAH164245 level translators. # The FPGA connections for the D_CBL_zz signals are in the file backplane_cable_io_n2r.txt # in the Net_Lists/Base_Fpga_Assign directory # # 'I_CBL_zz_B' are the intermediate cable IO signals with zz=00 to 83. # These signals connect the single ended side of the LVDS transceiver # to the 3.3V side of the 74AVCAH164245 level translators. # The "_B" postfix is used to indicate that these signals are inverted with respect # to the LVDS signal polarity on the data cables. # # # Note: Trace layer information is appended as comments below. # ----- # NET 'M_00_POS' U21-24 #> T02 # # ^ ^ # | | # Tailored comment flag to help with string searches -+ | # | # Target Trace Layer number to use for this net ----------+ # T01 is top layer, T02 the first inner layer, etc # ############################################################################################ # # Cable #1 consists of signals M_00 to M_26 plus M_81 # --------------------------------------------------- NET 'M_00_POS' U21-24 R21-1 #> T02 non-inverted Cable IO LVDS signal #00 # from backplane to non-inverted side of the # transceiver and termination resistor NET 'M_00_NEG' U21-23 R21-2 #> T02 inverted Cable IO LVDS signal #00 # from backplane to inverted side of the # transceiver and termination resistor NET 'I_CBL_00_B' U21-1 U21-2 U42-17 # intermediate connection between the two # 3.3V single ended ends of the LVDS # transceiver and the level translator NET 'D_CBL_00_B' U42-32 #> T02 2.5V side of the level translator NET 'M_01_POS' U21-22 R22-1 #> T05 (ditto for Cable IO signals 01 to 83 below...) NET 'M_01_NEG' U21-21 R22-2 #> T05 NET 'I_CBL_01_B' U21-3 U21-4 U42-16 NET 'D_CBL_01_B' U42-33 #> T02 NET 'M_02_POS' U21-20 R23-1 #> T03 NET 'M_02_NEG' U21-19 R23-2 #> T03 NET 'I_CBL_02_B' U21-5 U21-6 U42-14 NET 'D_CBL_02_B' U42-35 #> T02 NET 'M_03_POS' U21-18 R24-1 #> T09 NET 'M_03_NEG' U21-17 R24-2 #> T09 NET 'I_CBL_03_B' U21-7 U21-8 U42-13 NET 'D_CBL_03_B' U42-36 #> T02 NET 'M_04_POS' U22-24 R25-1 #> T04 NET 'M_04_NEG' U22-23 R25-2 #> T04 NET 'I_CBL_04_B' U22-1 U22-2 U42-12 NET 'D_CBL_04_B' U42-37 #> T02 NET 'M_05_POS' U22-22 R26-1 #> T02 NET 'M_05_NEG' U22-21 R26-2 #> T02 NET 'I_CBL_05_B' U22-3 U22-4 U42-11 NET 'D_CBL_05_B' U42-38 #> T02 NET 'M_06_POS' U22-20 R27-1 #> T05 NET 'M_06_NEG' U22-19 R27-2 #> T05 NET 'I_CBL_06_B' U22-5 U22-6 U42-9 NET 'D_CBL_06_B' U42-40 #> T02 NET 'M_07_POS' U22-18 R28-1 #> T03 NET 'M_07_NEG' U22-17 R28-2 #> T03 NET 'I_CBL_07_B' U22-7 U22-8 U42-8 NET 'D_CBL_07_B' U42-41 #> T02 NET 'M_08_POS' U23-24 R29-1 #> T04 NET 'M_08_NEG' U23-23 R29-2 #> T04 NET 'I_CBL_08_B' U23-1 U23-2 U42-6 NET 'D_CBL_08_B' U42-43 #> T02 NET 'M_09_POS' U23-22 R30-1 #> T02 NET 'M_09_NEG' U23-21 R30-2 #> T02 NET 'I_CBL_09_B' U23-3 U23-4 U42-5 NET 'D_CBL_09_B' U42-44 #> T02 NET 'M_10_POS' U23-20 R31-1 #> T05 NET 'M_10_NEG' U23-19 R31-2 #> T05 NET 'I_CBL_10_B' U23-5 U23-6 U42-3 NET 'D_CBL_10_B' U42-46 #> T02 NET 'M_11_POS' U23-18 R32-1 #> T03 NET 'M_11_NEG' U23-17 R32-2 #> T03 NET 'I_CBL_11_B' U23-7 U23-8 U42-2 NET 'D_CBL_11_B' U42-47 #> T02 NET 'M_12_POS' U24-24 R33-1 #> T09 NET 'M_12_NEG' U24-23 R33-2 #> T09 NET 'I_CBL_12_B' U24-1 U24-2 U43-23 NET 'D_CBL_12_B' U43-26 #> T02 NET 'M_13_POS' U24-22 R34-1 #> T04 NET 'M_13_NEG' U24-21 R34-2 #> T04 NET 'I_CBL_13_B' U24-3 U24-4 U43-22 NET 'D_CBL_13_B' U43-27 #> T02 NET 'M_14_POS' U24-20 R35-1 #> T02 NET 'M_14_NEG' U24-19 R35-2 #> T02 NET 'I_CBL_14_B' U24-5 U24-6 U43-20 NET 'D_CBL_14_B' U43-29 #> T02 NET 'M_15_POS' U24-18 R36-1 #> T03 NET 'M_15_NEG' U24-17 R36-2 #> T03 NET 'I_CBL_15_B' U24-7 U24-8 U43-19 NET 'D_CBL_15_B' U43-30 #> T02 NET 'M_16_POS' U25-24 R37-1 #> T09 NET 'M_16_NEG' U25-23 R37-2 #> T09 NET 'I_CBL_16_B' U25-1 U25-2 U43-17 NET 'D_CBL_16_B' U43-32 #> T02 NET 'M_17_POS' U25-22 R38-1 #> T04 NET 'M_17_NEG' U25-21 R38-2 #> T04 NET 'I_CBL_17_B' U25-3 U25-4 U43-16 NET 'D_CBL_17_B' U43-33 #> T02 NET 'M_18_POS' U25-20 R39-1 #> T02 NET 'M_18_NEG' U25-19 R39-2 #> T02 NET 'I_CBL_18_B' U25-5 U25-6 U43-14 NET 'D_CBL_18_B' U43-35 #> T05 NET 'M_19_POS' U25-18 R40-1 #> T05 NET 'M_19_NEG' U25-17 R40-2 #> T05 NET 'I_CBL_19_B' U25-7 U25-8 U43-13 NET 'D_CBL_19_B' U43-36 #> T05 NET 'M_20_POS' U26-24 R41-1 #> T03 NET 'M_20_NEG' U26-23 R41-2 #> T03 NET 'I_CBL_20_B' U26-1 U26-2 U43-12 NET 'D_CBL_20_B' U43-37 #> T05 NET 'M_21_POS' U26-22 R42-1 #> T09 NET 'M_21_NEG' U26-21 R42-2 #> T09 NET 'I_CBL_21_B' U26-3 U26-4 U43-11 NET 'D_CBL_21_B' U43-38 #> T05 NET 'M_22_POS' U26-20 R43-1 #> T04 NET 'M_22_NEG' U26-19 R43-2 #> T04 NET 'I_CBL_22_B' U26-5 U26-6 U43-9 NET 'D_CBL_22_B' U43-40 #> T05 NET 'M_23_POS' U26-18 R44-1 #> T02 NET 'M_23_NEG' U26-17 R44-2 #> T02 NET 'I_CBL_23_B' U26-7 U26-8 U43-8 NET 'D_CBL_23_B' U43-41 #> T05 NET 'M_24_POS' U27-24 R45-1 #> T05 NET 'M_24_NEG' U27-23 R45-2 #> T05 NET 'I_CBL_24_B' U27-1 U27-2 U43-6 NET 'D_CBL_24_B' U43-43 #> T04 NET 'M_25_POS' U27-22 R46-1 #> T03 NET 'M_25_NEG' U27-21 R46-2 #> T03 NET 'I_CBL_25_B' U27-3 U27-4 U43-5 NET 'D_CBL_25_B' U43-44 #> T04 NET 'M_26_POS' U27-20 R47-1 #> T04 NET 'M_26_NEG' U27-19 R47-2 #> T04 NET 'I_CBL_26_B' U27-5 U27-6 U43-3 NET 'D_CBL_26_B' U43-46 #> T04 NET 'M_81_POS' U27-18 R48-1 #> T10 NET 'M_81_NEG' U27-17 R48-2 #> T10 NET 'I_CBL_81_B' U27-7 U27-8 U43-2 NET 'D_CBL_81_B' U43-47 #> T04 # # Cable #2 consists of signals M_27 to M_53 plus M_82 # --------------------------------------------------- NET 'M_27_POS' U28-24 R49-1 #> T02 NET 'M_27_NEG' U28-23 R49-2 #> T02 NET 'I_CBL_27_B' U28-1 U28-2 U44-20 NET 'D_CBL_27_B' U44-29 #> T04 NET 'M_28_POS' U28-22 R50-1 #> T05 NET 'M_28_NEG' U28-21 R50-2 #> T05 NET 'I_CBL_28_B' U28-3 U28-4 U44-19 NET 'D_CBL_28_B' U44-30 #> T04 NET 'M_29_POS' U28-20 R51-1 #> T03 NET 'M_29_NEG' U28-19 R51-2 #> T03 NET 'I_CBL_29_B' U28-5 U28-6 U44-17 NET 'D_CBL_29_B' U44-32 #> T04 NET 'M_30_POS' U28-18 R52-1 #> T09 NET 'M_30_NEG' U28-17 R52-2 #> T09 NET 'I_CBL_30_B' U28-7 U28-8 U44-16 NET 'D_CBL_30_B' U44-33 #> T04 NET 'M_31_POS' U29-24 R53-1 #> T04 NET 'M_31_NEG' U29-23 R53-2 #> T04 NET 'I_CBL_31_B' U29-1 U29-2 U44-14 NET 'D_CBL_31_B' U44-35 #> T04 NET 'M_32_POS' U29-22 R54-1 #> T02 NET 'M_32_NEG' U29-21 R54-2 #> T02 NET 'I_CBL_32_B' U29-3 U29-4 U44-13 NET 'D_CBL_32_B' U44-36 #> T04 NET 'M_33_POS' U29-20 R55-1 #> T03 NET 'M_33_NEG' U29-19 R55-2 #> T03 NET 'I_CBL_33_B' U29-5 U29-6 U44-12 NET 'D_CBL_33_B' U44-37 #> T09 NET 'M_34_POS' U29-18 R56-1 #> T09 NET 'M_34_NEG' U29-17 R56-2 #> T09 NET 'I_CBL_34_B' U29-7 U29-8 U44-11 NET 'D_CBL_34_B' U44-38 #> T09 NET 'M_35_POS' U30-24 R57-1 #> T04 NET 'M_35_NEG' U30-23 R57-2 #> T04 NET 'I_CBL_35_B' U30-1 U30-2 U44-9 NET 'D_CBL_35_B' U44-40 #> T09 NET 'M_36_POS' U30-22 R58-1 #> T02 NET 'M_36_NEG' U30-21 R58-2 #> T02 NET 'I_CBL_36_B' U30-3 U30-4 U44-8 NET 'D_CBL_36_B' U44-41 #> T09 NET 'M_37_POS' U30-20 R59-1 #> T05 NET 'M_37_NEG' U30-19 R59-2 #> T05 NET 'I_CBL_37_B' U30-5 U30-6 U44-6 NET 'D_CBL_37_B' U44-43 #> T09 NET 'M_38_POS' U30-18 R60-1 #> T03 NET 'M_38_NEG' U30-17 R60-2 #> T03 NET 'I_CBL_38_B' U30-7 U30-8 U44-5 NET 'D_CBL_38_B' U44-44 #> T08 NET 'M_39_POS' U31-24 R61-1 #> T09 NET 'M_39_NEG' U31-23 R61-2 #> T09 NET 'I_CBL_39_B' U31-1 U31-2 U44-3 NET 'D_CBL_39_B' U44-46 #> T08 NET 'M_40_POS' U31-22 R62-1 #> T04 NET 'M_40_NEG' U31-21 R62-2 #> T04 NET 'I_CBL_40_B' U31-3 U31-4 U44-2 NET 'D_CBL_40_B' U44-47 #> T10 NET 'M_41_POS' U31-20 R63-1 #> T02 NET 'M_41_NEG' U31-19 R63-2 #> T02 NET 'I_CBL_41_B' U31-5 U31-6 U45-23 NET 'D_CBL_41_B' U45-26 #> T10 NET 'M_42_POS' U31-18 R64-1 #> T05 NET 'M_42_NEG' U31-17 R64-2 #> T05 NET 'I_CBL_42_B' U31-7 U31-8 U45-22 NET 'D_CBL_42_B' U45-27 #> T10 NET 'M_43_POS' U32-24 R65-1 #> T03 NET 'M_43_NEG' U32-23 R65-2 #> T03 NET 'I_CBL_43_B' U32-1 U32-2 U45-20 NET 'D_CBL_43_B' U45-29 #> T10 NET 'M_44_POS' U32-22 R66-1 #> T04 NET 'M_44_NEG' U32-21 R66-2 #> T04 NET 'I_CBL_44_B' U32-3 U32-4 U45-19 NET 'D_CBL_44_B' U45-30 #> T03 NET 'M_45_POS' U32-20 R67-1 #> T02 NET 'M_45_NEG' U32-19 R67-2 #> T02 NET 'I_CBL_45_B' U32-5 U32-6 U45-17 NET 'D_CBL_45_B' U45-32 #> T03 NET 'M_46_POS' U32-18 R68-1 #> T05 NET 'M_46_NEG' U32-17 R68-2 #> T05 NET 'I_CBL_46_B' U32-7 U32-8 U45-16 NET 'D_CBL_46_B' U45-33 #> T03 NET 'M_47_POS' U33-24 R69-1 #> T03 NET 'M_47_NEG' U33-23 R69-2 #> T03 NET 'I_CBL_47_B' U33-1 U33-2 U45-14 NET 'D_CBL_47_B' U45-35 #> T03 NET 'M_48_POS' U33-22 R70-1 #> T09 NET 'M_48_NEG' U33-21 R70-2 #> T09 NET 'I_CBL_48_B' U33-3 U33-4 U45-13 NET 'D_CBL_48_B' U45-36 #> T03 NET 'M_49_POS' U33-20 R71-1 #> T04 NET 'M_49_NEG' U33-19 R71-2 #> T04 NET 'I_CBL_49_B' U33-5 U33-6 U45-12 NET 'D_CBL_49_B' U45-37 #> T03 NET 'M_50_POS' U33-18 R72-1 #> T02 NET 'M_50_NEG' U33-17 R72-2 #> T02 NET 'I_CBL_50_B' U33-7 U33-8 U45-11 NET 'D_CBL_50_B' U45-38 #> T03 NET 'M_51_POS' U34-24 R73-1 #> T05 NET 'M_51_NEG' U34-23 R73-2 #> T05 NET 'I_CBL_51_B' U34-1 U34-2 U45-9 NET 'D_CBL_51_B' U45-40 #> T03 NET 'M_52_POS' U34-22 R74-1 #> T09 NET 'M_52_NEG' U34-21 R74-2 #> T09 NET 'I_CBL_52_B' U34-3 U34-4 U45-8 NET 'D_CBL_52_B' U45-41 #> T03 NET 'M_53_POS' U34-20 R75-1 #> T04 NET 'M_53_NEG' U34-19 R75-2 #> T04 NET 'I_CBL_53_B' U34-5 U34-6 U45-6 NET 'D_CBL_53_B' U45-43 #> T03 NET 'M_82_POS' U34-18 R76-1 #> T10 NET 'M_82_NEG' U34-17 R76-2 #> T10 NET 'I_CBL_82_B' U34-7 U34-8 U45-5 NET 'D_CBL_82_B' U45-44 #> T03 # # Cable #3 consists of signals M_54 to M_80 plus M_83 # --------------------------------------------------- NET 'M_54_POS' U35-24 R77-1 #> T05 NET 'M_54_NEG' U35-23 R77-2 #> T05 NET 'I_CBL_54_B' U35-1 U35-2 U46-23 NET 'D_CBL_54_B' U46-26 #> T03 NET 'M_55_POS' U35-22 R78-1 #> T03 NET 'M_55_NEG' U35-21 R78-2 #> T03 NET 'I_CBL_55_B' U35-3 U35-4 U46-22 NET 'D_CBL_55_B' U46-27 #> T02 NET 'M_56_POS' U35-20 R79-1 #> T09 NET 'M_56_NEG' U35-19 R79-2 #> T09 NET 'I_CBL_56_B' U35-5 U35-6 U46-20 NET 'D_CBL_56_B' U46-29 #> T02 NET 'M_57_POS' U35-18 R80-1 #> T04 NET 'M_57_NEG' U35-17 R80-2 #> T04 NET 'I_CBL_57_B' U35-7 U35-8 U46-19 NET 'D_CBL_57_B' U46-30 #> T02 NET 'M_58_POS' U36-24 R81-1 #> T05 NET 'M_58_NEG' U36-23 R81-2 #> T05 NET 'I_CBL_58_B' U36-1 U36-2 U46-17 NET 'D_CBL_58_B' U46-32 #> T02 NET 'M_59_POS' U36-22 R82-1 #> T09 NET 'M_59_NEG' U36-21 R82-2 #> T09 NET 'I_CBL_59_B' U36-3 U36-4 U46-16 NET 'D_CBL_59_B' U46-33 #> T02 NET 'M_60_POS' U36-20 R83-1 #> T04 NET 'M_60_NEG' U36-19 R83-2 #> T04 NET 'I_CBL_60_B' U36-5 U36-6 U46-14 NET 'D_CBL_60_B' U46-35 #> T05 NET 'M_61_POS' U36-18 R84-1 #> T03 NET 'M_61_NEG' U36-17 R84-2 #> T03 NET 'I_CBL_61_B' U36-7 U36-8 U46-13 NET 'D_CBL_61_B' U46-36 #> T05 NET 'M_62_POS' U37-24 R85-1 #> T09 NET 'M_62_NEG' U37-23 R85-2 #> T09 NET 'I_CBL_62_B' U37-1 U37-2 U46-12 NET 'D_CBL_62_B' U46-37 #> T05 NET 'M_63_POS' U37-22 R86-1 #> T04 NET 'M_63_NEG' U37-21 R86-2 #> T04 NET 'I_CBL_63_B' U37-3 U37-4 U46-11 NET 'D_CBL_63_B' U46-38 #> T05 NET 'M_64_POS' U37-20 R87-1 #> T05 NET 'M_64_NEG' U37-19 R87-2 #> T05 NET 'I_CBL_64_B' U37-5 U37-6 U46-9 NET 'D_CBL_64_B' U46-40 #> T05 NET 'M_65_POS' U37-18 R88-1 #> T03 NET 'M_65_NEG' U37-17 R88-2 #> T03 NET 'I_CBL_65_B' U37-7 U37-8 U46-8 NET 'D_CBL_65_B' U46-41 #> T05 NET 'M_66_POS' U38-24 R89-1 #> T04 NET 'M_66_NEG' U38-23 R89-2 #> T04 NET 'I_CBL_66_B' U38-1 U38-2 U46-6 NET 'D_CBL_66_B' U46-43 #> T09 NET 'M_67_POS' U38-22 R90-1 #> T03 NET 'M_67_NEG' U38-21 R90-2 #> T03 NET 'I_CBL_67_B' U38-3 U38-4 U46-5 NET 'D_CBL_67_B' U46-44 #> T09 NET 'M_68_POS' U38-20 R91-1 #> T09 NET 'M_68_NEG' U38-19 R91-2 #> T09 NET 'I_CBL_68_B' U38-5 U38-6 U46-3 NET 'D_CBL_68_B' U46-46 #> T09 NET 'M_69_POS' U38-18 R92-1 #> T04 NET 'M_69_NEG' U38-17 R92-2 #> T04 NET 'I_CBL_69_B' U38-7 U38-8 U46-2 NET 'D_CBL_69_B' U46-47 #> T09 NET 'M_70_POS' U39-24 R93-1 #> T03 NET 'M_70_NEG' U39-23 R93-2 #> T03 NET 'I_CBL_70_B' U39-1 U39-2 U47-23 NET 'D_CBL_70_B' U47-26 #> T04 NET 'M_71_POS' U39-22 R94-1 #> T09 NET 'M_71_NEG' U39-21 R94-2 #> T09 NET 'I_CBL_71_B' U39-3 U39-4 U47-22 NET 'D_CBL_71_B' U47-27 #> T10 NET 'M_72_POS' U39-20 R95-1 #> T04 NET 'M_72_NEG' U39-19 R95-2 #> T04 NET 'I_CBL_72_B' U39-5 U39-6 U47-20 NET 'D_CBL_72_B' U47-29 #> T10 NET 'M_73_POS' U39-18 R96-1 #> T09 NET 'M_73_NEG' U39-17 R96-2 #> T09 NET 'I_CBL_73_B' U39-7 U39-8 U47-19 NET 'D_CBL_73_B' U47-30 #> T10 NET 'M_74_POS' U40-24 R97-1 #> T04 NET 'M_74_NEG' U40-23 R97-2 #> T04 NET 'I_CBL_74_B' U40-1 U40-2 U47-17 NET 'D_CBL_74_B' U47-32 #> T10 NET 'M_75_POS' U40-22 R98-1 #> T09 NET 'M_75_NEG' U40-21 R98-2 #> T09 NET 'I_CBL_75_B' U40-3 U40-4 U47-16 NET 'D_CBL_75_B' U47-33 #> T10 NET 'M_76_POS' U40-20 R99-1 #> T09 NET 'M_76_NEG' U40-19 R99-2 #> T09 NET 'I_CBL_76_B' U40-5 U40-6 U47-14 NET 'D_CBL_76_B' U47-35 #> T10 NET 'M_77_POS' U40-18 R100-1 #> T04 NET 'M_77_NEG' U40-17 R100-2 #> T04 NET 'I_CBL_77_B' U40-7 U40-8 U47-13 NET 'D_CBL_77_B' U47-36 #> T08 NET 'M_78_POS' U41-24 R101-1 #> T04 NET 'M_78_NEG' U41-23 R101-2 #> T04 NET 'I_CBL_78_B' U41-1 U41-2 U47-12 NET 'D_CBL_78_B' U47-37 #> T08 NET 'M_79_POS' U41-22 R102-1 #> T04 NET 'M_79_NEG' U41-21 R102-2 #> T04 NET 'I_CBL_79_B' U41-3 U41-4 U47-11 NET 'D_CBL_79_B' U47-38 #> T08 NET 'M_80_POS' U41-20 R103-1 #> T04 NET 'M_80_NEG' U41-19 R103-2 #> T04 NET 'I_CBL_80_B' U41-5 U41-6 U47-9 NET 'D_CBL_80_B' U47-40 #> T08 NET 'M_83_POS' U41-18 R104-1 #> T10 NET 'M_83_NEG' U41-17 R104-2 #> T10 NET 'I_CBL_83_B' U41-7 U41-8 U47-8 NET 'D_CBL_83_B' U47-41 #> T08 # # CMX-0 Nets File # # Backplane LVDS Management Nets # --=========------------------------ # # # Original Rev. 1-Nov-2012 # Most Recent Rev. 4-Apr-2013 # # # # This file holds the nets involved in the management of the # Backplane LVDS Transceivers and Level Translators. # -------------- # # # The intent is to provide management of the backplane LVDS # connections so that the BF FPGA can independently choose # to Receive, Drive, or Ignore the 3 Backplane LVDS Cables. # # For each of the 3 Backplane LVDS Cables the intent is # that the BF_FPGA will have just 1 control signals, i.e. # a Direction signal signals. # # For each of the 3 Backplane LVDS Cables there will be # logic in the BSPT FPGA that take the direction request # signal from the BF FPGA and makes up the 3 control # signals that run to the Transceivers and Translators # for each Cable. The OE_B control signal to the # Translators goes through Hardwired Oversight Logic # that is between the BSPT and the Cable Translator # chips. # # The control to the OE_B pins to the Cable Translator # chips come from U363 in the Hardwired Oversight Logic. # # These OE_B signals to the Translator chips are named: # # CABLE_1_TRNSLT_OE_B # CABLE_2_TRNSLT_OE_B # CABLE_3_TRNSLT_OE_B # # These control signals originate in the BSPT FPGA but # pass through the Hardwired Oversight Logic on their # way to the OE_B pins on the Cable Translator chips. # As these signals come out of the BSPT FPGA that # are named: # # BSPT_CABLE_1_TRNSLT_OE_B # BSPT_CABLE_2_TRNSLT_OE_B # BSPT_CABLE_3_TRNSLT_OE_B # # # The UPPER set of Backplane LVDS management signals # ------- -------------- NET 'CABLE_1_TRNSLT_DIR' U42-1 U42-24 # Direction of 2V5<->3V3 Translators NET 'CABLE_1_TRNSLT_DIR' U43-1 U43-24 # Direction of 2V5<->3V3 Translators NET 'CABLE_1_TRNSLT_OE_B' U42-25 U42-48 # Output Enable Bar of Translators NET 'CABLE_1_TRNSLT_OE_B' U43-25 U43-48 # Output Enable Bar of Translators NET 'CABLE_1_TRNCVR_DIR' U21-13 U21-15 U21-26 U21-28 # Receiver Enb_B NET 'CABLE_1_TRNCVR_DIR' U22-13 U22-15 U22-26 U22-28 # Receiver Enb_B NET 'CABLE_1_TRNCVR_DIR' U23-13 U23-15 U23-26 U23-28 # Receiver Enb_B NET 'CABLE_1_TRNCVR_DIR' U24-13 U24-15 U24-26 U24-28 # Receiver Enb_B NET 'CABLE_1_TRNCVR_DIR' U25-13 U25-15 U25-26 U25-28 # Receiver Enb_B NET 'CABLE_1_TRNCVR_DIR' U26-13 U26-15 U26-26 U26-28 # Receiver Enb_B NET 'CABLE_1_TRNCVR_DIR' U27-13 U27-15 U27-26 U27-28 # Receiver Enb_B NET 'CABLE_1_TRNCVR_DIR' U21-14 U21-16 U21-25 U21-27 # Driver Enable NET 'CABLE_1_TRNCVR_DIR' U22-14 U22-16 U22-25 U22-27 # Driver Enable NET 'CABLE_1_TRNCVR_DIR' U23-14 U23-16 U23-25 U23-27 # Driver Enable NET 'CABLE_1_TRNCVR_DIR' U24-14 U24-16 U24-25 U24-27 # Driver Enable NET 'CABLE_1_TRNCVR_DIR' U25-14 U25-16 U25-25 U25-27 # Driver Enable NET 'CABLE_1_TRNCVR_DIR' U26-14 U26-16 U26-25 U26-27 # Driver Enable NET 'CABLE_1_TRNCVR_DIR' U27-14 U27-16 U27-25 U27-27 # Driver Enable NET 'BACK_UPPER_LVDS_FAILSAFE' U21-9 U21-32 U22-9 U22-32 # Receiver Failsafe NET 'BACK_UPPER_LVDS_FAILSAFE' U23-9 U23-32 U24-9 U24-32 # Receiver Failsafe NET 'BACK_UPPER_LVDS_FAILSAFE' U25-9 U25-32 U26-9 U26-32 # Receiver Failsafe NET 'BACK_UPPER_LVDS_FAILSAFE' U27-9 U27-32 # Receiver Failsafe NET 'BACK_UPPER_LVDS_MASTER_ENB' U21-10 U22-10 U23-10 U24-10 # Trncvr Master Enable NET 'BACK_UPPER_LVDS_MASTER_ENB' U25-10 U26-10 U27-10 # Trncvr Master Enable # The MIDDLE set of Backplane LVDS management signals # -------- -------------- NET 'CABLE_2_TRNSLT_DIR' U44-1 U44-24 # Direction of 2V5<->3V3 Translators NET 'CABLE_2_TRNSLT_DIR' U45-1 U45-24 # Direction of 2V5<->3V3 Translators NET 'CABLE_2_TRNSLT_OE_B' U44-25 U44-48 # Output Enable Bar of Translators NET 'CABLE_2_TRNSLT_OE_B' U45-25 U45-48 # Output Enable Bar of Translators NET 'CABLE_2_TRNCVR_DIR' U28-13 U28-15 U28-26 U28-28 # Receiver Enb_B NET 'CABLE_2_TRNCVR_DIR' U29-13 U29-15 U29-26 U29-28 # Receiver Enb_B NET 'CABLE_2_TRNCVR_DIR' U30-13 U30-15 U30-26 U30-28 # Receiver Enb_B NET 'CABLE_2_TRNCVR_DIR' U31-13 U31-15 U31-26 U31-28 # Receiver Enb_B NET 'CABLE_2_TRNCVR_DIR' U32-13 U32-15 U32-26 U32-28 # Receiver Enb_B NET 'CABLE_2_TRNCVR_DIR' U33-13 U33-15 U33-26 U33-28 # Receiver Enb_B NET 'CABLE_2_TRNCVR_DIR' U34-13 U34-15 U34-26 U34-28 # Receiver Enb_B NET 'CABLE_2_TRNCVR_DIR' U28-14 U28-16 U28-25 U28-27 # Driver Enable NET 'CABLE_2_TRNCVR_DIR' U29-14 U29-16 U29-25 U29-27 # Driver Enable NET 'CABLE_2_TRNCVR_DIR' U30-14 U30-16 U30-25 U30-27 # Driver Enable NET 'CABLE_2_TRNCVR_DIR' U31-14 U31-16 U31-25 U31-27 # Driver Enable NET 'CABLE_2_TRNCVR_DIR' U32-14 U32-16 U32-25 U32-27 # Driver Enable NET 'CABLE_2_TRNCVR_DIR' U33-14 U33-16 U33-25 U33-27 # Driver Enable NET 'CABLE_2_TRNCVR_DIR' U34-14 U34-16 U34-25 U34-27 # Driver Enable NET 'BACK_MIDDLE_LVDS_FAILSAFE' U28-9 U28-32 U29-9 U29-32 # Receiver Failsafe NET 'BACK_MIDDLE_LVDS_FAILSAFE' U30-9 U30-32 U31-9 U31-32 # Receiver Failsafe NET 'BACK_MIDDLE_LVDS_FAILSAFE' U32-9 U32-32 U33-9 U33-32 # Receiver Failsafe NET 'BACK_MIDDLE_LVDS_FAILSAFE' U34-9 U34-32 # Receiver Failsafe NET 'BACK_MIDDLE_LVDS_MASTER_ENB' U28-10 U29-10 U30-10 U31-10 # Trncvr Master Enable NET 'BACK_MIDDLE_LVDS_MASTER_ENB' U32-10 U33-10 U34-10 # Trncvr Master Enable # The LOWER set of Backplane LVDS management signals # ------- -------------- NET 'CABLE_3_TRNSLT_DIR' U46-1 U46-24 # Direction of 2V5<->3V3 Translators NET 'CABLE_3_TRNSLT_DIR' U47-1 U47-24 # Direction of 2V5<->3V3 Translators NET 'CABLE_3_TRNSLT_OE_B' U46-25 U46-48 # Output Enable Bar of Translators NET 'CABLE_3_TRNSLT_OE_B' U47-25 U47-48 # Output Enable Bar of Translators NET 'CABLE_3_TRNCVR_DIR' U35-13 U35-15 U35-26 U35-28 # Receiver Enb_B NET 'CABLE_3_TRNCVR_DIR' U36-13 U36-15 U36-26 U36-28 # Receiver Enb_B NET 'CABLE_3_TRNCVR_DIR' U37-13 U37-15 U37-26 U37-28 # Receiver Enb_B NET 'CABLE_3_TRNCVR_DIR' U38-13 U38-15 U38-26 U38-28 # Receiver Enb_B NET 'CABLE_3_TRNCVR_DIR' U39-13 U39-15 U39-26 U39-28 # Receiver Enb_B NET 'CABLE_3_TRNCVR_DIR' U40-13 U40-15 U40-26 U40-28 # Receiver Enb_B NET 'CABLE_3_TRNCVR_DIR' U41-13 U41-15 U41-26 U41-28 # Receiver Enb_B NET 'CABLE_3_TRNCVR_DIR' U35-14 U35-16 U35-25 U35-27 # Driver Enable NET 'CABLE_3_TRNCVR_DIR' U36-14 U36-16 U36-25 U36-27 # Driver Enable NET 'CABLE_3_TRNCVR_DIR' U37-14 U37-16 U37-25 U37-27 # Driver Enable NET 'CABLE_3_TRNCVR_DIR' U38-14 U38-16 U38-25 U38-27 # Driver Enable NET 'CABLE_3_TRNCVR_DIR' U39-14 U39-16 U39-25 U39-27 # Driver Enable NET 'CABLE_3_TRNCVR_DIR' U40-14 U40-16 U40-25 U40-27 # Driver Enable NET 'CABLE_3_TRNCVR_DIR' U41-14 U41-16 U41-25 U41-27 # Driver Enable NET 'BACK_LOWER_LVDS_FAILSAFE' U35-9 U35-32 U36-9 U36-32 # Receiver Failsafe NET 'BACK_LOWER_LVDS_FAILSAFE' U37-9 U37-32 U38-9 U38-32 # Receiver Failsafe NET 'BACK_LOWER_LVDS_FAILSAFE' U39-9 U39-32 U40-9 U40-32 # Receiver Failsafe NET 'BACK_LOWER_LVDS_FAILSAFE' U41-9 U41-32 # Receiver Failsafe NET 'BACK_LOWER_LVDS_MASTER_ENB' U35-10 U36-10 U37-10 U38-10 # Trncvr Master Enable NET 'BACK_LOWER_LVDS_MASTER_ENB' U39-10 U40-10 U41-10 # Trncvr Master Enable # # There are 2 functions of the DS91M040 LVDS Transceivers # that will be controlled only by the placement of # jumpers on the CMX card. These functions are: # Receiver Failsafe and Master_Enable # # Receiver Failsafe # # These are jumpers that pull the FSEN1 and FSEN2 pins # down to ground. There is a separate jumper for each # group of transceivers, i.e. the upper, middle, and # lower LVDS Cable transceivers. Normally we expect # all 3 of these jumpers to be installed so that all # 3 cables will have "Type 1" i.e. voltage symmetric # receivers. These 3 jumpers are reference designators # JMP 5, 6, and 7. JMP5 controlls the Upper Backplane # LVDS Cable receivers. JMP6 the Middle and JMP7 the # Lower LVDS Cable receivers. # NET 'BACK_UPPER_LVDS_FAILSAFE' JMP5-1 # Upper Cable Failsafe Jumper NET 'BACK_MIDDLE_LVDS_FAILSAFE' JMP6-1 # Middle Cable Failsafe Jumper NET 'BACK_LOWER_LVDS_FAILSAFE' JMP7-1 # Lower Cable Failsafe Jumper NET 'GROUND' JMP5-2 JMP6-2 JMP7-2 # Pull-Down to Ground # Master Enable # # When Master Enable is voltage HI then the DS91M040 # LVDS Transceiver will power up and operate. We expect # to always have these transceivers powered up. These # jumpers will actually be given resistor reference # designators on the CMX card because we never expect # to remove or change them. These will be nominal 1k # Ohm resistors from the Master Enable pin to BULK_3V3. # There will be a separate jumper (resistor) for each # group of tranceivers that services a cable, i.e. # upper, middle, or lower cables. R181 enables the # transceivers for the Upper Backplane LVDS Cable. # R182 the Middle and R183 the Lower Cable transceivers. NET 'BACK_UPPER_LVDS_MASTER_ENB' R181-1 # Lower Cable Trncvr Master Enable NET 'BACK_MIDDLE_LVDS_MASTER_ENB' R182-1 # Middle Cable Trncvr Master Enable NET 'BACK_LOWER_LVDS_MASTER_ENB' R183-1 # Upper Cable Trncvr Master Enable NET 'BULK_3V3' R181-2 R182-2 R183-2 # Pull-Up to 3.3 Volts # # CMX-0 Nets File # # Backplane LVDS Power Ground Bypass Cap Nets # --==============--------------------------------- # # # Original Rev. 2-Nov-2012 # Most Recent Rev. 27-Nov-2012 # # # # This file holds the nets that connect power, ground, # and the bypass capacitors to the Backplane LVDS # transceiver and level translators chips. # # # Power and ByPass for U42 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U42-7 U42-18 # U42 3.3V Vccb power NET 'BULK_2V5' U42-31 U42-42 # U42 2.5V Vcca power NET 'GROUND' U42-4 U42-10 # U42 Ground connections NET 'GROUND' U42-15 U42-21 # U42 Ground connections NET 'GROUND' U42-28 U42-34 # U42 Ground connections NET 'GROUND' U42-39 U42-45 # U42 Ground connections NET 'BULK_3V3' C502-1 C503-1 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C501-2 C504-2 # ByPass Cap 2.5V Vcca power NET 'GROUND' C502-2 C503-2 # ByPass Cap Ground connections NET 'GROUND' C501-1 C504-1 # ByPass Cap Ground connections # Power and ByPass for U43 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U43-7 U43-18 # U43 3.3V Vccb power NET 'BULK_2V5' U43-31 U43-42 # U43 2.5V Vcca power NET 'GROUND' U43-4 U43-10 # U43 Ground connections NET 'GROUND' U43-15 U43-21 # U43 Ground connections NET 'GROUND' U43-28 U43-34 # U43 Ground connections NET 'GROUND' U43-39 U43-45 # U43 Ground connections NET 'BULK_3V3' C506-1 C507-1 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C505-2 C508-2 # ByPass Cap 2.5V Vcca power NET 'GROUND' C506-2 C507-2 # ByPass Cap Ground connections NET 'GROUND' C505-1 C508-1 # ByPass Cap Ground connections # Power and ByPass for U44 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U44-7 U44-18 # U44 3.3V Vccb power NET 'BULK_2V5' U44-31 U44-42 # U44 2.5V Vcca power NET 'GROUND' U44-4 U44-10 # U44 Ground connections NET 'GROUND' U44-15 U44-21 # U44 Ground connections NET 'GROUND' U44-28 U44-34 # U44 Ground connections NET 'GROUND' U44-39 U44-45 # U44 Ground connections NET 'BULK_3V3' C510-1 C511-1 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C509-2 C512-2 # ByPass Cap 2.5V Vcca power NET 'GROUND' C510-2 C511-2 # ByPass Cap Ground connections NET 'GROUND' C509-1 C512-1 # ByPass Cap Ground connections # Power and ByPass for U45 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U45-7 U45-18 # U45 3.3V Vccb power NET 'BULK_2V5' U45-31 U45-42 # U45 2.5V Vcca power NET 'GROUND' U45-4 U45-10 # U45 Ground connections NET 'GROUND' U45-15 U45-21 # U45 Ground connections NET 'GROUND' U45-28 U45-34 # U45 Ground connections NET 'GROUND' U45-39 U45-45 # U45 Ground connections NET 'BULK_3V3' C514-1 C515-1 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C513-2 C516-2 # ByPass Cap 2.5V Vcca power NET 'GROUND' C514-2 C515-2 # ByPass Cap Ground connections NET 'GROUND' C513-1 C516-1 # ByPass Cap Ground connections # Power and ByPass for U46 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U46-7 U46-18 # U46 3.3V Vccb power NET 'BULK_2V5' U46-31 U46-42 # U46 2.5V Vcca power NET 'GROUND' U46-4 U46-10 # U46 Ground connections NET 'GROUND' U46-15 U46-21 # U46 Ground connections NET 'GROUND' U46-28 U46-34 # U46 Ground connections NET 'GROUND' U46-39 U46-45 # U46 Ground connections NET 'BULK_3V3' C518-1 C519-1 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C517-2 C520-2 # ByPass Cap 2.5V Vcca power NET 'GROUND' C518-2 C519-2 # ByPass Cap Ground connections NET 'GROUND' C517-1 C520-1 # ByPass Cap Ground connections # Power and ByPass for U47 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U47-7 U47-18 # U47 3.3V Vccb power NET 'BULK_2V5' U47-31 U47-42 # U47 2.5V Vcca power NET 'GROUND' U47-4 U47-10 # U47 Ground connections NET 'GROUND' U47-15 U47-21 # U47 Ground connections NET 'GROUND' U47-28 U47-34 # U47 Ground connections NET 'GROUND' U47-39 U47-45 # U47 Ground connections NET 'BULK_3V3' C522-1 C523-1 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C521-2 C524-2 # ByPass Cap 2.5V Vcca power NET 'GROUND' C522-2 C523-2 # ByPass Cap Ground connections NET 'GROUND' C521-1 C524-1 # ByPass Cap Ground connections # LVDS<-->3.3V_CMOS DS91M040 Transceivers # # DS91M040 +3.3V Power Connections NET 'BULK_3V3' U21-11 U21-12 U21-29 U21-30 NET 'BULK_3V3' U22-11 U22-12 U22-29 U22-30 NET 'BULK_3V3' U23-11 U23-12 U23-29 U23-30 NET 'BULK_3V3' U24-11 U24-12 U24-29 U24-30 NET 'BULK_3V3' U25-11 U25-12 U25-29 U25-30 NET 'BULK_3V3' U26-11 U26-12 U26-29 U26-30 NET 'BULK_3V3' U27-11 U27-12 U27-29 U27-30 NET 'BULK_3V3' U28-11 U28-12 U28-29 U28-30 NET 'BULK_3V3' U29-11 U29-12 U29-29 U29-30 NET 'BULK_3V3' U30-11 U30-12 U30-29 U30-30 NET 'BULK_3V3' U31-11 U31-12 U31-29 U31-30 NET 'BULK_3V3' U32-11 U32-12 U32-29 U32-30 NET 'BULK_3V3' U33-11 U33-12 U33-29 U33-30 NET 'BULK_3V3' U34-11 U34-12 U34-29 U34-30 NET 'BULK_3V3' U35-11 U35-12 U35-29 U35-30 NET 'BULK_3V3' U36-11 U36-12 U36-29 U36-30 NET 'BULK_3V3' U37-11 U37-12 U37-29 U37-30 NET 'BULK_3V3' U38-11 U38-12 U38-29 U38-30 NET 'BULK_3V3' U39-11 U39-12 U39-29 U39-30 NET 'BULK_3V3' U40-11 U40-12 U40-29 U40-30 NET 'BULK_3V3' U41-11 U41-12 U41-29 U41-30 # LVDS<-->3.3V_CMOS DS91M040 Transceivers # # DS91M040 GROUND Connections NET 'GROUND' U21-31 NET 'GROUND' U22-31 NET 'GROUND' U23-31 NET 'GROUND' U24-31 NET 'GROUND' U25-31 NET 'GROUND' U26-31 NET 'GROUND' U27-31 NET 'GROUND' U28-31 NET 'GROUND' U29-31 NET 'GROUND' U21-33 U21-34 U21-35 U21-36 NET 'GROUND' U22-33 U22-34 U22-35 U22-36 NET 'GROUND' U23-33 U23-34 U23-35 U23-36 NET 'GROUND' U24-33 U24-34 U24-35 U24-36 NET 'GROUND' U25-33 U25-34 U25-35 U25-36 NET 'GROUND' U26-33 U26-34 U26-35 U26-36 NET 'GROUND' U27-33 U27-34 U27-35 U27-36 NET 'GROUND' U28-33 U28-34 U28-35 U28-36 NET 'GROUND' U29-33 U29-34 U29-35 U29-36 NET 'GROUND' U30-31 NET 'GROUND' U31-31 NET 'GROUND' U32-31 NET 'GROUND' U33-31 NET 'GROUND' U34-31 NET 'GROUND' U35-31 NET 'GROUND' U36-31 NET 'GROUND' U37-31 NET 'GROUND' U38-31 NET 'GROUND' U39-31 NET 'GROUND' U30-33 U30-34 U30-35 U30-36 NET 'GROUND' U31-33 U31-34 U31-35 U31-36 NET 'GROUND' U32-33 U32-34 U32-35 U32-36 NET 'GROUND' U33-33 U33-34 U33-35 U33-36 NET 'GROUND' U34-33 U34-34 U34-35 U34-36 NET 'GROUND' U35-33 U35-34 U35-35 U35-36 NET 'GROUND' U36-33 U36-34 U36-35 U36-36 NET 'GROUND' U37-33 U37-34 U37-35 U37-36 NET 'GROUND' U38-33 U38-34 U38-35 U38-36 NET 'GROUND' U39-33 U39-34 U39-35 U39-36 NET 'GROUND' U40-31 NET 'GROUND' U41-31 NET 'GROUND' U40-33 U40-34 U40-35 U40-36 NET 'GROUND' U41-33 U41-34 U41-35 U41-36 # # Bypass Capacitors C601:C621 on the # DS91M040 LVDS Transceivers U21:U41 # NET 'BULK_3V3' C601-1 C602-1 C603-1 # ByPass Cap on 3.3V power NET 'BULK_3V3' C604-1 C605-1 C606-1 # ByPass Cap on 3.3V power NET 'BULK_3V3' C607-1 C608-1 C609-1 # ByPass Cap on 3.3V power NET 'BULK_3V3' C610-1 C611-1 C612-1 # ByPass Cap on 3.3V power NET 'BULK_3V3' C613-1 C614-1 C615-1 # ByPass Cap on 3.3V power NET 'BULK_3V3' C616-1 C617-1 C618-1 # ByPass Cap on 3.3V power NET 'BULK_3V3' C619-1 C620-1 C621-1 # ByPass Cap on 3.3V power NET 'GROUND' C601-2 C602-2 C603-2 # and its Ground connection NET 'GROUND' C604-2 C605-2 C606-2 # and its Ground connection NET 'GROUND' C607-2 C608-2 C609-2 # and its Ground connection NET 'GROUND' C610-2 C611-2 C612-2 # and its Ground connection NET 'GROUND' C613-2 C614-2 C615-2 # and its Ground connection NET 'GROUND' C616-2 C617-2 C618-2 # and its Ground connection NET 'GROUND' C619-2 C620-2 C621-2 # and its Ground connection