############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for the 400 Backplane Processor Inputs # -=============------------------------------------------------------------- # # # Original Rev. 26-Sep-2011 as separate PN files # Rev. 3-Nov-2011 merged and ordered into one file # Rev. 21-May-2012 rework assignment using paper and pencil # Rev. 22-Jun-2012 move P08-P11 and P12-P15 to inner column # and reroute all while preserving all VREF and # one set of VRP/VRN per group of 3 IO banks. # Rev. 25-Jun-2012 move P00-P03 from IO banks 36-37-38 to 35-36-37, # move P4, P5, P6 clocks to remain at 2 clocks per H-row # (and fix IO bank used for P5_21, P5_22, P7_00, P7_01) # Rev. 27-Jun-2012 fix typo from P12_17 BA29 # to P12_17 BA20 # Rev. 29-Jun-2012 allow a few traces on top layer for P08-P11 group (banks 21-23) # in order to only use 10 layers (top+9) # Rev. 10-Jul-2012 fix problem: a VREF signal had been assigned to P12_13 # Rev. 12-Jul-2012 expunge information about "rank" # Rev. 20-Aug-2012 Assignment redone with corrected backplane pin order # Rev. 29-Aug-2012 switch P08-P11 to 11 layers, fixed P04-P07 template error # Rev. 07-Sep-2012 cosmetic changes to header comments # Rev. 12-Nov-2012 Complete re-think with a ring of vias and only 8 internal trace layers # Rev. 19-Nov-2012 Free up 4x SysMonit pairs on Bank 35 and 1x Global Clock pair on Bank 34 # Rev. 28-Nov-2012 cross-check assignments and add via row and number # Rev: 11-Dec-2012 Cosmetic changes for uniformity and consistency between Base and TP files # Rev: 24-Jan-2013 Bug fix: Move P12_17 to bank 33 (was in 34) by swapping with P15_20 # Rev: 28-Mar-2013 Move seven P14 and P15 signals to free the second Global Clock from Bank 34 # Rev: 08-May-2013 Swap location of P8_0:2 to match the newly displaced vias # Rev: 17-May-2013 Rearrange P14_1,2,6:9 to solve layer 4 boundary conflict (P08:11 vs P12:14), # swap P9_17 & _19 to better spread traces among via channels on layer 4 # and rearrange P12_18:21 to solve layer 9 boundary conflict (P08:11 vs P12:14) # which also involved putting pin AV23 into use and dropping AY24 # Most Recent Rev: 22-May-2013 Rearrange P6_8,9,10 to ease layer 3 trace density # # Here we assign Base FPGA resources for the 400x Px_y backplane signals, # with x=0:15 corresponding to the relative source processor module (JEM or CPM) in the crate, # and y=0:24 corresponding to the signal index number from that processor source. # Each Px_24 signal carries the clock/parity signal from a given source processor board. # All Px_24 signals must be connected to a single ended regional clock resource pin # (i.e. a signal named IO_L9P_MRCC_nn or IO_L10P_MRCC_nn, nn being the IO block number) # # Note: Trace layer information is appended as comments below. # ----- # # The Match Resource To Pin program will preserve this comment field, and append additional info. # # NET 'P0_7' U1- #> F07 R1V3 #> T04 J1-A18 P00_07 D13 # # ^ ^ ^ ^ ^ ^ ^ ^ # | | | | | | | | # Virtex 6 Resource name --------+ | | | | | | | # for Match_res2pin translation | | | | | | | # | | | | | | | # Tailored comment flag to help with string searches + | | | | | | # | | | | | | # Target Trace Layer number to use for this net --------+ | | | | | # as it exits the FPGA (to a near via or the backplane) | | | | | # F01 is top layer, F02 the first inner layer, etc | | | | | # | | | | | # When applicable: Via row (R1 is top row on sheet) --------+ | | | | # and via number (V1 is leftmost) as determined in paper study | | | | # | | | | # Target Trace Layer number to use for this net --------------------+ | | | # as it attaches to the backplane connector. | | | # T01 is top layer, T02 the first inner layer, etc | | | # | | | # Backplane Connector and Pin Number -----------------------------------+ | | # | | # Net Name repeated to help manual entry of Pin Number ---------------------------+ | # | # Target Pin Number read from paper drawing ---------------------------------------------+ # and cross-checked after Match_Res2Pin # ############################################################################################ ######################################################################################### # # The Processor Inputs in P0-P1-P2-P3 use IO resources from banks 35-36-37 # P0_24 uses a regional clock in IO bank 35 on trace layer 9 # P1_24 uses a regional clock in IO bank 35 on trace layer 9 # P2_24 uses a regional clock in IO bank 37 on trace layer 4 # P3_24 uses a regional clock in IO bank 36 on trace layer 9 # The DCI master for this group is IO bank 36 # NET 'P0_0' U1- #> F02 #> T02 J1-A11 P00_00 L11 NET 'P0_1' U1- #> F02 #> T02 J1-A12 P00_01 M12 NET 'P0_2' U1- #> F02 #> T02 J1-A13 P00_02 N13 NET 'P0_3' U1- #> F02 #> T02 J1-A14 P00_03 N14 NET 'P0_4' U1- #> F02 #> T02 J1-A15 P00_04 C14 NET 'P0_5' U1- #> F04 #> T04 J1-A16 P00_05 L12 NET 'P0_6' U1- #> F04 #> T04 J1-A17 P00_06 J13 NET 'P0_7' U1- #> F07 R1V3 #> T04 J1-A18 P00_07 D13 NET 'P0_8' U1- #> F07 R1V1 #> T04 J1-A19 P00_08 E12 NET 'P0_9' U1- #> F04 #> T04 J2-A1 P00_09 H14 NET 'P0_10' U1- #> F04 #> T04 J2-A2 P00_10 F14 NET 'P0_11' U1- #> F06 R2V3 #> T04 J2-A3 P00_11 D17 NET 'P0_12' U1- #> F01 R2V4 #> T04 J2-A4 P00_12 B16 NET 'P0_13' U1- #> F07 R2V1 #> T04 J2-A5 P00_13 F15 NET 'P0_14' U1- #> F04 #> T04 J2-A6 P00_14 J16 NET 'P0_15' U1- #> F04 #> T04 J2-A7 P00_15 J17 NET 'P0_16' U1- #> F04 #> T04 J2-A8 P00_16 K18 NET 'P0_17' U1- #> F01 R3V6 #> T04 J2-A9 P00_17 B18 NET 'P0_18' U1- #> F07 R3V3 #> T04 J2-A10 P00_18 E18 NET 'P0_19' U1- #> F07 R3V1 #> T04 J2-A11 P00_19 G18 NET 'P0_20' U1- #> F04 #> T04 J2-A12 P00_20 J18 NET 'P0_21' U1- #> F04 #> T04 J2-A13 P00_21 F19 NET 'P0_22' U1- #> F09 R4V4 #> T04 J2-A14 P00_22 E17 NET 'P0_23' U1- #> F09 R4V2 #> T04 J2-A15 P00_23 P18 NET 'P0_24' U1- #> F09 #> T09 J2-A16 P00_24 M13 NET 'P1_0' U1- #> F03 #> T03 J1-B15 P01_00 K14 NET 'P1_1' U1- #> F09 #> T09 J1-C16 P01_01 J11 NET 'P1_2' U1- #> F09 #> T09 J1-B17 P01_02 J12 NET 'P1_3' U1- #> F09 #> T09 J1-C18 P01_03 F12 NET 'P1_4' U1- #> F01 R1V2 #> T05 J1-B19 P01_04 B14 NET 'P1_5' U1- #> F01 R1V4 #> T05 J2-C1 P01_05 A14 NET 'P1_6' U1- #> F03 R1V8 #> T05 J2-B2 P01_06 K13 NET 'P1_7' U1- #> F05 #> T05 J2-C3 P01_07 K12 NET 'P1_8' U1- #> F05 #> T05 J2-B4 P01_08 E13 NET 'P1_9' U1- #> F05 #> T05 J2-C5 P01_09 G14 NET 'P1_10' U1- #> F05 #> T05 J2-B6 P01_10 J15 NET 'P1_11' U1- #> F01 R2V5 #> T05 J2-C7 P01_11 A16 NET 'P1_12' U1- #> F01 R2V7 #> T05 J2-B8 P01_12 A15 NET 'P1_13' U1- #> F07 R2V2 #> T05 J2-C9 P01_13 E14 NET 'P1_14' U1- #> F05 #> T05 J2-B10 P01_14 G16 NET 'P1_15' U1- #> F05 #> T05 J2-C11 P01_15 G17 NET 'P1_16' U1- #> F06 R3V5 #> T05 J2-B12 P01_16 D18 NET 'P1_17' U1- #> F09 R3V7 #> T05 J2-C13 P01_17 H15 NET 'P1_18' U1- #> F07 R3V4 #> T05 J2-B14 P01_18 E15 NET 'P1_19' U1- #> F07 R3V2 #> T05 J2-C15 P01_19 F16 NET 'P1_20' U1- #> F05 #> T05 J2-B16 P01_20 F17 NET 'P1_21' U1- #> F05 #> T05 J2-B17 P01_21 H18 NET 'P1_22' U1- #> F01 R4V6 #> T05 J2-B18 P01_22 A19 NET 'P1_23' U1- #> F05 #> T05 J2-C19 P01_23 E19 NET 'P1_24' U1- #> F09 #> T09 J3-B1 P01_24 M14 NET 'P2_0' U1- #> F03 #> T03 J1-D15 P02_00 L15 NET 'P2_1' U1- #> F03 #> T03 J1-D16 P02_01 L16 NET 'P2_2' U1- #> F01 R2V6 #> T03 J1-C17 P02_02 B17 NET 'P2_3' U1- #> F03 #> T03 J1-D18 P02_03 K17 NET 'P2_4' U1- #> F03 #> T03 J1-C19 P02_04 M18 NET 'P2_5' U1- #> F03 #> T03 J2-D1 P02_05 K19 NET 'P2_6' U1- #> F03 #> T03 J2-C2 P02_06 G19 NET 'P2_7' U1- #> F03 #> T03 J2-D3 P02_07 F20 NET 'P2_8' U1- #> F03 #> T03 J2-C4 P02_08 G21 NET 'P2_9' U1- #> F09 R4V1 #> T03 J2-D5 P02_09 C20 NET 'P2_10' U1- #> F01 R4V3 #> T03 J2-C6 P02_10 A20 NET 'P2_11' U1- #> F01 R4V5 #> T03 J2-D7 P02_11 C21 NET 'P2_12' U1- #> F03 #> T03 J2-C8 P02_12 H21 NET 'P2_13' U1- #> F03 #> T03 J2-D9 P02_13 G22 NET 'P2_14' U1- #> F03 #> T03 J2-C10 P02_14 E23 NET 'P2_15' U1- #> F01 R5V2 #> T03 J2-D11 P02_15 B22 NET 'P2_16' U1- #> F01 R5V5 #> T03 J2-C12 P02_16 B24 NET 'P2_17' U1- #> F01 R5V3 #> T03 J2-D13 P02_17 A24 NET 'P2_18' U1- #> F01 R5V1 #> T03 J2-C14 P02_18 B23 NET 'P2_19' U1- #> F03 #> T03 J2-D15 P02_19 D23 NET 'P2_20' U1- #> F04 #> T04 J2-C16 P02_20 E20 NET 'P2_21' U1- #> F04 #> T04 J2-D17 P02_21 F21 NET 'P2_22' U1- #> F04 #> T04 J2-C18 P02_22 F22 NET 'P2_23' U1- #> F04 #> T04 J2-D19 P02_23 D22 NET 'P2_24' U1- #> F04 #> T04 J3-C1 P02_24 J22 NET 'P3_0' U1- #> F02 #> T02 J1-E15 P03_00 N15 NET 'P3_1' U1- #> F01 R2V8 #> T02 J1-E16 P03_01 A17 NET 'P3_2' U1- #> F02 #> T02 J1-E17 P03_02 M16 NET 'P3_3' U1- #> F02 #> T02 J1-E18 P03_03 P17 NET 'P3_4' U1- #> F02 #> T02 J1-E19 P03_04 N18 NET 'P3_5' U1- #> F02 #> T02 J2-E1 P03_05 C18 NET 'P3_6' U1- #> F02 #> T02 J2-E2 P03_06 L19 NET 'P3_7' U1- #> F01 R3V8 #> T02 J2-E3 P03_07 B19 NET 'P3_8' U1- #> F02 #> T02 J2-E4 P03_08 C19 NET 'P3_9' U1- #> F02 #> T02 J2-E5 P03_09 H20 NET 'P3_10' U1- #> F02 #> T02 J2-E6 P03_10 J20 NET 'P3_11' U1- #> F02 #> T02 J2-E7 P03_11 D21 NET 'P3_12' U1- #> F02 #> T02 J2-E8 P03_12 J21 NET 'P3_13' U1- #> F01 R4V8 #> T02 J2-E9 P03_13 A21 NET 'P3_14' U1- #> F02 #> T02 J2-E10 P03_14 L22 NET 'P3_15' U1- #> F02 #> T02 J2-E11 P03_15 K22 NET 'P3_16' U1- #> F02 #> T02 J2-E12 P03_16 G23 NET 'P3_17' U1- #> F02 #> T02 J2-E13 P03_17 C23 NET 'P3_18' U1- #> F01 R5V4 #> T02 J2-E14 P03_18 A22 NET 'P3_19' U1- #> F01 R5V8 #> T02 J2-E15 P03_19 B21 NET 'P3_20' U1- #> F02 #> T02 J2-E16 P03_20 H23 NET 'P3_21' U1- #> F02 #> T02 J2-E17 P03_21 C24 NET 'P3_22' U1- #> F02 #> T02 J2-E18 P03_22 E24 NET 'P3_23' U1- #> F05 #> T05 J2-E19 P03_23 D20 NET 'P3_24' U1- #> F09 #> T09 J3-E1 P03_24 N16 NET 'P0TO3_DCI_P' U1- #> T08 M17 NET 'P0TO3_DCI_N' U1- #> T08 L17 NET 'VREF_P' U1- #> T08 G13 NET 'VREF_P' U1- #> T08 L14 NET 'VREF_P' U1- #> T08 H16 NET 'VREF_P' U1- #> T08 K15 NET 'VREF_P' U1- #> T08 E22 NET 'VREF_P' U1- #> T08 H19 ######################################################################################### # # The Processor Inputs in P4-P5-P6-P7 use IO resources from banks 26-27-28 # P4_24 uses a regional clock in IO bank 28 on trace layer 9 # P5_24 uses a regional clock in IO bank 28 on trace layer 9 # P6_24 uses a regional clock in IO bank 26 on trace layer 5 # P7_24 uses a regional clock in IO bank 27 on trace layer 9 # The DCI master for this group is IO bank 28 # NET 'P4_0' U1- #> F02 #> T02 J3-A1 P04_00 N25 NET 'P4_1' U1- #> F02 #> T02 J3-A2 P04_01 M26 NET 'P4_2' U1- #> F02 #> T02 J3-A3 P04_02 L27 NET 'P4_3' U1- #> F02 #> T02 J3-A4 P04_03 H28 NET 'P4_4' U1- #> F02 #> T02 J3-A5 P04_04 C29 NET 'P4_5' U1- #> F02 #> T02 J3-A6 P04_05 M29 NET 'P4_6' U1- #> F02 #> T02 J3-A7 P04_06 E30 NET 'P4_7' U1- #> F02 #> T02 J3-A8 P04_07 C31 NET 'P4_8' U1- #> F02 #> T02 J3-A9 P04_08 H31 NET 'P4_9' U1- #> F02 #> T02 J3-A10 P04_09 G32 NET 'P4_10' U1- #> F02 #> T02 J3-A11 P04_10 C33 NET 'P4_11' U1- #> F02 #> T02 J3-A12 P04_11 H33 NET 'P4_12' U1- #> F03 R1V2 #> T05 J3-A13 P04_12 L25 NET 'P4_13' U1- #> F03 R1V4 #> T05 J3-A14 P04_13 J26 NET 'P4_14' U1- #> F01 R1V5 #> T05 J3-A15 P04_14 A30 NET 'P4_15' U1- #> F01 R1V3 #> T05 J3-A16 P04_15 B29 NET 'P4_16' U1- #> F01 R1V1 #> T05 J3-A17 P04_16 A29 NET 'P4_17' U1- #> F05 #> T05 J3-A18 P04_17 F27 NET 'P4_18' U1- #> F05 #> T05 J3-A19 P04_18 D28 NET 'P4_19' U1- #> F05 #> T05 J4-A1 P04_19 E29 NET 'P4_20' U1- #> F05 #> T05 J4-A2 P04_20 C30 NET 'P4_21' U1- #> F05 #> T05 J4-A3 P04_21 D31 NET 'P4_22' U1- #> F05 #> T05 J4-A4 P04_22 D32 NET 'P4_23' U1- #> F05 #> T05 J4-A5 P04_23 D33 NET 'P4_24' U1- #> F09 #> T09 J4-A6 P04_24 N24 NET 'P5_0' U1- #> F03 #> T03 J3-C2 P05_00 G28 NET 'P5_1' U1- #> F04 #> T04 J3-B3 P05_01 P23 NET 'P5_2' U1- #> F04 #> T04 J3-C4 P05_02 R23 NET 'P5_3' U1- #> F04 #> T04 J3-B5 P05_03 P25 NET 'P5_4' U1- #> F01 R1V8 #> T04 J3-C6 P05_04 A31 NET 'P5_5' U1- #> F03 R1V6 #> T04 J3-B7 P05_05 K27 NET 'P5_6' U1- #> F04 #> T04 J3-C8 P05_06 J27 NET 'P5_7' U1- #> F04 #> T04 J3-B9 P05_07 G27 NET 'P5_8' U1- #> F04 #> T04 J3-C10 P05_08 E28 NET 'P5_9' U1- #> F01 R2V7 #> T04 J3-B11 P05_09 B31 NET 'P5_10' U1- #> F03 R2V8 #> T04 J3-C12 P05_10 F32 NET 'P5_11' U1- #> F03 R2V6 #> T04 J3-B13 P05_11 G31 NET 'P5_12' U1- #> F04 #> T04 J3-C14 P05_12 G29 NET 'P5_13' U1- #> F04 #> T04 J3-B15 P05_13 D30 NET 'P5_14' U1- #> F04 #> T04 J3-C16 P05_14 F31 NET 'P5_15' U1- #> F01 R3V7 #> T04 J3-B17 P05_15 A36 NET 'P5_16' U1- #> F01 R3V8 #> T04 J3-C18 P05_16 B36 NET 'P5_17' U1- #> F01 R3V6 #> T04 J3-B19 P05_17 A35 NET 'P5_18' U1- #> F04 #> T04 J4-C1 P05_18 E32 NET 'P5_19' U1- #> F04 #> T04 J4-B2 P05_19 E33 NET 'P5_20' U1- #> F04 #> T04 J4-C3 P05_20 E34 NET 'P5_21' U1- #> F04 #> T04 J4-B4 P05_21 E35 NET 'P5_22' U1- #> F04 #> T04 J4-C5 P05_22 D36 NET 'P5_23' U1- #> F04 #> T04 J4-B6 P05_23 D37 NET 'P5_24' U1- #> F09 #> T09 J4-C7 P05_24 L26 NET 'P6_0' U1- #> F01 R4V1 #> T03 J3-D2 P06_00 A37 NET 'P6_1' U1- #> F05 R4V3 #> T03 J3-C3 P06_01 C35 NET 'P6_2' U1- #> F05 R4V5 #> T03 J3-D4 P06_02 F36 NET 'P6_3' U1- #> F01 R4V6 #> T03 J3-C5 P06_03 A39 NET 'P6_4' U1- #> F01 R4V4 #> T03 J3-D6 P06_04 B38 NET 'P6_5' U1- #> F01 R4V2 #> T03 J3-C7 P06_05 B37 NET 'P6_6' U1- #> F03 #> T03 J3-D8 P06_06 G36 NET 'P6_7' U1- #> F03 #> T03 J3-C9 P06_07 F37 NET 'P6_8' U1- #> F01 R5V3 #> T03 J3-D10 P06_08 G42 NET 'P6_9' U1- #> F01 R5V5 #> T03 J3-C11 P06_09 F42 NET 'P6_10' U1- #> F01 R5V4 #> T03 J3-D12 P06_10 E42 NET 'P6_11' U1- #> F01 R5V2 #> T03 J3-C13 P06_11 A41 NET 'P6_12' U1- #> F01 R5V1 #> T03 J3-D14 P06_12 A40 NET 'P6_13' U1- #> F03 #> T03 J3-C15 P06_13 D38 NET 'P6_14' U1- #> F03 #> T03 J3-D16 P06_14 B39 NET 'P6_15' U1- #> F03 #> T03 J3-C17 P06_15 C39 NET 'P6_16' U1- #> F03 #> T03 J3-D18 P06_16 C40 NET 'P6_17' U1- #> F03 #> T03 J3-C19 P06_17 B41 NET 'P6_18' U1- #> F03 #> T03 J4-D1 P06_18 C41 NET 'P6_19' U1- #> F03 #> T03 J4-C2 P06_19 D41 NET 'P6_20' U1- #> F03 #> T03 J4-D3 P06_20 E40 NET 'P6_21' U1- #> F03 #> T03 J4-C4 P06_21 F40 NET 'P6_22' U1- #> F03 #> T03 J4-D5 P06_22 F41 NET 'P6_23' U1- #> F03 #> T03 J4-C6 P06_23 G41 NET 'P6_24' U1- #> F05 #> T05 J4-D7 P06_24 G34 NET 'P7_0' U1- #> F03 R2V2 #> T09 J3-E2 P07_00 K29 NET 'P7_1' U1- #> F03 R2V4 #> T09 J3-E3 P07_01 H30 NET 'P7_2' U1- #> F01 R2V5 #> T09 J3-E4 P07_02 B33 NET 'P7_3' U1- #> F01 R2V3 #> T09 J3-E5 P07_03 B32 NET 'P7_4' U1- #> F01 R2V1 #> T09 J3-E6 P07_04 A32 NET 'P7_5' U1- #> F01 R3V2 #> T09 J3-E7 P07_05 A34 NET 'P7_6' U1- #> F01 R3V4 #> T09 J3-E8 P07_06 B34 NET 'P7_7' U1- #> F03 R3V5 #> T09 J3-E9 P07_07 F35 NET 'P7_8' U1- #> F03 R3V3 #> T09 J3-E10 P07_08 F34 NET 'P7_9' U1- #> F03 R3V1 #> T09 J3-E11 P07_09 G33 NET 'P7_10' U1- #> F02 #> T02 J3-E12 P07_10 C34 NET 'P7_11' U1- #> F02 #> T02 J3-E13 P07_11 H34 NET 'P7_12' U1- #> F02 #> T02 J3-E14 P07_12 H35 NET 'P7_13' U1- #> F02 #> T02 J3-E15 P07_13 C36 NET 'P7_14' U1- #> F02 #> T02 J3-E16 P07_14 H36 NET 'P7_15' U1- #> F02 #> T02 J3-E17 P07_15 G37 NET 'P7_16' U1- #> F02 #> T02 J3-E18 P07_16 C38 NET 'P7_17' U1- #> F02 #> T02 J3-E19 P07_17 E38 NET 'P7_18' U1- #> F02 #> T02 J4-E1 P07_18 D40 NET 'P7_19' U1- #> F02 #> T02 J4-E2 P07_19 B42 NET 'P7_20' U1- #> F02 #> T02 J4-E3 P07_20 D42 NET 'P7_21' U1- #> F02 #> T02 J4-E4 P07_21 E39 NET 'P7_22' U1- #> F02 #> T02 J4-E5 P07_22 F39 NET 'P7_23' U1- #> F02 #> T02 J4-E6 P07_23 G39 NET 'P7_24' U1- #> F09 #> T09 J4-E7 P07_24 L29 NET 'P4TO7_DCI_P' U1- #> T08 N26 NET 'P4TO7_DCI_N' U1- #> T08 P26 NET 'VREF_P' U1- #> T08 E37 NET 'VREF_P' U1- #> T08 G38 NET 'VREF_P' U1- #> T08 D35 NET 'VREF_P' U1- #> T08 J31 NET 'VREF_P' U1- #> T08 F29 NET 'VREF_P' U1- #> T08 H29 ######################################################################################### # # The Processor Inputs in P8-P9-P10-P11 use IO resources from banks 21-22-23 # P8_24 uses a regional clock in IO bank 22 on trace layer 9 # P9_24 uses a regional clock in IO bank 23 on trace layer 9 # P10_24 uses a regional clock in IO bank 21 on trace layer 9 # P11_24 uses a regional clock in IO bank 21 on trace layer 9 # The DCI master for this group is IO bank 23 # NET 'P8_0' U1- #> F01 R1V5 #> T02 J5-A14 P08_00 BA32 NET 'P8_1' U1- #> F01 R1V8 #> T02 J5-A15 P08_01 BB33 NET 'P8_2' U1- #> F01 R1V6 #> T02 J5-A16 P08_02 BA31 NET 'P8_3' U1- #> F06 R1V3 #> T02 J5-A17 P08_03 AV33 NET 'P8_4' U1- #> F06 R1V1 #> T02 J5-A18 P08_04 AW33 NET 'P8_5' U1- #> F02 #> T02 J5-A19 P08_05 AM33 NET 'P8_6' U1- #> F02 #> T02 J5-A20 P08_06 AM32 NET 'P8_7' U1- #> F01 R2V8 #> T02 J5-A21 P08_07 BA29 NET 'P8_8' U1- #> F02 #> T02 J5-A22 P08_08 AY32 NET 'P8_9' U1- #> F02 #> T02 J5-A23 P08_09 AM31 NET 'P8_10' U1- #> F02 #> T02 J5-A24 P08_10 AL30 NET 'P8_11' U1- #> F02 #> T02 J5-A25 P08_11 AY30 NET 'P8_12' U1- #> F02 #> T02 J6-A1 P08_12 AK29 NET 'P8_13' U1- #> F02 #> T02 J6-A2 P08_13 AY29 NET 'P8_14' U1- #> F02 #> T02 J6-A3 P08_14 AM28 NET 'P8_15' U1- #> F02 #> T02 J6-A4 P08_15 AK27 NET 'P8_16' U1- #> F09 #> T09 J6-A5 P08_16 AN34 NET 'P8_17' U1- #> F09 #> T09 J6-A6 P08_17 AU33 NET 'P8_18' U1- #> F09 #> T09 J6-A7 P08_18 AU32 NET 'P8_19' U1- #> F09 #> T09 J6-A8 P08_19 AU31 NET 'P8_20' U1- #> F09 #> T09 J6-A9 P08_20 AT30 NET 'P8_21' U1- #> F09 #> T09 J6-A10 P08_21 AT29 NET 'P8_22' U1- #> F09 #> T09 J6-A11 P08_22 AN28 NET 'P8_23' U1- #> F09 #> T09 J6-A12 P08_23 AR27 NET 'P8_24' U1- #> F09 #> T09 J6-A13 P08_24 AM26 NET 'P9_0' U1- #> F05 #> T05 J5-B23 P09_00 AR33 NET 'P9_1' U1- #> F05 #> T05 J5-B24 P09_01 AT32 NET 'P9_2' U1- #> F03 #> T03 J5-B25 P09_02 AR34 NET 'P9_3' U1- #> F03 #> T03 J6-C1 P09_03 AN33 NET 'P9_4' U1- #> F03 #> T03 J6-B2 P09_04 AP32 NET 'P9_5' U1- #> F07 R2V5 #> T03 J6-C3 P09_05 AW31 NET 'P9_6' U1- #> F01 R2V7 #> T03 J6-B4 P09_06 BB31 NET 'P9_7' U1- #> F01 R2V6 #> T03 J6-C5 P09_07 BA30 NET 'P9_8' U1- #> F03 #> T03 J6-B6 P09_08 AN31 NET 'P9_9' U1- #> F03 #> T03 J6-C7 P09_09 AN30 NET 'P9_10' U1- #> F03 #> T03 J6-B8 P09_10 AL29 NET 'P9_11' U1- #> F07 R3V4 #> T03 J6-C9 P09_11 AV29 NET 'P9_12' U1- #> F01 R3V6 #> T03 J6-B10 P09_12 BB28 NET 'P9_13' U1- #> F06 R3V2 #> T03 J6-C11 P09_13 AV28 NET 'P9_14' U1- #> F03 #> T03 J6-B12 P09_14 AP28 NET 'P9_15' U1- #> F03 #> T03 J6-C13 P09_15 AL27 NET 'P9_16' U1- #> F04 #> T04 J6-B14 P09_16 AP33 NET 'P9_17' U1- #> F07 R2V4 #> T04 J6-C15 P09_17 AR32 NET 'P9_18' U1- #> F06 R2V2 #> T04 J6-B16 P09_18 AV30 NET 'P9_19' U1- #> F04 #> T04 J6-C17 P09_19 AW30 NET 'P9_20' U1- #> F04 #> T04 J6-B18 P09_20 AP31 NET 'P9_21' U1- #> F04 #> T04 J6-C19 P09_21 AP30 NET 'P9_22' U1- #> F04 #> T04 J7-B1 P09_22 AN29 NET 'P9_23' U1- #> F04 #> T04 J7-B2 P09_23 AR28 NET 'P9_24' U1- #> F09 #> T09 J7-B3 P09_24 AJ25 NET 'P10_0' U1- #> F07 R1V4 #> T05 J6-D6 P10_00 AY33 NET 'P10_1' U1- #> F06 R1V2 #> T05 J6-D7 P10_01 AV31 NET 'P10_2' U1- #> F05 #> T05 J6-D8 P10_02 AT31 NET 'P10_3' U1- #> F05 #> T05 J6-D9 P10_03 AR30 NET 'P10_4' U1- #> F05 #> T05 J6-C10 P10_04 AR29 NET 'P10_5' U1- #> F06 R2V3 #> T05 J6-D11 P10_05 AU29 NET 'P10_6' U1- #> F05 #> T05 J6-C12 P10_06 AU28 NET 'P10_7' U1- #> F05 #> T05 J6-D13 P10_07 AP27 NET 'P10_8' U1- #> F06 R3V1 #> T05 J6-C14 P10_08 AT27 NET 'P10_9' U1- #> F06 R3V3 #> T05 J6-D15 P10_09 AU27 NET 'P10_10' U1- #> F07 R3V5 #> T05 J6-C16 P10_10 AW28 NET 'P10_11' U1- #> F01 R3V8 #> T05 J6-D17 P10_11 BB29 NET 'P10_12' U1- #> F05 #> T05 J6-C18 P10_12 AV26 NET 'P10_13' U1- #> F05 #> T05 J6-D19 P10_13 AU26 NET 'P10_14' U1- #> F02 R4V1 #> T05 J7-D1 P10_14 AL25 NET 'P10_15' U1- #> F06 R4V3 #> T05 J7-C2 P10_15 AW25 NET 'P10_16' U1- #> F07 R4V5 #> T05 J7-D3 P10_16 AW27 NET 'P10_17' U1- #> F01 R4V8 #> T05 J7-C4 P10_17 BB26 NET 'P10_18' U1- #> F05 #> T05 J7-D5 P10_18 AV25 NET 'P10_19' U1- #> F05 #> T05 J7-C6 P10_19 AU24 NET 'P10_20' U1- #> F05 #> T05 J7-D7 P10_20 AR23 NET 'P10_21' U1- #> F07 R5V1 #> T05 J7-C8 P10_21 AV24 NET 'P10_22' U1- #> F06 R5V2 #> T05 J7-D9 P10_22 AU23 NET 'P10_23' U1- #> F01 R5V8 #> T05 J7-C10 P10_23 BA25 NET 'P10_24' U1- #> F09 #> T09 J7-D11 P10_24 AP25 NET 'P11_0' U1- #> F02 #> T02 J6-E14 P11_00 AY27 NET 'P11_1' U1- #> F02 #> T02 J6-E15 P11_01 AN26 NET 'P11_2' U1- #> F02 #> T02 J6-E16 P11_02 AM24 NET 'P11_3' U1- #> F02 #> T02 J6-E17 P11_03 AK23 NET 'P11_4' U1- #> F02 #> T02 J6-E18 P11_04 AM23 NET 'P11_5' U1- #> F02 #> T02 J6-E19 P11_05 AK22 NET 'P11_6' U1- #> F02 #> T02 J7-E1 P11_06 AJ22 NET 'P11_7' U1- #> F04 #> T04 J7-E2 P11_07 AM27 NET 'P11_8' U1- #> F04 #> T04 J7-E3 P11_08 AT26 NET 'P11_9' U1- #> F06 R4V2 #> T04 J7-E4 P11_09 AW26 NET 'P11_10' U1- #> F01 R4V6 #> T04 J7-E5 P11_10 BA26 NET 'P11_11' U1- #> F07 R4V4 #> T04 J7-E6 P11_11 AY28 NET 'P11_12' U1- #> F04 #> T04 J7-E7 P11_12 AR25 NET 'P11_13' U1- #> F04 #> T04 J7-E8 P11_13 AT25 NET 'P11_14' U1- #> F04 #> T04 J7-E9 P11_14 AT24 NET 'P11_15' U1- #> F04 #> T04 J7-E10 P11_15 AP23 NET 'P11_16' U1- #> F01 R4V7 #> T03 J7-E11 P11_16 BB27 NET 'P11_17' U1- #> F03 #> T03 J7-E12 P11_17 AP26 NET 'P11_18' U1- #> F03 #> T03 J7-E13 P11_18 AN25 NET 'P11_19' U1- #> F03 #> T03 J7-E14 P11_19 AR24 NET 'P11_20' U1- #> F03 #> T03 J7-E15 P11_20 AN24 NET 'P11_21' U1- #> F03 #> T03 J7-E16 P11_21 AN23 NET 'P11_22' U1- #> F03 #> T03 J7-E17 P11_22 AM22 NET 'P11_23' U1- #> F03 #> T03 J7-E18 P11_23 AL22 NET 'P11_24' U1- #> F09 #> T09 J7-E19 P11_24 AK24 NET 'P8TO11_DCI_P' U1- #> T08 AJ28 NET 'P8TO11_DCI_N' U1- #> T08 AH28 NET 'VREF_P' U1- #> T08 BA27 NET 'VREF_P' U1- #> T08 AY25 NET 'VREF_P' U1- #> T08 AW32 NET 'VREF_P' U1- #> T08 BB32 NET 'VREF_P' U1- #> T08 AM29 NET 'VREF_P' U1- #> T08 AG27 ######################################################################################### # # The Processor Inputs in P12-P13-P14-P15 use IO resources from banks 32-33-34 # P12_24 uses a regional clock in IO bank 32 on trace layer 9 # P13_24 uses a regional clock in IO bank 33 on trace layer 9 # P14_24 uses a regional clock in IO bank 34 on trace layer 9 # P15_24 uses a regional clock in IO bank 34 on trace layer 9 # The DCI master for this group is IO bank 34 # NET 'P12_0' U1- #> F01 R1V7 #> T02 J7-A10 P12_00 BB22 NET 'P12_1' U1- #> F01 R1V6 #> T02 J7-A11 P12_01 BA24 NET 'P12_2' U1- #> F01 R1V5 #> T02 J7-A12 P12_02 BA22 NET 'P12_3' U1- #> F01 R1V3 #> T02 J7-A13 P12_03 BB23 NET 'P12_4' U1- #> F02 #> T02 J7-A14 P12_04 AL21 NET 'P12_5' U1- #> F02 #> T02 J7-A15 P12_05 AM21 NET 'P12_6' U1- #> F02 #> T02 J7-A16 P12_06 AR20 NET 'P12_7' U1- #> F02 #> T02 J7-A17 P12_07 AY20 NET 'P12_8' U1- #> F02 #> T02 J7-A18 P12_08 AP20 NET 'P12_9' U1- #> F02 #> T02 J7-A19 P12_09 AY19 NET 'P12_10' U1- #> F09 R3V8 #> T02 J8-A1 P12_10 AV18 NET 'P12_11' U1- #> F02 #> T02 J8-A2 P12_11 AK19 NET 'P12_12' U1- #> F02 #> T02 J8-A3 P12_12 AK18 NET 'P12_13' U1- #> F02 #> T02 J8-A4 P12_13 AK17 NET 'P12_14' U1- #> F04 #> T04 J8-A5 P12_14 AM17 NET 'P12_15' U1- #> F04 #> T04 J8-A6 P12_15 AN16 NET 'P12_16' U1- #> F04 #> T04 J8-A7 P12_16 AN15 NET 'P12_17' U1- #> F04 #> T04 J8-A8 P12_17 AM14 NET 'P12_18' U1- #> F09 #> T09 J8-A9 P12_18 AW23 NET 'P12_19' U1- #> F09 #> T09 J8-A10 P12_19 AY22 NET 'P12_20' U1- #> F09 #> T09 J8-A11 P12_20 AW22 NET 'P12_21' U1- #> F09 #> T09 J8-A12 P12_21 AV23 NET 'P12_22' U1- #> F09 #> T09 J8-A13 P12_22 AW21 NET 'P12_23' U1- #> F09 #> T09 J8-A14 P12_23 AW20 NET 'P12_24' U1- #> F09 #> T09 J8-A15 P12_24 AK20 NET 'P13_0' U1- #> F04 #> T04 J7-B10 P13_00 AR22 NET 'P13_1' U1- #> F04 #> T04 J7-C11 P13_01 AP22 NET 'P13_2' U1- #> F04 #> T04 J7-B12 P13_02 AT21 NET 'P13_3' U1- #> F01 R1V4 #> T05 J7-C13 P13_03 BB24 NET 'P13_4' U1- #> F05 #> T05 J7-B14 P13_04 AU22 NET 'P13_5' U1- #> F05 #> T05 J7-C15 P13_05 AT22 NET 'P13_6' U1- #> F05 #> T05 J7-B16 P13_06 AU21 NET 'P13_7' U1- #> F05 #> T05 J7-C17 P13_07 AV21 NET 'P13_8' U1- #> F05 #> T05 J7-B18 P13_08 AV20 NET 'P13_9' U1- #> F05 #> T05 J7-C19 P13_09 AR19 NET 'P13_10' U1- #> F03 #> T03 J8-B1 P13_10 AN21 NET 'P13_11' U1- #> F03 #> T03 J8-C2 P13_11 AP21 NET 'P13_12' U1- #> F01 R2V7 #> T03 J8-B3 P13_12 BB21 NET 'P13_13' U1- #> F01 R2V8 #> T03 J8-C4 P13_13 BB19 NET 'P13_14' U1- #> F01 R2V6 #> T03 J8-B5 P13_14 BA20 NET 'P13_15' U1- #> F03 #> T03 J8-C6 P13_15 AT20 NET 'P13_16' U1- #> F03 #> T03 J8-B7 P13_16 AM19 NET 'P13_17' U1- #> F03 #> T03 J8-C8 P13_17 AL19 NET 'P13_18' U1- #> F03 #> T03 J8-B9 P13_18 AN18 NET 'P13_19' U1- #> F01 R3V7 #> T03 J8-C10 P13_19 BA19 NET 'P13_20' U1- #> F09 R3V6 #> T03 J8-B11 P13_20 AT19 NET 'P13_21' U1- #> F03 #> T03 J8-C12 P13_21 AL17 NET 'P13_22' U1- #> F03 #> T03 J8-B13 P13_22 AM16 NET 'P13_23' U1- #> F09 R4V6 #> T03 J8-C14 P13_23 AP16 NET 'P13_24' U1- #> F09 #> T09 J8-B15 P13_24 AK15 NET 'P14_0' U1- #> F06 R2V2 #> T04 J7-C12 P14_00 AU19 NET 'P14_1' U1- #> F06 R2V4 #> T04 J7-D13 P14_01 AY17 NET 'P14_2' U1- #> F07 R2V5 #> T04 J7-C14 P14_02 AW18 NET 'P14_3' U1- #> F07 R2V3 #> T04 J7-D15 P14_03 AY18 NET 'P14_4' U1- #> F07 R2V1 #> T04 J7-C16 P14_04 AV19 NET 'P14_5' U1- #> F04 #> T04 J7-D17 P14_05 AN19 NET 'P14_6' U1- #> F04 #> T04 J7-C18 P14_06 BB18 NET 'P14_7' U1- #> F01 R3V5 #> T04 J7-D19 P14_07 AW16 NET 'P14_8' U1- #> F06 R3V3 #> T04 J8-C1 P14_08 AU17 NET 'P14_9' U1- #> F06 R3V1 #> T04 J8-D2 P14_09 AR18 NET 'P14_10' U1- #> F04 #> T04 J8-C3 P14_10 AP18 NET 'P14_11' U1- #> F02 #> T02 J8-D4 P14_11 AJ16 NET 'P14_12' U1- #> F06 R4V3 #> T02 J8-C5 P14_12 AV16 NET 'P14_13' U1- #> F09 R4V8 #> T02 J8-D6 P14_13 AT17 NET 'P14_14' U1- #> F02 #> T02 J8-C7 P14_14 AY15 NET 'P14_15' U1- #> F02 #> T02 J8-D8 P14_15 AL15 NET 'P14_16' U1- #> F02 #> T02 J8-C9 P14_16 AK14 NET 'P14_17' U1- #> F02 #> T02 J8-D10 P14_17 AN13 NET 'P14_18' U1- #> F06 R5V2 #> T02 J8-C11 P14_18 AV13 NET 'P14_19' U1- #> F01 R5V8 #> T02 J8-D12 P14_19 BA16 NET 'P14_20' U1- #> F01 R5V6 #> T02 J8-C13 P14_20 BB14 NET 'P14_21' U1- #> F01 R5V4 #> T02 J8-D14 P14_21 BB13 NET 'P14_22' U1- #> F07 R5V1 #> T02 J8-C15 P14_22 AW13 NET 'P14_23' U1- #> F02 #> T02 J8-D16 P14_23 AM12 NET 'P14_24' U1- #> F09 #> T09 J8-C17 P14_24 AN14 NET 'P15_0' U1- #> F05 #> T05 J8-E1 P15_00 AU18 NET 'P15_1' U1- #> F07 R3V2 #> T05 J8-E2 P15_01 AW17 NET 'P15_2' U1- #> F07 R3V4 #> T05 J8-E3 P15_02 AW15 NET 'P15_3' U1- #> F05 #> T05 J8-E4 P15_03 AP17 NET 'P15_4' U1- #> F05 #> T05 J8-E5 P15_04 AR17 NET 'P15_5' U1- #> F05 #> T05 J8-E6 P15_05 AT16 NET 'P15_6' U1- #> F07 R4V1 #> T05 J8-E7 P15_06 AV15 NET 'P15_7' U1- #> F07 R4V4 #> T05 J8-E8 P15_07 AT14 NET 'P15_8' U1- #> F01 R4V7 #> T05 J8-E9 P15_08 BB17 NET 'P15_9' U1- #> F01 R4V5 #> T05 J8-E10 P15_09 BB16 NET 'P15_10' U1- #> F06 R4V2 #> T05 J8-E11 P15_10 AV14 NET 'P15_11' U1- #> F05 #> T05 J8-E12 P15_11 AR15 NET 'P15_12' U1- #> F05 #> T05 J8-E13 P15_12 AR14 NET 'P15_13' U1- #> F01 R5V7 #> T05 J8-E14 P15_13 BA15 NET 'P15_14' U1- #> F01 R5V5 #> T05 J8-E15 P15_14 BA14 NET 'P15_15' U1- #> F05 #> T05 J8-E16 P15_15 AU13 NET 'P15_16' U1- #> F05 #> T05 J8-E17 P15_16 AU12 NET 'P15_17' U1- #> F04 #> T04 J8-E18 P15_17 AR13 NET 'P15_18' U1- #> F04 #> T04 J8-E19 P15_18 AT12 NET 'P15_19' U1- #> F03 #> T03 J8-E20 P15_19 AP15 NET 'P15_20' U1- #> F03 #> T03 J8-E21 P15_20 AL14 NET 'P15_21' U1- #> F03 #> T03 J8-E22 P15_21 AP13 NET 'P15_22' U1- #> F03 #> T03 J8-E23 P15_22 AR12 NET 'P15_23' U1- #> F09 R5V3 #> T03 J8-E24 P15_23 AW12 NET 'P15_24' U1- #> F09 #> T09 J8-E25 P15_24 AM13 NET 'P12TO15_DCI_P' U1- #> T08 AU16 NET 'P12TO15_DCI_N' U1- #> T08 AT15 NET 'VREF_P' U1- #> T08 AY23 NET 'VREF_P' U1- #> T08 BA21 NET 'VREF_P' U1- #> T08 AL16 NET 'VREF_P' U1- #> T08 AM18 NET 'VREF_P' U1- #> T08 AU14 NET 'VREF_P' U1- #> T08 BA17 ############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for the LVDS cable IO # -=============---------------------------------------------- # # # Original Rev. 18-Nov-2011 # Rev. 22-Jun-2012 comment all out because processor inputs have moved to banks 22&23 # Rev. 31-Aug-2012 Now on IO banks 15,16,17 and layer assigned # Rev: 07-Sep-2012 Add header comments # Rev: 19-Nov-2012 Re-do breakout strategy which frees up layers 6 and 7 now unused # Skip the 8 System Monitor pin pairs from IO Bank 15 # Rev. 30-Nov-2012 Studying the set of unused pins generated 2 allocation improvements here # Most Recent Rev: 03-Jun-2013 swap pin used for cable IO signal 83 (AE35 is now used; AF41 now unused) # # Signal Nets referenced in this file: # ------------------------------------ # # 'D_CBL_zz_B' are the cable IO signals available to the Base FPGA with zz=00 to 83. # The "_B" postfix is used to indicate that these signals are inverted with respect # to the LVDS signal polarity on the data cables. # # There are up to 3 cables used for a given CMX card. # A Crate CMX card uses one cable as output only, # while a System CMX card receives 2 or 3 cables as input. # # A Rear Transition Module (RTM) card provides the interface to the three 34-signal # LVDS connectors where the IO cables can be connected. # Only 27 signals from each connector are routed on the current RTM cards. # zz=0 to 26 correspond to the first cable, # zz=27 to 53 correspond to the second cable, and # zz=54 to 80 correspond to the third cable. # # Additionally, 3 more differential pairs of signals are labelled on the backplane # but are not routed on the RTM: zz= 31 to 83 # The CMX card will route the currently unused M_81, M_82, and M_83 signals # to become usable as cable IO signals. The sets of cable signals thus are: # Cable #1 consists of signals M_00 to M_26 plus M_81 # Cable #2 consists of signals M_27 to M_53 plus M_82 # Cable #3 consists of signals M_54 to M_80 plus M_83 # The CMX card could thus be able to use 28 LVDS signals per cable while the CMM was only able # to use 27 signals. Using 28 signals would however require a new version of the RTM card. # This 28th signal can be left unused and set to a fixed state by the FPGA of the source Crate CMX # while the LVDS transceiver of the receiving System CMX will default to a defined value # for all non-connected inputs. # # The path to the LVDS transceivers D_CBL_zz signals are in the file backplane_cable_tx_n2p.txt # in the Net_Lists/Components_Backplane_Tx directory # # Note: Trace layer information is appended as comments below. # ----- # # NET 'D_CBL_00' U1- #> T02 00 L12 # # ^ ^ ^ ^ # | | | | # Tailored comment flag to help with string searches -------------------+ | | | # | | | # Target Trace Layer number to use for this net ----------------------------+ | | # T01 is top layer, T02 the first inner layer, etc | | # | | # Signal number is repeated to help manual entry of Pin Number ----------------+ | # | # Target Pin Number read from paper drawing ----------------------------------------+ # and cross-checked after Match_Res2Pin # ############################################################################################ # # IO Cable #1 # # This group uses signals from IO banks 16 and 17 and a regional clock from bank 17 NET 'D_CBL_00_B' U1- #> T02 00 L39 NET 'D_CBL_01_B' U1- #> T02 01 L42 NET 'D_CBL_02_B' U1- #> T02 02 M36 NET 'D_CBL_03_B' U1- #> T02 03 M42 NET 'D_CBL_04_B' U1- #> T02 04 N36 NET 'D_CBL_05_B' U1- #> T02 05 P37 NET 'D_CBL_06_B' U1- #> T02 06 P42 NET 'D_CBL_07_B' U1- #> T02 07 R35 NET 'D_CBL_08_B' U1- #> T02 08 R42 NET 'D_CBL_09_B' U1- #> T02 09 T35 NET 'D_CBL_10_B' U1- #> T02 10 T42 NET 'D_CBL_11_B' U1- #> T02 11 U36 NET 'D_CBL_12_B' U1- #> T02 12 U42 NET 'D_CBL_13_B' U1- #> T02 13 V36 NET 'D_CBL_14_B' U1- #> T02 14 W35 NET 'D_CBL_15_B' U1- #> T02 15 W42 NET 'D_CBL_16_B' U1- #> T02 16 Y34 NET 'D_CBL_17_B' U1- #> T02 17 Y42 NET 'D_CBL_18_B' U1- #> T02 18 Y35 NET 'D_CBL_19_B' U1- #> T02 19 AA34 NET 'D_CBL_20_B' U1- #> T02 20 AA32 NET 'D_CBL_21_B' U1- #> T03 21 L40 NET 'D_CBL_22_B' U1- #> T03 22 M37 NET 'D_CBL_23_B' U1- #> T09 23 M41 NET 'D_CBL_24_B' U1- #> T09 24 N41 NET 'D_CBL_25_B' U1- # Clock #> T09 25 P36 NET 'D_CBL_26_B' U1- # Parity #> T09 26 R40 NET 'D_CBL_81_B' U1- #> T03 81 N38 # # IO Cable #2 # # This group uses signals from IO banks 16 and 17 and a regional clock from bank 17 NET 'D_CBL_27_B' U1- #> T03 27 P38 NET 'D_CBL_28_B' U1- #> T03 28 R37 NET 'D_CBL_29_B' U1- #> T03 29 T36 NET 'D_CBL_30_B' U1- #> T03 30 U37 NET 'D_CBL_31_B' U1- #> T03 31 V38 NET 'D_CBL_32_B' U1- #> T03 32 W36 NET 'D_CBL_33_B' U1- #> T03 33 W37 NET 'D_CBL_34_B' U1- #> T03 34 Y37 NET 'D_CBL_35_B' U1- #> T03 35 AA36 NET 'D_CBL_36_B' U1- #> T03 36 AA35 NET 'D_CBL_37_B' U1- #> T04 37 L41 NET 'D_CBL_38_B' U1- #> T04 38 M38 NET 'D_CBL_39_B' U1- #> T04 39 N39 NET 'D_CBL_40_B' U1- #> T04 40 P40 NET 'D_CBL_41_B' U1- #> T04 41 R38 NET 'D_CBL_42_B' U1- #> T04 42 T37 NET 'D_CBL_43_B' U1- #> T04 43 U38 NET 'D_CBL_44_B' U1- #> T04 44 V39 NET 'D_CBL_45_B' U1- #> T04 45 V40 NET 'D_CBL_46_B' U1- #> T04 46 W38 NET 'D_CBL_47_B' U1- #> T04 47 Y38 NET 'D_CBL_48_B' U1- # Clock #> T09 48 T39 NET 'D_CBL_49_B' U1- # Parity #> T09 49 T41 NET 'D_CBL_50_B' U1- #> T05 50 M39 NET 'D_CBL_51_B' U1- #> T05 51 N40 NET 'D_CBL_52_B' U1- #> T05 52 P41 NET 'D_CBL_53_B' U1- #> T05 53 R39 NET 'D_CBL_82_B' U1- #> T05 82 T40 # # IO Cable #3 # # This group uses signals from IO banks 15 and 16 and a regional clock from bank 16 NET 'D_CBL_54_B' U1- #> T02 54 AC36 NET 'D_CBL_55_B' U1- #> T02 55 AC35 NET 'D_CBL_56_B' U1- #> T02 56 AE37 NET 'D_CBL_57_B' U1- #> T02 57 AF42 NET 'D_CBL_58_B' U1- #> T03 58 AB34 NET 'D_CBL_59_B' U1- #> T03 59 AB36 NET 'D_CBL_60_B' U1- #> T03 60 AC38 NET 'D_CBL_61_B' U1- #> T03 61 AD37 NET 'D_CBL_62_B' U1- #> T03 62 AD36 NET 'D_CBL_63_B' U1- #> T03 63 AE39 NET 'D_CBL_64_B' U1- #> T04 64 AA39 NET 'D_CBL_65_B' U1- #> T04 65 AA37 NET 'D_CBL_66_B' U1- #> T04 66 AB37 NET 'D_CBL_67_B' U1- #> T04 67 AB38 NET 'D_CBL_68_B' U1- #> T04 68 AC39 NET 'D_CBL_69_B' U1- #> T05 69 U39 NET 'D_CBL_70_B' U1- #> T05 70 U41 NET 'D_CBL_71_B' U1- #> T05 71 V41 NET 'D_CBL_72_B' U1- #> T05 72 W40 NET 'D_CBL_73_B' U1- #> T05 73 Y39 NET 'D_CBL_74_B' U1- #> T05 74 AC41 NET 'D_CBL_75_B' U1- #> T05 75 AD41 NET 'D_CBL_76_B' U1- #> T05 76 AE40 NET 'D_CBL_77_B' U1- #> T09 77 V35 NET 'D_CBL_78_B' U1- # Clock #> T09 78 W32 NET 'D_CBL_79_B' U1- # Parity #> T09 79 W41 NET 'D_CBL_80_B' U1- #> T09 80 Y40 NET 'D_CBL_83_B' U1- #> T09 83 AE35 ############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for Front Panel CTP Output # -=============--------------------------------------------- # # # Original Rev. 15-Nov-2011 assign to banks 33 & 34 # Rev. 22-Jun-2012 comment everything out as 33&34 taken by Processor inputs # Rev. 10-Sep-2012 Reassign to IO Banks 12 & part of 13 # Rev: 19-Nov-2012 Re-do breakout strategy # and plan for "a matrix of vias" near FPGA South East corner # The long haul is temporarily recoreded as layer 1 (T01), to be determined. # Rename nets to make Base Function a prefix (DOUT_CTP_xx_BF -> BF_DOUT_CTP_xx) # Rev: 11-Dec-2012 File name changed for uniformity and consistency between Base and TP files # Rev: 14-Jan-2013 Edit header comments # Rev: 05-Apr-2013 Tentatively flag these signals to belong to layer 7 # Rev: 20-May-2013 Swap BF_DOUT_CTP_51 and BF_DOUT_CTP_57 to solve problem with backplane IO # Most Recent Rev: 06-Jun-2013 Update position of signal #65 and rotate position of upper half signals # after final location of 5th translator # # # Signal Nets referenced in this file: # ------------------------------------ # # There are 0, 1 or 2 CTP cables connected to a given CMX card. # A Crate CMX with only Base CMX functionality does not send any data to the CTP # A System CMX in a CPM crate sends information to the CTP over one cable # A System CMX in a JEM crate sends information to the CTP over two cables # A Crate CMX with TP functionality would probably send information to the CTP over two cables # # 'BF_DOUT_CTP_xx' are the CTP output signals from the Base FPGA with xx=00 to 65. # Each CTP output cable carries 33 LVDS signals consisting of 31 data bits, one clock # and one parity bit. # xx=0 to 30 carry data bits on cable #1 # xx=31 carry the clock on cable #1 # xx=64 carry the parity on cable #1 # xx=32 to 62 carry data bits on cable #2 # xx=63 carry the clock on cable #2 # xx=65 carry the parity on cable #2 # Note that regional clock signals are assigned to CTP output signals # 31 and 63 # for flexibility, so that the CTP output cables could be used as inputs instead. # # These CTP output signals are assigned here to resources in IO banks 12 and 13. # Only part of IO bank 13 is used here, namely only the pins in rows AN to BB # while 11 io pins in rows AK, AL and AM are used for the on-card bus. # # The rest of the circuitry used to drive the LVDS cables is in the file front_panel_ctp_driver_n2p.txt # in the Net_Lists/Front_Panel_CTP_IO_Nets directory # # # Note: Trace layer information is appended as comments below. # ----- # # NET 'BF_DOUT_CTP_00' U1- #> F02 #> T01 00 AW37 # # ^ ^ ^ ^ ^ # | | | | | # Tailored comment flag to help with string searches -----------------+ | | | | # | | | | # Target Trace Layer number to use for this net --------------------------+ | | | # as it exits the FPGA (to reach a via in the via matrix) | | | # F01 is top layer, F02 the first inner layer, etc | | | # | | | # Target Trace Layer number to use for this net ---------------------------------+ | | # as it reaches the level translator near the front of the card | | # T01 is top layer, T02 the first inner layer, etc | | # | | # Signal number is repeated to help manual entry of Pin Number ---------------------+ | # | # Target Pin Number read from paper study -----------------------------------------------+ # and cross-checked after Match_Res2Pin # ############################################################################################ # # CTP Cable #1 # # This group uses signals from IO banks 12 and 13 and a regional clock from bank 13 NET 'BF_DOUT_CTP_00' U1- #> F02 #> T07 00 AW37 NET 'BF_DOUT_CTP_01' U1- #> F02 #> T07 01 AU42 NET 'BF_DOUT_CTP_02' U1- #> F02 #> T07 02 AT36 NET 'BF_DOUT_CTP_03' U1- #> F03 #> T07 03 AR37 NET 'BF_DOUT_CTP_04' U1- #> F05 #> T07 04 AY35 NET 'BF_DOUT_CTP_05' U1- #> F09 #> T07 05 AP36 NET 'BF_DOUT_CTP_06' U1- #> F02 #> T07 06 BB38 NET 'BF_DOUT_CTP_07' U1- #> F02 #> T07 07 AV38 NET 'BF_DOUT_CTP_08' U1- #> F02 #> T07 08 AU37 NET 'BF_DOUT_CTP_09' U1- #> F03 #> T07 09 AT37 NET 'BF_DOUT_CTP_10' U1- #> F05 #> T07 10 BA36 NET 'BF_DOUT_CTP_11' U1- #> F09 #> T07 11 AR40 NET 'BF_DOUT_CTP_12' U1- #> F02 #> T07 12 AW38 NET 'BF_DOUT_CTP_13' U1- #> F02 #> T07 13 AW40 NET 'BF_DOUT_CTP_14' U1- #> F02 #> T07 14 AW42 NET 'BF_DOUT_CTP_15' U1- #> F03 #> T07 15 AU38 NET 'BF_DOUT_CTP_16' U1- #> F05 #> T07 16 AT41 NET 'BF_DOUT_CTP_17' U1- #> F03 #> T07 17 AY37 NET 'BF_DOUT_CTP_18' U1- #> F02 #> T07 18 BB39 NET 'BF_DOUT_CTP_19' U1- #> F02 #> T07 19 AY40 NET 'BF_DOUT_CTP_20' U1- #> F02 #> T07 20 AY42 NET 'BF_DOUT_CTP_21' U1- #> F03 #> T07 21 AV39 NET 'BF_DOUT_CTP_22' U1- #> F05 #> T07 22 AU41 NET 'BF_DOUT_CTP_23' U1- #> F03 #> T07 23 AY38 NET 'BF_DOUT_CTP_24' U1- #> F02 #> T07 24 AY39 NET 'BF_DOUT_CTP_25' U1- #> F02 #> T07 25 BA41 NET 'BF_DOUT_CTP_26' U1- #> F02 #> T07 26 BA42 NET 'BF_DOUT_CTP_27' U1- #> F03 #> T07 27 AW41 NET 'BF_DOUT_CTP_28' U1- #> F05 #> T07 28 AV41 NET 'BF_DOUT_CTP_29' U1- #> F03 #> T07 29 BA39 NET 'BF_DOUT_CTP_30' U1- #> F02 #> T07 30 BA40 NET 'BF_DOUT_CTP_31' U1- #> F09 #> T07 31 AT40 NET 'BF_DOUT_CTP_64' U1- #> F02 #> T07 64 BB41 # # CTP Cable #2 # # This group uses signals from IO banks 12 and 13 and a regional clock from bank 12 NET 'BF_DOUT_CTP_32' U1- #> F02 #> T07 32 AN38 NET 'BF_DOUT_CTP_33' U1- #> F04 #> T07 33 BB34 NET 'BF_DOUT_CTP_34' U1- #> F02 #> T07 34 AN40 NET 'BF_DOUT_CTP_35' U1- #> F02 #> T07 35 AU34 NET 'BF_DOUT_CTP_36' U1- #> F04 #> T07 36 AP42 NET 'BF_DOUT_CTP_37' U1- #> F05 #> T07 37 AP40 NET 'BF_DOUT_CTP_38' U1- #> F04 #> T07 38 AN41 NET 'BF_DOUT_CTP_39' U1- #> F03 #> T07 39 AV34 NET 'BF_DOUT_CTP_40' U1- #> F02 #> T07 40 AV35 NET 'BF_DOUT_CTP_41' U1- #> F02 #> T07 41 AT35 NET 'BF_DOUT_CTP_42' U1- #> F04 #> T07 42 AP37 NET 'BF_DOUT_CTP_43' U1- #> F05 #> T07 43 AR38 NET 'BF_DOUT_CTP_44' U1- #> F04 #> T07 44 AP41 NET 'BF_DOUT_CTP_45' U1- #> F03 #> T07 45 AW35 NET 'BF_DOUT_CTP_46' U1- #> F02 #> T07 46 AV36 NET 'BF_DOUT_CTP_47' U1- #> F02 #> T07 47 BB36 NET 'BF_DOUT_CTP_48' U1- #> F04 #> T07 48 AR42 NET 'BF_DOUT_CTP_49' U1- #> F05 #> T07 49 AT39 NET 'BF_DOUT_CTP_50' U1- #> F04 #> T07 50 AR39 NET 'BF_DOUT_CTP_51' U1- #> F09 #> T07 51 AW36 NET 'BF_DOUT_CTP_52' U1- #> F02 #> T07 52 BA35 NET 'BF_DOUT_CTP_53' U1- #> F02 #> T07 53 AU36 NET 'BF_DOUT_CTP_54' U1- #> F04 #> T07 54 AR35 NET 'BF_DOUT_CTP_55' U1- #> F03 #> T07 55 AU39 NET 'BF_DOUT_CTP_56' U1- #> F04 #> T07 56 AN39 NET 'BF_DOUT_CTP_57' U1- #> F09 #> T07 57 BA37 NET 'BF_DOUT_CTP_58' U1- #> F02 #> T07 58 BA34 NET 'BF_DOUT_CTP_59' U1- #> F02 #> T07 59 BB37 NET 'BF_DOUT_CTP_60' U1- #> F04 #> T07 60 AT42 NET 'BF_DOUT_CTP_61' U1- #> F03 #> T07 61 AV40 NET 'BF_DOUT_CTP_62' U1- #> F05 #> T07 62 AP38 NET 'BF_DOUT_CTP_63' U1- #> F09 #> T07 63 AN35 NET 'BF_DOUT_CTP_65' U1- #> F02 #> T07 65 AY34 ############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for the highspeed GTX Transmitters # -=============--------------------------------------------------------- # # # Base Function FPGA # ---------------------- # # # Original Rev. 16-Mar-2012 # Rev. 19-Nov-2012 Add termination resistors # Rev: 11-Dec-2012 File name changed for uniformity and consistency between Base and TP files # Rev: 31-Dec-2012 Change the net-name on the MGTAVTTRCAL_115 Calibration Resistor pin. # Rev. 16-Jan-2013 Add unused MGT transceiver pins and rename file # base_function_gtx_transceivers_n2r.txt # Rev. 14-May-2013 Rearrange the GTX Quad to MiniPOD connections to facilitate trace routing. # Most Recent Rev. 2-Oct-2013 Swap 4 Transceiver vs MiniPOD Fiber to equalize differential trace lengths. # # # Signal Nets referenced in this file: # ------------------------------------ # # 'MPn_Fpp_QUAD_qqq_TRN_r_xxx' are the net names assigned to the MGT Transmitter IO signals with: # "n" is the miniPOD device number (n=1:2 for transmitter 1:2) # "pp" is the fiber number on the minipod device (pp = 0:11) # "qqq" is the FPGA Quad number (qqq = 110:118, but only 110:115 used here) # "r" is the transmitter number on that Quad (r = 0:3) # "xxx" is the signal polarity (xxx = "DIR" for Direct aka Positive or Non-Inverted # or "CMP" for Complement aka Negative or Inverted) # ############################################################################################ # Transmitter 1 is MiniPOD device MP1 NET 'MP1_F01_QUAD_110_TRN_0_DIR' U1- NET 'MP1_F01_QUAD_110_TRN_0_CMP' U1- NET 'MP1_F03_QUAD_110_TRN_1_DIR' U1- NET 'MP1_F03_QUAD_110_TRN_1_CMP' U1- NET 'MP1_F07_QUAD_110_TRN_2_DIR' U1- NET 'MP1_F07_QUAD_110_TRN_2_CMP' U1- NET 'MP1_F05_QUAD_110_TRN_3_DIR' U1- NET 'MP1_F05_QUAD_110_TRN_3_CMP' U1- NET 'MP1_F09_QUAD_111_TRN_0_DIR' U1- NET 'MP1_F09_QUAD_111_TRN_0_CMP' U1- NET 'MP1_F11_QUAD_111_TRN_1_DIR' U1- NET 'MP1_F11_QUAD_111_TRN_1_CMP' U1- NET 'MP1_F10_QUAD_111_TRN_2_DIR' U1- NET 'MP1_F10_QUAD_111_TRN_2_CMP' U1- NET 'MP1_F08_QUAD_111_TRN_3_DIR' U1- NET 'MP1_F08_QUAD_111_TRN_3_CMP' U1- NET 'MP1_F04_QUAD_112_TRN_0_DIR' U1- NET 'MP1_F04_QUAD_112_TRN_0_CMP' U1- NET 'MP1_F06_QUAD_112_TRN_1_DIR' U1- NET 'MP1_F06_QUAD_112_TRN_1_CMP' U1- NET 'MP1_F02_QUAD_112_TRN_2_DIR' U1- NET 'MP1_F02_QUAD_112_TRN_2_CMP' U1- NET 'MP1_F00_QUAD_112_TRN_3_DIR' U1- NET 'MP1_F00_QUAD_112_TRN_3_CMP' U1- # Transmitter 2 is MiniPOD device MP2 NET 'MP2_F01_QUAD_113_TRN_0_DIR' U1- NET 'MP2_F01_QUAD_113_TRN_0_CMP' U1- NET 'MP2_F03_QUAD_113_TRN_1_DIR' U1- NET 'MP2_F03_QUAD_113_TRN_1_CMP' U1- NET 'MP2_F07_QUAD_113_TRN_2_DIR' U1- NET 'MP2_F07_QUAD_113_TRN_2_CMP' U1- NET 'MP2_F05_QUAD_113_TRN_3_DIR' U1- NET 'MP2_F05_QUAD_113_TRN_3_CMP' U1- NET 'MP2_F09_QUAD_114_TRN_0_DIR' U1- NET 'MP2_F09_QUAD_114_TRN_0_CMP' U1- NET 'MP2_F11_QUAD_114_TRN_1_DIR' U1- NET 'MP2_F11_QUAD_114_TRN_1_CMP' U1- NET 'MP2_F10_QUAD_114_TRN_2_DIR' U1- NET 'MP2_F10_QUAD_114_TRN_2_CMP' U1- NET 'MP2_F08_QUAD_114_TRN_3_DIR' U1- NET 'MP2_F08_QUAD_114_TRN_3_CMP' U1- NET 'MP2_F04_QUAD_115_TRN_0_DIR' U1- NET 'MP2_F04_QUAD_115_TRN_0_CMP' U1- NET 'MP2_F06_QUAD_115_TRN_1_DIR' U1- NET 'MP2_F06_QUAD_115_TRN_1_CMP' U1- NET 'MP2_F02_QUAD_115_TRN_2_DIR' U1- NET 'MP2_F02_QUAD_115_TRN_2_CMP' U1- NET 'MP2_F00_QUAD_115_TRN_3_DIR' U1- NET 'MP2_F00_QUAD_115_TRN_3_CMP' U1- # Now connect the GTX Termination Calibration Resistor # This is a precision 100 Ohm resistor. # See Chapter 5 page 274 of the # Virtex-6 GTX User Guide. # # The other half of these connections is in: # # ..../Everything_Else/dci_gtx_res_nets_n2p.txt # NET 'BF_MGTRREF' U1- # B11 Base Function MGTRREF pin NET 'BF_GTX_AVTT' U1- # A12 Base Function MGTAVTTRCAL # connected to the BF_GTX_AVTT bus # as indicated in the User Guide ############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for the SFP Low-Speed DAQ & ROI Data # -=============---------------------------------------------------------- # # # This file includes the nets for: # # - the Base Function DAQ output data to SFP1 Transmitter # - the Base Function ROI output data to SFP2 Transmitter # - the S-Link Control Signals received on SFP1 SFP2 SFP3 SFP4 # # # Original Rev. 5-Dec-2012 # Rev: 11-Dec-2012 File name changed for uniformity and # consistency between Base and TP files # Rev: 16-Jan-2013 Rename nets to start with "BF_" # Most Recent Rev: 26-Apr-2013 Add the S-Link control signls received # from SFP1 SFP2 SFP3 SFP4 # # # Base Function FPGA # # DAQ and ROI Data Outputs to SFP Optical Transmitters # # SFP1 Base Function DAQ SFP Optical Output # SFP2 Base Function RIO SFP Optical Output # NET 'BF_DAQ_DATA_OUT_DIR' U1- # B3 DAQ Data Output Direct NET 'BF_DAQ_DATA_OUT_CMP' U1- # B4 DAQ Data Output Complement NET 'BF_ROI_DATA_OUT_DIR' U1- # C1 ROI Data Output Direct NET 'BF_ROI_DATA_OUT_CMP' U1- # C2 ROI Data Output Complement # # S-Link Control Singal Inputs from SFP1:SFP4 # # # SFP1 Received Data goes to Quad 117 Receiver 3 # SFP2 Received Data goes to Quad 117 Receiver 2 # SFP3 Received Data goes to Quad 117 Receiver 1 # SFP4 Received Data goes to Quad 117 Receiver 0 # NET 'SFP1_RD_DIR' U1- # E5 SFP1 Receiver Data Direct NET 'SFP1_RD_CMP' U1- # E6 SFP1 Receiver Data Complement NET 'SFP2_RD_DIR' U1- # F7 SFP2 Receiver Data Direct NET 'SFP2_RD_CMP' U1- # F8 SFP2 Receiver Data Complement NET 'SFP3_RD_DIR' U1- # G5 SFP3 Receiver Data Direct NET 'SFP3_RD_CMP' U1- # G6 SFP3 Receiver Data Complement NET 'SFP4_RD_DIR' U1- # H7 SFP4 Receiver Data Direct NET 'SFP4_RD_CMP' U1- # H8 SFP4 Receiver Data Complement ############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for the System Monitor IO signals # -=============-------------------------------------------------------- # # # Original Rev. 21-Nov-2012 Collect System Monitor signals freed from backplane input resources # Most Recent Rev: 11-Dec-2012 File name changed for uniformity and consistency between Base and TP files # # # Signal Nets referenced in this file: # ------------------------------------ # # 'BF_SYSMON_xx_P' and 'BF_SYSMON_xx_N' form the pair of pins used as system monitor inputs # The "_P" postfix is used for the positive pin and "_N" for the negative pin of the differential input. # The CMX is only able to use 12 of the 16 user inputs on the FPGA. # To help with Firmware, we keep the Virtex 6 channel numbering and end up with a # non-contiguous set of 12 channel numbers, namely xx= 2, 3, 4, 7, 8, 9, 10, 11, 12, 13, 14, 15 # # Note: Trace layer information is appended as comments below. # ----- # # NET 'BF_SYSMON_03_P' U1- #> F06 #> T01 00 H137 # # ^ ^ ^ ^ ^ # | | | | | # Tailored comment flag to help with string searches -----------------+ | | | | # | | | | # Target Trace Layer number to use for this net --------------------------+ | | | # as it exits the FPGA (to reach a via near the perimeter) | | | # F01 is top layer, F02 the first inner layer, etc | | | # | | | # Target Trace Layer number to use for this net ---------------------------------+ | | # for the long haul to the resource being monitored | | # T01 is top layer, T02 the first inner layer, etc | | # | | # Signal number is repeated to help manual entry of Pin Number ---------------------+ | # | # Target Pin Number read from paper study -----------------------------------------------+ # and cross-checked after Match_Res2Pin # ############################################################################################ # 'BF_SYSMON_00_P' This system Monitor user input is unaccessible # 'BF_SYSMON_00_N' as these pins are used for backplane inputs NET 'BF_SYSMON_01_P' U1- #> F10 #> T0 00 D16 NET 'BF_SYSMON_01_N' U1- #> F10 #> T0 00 C16 # 'BF_SYSMON_02_P' This system Monitor user input is unaccessible # 'BF_SYSMON_02_N' as these pins are used for backplane inputs NET 'BF_SYSMON_03_P' U1- #> F06 #> T0 00 H13 NET 'BF_SYSMON_03_N' U1- #> F06 #> T0 00 G12 NET 'BF_SYSMON_04_P' U1- #> F06 #> T0 00 C15 NET 'BF_SYSMON_04_N' U1- #> F06 #> T0 00 D15 # 'BF_SYSMON_05_P' This system Monitor user input is unaccessible # 'BF_SYSMON_05_N' as these pins are used for backplane inputs # 'BF_SYSMON_06_P' This system Monitor user input is unaccessible # 'BF_SYSMON_06_N' as these pins are used for backplane inputs NET 'BF_SYSMON_07_P' U1- #> F10 #> T0 00 C13 NET 'BF_SYSMON_07_N' U1- #> F10 #> T0 00 D12 NET 'BF_SYSMON_08_P' U1- #> F07 #> T0 00 AE33 NET 'BF_SYSMON_08_N' U1- #> F07 #> T0 00 AD33 NET 'BF_SYSMON_09_P' U1- #> F05 #> T0 00 AB39 NET 'BF_SYSMON_09_N' U1- #> F05 #> T0 00 AA40 NET 'BF_SYSMON_10_P' U1- #> F07 #> T0 00 AA41 NET 'BF_SYSMON_10_N' U1- #> F07 #> T0 00 AB41 NET 'BF_SYSMON_11_P' U1- #> F04 #> T0 00 AD38 NET 'BF_SYSMON_11_N' U1- #> F04 #> T0 00 AE38 NET 'BF_SYSMON_12_P' U1- #> F09 #> T0 00 AA42 NET 'BF_SYSMON_12_N' U1- #> F09 #> T0 00 AB42 NET 'BF_SYSMON_13_P' U1- #> F02 #> T0 00 AB32 NET 'BF_SYSMON_13_N' U1- #> F02 #> T0 00 AB33 NET 'BF_SYSMON_14_P' U1- #> F09 #> T0 00 AC40 NET 'BF_SYSMON_14_N' U1- #> F09 #> T0 00 AD40 NET 'BF_SYSMON_15_P' U1- #> F02 #> T0 00 AD42 NET 'BF_SYSMON_15_N' U1- #> F02 #> T0 00 AE42 ############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for the On-Card VME bus signals # -=============------------------------------------------------------ # # # Original Rev. 13-Sep-2012 # Rev: 17-Sep-2012 Arbitrary temporary assignement # Rev: 19-Nov-2012 Re-do breakout strategy and Add Goeographic Address signals. # Pick the quietest lines to share IO bank 13 with CTP output # Rev. 30-Nov-2012 Studying the set of unused pins generated 1 allocation improvement here # Rev: 11-Dec-2012 File name changed for uniformity and consistency between Base and TP files # Rev: 14-Jan-2013 Edit header comments and tentatively set comments to specify layer 7 for vertical run # Rev: 30-May-2013 Fix order of geographic address lines # Most Recent Rev: 03-Jun-2013 swap pins for OCB_GEO_ADRS_1 and _3 to avoid additional via # # # # Signal Nets referenced in this file: # ------------------------------------ # # 'OCB_Axx' are the On-Card Bus Address lines to the Base FPGA with xx=01 to 23 # (note there is no "A00" signal) # # 'OCB_Dyy' are the On-Card Bus Data lines to the Base FPGA with yy=00 to 15 # # 'OCB_GEO_ADRS_z' are the On-Card Bus Geographic Section Address lines with z=0 to 6 # # # 'OCB_SYS_RESET_B' is the On-Card Bus VME SYS_RESET signal # The "_B" postfix is used to indicate that the reset request is active # when the electrical signal is low # # 'OCB_DS_B' is the On-Card Bus Data strobe. # The "_B" postfix is used to indicate that the data strobe signal is on the # falling edge of the electrical signal. # # 'OCB_WRITE_B' is the On-Card Bus Data Direction # The "_B" postfix is used to indicate that the Write direction is # requested when the electrical signal is low. # # # IO Banks used # ------------- # # Most signal nets are assigned to IO Bank 14 and a few to Io Bank 13 # - All address line nets are in IO Bank 14 # - All data line nets are in IO Bank 14 # - The Data Strobe net is assigned to a regional clock pin in IO Bank 14 # - The Board Select net is assigned to a regional clock pin in IO Bank 13 # - The Write Net is assigned to an IO input pin in Bank 13 # - The Sys_Reset net is assigned to an IO input pin in Bank 13 # # The bulk of IO Bank 13 is used for the CTP output signals # # Note: Trace layer information is appended as comments below. # ----- # # NET 'OCB_A01' U1- #> F06 #> T07 A01 AM41 # # ^ ^ ^ ^ ^ # | | | | | # Tailored comment flag to help with string searches ------------------+ | | | | # | | | | # Target Trace Layer number to use for this net --------------------------+ | | | # as it exits the FPGA (to reach a nearby via) | | | # F01 is top layer, F02 the first inner layer, etc | | | # | | | # Target Trace Layer number to use for this net ---------------------------------+ | | # as it connects the VME bus transceiver section to the two FPGAs | | # T01 is top layer, T02 the first inner layer, etc | | # | | # Signal number is repeated to help manual entry of Pin Number ---------------------+ | # | # Target Pin Number read from paper drawing ---------------------------------------------+ # and cross-checked after Match_Res2Pin # ############################################################################################ # The lower Address (1:20), all Data, the Data Strobe, Direction and SysReset signals are in IO Bank 14 # The data strobe is assigned to a regional clock input pin (but probably not used as a clock) NET 'OCB_A01' U1- #> F06 #> T07 A01 AM41 NET 'OCB_A02' U1- #> F06 #> T07 A02 AM42 NET 'OCB_A03' U1- #> F06 #> T07 A03 AL41 NET 'OCB_A04' U1- #> F06 #> T07 A04 AL42 NET 'OCB_A05' U1- #> F06 #> T07 A05 AK40 NET 'OCB_A06' U1- #> F06 #> T07 A06 AK42 NET 'OCB_A07' U1- #> F06 #> T07 A07 AJ41 NET 'OCB_A08' U1- #> F06 #> T07 A08 AJ42 NET 'OCB_A09' U1- #> F06 #> T07 A09 AH40 NET 'OCB_A10' U1- #> F06 #> T07 A10 AH41 NET 'OCB_A11' U1- #> F06 #> T07 A11 AG42 NET 'OCB_A12' U1- #> F06 #> T07 A12 AG38 NET 'OCB_A13' U1- #> F03 #> T07 A13 AJ36 NET 'OCB_A14' U1- #> F03 #> T07 A14 AH36 NET 'OCB_A15' U1- #> F03 #> T07 A15 AG34 NET 'OCB_A16' U1- #> F03 #> T07 A16 AF35 NET 'OCB_A17' U1- #> F05 #> T07 A17 AL40 NET 'OCB_A18' U1- #> F05 #> T07 A18 AK38 NET 'OCB_A19' U1- #> F05 #> T07 A19 AJ40 NET 'OCB_A20' U1- #> F05 #> T07 A20 AH39 NET 'OCB_D00' U1- #> F02 #> T07 D00 AF34 NET 'OCB_D01' U1- #> F02 #> T07 D01 AG33 NET 'OCB_D02' U1- #> F02 #> T07 D02 AH35 NET 'OCB_D03' U1- #> F02 #> T07 D03 AJ35 NET 'OCB_D04' U1- #> F04 #> T07 D04 AF36 NET 'OCB_D05' U1- #> F04 #> T07 D05 AG36 NET 'OCB_D06' U1- #> F04 #> T07 D06 AH38 NET 'OCB_D07' U1- #> F04 #> T07 D07 AJ38 NET 'OCB_D08' U1- #> F04 #> T07 D08 AK37 NET 'OCB_D09' U1- #> F04 #> T07 D09 AL39 NET 'OCB_D10' U1- #> F05 #> T07 D10 AF39 NET 'OCB_D11' U1- #> F05 #> T07 D11 AF37 NET 'OCB_D12' U1- #> F05 #> T07 D12 AG37 NET 'OCB_D13' U1- #> F09 #> T07 D13 AF40 NET 'OCB_D14' U1- #> F09 #> T07 D14 AG41 NET 'OCB_D15' U1- #> F09 #> T07 D15 AG39 NET 'OCB_SYS_RESET_B' U1- #> F09 #> T07 RES AK39 NET 'OCB_WRITE_B' U1- #> F09 #> T07 WRI AJ37 NET 'OCB_DS_B' U1- #> F09 #> T07 DS AH34 # The upper Address (21:23), and all Geographic Address signals are in IO Bank 13 # as these signals are static or thought to change less often and will probably # minimize interaction with the CTP output also using Bank 13. NET 'OCB_A21' U1- #> F02 #> T07 A21 AM34 NET 'OCB_A22' U1- #> F02 #> T07 A22 AL36 NET 'OCB_A23' U1- #> F02 #> T07 A23 AK34 NET 'OCB_GEO_ADRS_0' U1- #> F03 #> T07 GA0 AM37 NET 'OCB_GEO_ADRS_1' U1- #> F03 #> T07 GA1 AM36 NET 'OCB_GEO_ADRS_2' U1- #> F03 #> T07 GA2 AL37 NET 'OCB_GEO_ADRS_3' U1- #> F04 #> T07 GA3 AK35 NET 'OCB_GEO_ADRS_4' U1- #> F05 #> T07 GA4 AM38 NET 'OCB_GEO_ADRS_5' U1- #> F09 #> T07 GA5 AL35 NET 'OCB_GEO_ADRS_6' U1- #> F09 #> T07 GA6 AM39 ############################################################################################ # # CMX Net-to-Resource File # -------------------------- # # # Clock Connections to the Base Function FPGA # ----------------------------=============------- # # # # Original Rev. 24-AUG-2012 # Rev. 26-Nov-2012 # Rev: 11-Dec-2012 File name changed for uniformity and consistency between Base and TP files # Rev: 26-Dec-2012 Change "Clk" in net_names to "CLK". # Rev: 29-Dec-2012 Remove the JTAG nets from this file. Remove "jtag" from the filename. # Rev: 16-Jan-2013 Change "Not_Used_" to "No_Conn_". # Rev: 28-Mar-2013 Add third logic global clock # Most Recent Rev: 2-May-2013 Change Logic and GTX clock net names to # reflect the 40.08 or 320.64 MHz LHC clocks # and the 40.000 or 100.000 MHz Crystal clocks # # # Base Function FPGA Clocks for Logic and Transceivers # ---------------------======---------------------------- # # # LHC Locked Logic Clocks # # Connect the 40.08 MHz and 320.64 MHz Logic Clocks to # the Base Function FPGA. These are LHC locked LVDS clock # signals to the Logic in the Base Function FPGA. # # A Global Clock input in I/O Bank 34 receives the DeSkew #1 40.08 MHz Logic clock. # # A Global Clock input in I/O Bank 25 receives the DeSkew #2 40.08 MHz Logic clock. # # A Global Clock input in I/O Bank 34 receives the 320.64 MHz Logic clock. # NET 'CLK_40MHz08_DSKW_1_BF_LOGIC_DIR' U1- # AY14 40.08 MHz DeSkew-1 LHC Logic NET 'CLK_40MHz08_DSKW_1_BF_LOGIC_CMP' U1- # AY13 Clk to the Base Function FPGA NET 'CLK_40MHz08_DSKW_2_BF_LOGIC_DIR' U1- # J42 40.08 MHz DeSkew-2 LHC Logic NET 'CLK_40MHz08_DSKW_2_BF_LOGIC_CMP' U1- # K42 Clk to the Base Function FPGA NET 'CLK_320MHz64_LHC_BF_LOGIC_DIR' U1- # AP12 320.64 MHz LHC Logic Clock NET 'CLK_320MHz64_LHC_BF_LOGIC_CMP' U1- # AP11 to the Base Function FPGA # # Crystal Oscillator #1 GTX Clock # # Now to the Base Function FPGA connect the 40.000 MHz # Crystal Oscillator #1 LVPECL clock to the clock "0" # input of the GTX Transceiver Quad 118. # # This is the "G-Link" transciever for DAQ and RIO readout. # NET 'CLK_40MHz000_XTAL_1_BF_TRNCV_DIR' U1- # C10 40.000 MHz Crystal Osc #1 NET 'CLK_40MHz000_XTAL_1_BF_TRNCV_CMP' U1- # C9 GTX Clk to the BF FPGA # # Crystal Oscillator #2 GTX Clock # # Now to the Base Function FPGA connect the 40.000 MHz # or 100.000 Mhz Crystal Oscillator #2 LVPECL clock to # the clock "0" input of the GTX Transceiver Quad 117. # # This is the clock to the GTX Transcievers that receive # data from the 4 SFP optical components and thus may be # used to receive S-Link control information. # NET 'CLK_100MHz000_XTAL_2_BF_TRNCV_DIR' U1- # G10 100.000 MHz Crystal Osc #2 NET 'CLK_100MHz000_XTAL_2_BF_TRNCV_CMP' U1- # G9 GTX Clk to the BF FPGA # This could also be 40.000 MHz # # LHC Locked GTX Clocks # # Now on the Base Function FPGA connect the 320.64 MHz # LHC locked LVPECL clocks to the clock inputs for # the GTX Transceivers. # # We will use the "0" clock inputs to the Quad Banks # 111 and 114 to receive these Transceiver clocks. # These are the Base Function GTX Transceivers that # send out 6.4 Gbps data to the L1Topo system. # NET 'CLK_320MHz64_LHC_BF_QUAD_111_DIR' U1- # AU10 320.64 MHz LHC GTX Clk #1 NET 'CLK_320MHz64_LHC_BF_QUAD_111_CMP' U1- # AU9 to the Base Function FPGA NET 'CLK_320MHz64_LHC_BF_QUAD_114_DIR' U1- # AB8 320.64 MHz LHC GTX Clk #2 NET 'CLK_320MHz64_LHC_BF_QUAD_114_CMP' U1- # AB7 to the Base Function FPGA # # Now on the Base Function FPGA connect ALL of the # UN-Used Tranceiver Clock Inputs to single point nets. # # Not Used Bank 110 Clock Inputs NET 'No_Conn_BF_GTX_CLK_0_110_DIR' U1- # pin BA10 NET 'No_Conn_BF_GTX_CLK_0_110_CMP' U1- # pin BA9 NET 'No_Conn_BF_GTX_CLK_1_110_DIR' U1- # pin AW10 NET 'No_Conn_BF_GTX_CLK_1_110_CMP' U1- # pin AW9 # Not Used Bank 111 Clock Input NET 'No_Conn_BF_GTX_CLK_1_111_DIR' U1- # pin AT8 NET 'No_Conn_BF_GTX_CLK_1_111_CMP' U1- # pin AT7 # Not Used Bank 112 Clock Inputs NET 'No_Conn_BF_GTX_CLK_0_112_DIR' U1- # pin AK8 NET 'No_Conn_BF_GTX_CLK_0_112_CMP' U1- # pin AK7 NET 'No_Conn_BF_GTX_CLK_1_112_DIR' U1- # pin AH8 NET 'No_Conn_BF_GTX_CLK_1_112_CMP' U1- # pin AH7 # Not Used Bank 113 Clock Inputs NET 'No_Conn_BF_GTX_CLK_0_113_DIR' U1- # pin AF8 NET 'No_Conn_BF_GTX_CLK_0_113_CMP' U1- # pin AF7 NET 'No_Conn_BF_GTX_CLK_1_113_DIR' U1- # pin AD8 NET 'No_Conn_BF_GTX_CLK_1_113_CMP' U1- # pin AD7 # Not Used Bank 114 Clock Input NET 'No_Conn_BF_GTX_CLK_1_114_DIR' U1- # pin Y8 NET 'No_Conn_BF_GTX_CLK_1_114_CMP' U1- # pin Y7 # Not Used Bank 115 Clock Inputs NET 'No_Conn_BF_GTX_CLK_0_115_DIR' U1- # pin V8 NET 'No_Conn_BF_GTX_CLK_0_115_CMP' U1- # pin V7 NET 'No_Conn_BF_GTX_CLK_1_115_DIR' U1- # pin T8 NET 'No_Conn_BF_GTX_CLK_1_115_CMP' U1- # pin T7 # Not Used Bank 116 Clock Inputs NET 'No_Conn_BF_GTX_CLK_0_116_DIR' U1- # pin M8 NET 'No_Conn_BF_GTX_CLK_0_116_CMP' U1- # pin M7 NET 'No_Conn_BF_GTX_CLK_1_116_DIR' U1- # pin K8 NET 'No_Conn_BF_GTX_CLK_1_116_CMP' U1- # pin K7 # Not Used Bank 117 Clock Input NET 'No_Conn_BF_GTX_CLK_1_117_DIR' U1- # pin E10 NET 'No_Conn_BF_GTX_CLK_1_117_CMP' U1- # pin E9 # Not Used Bank 118 Clock Input NET 'No_Conn_BF_GTX_CLK_1_118_DIR' U1- # pin A10 NET 'No_Conn_BF_GTX_CLK_1_118_CMP' U1- # pin A9 ############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for the connections to the TTC signals # -=============------------------------------------------================== # # # Original Rev. 28-Mar-2012 # Most Recent Rev. 28-Mar-2013 find location for these 2x signals without interfering with backplane inputs # # Signal Nets referenced in this file: # ------------------------------------ # # BUF_TTC_L1_ACCEPT Buffered and series terminated copy of TTCdec L1 Accept signal # # BUF_TTC_BNCH_CNT_RES Buffered and series terminated copy of TTCdec Bunch Count Reset signal # ############################################################################################ # 2x signals are connecting to the buffered version of the TTCdec signals NET 'BUF_TTC_L1_ACCEPT' U1- #> F05 #> T06 H39 NET 'BUF_TTC_BNCH_CNT_RES' U1- #> F05 #> T06 K40 # Note: One global clock from this IO Bank is also used cf. base_function_22_clocks_n2r.txt # Note: Two differential signals from this IO Bank are also used cf. base_function_24_to_tp_fpga_n2r.txt ############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for the connections to the TP FPGA # -=============------------------------------------------================ # # Original Rev. 02-Apr-2012 # Most Recent Rev. 02-Apr-2013 find location for these signals whithout interfering with other signals # # BF to TP connections for support of S-link return channels # ========----------------------------====================== # # If the TP function needs to support S-link protocol (rather than G-link) # the CMX will need to receive the return channel of the Duplex S-link. # # The SFP optical receiver from the 2x S-link connections (DAQ and ROI) # cannot be directly received in the TP FPGA because all 36x MGT receivers # of the TP FPGA are already used with the 3x12 Avago optical receivers. # # The SFP optical receivers are instead routed to MGT receivers located # on the BF FPGA and the serial signal received is sent from the BF FPGA # to the TP FPGA via two differential Select IO signals. # # Signal Nets referenced in this file: # ------------------------------------ # # BF_TO_TP_DAQ_SLINK_RETURN_DIR Direct signal # BF_TO_TP_DAQ_SLINK_RETURN_CMP Complement signal # for the return S-link channel for DAQ readout # # BF_TO_TP_ROI_SLINK_RETURN_DIR Direct signal # BF_TO_TP_ROI_SLINK_RETURN_CMP Complement signal # for the return S-link channel for ROI readout # ############################################################################################ # 4x Select IO pins forming 2x differential signals going to the TP FPGA # This is IO Bank 25 and the signals will be routed south on trace layer 6. NET 'BF_TO_TP_DAQ_SLINK_RETURN_DIR' U1- #> F05 #> T06 H40 NET 'BF_TO_TP_DAQ_SLINK_RETURN_CMP' U1- #> F05 #> T06 H41 NET 'BF_TO_TP_ROI_SLINK_RETURN_DIR' U1- #> F07 #> T06 J40 NET 'BF_TO_TP_ROI_SLINK_RETURN_CMP' U1- #> F07 #> T06 J41 # Note: One global clock from this IO Bank is also used cf. base_function_22_clocks_n2r.txt # Note: Two pins from this IO Bank are also used for TTC cf. base_function_23_ttc_connections_n2r.txt ############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for the connections to the Board Support FPGA # -=============------------------------------------------========================== # # # Original Rev. 28-Mar-2012 # Rev. 28-Mar-2013 find location for these 18x signals without interfering with backplane inputs # Most Recent Rev: 30-May-2013 BF to BSPT connections were re-arranged after the layout of the backplane inputs # # Signal Nets referenced in this file: # ------------------------------------ # # BF_REQ_CTP_n_INPUT (n=1:2) 2x direction request for CTP cable n sent to BSPT FPGA # # BF_REQ_CABLE_n_INPUT (n=1:3) 3x direction request for Merger Cable n sent to BSPT FPGA # # BF_LED_REQ_n (n=0:4) 5x LED state request sent to BSPT FPGA # # BF_TO_FROM_BSPT_n (n=0:7) 8x un-assigned Input or Ouput connections to BSPT FPGA # ############################################################################################ # 18x signals are going to the Board Support FPGA on layer 7 # These signals are listed in west to east order as they leave the FPGA area on layer 7 # The middle 8 signals first reach a row of vias on layer 1 or 6 and exit on layer 7 NET 'BF_REQ_CTP_1_INPUT' U1- #> F07 #> T07 N19 NET 'BF_REQ_CTP_2_INPUT' U1- #> F07 #> T07 N20 NET 'BF_REQ_CABLE_1_INPUT' U1- #> F07 #> T07 P21 NET 'BF_REQ_CABLE_2_INPUT' U1- #> F07 #> T07 P22 NET 'BF_REQ_CABLE_3_INPUT' U1- #> F07 #> T07 K23 NET 'BF_LED_REQ_0' U1- #> F07 #> T07 G24 NET 'BF_LED_REQ_1' U1- #> F07 #> T07 F25 NET 'BF_LED_REQ_2' U1- #> F01 #> T07 A25 NET 'BF_LED_REQ_3' U1- #> F01 #> T07 C25 NET 'BF_LED_REQ_4' U1- #> F01 #> T07 F24 NET 'BF_TO_FROM_BSPT_0' U1- #> F06 #> T07 A26 NET 'BF_TO_FROM_BSPT_1' U1- #> F06 #> T07 B26 NET 'BF_TO_FROM_BSPT_2' U1- #> F01 #> T07 D25 NET 'BF_TO_FROM_BSPT_3' U1- #> F01 #> T07 A27 NET 'BF_TO_FROM_BSPT_4' U1- #> F01 #> T07 F26 NET 'BF_TO_FROM_BSPT_5' U1- #> F07 #> T07 E25 NET 'BF_TO_FROM_BSPT_6' U1- #> F07 #> T07 D26 NET 'BF_TO_FROM_BSPT_7' U1- #> F07 #> T07 E27 # note: other Select IO pins on IO Bank 38 are used for connections to the debug connector # cf. base_function_26_debug_connections_n2r.txt ############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for the connections to the Debug Connector # -=============------------------------------------------====================== # # # Original Rev. 28-Mar-2012 # Rev. 28-Mar-2013 find location for these 10x signals without interfering with backplane inputs # Rev: 30-May-2013 BF debug connections were re-arranged after the layout of the backplane inputs # Most Recent Rev: 10-Jul-2013 Reorder pin assignment for straight route near debug connector # # Signal Nets referenced in this file: # ------------------------------------ # # BF_DEBUG_n (n=0:9) 10x spare connections from the BF FPGA to debug connector J14 # ############################################################################################ # 10x signals are going to the Debug Connector on layer 6 # These signals are listed in west to east order as they come out of the FPGA on layer 6 # The order of the BF_DEBUG_n nets may be adjusted to optimize access near J14 NET 'BF_DEBUG_0' U1- #> F06 #> T06 B27 NET 'BF_DEBUG_1' U1- #> F06 #> T06 M21 NET 'BF_DEBUG_2' U1- #> F06 #> T06 C26 NET 'BF_DEBUG_3' U1- #> F06 #> T06 N21 NET 'BF_DEBUG_4' U1- #> F06 #> T06 D27 NET 'BF_DEBUG_5' U1- #> F06 #> T06 M19 NET 'BF_DEBUG_6' U1- #> F06 #> T06 C28 NET 'BF_DEBUG_7' U1- #> F06 #> T06 M22 NET 'BF_DEBUG_8' U1- #> F06 #> T06 B28 NET 'BF_DEBUG_9' U1- #> F06 #> T06 J23 # note: other Select IO pins on IO Bank 38 are used for connections to the BSPT FPGA # cf. base_function_25_bspt_connections_n2r.txt ############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for all unused and Not Connected MGT IO pins # -=============-----------------------------------------====================---------- # # # Original Rev. 16-Jan-2013 All 1760 pins on the Base function FPGA will have a net assigned # # Rev. 26-Apr-2013 The Quad 117 Receiver inputs are now used # for the 4 used for SFP Receiver signals. # # # # On the Base Function FPGA connect ALL of the # UN-Used Tranceiver IO Pins to single point nets. # # Signal Nets referenced in this file: # ------------------------------------ # # 'No_Conn_BF_xxxx' are the unique net names assigned to these MGT IO signals # where "xxxx" is the fpga MGT IO signal name # ############################################################################################ ################ # Receivers ################ # All Receiver Channels from MGT Quad 110 are unused NET 'No_Conn_BF_MGTRXP0_110' U1- # 110 BB7 NET 'No_Conn_BF_MGTRXN0_110' U1- # 110 BB8 NET 'No_Conn_BF_MGTRXP1_110' U1- # 110 BA5 NET 'No_Conn_BF_MGTRXN1_110' U1- # 110 BA6 NET 'No_Conn_BF_MGTRXP2_110' U1- # 110 AY7 NET 'No_Conn_BF_MGTRXN2_110' U1- # 110 AY8 NET 'No_Conn_BF_MGTRXP3_110' U1- # 110 AW5 NET 'No_Conn_BF_MGTRXN3_110' U1- # 110 AW6 # All Receiver Channels from MGT Quad 111 are unused NET 'No_Conn_BF_MGTRXP0_111' U1- # 111 AV7 NET 'No_Conn_BF_MGTRXN0_111' U1- # 111 AV8 NET 'No_Conn_BF_MGTRXP1_111' U1- # 111 AU5 NET 'No_Conn_BF_MGTRXN1_111' U1- # 111 AU6 NET 'No_Conn_BF_MGTRXP2_111' U1- # 111 AR5 NET 'No_Conn_BF_MGTRXN2_111' U1- # 111 AR6 NET 'No_Conn_BF_MGTRXP3_111' U1- # 111 AP7 NET 'No_Conn_BF_MGTRXN3_111' U1- # 111 AP8 # All Receiver Channels from MGT Quad 112 are unused NET 'No_Conn_BF_MGTRXP0_112' U1- # 112 AN5 NET 'No_Conn_BF_MGTRXN0_112' U1- # 112 AN6 NET 'No_Conn_BF_MGTRXP1_112' U1- # 112 AM7 NET 'No_Conn_BF_MGTRXN1_112' U1- # 112 AM8 NET 'No_Conn_BF_MGTRXP2_112' U1- # 112 AL5 NET 'No_Conn_BF_MGTRXN2_112' U1- # 112 AL6 NET 'No_Conn_BF_MGTRXP3_112' U1- # 112 AJ5 NET 'No_Conn_BF_MGTRXN3_112' U1- # 112 AJ6 # All Receiver Channels from MGT Quad 113 are unused NET 'No_Conn_BF_MGTRXP0_113' U1- # 113 AG5 NET 'No_Conn_BF_MGTRXN0_113' U1- # 113 AG6 NET 'No_Conn_BF_MGTRXP1_113' U1- # 113 AF3 NET 'No_Conn_BF_MGTRXN1_113' U1- # 113 AF4 NET 'No_Conn_BF_MGTRXP2_113' U1- # 113 AE5 NET 'No_Conn_BF_MGTRXN2_113' U1- # 113 AE6 NET 'No_Conn_BF_MGTRXP3_113' U1- # 113 AD3 NET 'No_Conn_BF_MGTRXN3_113' U1- # 113 AD4 NET 'No_Conn_BF_MGTRXP0_114' U1- # 114 AC5 # All Receiver Channels from MGT Quad 114 are unused NET 'No_Conn_BF_MGTRXN0_114' U1- # 114 AC6 NET 'No_Conn_BF_MGTRXP1_114' U1- # 114 AB3 NET 'No_Conn_BF_MGTRXN1_114' U1- # 114 AB4 NET 'No_Conn_BF_MGTRXP2_114' U1- # 114 AA5 NET 'No_Conn_BF_MGTRXN2_114' U1- # 114 AA6 NET 'No_Conn_BF_MGTRXP3_114' U1- # 114 Y3 NET 'No_Conn_BF_MGTRXN3_114' U1- # 114 Y4 NET 'No_Conn_BF_MGTRXP0_115' U1- # 115 W5 # All Receiver Channels from MGT Quad 115 are unused NET 'No_Conn_BF_MGTRXN0_115' U1- # 115 W6 NET 'No_Conn_BF_MGTRXP1_115' U1- # 115 V3 NET 'No_Conn_BF_MGTRXN1_115' U1- # 115 V4 NET 'No_Conn_BF_MGTRXP2_115' U1- # 115 U5 NET 'No_Conn_BF_MGTRXN2_115' U1- # 115 U6 NET 'No_Conn_BF_MGTRXP3_115' U1- # 115 R5 NET 'No_Conn_BF_MGTRXN3_115' U1- # 115 R6 # All Receiver Channels from MGT Quad 116 are unused NET 'No_Conn_BF_MGTRXP0_116' U1- # 116 P7 NET 'No_Conn_BF_MGTRXN0_116' U1- # 116 P8 NET 'No_Conn_BF_MGTRXP1_116' U1- # 116 N5 NET 'No_Conn_BF_MGTRXN1_116' U1- # 116 N6 NET 'No_Conn_BF_MGTRXP2_116' U1- # 116 L5 NET 'No_Conn_BF_MGTRXN2_116' U1- # 116 L6 NET 'No_Conn_BF_MGTRXP3_116' U1- # 116 J5 NET 'No_Conn_BF_MGTRXN3_116' U1- # 116 J6 # All Receiver Channels in MGT Quad 117 are # now used for the SFP Receiver signals. ##NET 'No_Conn_BF_MGTRXP0_117' U1- # 117 H7 ##NET 'No_Conn_BF_MGTRXN0_117' U1- # 117 H8 ##NET 'No_Conn_BF_MGTRXP1_117' U1- # 117 G5 ##NET 'No_Conn_BF_MGTRXN1_117' U1- # 117 G6 ##NET 'No_Conn_BF_MGTRXP2_117' U1- # 117 F7 ##NET 'No_Conn_BF_MGTRXN2_117' U1- # 117 F8 ##NET 'No_Conn_BF_MGTRXP3_117' U1- # 117 E5 ##NET 'No_Conn_BF_MGTRXN3_117' U1- # 117 E6 # All Receiver Channels from MGT Quad 118 are unused NET 'No_Conn_BF_MGTRXP0_118' U1- # 118 D7 NET 'No_Conn_BF_MGTRXN0_118' U1- # 118 D8 NET 'No_Conn_BF_MGTRXP1_118' U1- # 118 C5 NET 'No_Conn_BF_MGTRXN1_118' U1- # 118 C6 NET 'No_Conn_BF_MGTRXP2_118' U1- # 118 B7 NET 'No_Conn_BF_MGTRXN2_118' U1- # 118 B8 NET 'No_Conn_BF_MGTRXP3_118' U1- # 118 A5 NET 'No_Conn_BF_MGTRXN3_118' U1- # 118 A6 ################ # Transmitters ################ # All Tramsmitter Channels from MGT Quad 110 to 115 are used to drive the miniPOD transmitters # Those nets are defined in base_function_gtx_transmitters_n2r.txt # # All Tramsmitter Channels from MGT Quad 116 are unused NET 'No_Conn_BF_MGTTXP0_116' U1- # 116 N1 NET 'No_Conn_BF_MGTTXN0_116' U1- # 116 N2 NET 'No_Conn_BF_MGTTXP1_116' U1- # 116 M3 NET 'No_Conn_BF_MGTTXN1_116' U1- # 116 M4 NET 'No_Conn_BF_MGTTXP2_116' U1- # 116 L1 NET 'No_Conn_BF_MGTTXN2_116' U1- # 116 L2 NET 'No_Conn_BF_MGTTXP3_116' U1- # 116 K3 NET 'No_Conn_BF_MGTTXN3_116' U1- # 116 K4 # All Tramsmitter Channels from MGT Quad 117 are unused NET 'No_Conn_BF_MGTTXP0_117' U1- # 117 J1 NET 'No_Conn_BF_MGTTXN0_117' U1- # 117 J2 NET 'No_Conn_BF_MGTTXP1_117' U1- # 117 H3 NET 'No_Conn_BF_MGTTXN1_117' U1- # 117 H4 NET 'No_Conn_BF_MGTTXP2_117' U1- # 117 G1 NET 'No_Conn_BF_MGTTXN2_117' U1- # 117 G2 NET 'No_Conn_BF_MGTTXP3_117' U1- # 117 F3 NET 'No_Conn_BF_MGTTXN3_117' U1- # 117 F4 # Two of the Tramsmitter channels from MGT Quad 118 are used for the g-link output # Those nets are defined in base_function_low_speed_daq_roi_data_out_n2r.txt # The other two channels are unused NET 'No_Conn_BF_MGTTXP0_118' U1- # 118 E1 NET 'No_Conn_BF_MGTTXN0_118' U1- # 118 E2 NET 'No_Conn_BF_MGTTXP1_118' U1- # 118 D3 NET 'No_Conn_BF_MGTTXN1_118' U1- # 118 D4 ############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals for all unused and Not Connected Select IO pins # -=============------------------------------------=======================------- # # # Original Rev. 28-Nov-2012 Initial collection of all unused pins # Rev. 30-Nov-2012 Studying the set of unused pins generated 3 allocation improvements # Rev. 11-Dec-2012 Sort unused pins in alphabetical order # Rev. 16-Jan-2013 Adopt NET naming convention to pre-pend "No_Conn_" for unused pins, # replace pin number with IO signal name to make unique net names # and add "Select IO" to file name: base_function_unconnected_select_io_pins_n2r.txt # 03-Apr-2013 Remove pins now assigned to connections to Board Support FPGA, Debug Connector, # BF to TP S-Link, TTC signals, and adding one Global Clock. # Rev: 17-May-2013 Rearranged P12_18:21 to solve layer 9 boundary conflict (P08:11 vs P12:14) # which also involved putting pin AV23 into use and dropping AY24 # Rev: 30-May-2013 P20 now unused while N19 now used (after BF to BSPT and debug connections rework) # Most Recent Rev: 03-Jun-2013 AE35 is now used and AF41 now unused (swap pin used for cable IO signal 83) # # Signal Nets referenced in this file: # ------------------------------------ # # 'No_Conn_BF_xxxx' are the unique net names assigned to these Select IO signals # where "xxxx" is the fpga Select IO signal name # ############################################################################################ # Unused pins from IO bank 12 ############################# # note: This bank is otherwise used for the CTP output NET 'No_Conn_BF_IO_L9N_MRCC_12' U1- # 12 AN36 NET 'No_Conn_BF_IO_L10N_MRCC_12' U1- # 12 AP35 NET 'No_Conn_BF_IO_L16N_12' U1- # 12 AT34 # Unused pins from IO bank 13 ############################# # note: This bank is otherwise used for the CTP output and On-Card Bus NET 'No_Conn_BF_IO_L9P_MRCC_13' U1- # 13 AL34 # Unused pins from IO bank 14 ############################# # note: This bank is otherwise used for the On-Card Bus NET 'No_Conn_BF_IO_L18P_14' U1- # 14 AF32 # Unused pins from IO bank 15 ############################# # note: This bank is otherwise used for the Cable IO # and System Monitor differential User Inputs NET 'No_Conn_BF_IO_L18N_15' U1- # 15 AC33 NET 'No_Conn_BF_IO_L18P_15' U1- # 15 AC34 NET 'No_Conn_BF_IO_L9P_MRCC_15' U1- # 15 AD32 NET 'No_Conn_BF_IO_L14N_VREF_15' U1- # 15 AD35 NET 'No_Conn_BF_IO_L9N_MRCC_15' U1- # 15 AE32 NET 'No_Conn_BF_IO_L0P_15' U1- # 15 AE34 NET 'No_Conn_BF_IO_L17N_15' U1- # 15 AF41 # Unused pins from IO bank 16 ############################# # note: This bank is otherwise used for the Cable IO NET 'No_Conn_BF_IO_L16P_16' U1- # 16 U32 NET 'No_Conn_BF_IO_L16N_16' U1- # 16 U33 NET 'No_Conn_BF_IO_L10N_MRCC_16' U1- # 16 U34 NET 'No_Conn_BF_IO_L18P_16' U1- # 16 V33 NET 'No_Conn_BF_IO_L10P_MRCC_16' U1- # 16 V34 NET 'No_Conn_BF_IO_L18N_16' U1- # 16 W33 NET 'No_Conn_BF_IO_L12N_VRP_16' U1- # 16 Y32 NET 'No_Conn_BF_IO_L9N_MRCC_16' U1- # 16 Y33 # Unused pins from IO bank 17 ############################# # note: This bank is otherwise used for the Cable IO NET 'No_Conn_BF_IO_L4N_VREF_17' U1- # 17 N34 NET 'No_Conn_BF_IO_L4P_17' U1- # 17 N35 NET 'No_Conn_BF_IO_L9N_MRCC_17' U1- # 17 P35 NET 'No_Conn_BF_IO_L14N_VREF_17' U1- # 17 R34 NET 'No_Conn_BF_IO_L18P_17' U1- # 17 T34 # Unused pins from IO bank 21 ############################# # note: This bank is otherwise used for Backplane Inputs P10 and P11 NET 'No_Conn_BF_IO_L5P_21' U1- # 21 AJ23 NET 'No_Conn_BF_IO_L13N_21' U1- # 21 AL24 # Unused pins from IO bank 22 ############################# # note: This bank is otherwise used for Backplane Inputs P08, P09, P10 and P11 NET 'No_Conn_BF_IO_L9N_MRCC_22' U1- # 22 AL26 # Unused pins from IO bank 23 ############################# # note: This bank is otherwise used for Backplane Inputs P08 and P09 NET 'No_Conn_BF_IO_L14P_23' U1- # 23 AG28 NET 'No_Conn_BF_IO_L10P_MRCC_23' U1- # 23 AH24 NET 'No_Conn_BF_IO_L10N_MRCC_23' U1- # 23 AH25 NET 'No_Conn_BF_IO_L18N_23' U1- # 23 AH26 NET 'No_Conn_BF_IO_L18P_23' U1- # 23 AJ26 NET 'No_Conn_BF_IO_L16N_23' U1- # 23 AJ27 NET 'No_Conn_BF_IO_L9N_MRCC_23' U1- # 23 AK25 NET 'No_Conn_BF_IO_L8P_SRCC_23' U1- # 23 AK28 NET 'No_Conn_BF_IO_L1N_23' U1- # 23 AL31 # Unused pins from IO bank 24 ############################# # This IO bank has not yet been assigned NET 'No_Conn_BF_IO_L5P_D9_24' U1- # 24 N33 NET 'No_Conn_BF_IO_L7P_D5_24' U1- # 24 P32 NET 'No_Conn_BF_IO_L5N_D8_24' U1- # 24 P33 NET 'No_Conn_BF_IO_L3N_D12_24' U1- # 24 R30 NET 'No_Conn_BF_IO_L11P_SRCC_24' U1- # 24 R32 NET 'No_Conn_BF_IO_L7N_D4_24' U1- # 24 R33 NET 'No_Conn_BF_IO_L3P_D13_24' U1- # 24 T30 NET 'No_Conn_BF_IO_L13P_D1_FS1_24' U1- # 24 T31 NET 'No_Conn_BF_IO_L11N_SRCC_24' U1- # 24 T32 NET 'No_Conn_BF_IO_L13N_D0_FS0_24' U1- # 24 U31 NET 'No_Conn_BF_IO_L1N_GC_24' U1- # 24 V30 NET 'No_Conn_BF_IO_L15P_FWE_B_24' U1- # 24 V31 NET 'No_Conn_BF_IO_L1P_GC_24' U1- # 24 W30 NET 'No_Conn_BF_IO_L15N_RS1_24' U1- # 24 W31 NET 'No_Conn_BF_IO_L9P_MRCC_24' U1- # 24 Y30 NET 'No_Conn_BF_IO_L9N_MRCC_24' U1- # 24 AA30 NET 'No_Conn_BF_IO_L10P_MRCC_24' U1- # 24 AA31 NET 'No_Conn_BF_IO_L10N_MRCC_24' U1- # 24 AB31 NET 'No_Conn_BF_IO_L17N_VRP_24' U1- # 24 AC30 NET 'No_Conn_BF_IO_L17P_VRN_24' U1- # 24 AC31 NET 'No_Conn_BF_IO_L19N_24' U1- # 24 AD30 NET 'No_Conn_BF_IO_L19P_24' U1- # 24 AD31 NET 'No_Conn_BF_IO_L0P_GC_24' U1- # 24 AE30 NET 'No_Conn_BF_IO_L0N_GC_24' U1- # 24 AF30 NET 'No_Conn_BF_IO_L2N_D14_24' U1- # 24 AF31 NET 'No_Conn_BF_IO_L18N_24' U1- # 24 AG29 NET 'No_Conn_BF_IO_L4N_VREF_D10_24' U1- # 24 AG31 NET 'No_Conn_BF_IO_L2P_D15_24' U1- # 24 AG32 NET 'No_Conn_BF_IO_L18P_24' U1- # 24 AH29 NET 'No_Conn_BF_IO_L14P_FCS_B_24' U1- # 24 AH30 NET 'No_Conn_BF_IO_L4P_D11_24' U1- # 24 AH31 NET 'No_Conn_BF_IO_L6N_D6_24' U1- # 24 AH33 NET 'No_Conn_BF_IO_L14N_VREF_FOE_B_MOSI_24' U1- # 24 AJ30 NET 'No_Conn_BF_IO_L16P_RS0_24' U1- # 24 AJ31 NET 'No_Conn_BF_IO_L8N_SRCC_24' U1- # 24 AJ32 NET 'No_Conn_BF_IO_L6P_D7_24' U1- # 24 AJ33 NET 'No_Conn_BF_IO_L16N_CSO_B_24' U1- # 24 AK30 NET 'No_Conn_BF_IO_L12P_D3_24' U1- # 24 AK32 NET 'No_Conn_BF_IO_L8P_SRCC_24' U1- # 24 AK33 NET 'No_Conn_BF_IO_L12N_D2_FS2_24' U1- # 24 AL32 # Unused pins from IO bank 25 ############################# # note: This IO bank is otherwise used for one differential global clock input for a 40.08 MHz logic clock # and two differential signals carrying the S-link return channels to the TP FPGA # and two pins are receiving TTC information NET 'No_Conn_BF_IO_L6N_25' U1- # 25 H38 NET 'No_Conn_BF_IO_L4N_VREF_25' U1- # 25 J36 NET 'No_Conn_BF_IO_L4P_25' U1- # 25 J37 NET 'No_Conn_BF_IO_L8N_SRCC_25' U1- # 25 J38 NET 'No_Conn_BF_IO_L0N_25' U1- # 25 K32 NET 'No_Conn_BF_IO_L0P_25' U1- # 25 K33 NET 'No_Conn_BF_IO_L2N_25' U1- # 25 K34 NET 'No_Conn_BF_IO_L2P_25' U1- # 25 K35 NET 'No_Conn_BF_IO_L11P_SRCC_25' U1- # 25 K37 NET 'No_Conn_BF_IO_L8P_SRCC_25' U1- # 25 K38 NET 'No_Conn_BF_IO_L16P_VRN_25' U1- # 25 K39 NET 'No_Conn_BF_IO_L3P_25' U1- # 25 L31 NET 'No_Conn_BF_IO_L3N_25' U1- # 25 L32 NET 'No_Conn_BF_IO_L13P_25' U1- # 25 L34 NET 'No_Conn_BF_IO_L7P_25' U1- # 25 L35 NET 'No_Conn_BF_IO_L7N_25' U1- # 25 L36 NET 'No_Conn_BF_IO_L11N_SRCC_25' U1- # 25 L37 NET 'No_Conn_BF_IO_L17P_25' U1- # 25 M31 NET 'No_Conn_BF_IO_L15N_25' U1- # 25 M32 NET 'No_Conn_BF_IO_L15P_25' U1- # 25 M33 NET 'No_Conn_BF_IO_L13N_25' U1- # 25 M34 NET 'No_Conn_BF_IO_L1P_25' U1- # 25 N28 NET 'No_Conn_BF_IO_L5P_25' U1- # 25 N29 NET 'No_Conn_BF_IO_L5N_25' U1- # 25 N30 NET 'No_Conn_BF_IO_L17N_25' U1- # 25 N31 NET 'No_Conn_BF_IO_L9P_MRCC_25' U1- # 25 P27 NET 'No_Conn_BF_IO_L1N_25' U1- # 25 P28 NET 'No_Conn_BF_IO_L19P_GC_25' U1- # 25 P30 NET 'No_Conn_BF_IO_L19N_GC_25' U1- # 25 P31 NET 'No_Conn_BF_IO_L9N_MRCC_25' U1- # 25 R27 NET 'No_Conn_BF_IO_L10P_MRCC_25' U1- # 25 R28 NET 'No_Conn_BF_IO_L10N_MRCC_25' U1- # 25 R29 # Unused pins from IO bank 26 ############################# # note: This bank is otherwise used for Backplane Inputs P06 and P07 NET 'No_Conn_BF_IO_L2P_26' U1- # 26 J35 # Unused pins from IO bank 27 ############################# # note: This bank is otherwise used for Backplane Inputs P04, P05, P06 and P07 NET 'No_Conn_BF_IO_L16N_27' U1- # 27 J30 NET 'No_Conn_BF_IO_L14P_27' U1- # 27 J32 NET 'No_Conn_BF_IO_L12N_VRP_27' U1- # 27 J33 NET 'No_Conn_BF_IO_L18N_27' U1- # 27 K30 NET 'No_Conn_BF_IO_L9N_MRCC_27' U1- # 27 L30 NET 'No_Conn_BF_IO_L10P_MRCC_27' U1- # 27 M28 # Unused pins from IO bank 28 ############################# # note: This bank is otherwise used for Backplane Inputs P04 and P05 NET 'No_Conn_BF_IO_L3N_28' U1- # 28 F30 NET 'No_Conn_BF_IO_L16P_28' U1- # 28 J28 NET 'No_Conn_BF_IO_L16N_28' U1- # 28 K28 NET 'No_Conn_BF_IO_L19N_28' U1- # 28 M27 NET 'No_Conn_BF_IO_L8P_SRCC_28' U1- # 28 R25 # Unused pins from IO bank 32 ############################# # note: This bank is otherwise used for Backplane Inputs P12 and P13 NET 'No_Conn_BF_IO_L9N_MRCC_32' U1- # 32 AJ20 NET 'No_Conn_BF_IO_L9P_MRCC_32' U1- # 32 AJ21 NET 'No_Conn_BF_IO_L5P_32' U1- # 32 AL20 NET 'No_Conn_BF_IO_L7P_32' U1- # 32 AN20 NET 'No_Conn_BF_IO_L0P_32' U1- # 32 AY24 # Unused pins from IO bank 33 ############################# # note: This bank is otherwise used for Backplane Inputs P12, P13, P14 and P15 NET 'No_Conn_BF_IO_L10N_MRCC_33' U1- # 33 AJ15 NET 'No_Conn_BF_IO_L6P_33' U1- # 33 AJ17 NET 'No_Conn_BF_IO_L18N_33' U1- # 33 AJ18 # Unused pins from IO bank 34 ############################# # note: This bank is otherwise used for Backplane Inputs P14 and P15 # and two differential global clock inputs for 40.08 and 320.64 MHz logic clocks # All pins in this bank are used # Unused pins from IO bank 35 ############################# # note: This bank is otherwise used for Backplane Inputs P00 and P01 # and System Monitor differential User Inputs # All pins in this bank are used # Unused pins from IO bank 36 ############################# # note: This bank is otherwise used for Backplane Inputs P00, P01, P02 and P03 NET 'No_Conn_BF_IO_L10N_MRCC_36' U1- # 36 P16 # Unused pins from IO bank 37 ############################# # note: This bank is otherwise used for Backplane Inputs P02 and P03 NET 'No_Conn_BF_IO_L16P_37' U1- # 37 K20 NET 'No_Conn_BF_IO_L16N_37' U1- # 37 L20 NET 'No_Conn_BF_IO_L9N_MRCC_37' U1- # 37 L21 # Unused pins from IO bank 38 ############################# # note: This IO bank is otherwise used for connections to the Board Support FPGA # and connections to the Debug Connector NET 'No_Conn_BF_IO_L5P_38' U1- # 38 G26 NET 'No_Conn_BF_IO_L0P_38' U1- # 38 H24 NET 'No_Conn_BF_IO_L4N_VREF_38' U1- # 38 H25 NET 'No_Conn_BF_IO_L4P_38' U1- # 38 H26 NET 'No_Conn_BF_IO_L6N_38' U1- # 38 J25 NET 'No_Conn_BF_IO_L12N_VRP_38' U1- # 38 K24 NET 'No_Conn_BF_IO_L6P_38' U1- # 38 K25 NET 'No_Conn_BF_IO_L12P_VRN_38' U1- # 38 L24 NET 'No_Conn_BF_IO_L14N_VREF_38' U1- # 38 M23 NET 'No_Conn_BF_IO_L16N_38' U1- # 38 M24 NET 'No_Conn_BF_IO_L16P_38' U1- # 38 N23 NET 'No_Conn_BF_IO_L19P_38' U1- # 38 P20