# # CMX FF1759 Package NET-to-Pin File # -------------------------------------- # # # Original Rev. 30-Jan-2012 # Most Recent Rev. 14-Nov-2012 # # # # This is the N2P file is for Virtex-6 VCCO_xy Nets # in the FF1759 Package. # # This file is for the Base Function FPGA on the CMX card. # # The following 112 pins are the Virtex-6 VCCO power pins. # On the CMX card the VCCO power will come from the BULK_2V5 # power distribution bus. All Base Function FPGA I/O Banks # will have 2.5V signal levels. # NET 'BULK_2V5' U1-M10 U1-R11 # VCCO_0 NET 'BULK_2V5' U1-AP34 U1-AT38 U1-AU35 U1-AW39 U1-AY36 # VCCO_12 NET 'BULK_2V5' U1-AK36 U1-AN37 U1-AR41 U1-AV42 U1-BB40 # VCCO_13 NET 'BULK_2V5' U1-AF38 U1-AG35 U1-AH42 U1-AJ39 U1-AM40 # VCCO_14 NET 'BULK_2V5' U1-AA33 U1-AB40 U1-AC37 U1-AD34 U1-AE41 # VCCO_15 NET 'BULK_2V5' U1-U35 U1-V32 U1-V42 U1-W39 U1-Y36 # VCCO_16 NET 'BULK_2V5' U1-M40 U1-N37 U1-P34 U1-R41 U1-T38 # VCCO_17 NET 'BULK_2V5' U1-AH22 U1-AL23 U1-AP24 U1-AU25 U1-AY26 # VCCO_21 NET 'BULK_2V5' U1-AN27 U1-AT28 U1-AW29 U1-BA33 U1-BB30 # VCCO_22 NET 'BULK_2V5' U1-AG25 U1-AK26 U1-AL33 U1-AM30 U1-AR31 U1-AV32 # VCCO_23 NET 'BULK_2V5' U1-AB30 U1-AE31 U1-AH32 U1-AJ29 U1-R31 U1-W29 # VCCO_24 NET 'BULK_2V5' U1-H42 U1-J39 U1-K36 U1-L33 U1-M30 U1-T28 # VCCO_25 NET 'BULK_2V5' U1-B40 U1-C37 U1-E41 U1-F38 U1-G35 # VCCO_26 NET 'BULK_2V5' U1-A33 U1-D34 U1-E31 U1-H32 U1-J29 # VCCO_27 NET 'BULK_2V5' U1-B30 U1-F28 U1-K26 U1-N27 U1-P24 # VCCO_28 NET 'BULK_2V5' U1-AJ19 U1-AM20 U1-AR21 U1-AV22 U1-BA23 # VCCO_32 NET 'BULK_2V5' U1-AK16 U1-AL13 U1-AN17 U1-AT18 U1-AW19 U1-BB20 # VCCO_33 NET 'BULK_2V5' U1-AP14 U1-AR11 U1-AU15 U1-AV12 U1-AY16 U1-BA13 # VCCO_34 NET 'BULK_2V5' U1-C17 U1-D14 U1-G15 U1-H12 U1-L13 # VCCO_35 NET 'BULK_2V5' U1-B20 U1-F18 U1-K16 U1-N17 U1-P14 # VCCO_36 NET 'BULK_2V5' U1-A23 U1-D24 U1-E21 U1-H22 U1-J19 # VCCO_37 NET 'BULK_2V5' U1-C27 U1-G25 U1-L23 U1-M20 U1-R21 # VCCO_38 # # CMX FF1759 Package NET-to-Pin File # -------------------------------------- # # # Original Rev. 30-Jan-2012 # Most Recent Rev. 14-Nov-2012 # # # This is the N2P file is for Virtex-6 Ground Nets in the FF1759 Package. # # This file is for the Base Function FPGA on the CMX card. # # This file has 431 Ground Pins. # NET 'GROUND' U1-A2 U1-A3 U1-A4 U1-A7 U1-A8 U1-A11 U1-A13 U1-A18 U1-A28 NET 'GROUND' U1-A38 U1-AA3 U1-AA7 U1-AA9 U1-AA11 U1-AA13 U1-AA15 U1-AA17 U1-AA19 U1-AA23 NET 'GROUND' U1-AA25 U1-AA27 U1-AA29 U1-AA38 U1-AB1 U1-AB2 U1-AB5 U1-AB6 U1-AB9 U1-AB10 NET 'GROUND' U1-AB12 U1-AB14 U1-AB16 U1-AB18 U1-AB20 U1-AB24 U1-AB26 U1-AB28 U1-AB35 U1-AC3 NET 'GROUND' U1-AC7 U1-AC9 U1-AC11 U1-AC13 U1-AC15 U1-AC17 U1-AC19 U1-AC23 U1-AC25 U1-AC27 NET 'GROUND' U1-AC29 U1-AC32 U1-AC42 U1-AD1 U1-AD2 U1-AD5 U1-AD6 U1-AD9 U1-AD10 U1-AD12 NET 'GROUND' U1-AD14 U1-AD16 U1-AD18 U1-AD20 U1-AD22 U1-AD24 U1-AD26 U1-AD28 U1-AD39 U1-AE3 NET 'GROUND' U1-AE7 U1-AE9 U1-AE11 U1-AE13 U1-AE15 U1-AE17 U1-AE19 U1-AE21 U1-AE23 U1-AE25 NET 'GROUND' U1-AE27 U1-AE29 U1-AE36 U1-AF1 U1-AF2 U1-AF5 U1-AF6 U1-AF9 U1-AF10 U1-AF11 NET 'GROUND' U1-AF12 U1-AF14 U1-AF16 U1-AF18 U1-AF20 U1-AF22 U1-AF24 U1-AF26 U1-AF28 U1-AF33 NET 'GROUND' U1-AG3 U1-AG4 U1-AG7 U1-AG8 U1-AG9 U1-AG10 U1-AG11 U1-AG13 U1-AG15 U1-AG17 NET 'GROUND' U1-AG19 U1-AG21 U1-AG23 U1-AG30 U1-AG40 U1-AH1 U1-AH2 U1-AH5 U1-AH6 U1-AH9 NET 'GROUND' U1-AH11 U1-AH12 U1-AH14 U1-AH16 U1-AH17 U1-AH18 U1-AH20 U1-AH27 U1-AH37 U1-AJ3 NET 'GROUND' U1-AJ7 U1-AJ9 U1-AJ11 U1-AJ12 U1-AJ13 U1-AJ14 U1-AJ24 U1-AJ34 U1-AK1 U1-AK2 NET 'GROUND' U1-AK5 U1-AK6 U1-AK9 U1-AK11 U1-AK12 U1-AK13 U1-AK21 U1-AK31 U1-AK41 U1-AL3 NET 'GROUND' U1-AL7 U1-AL9 U1-AL12 U1-AL18 U1-AL28 U1-AL38 U1-AM1 U1-AM2 U1-AM5 U1-AM9 NET 'GROUND' U1-AM10 U1-AM15 U1-AM25 U1-AM35 U1-AN3 U1-AN7 U1-AN9 U1-AN12 U1-AN22 U1-AN32 NET 'GROUND' U1-AN42 U1-AP1 U1-AP2 U1-AP5 U1-AP9 U1-AP19 U1-AP29 U1-AP39 U1-AR3 U1-AR7 NET 'GROUND' U1-AR9 U1-AR16 U1-AR26 U1-AR36 U1-AT1 U1-AT2 U1-AT5 U1-AT6 U1-AT9 U1-AT10 NET 'GROUND' U1-AT11 U1-AT13 U1-AT23 U1-AT33 U1-AU3 U1-AU7 U1-AU11 U1-AU20 U1-AU30 U1-AU40 NET 'GROUND' U1-AV1 U1-AV2 U1-AV5 U1-AV9 U1-AV10 U1-AV11 U1-AV17 U1-AV27 U1-AV37 U1-AW3 NET 'GROUND' U1-AW7 U1-AW11 U1-AW14 U1-AW24 U1-AW34 U1-AY1 U1-AY2 U1-AY5 U1-AY9 U1-AY10 NET 'GROUND' U1-AY11 U1-AY12 U1-AY21 U1-AY31 U1-AY41 U1-B1 U1-B2 U1-B5 U1-B9 U1-B10 NET 'GROUND' U1-B12 U1-B13 U1-B15 U1-B25 U1-B35 U1-BA3 U1-BA7 U1-BA11 U1-BA12 U1-BA18 NET 'GROUND' U1-BA28 U1-BA38 U1-BB2 U1-BB5 U1-BB6 U1-BB9 U1-BB10 U1-BB11 U1-BB12 U1-BB15 NET 'GROUND' U1-BB25 U1-BB35 U1-C3 U1-C7 U1-C11 U1-C12 U1-C22 U1-C32 U1-C42 U1-D1 NET 'GROUND' U1-D2 U1-D5 U1-D9 U1-D10 U1-D11 U1-D19 U1-D29 U1-D39 U1-E3 U1-E7 NET 'GROUND' U1-E11 U1-E16 U1-E26 U1-E36 U1-F1 U1-F2 U1-F5 U1-F9 U1-F10 U1-F11 NET 'GROUND' U1-F13 U1-F23 U1-F33 U1-G3 U1-G7 U1-G11 U1-G20 U1-G30 U1-G40 U1-H1 NET 'GROUND' U1-H2 U1-H5 U1-H9 U1-H10 U1-H11 U1-H17 U1-H27 U1-H37 U1-J3 U1-J7 NET 'GROUND' U1-J9 U1-J14 U1-J24 U1-J34 U1-K1 U1-K2 U1-K5 U1-K6 U1-K9 U1-K11 NET 'GROUND' U1-K21 U1-K31 U1-K41 U1-L3 U1-L7 U1-L9 U1-L18 U1-L28 U1-L38 U1-M1 NET 'GROUND' U1-M2 U1-M5 U1-M6 U1-M9 U1-M15 U1-M25 U1-M35 U1-N3 U1-N7 U1-N9 NET 'GROUND' U1-N12 U1-N22 U1-N32 U1-N42 U1-P1 U1-P2 U1-P5 U1-P9 U1-P11 U1-P12 NET 'GROUND' U1-P19 U1-P29 U1-P39 U1-R3 U1-R7 U1-R9 U1-R13 U1-R15 U1-R16 U1-R17 NET 'GROUND' U1-R19 U1-R26 U1-R36 U1-T1 U1-T2 U1-T5 U1-T6 U1-T9 U1-T11 U1-T12 NET 'GROUND' U1-T14 U1-T16 U1-T18 U1-T20 U1-T22 U1-T24 U1-T26 U1-T33 U1-U3 U1-U4 NET 'GROUND' U1-U7 U1-U8 U1-U9 U1-U10 U1-U11 U1-U13 U1-U15 U1-U17 U1-U19 U1-U21 NET 'GROUND' U1-U23 U1-U25 U1-U27 U1-U29 U1-U30 U1-U40 U1-V1 U1-V2 U1-V5 U1-V6 NET 'GROUND' U1-V9 U1-V10 U1-V12 U1-V14 U1-V16 U1-V18 U1-V20 U1-V22 U1-V24 U1-V26 NET 'GROUND' U1-V28 U1-V37 U1-W3 U1-W7 U1-W9 U1-W11 U1-W13 U1-W15 U1-W17 U1-W19 NET 'GROUND' U1-W21 U1-W23 U1-W25 U1-W27 U1-W34 U1-Y1 U1-Y2 U1-Y5 U1-Y6 U1-Y9 NET 'GROUND' U1-Y10 U1-Y12 U1-Y14 U1-Y16 U1-Y18 U1-Y20 U1-Y24 U1-Y26 U1-Y28 U1-Y31 NET 'GROUND' U1-Y41 U1-AJ10 # # CMX FF1759 Package NET-to-Pin File # -------------------------------------- # # # Original Rev. 30-Jan-2012 # Most Recent Rev. 31-Dec-2012 # # # # This is the N2P file is for Virtex-6 MGTAVCC and MGTAVTT Nets # in the FF1759 Package. These are the analog power nets for # the high speed serial transceivers. # # This file is for the Base Function FPGA on the CMX card. # --------------- # # The following 18 pins are the Virtex-6 MGTAVCC power pins. # On the CMX card the MGTAVCC power will come from the GTX_AVTT # power distribution bus. NET 'BF_GTX_AVCC' U1-AA8 U1-C8 U1-E8 U1-G8 U1-J8 U1-L8 U1-N8 U1-R8 U1-W8 # MGTAVCC_N NET 'BF_GTX_AVCC' U1-AC8 U1-AE8 U1-AJ8 U1-AL8 U1-AN8 U1-AR8 U1-AU8 U1-AW8 U1-BA8 # MGTAVCC_S # The following 27 pins are the Virtex-6 MGTAVTT power pins. # On the CMX card the MGTAVTT power will come from the GTX_AVCC # power distribution bus. NET 'BF_GTX_AVTT' U1-B6 U1-C4 U1-D6 U1-E4 U1-F6 U1-G4 U1-H6 U1-J4 U1-L4 # MGTAVTT_N NET 'BF_GTX_AVTT' U1-N4 U1-P6 U1-R4 U1-W4 # MGTAVTT_N NET 'BF_GTX_AVTT' U1-AA4 U1-AC4 U1-AE4 U1-AJ4 U1-AL4 U1-AM6 U1-AN4 U1-AP6 # MGTAVTT_S NET 'BF_GTX_AVTT' U1-AR4 U1-AU4 U1-AV6 U1-AW4 U1-AY6 U1-BA4 # MGTAVTT_S # # CMX FF1759 Package NET-to-Pin File # -------------------------------------- # # # Bank 0 and Special Pins # ------===--------------------- # # # # Original Rev. 29-Dec-2012 # Most Recent Rev. 18-Mar-2012 # # # # This is the N2P file for Virtex-6 "Bank 0" and Special # Nets for the CMX Base Function FPGA. # # Pins with many and completely different functions are # included in what Xilinx calls "Bank 0". These are not # Select I/O pins. Rather these pins include those that # are involved with thinks like Configuration, System # Monitor, JTAG, Power Management, Si temperature # measurement, ... # # These are all special one of a kind fixed location pins. # # Other "special" pins, besides those in "Bank 0" should # be included in this Net to Pin file. Recall, we want # to assign a net to every one of the 1760 pins on this # component. # # # This file is for the Base Function FPGA on the CMX card. # ------------- # # # JTAG connections to the Base Function FPGA # # On the CMX's Virtex-6 FPGAs the JTAG connections # are pins in "Bank 0" NET 'CFG_TMS_from_ACE' U1-AN11 # TMS_0 CFG JTAG TMS from ACE pin 85 NET 'CFG_TCK_from_ACE' U1-AN10 # TCK_0 CFG JTAG TCK from ACE pin 80 NET 'CFG_ACE_TDO_to_BF_TDI' U1-AP10 # TDI_0 CFG JTAG Data from ACE to BF NET 'CFG_BF_TDO' U1-AR10 # TDO_0 CFG JTAG Data from BF to TP # # Configuration Nets NET 'BF_PROGRAM_B' U1-M11 # PROGRAM_B_0 NET 'BF_INIT_B' U1-N11 # INIT_B_0 NET 'BF_CONFIG_DONE' U1-N10 # DONE_0 NET 'BF_M0' U1-AL11 # M0_0 NET 'BF_M1' U1-AM11 # M1_0 NET 'BF_M2' U1-AL10 # M2_0 NET 'BF_CCLK' U1-K10 # CCLK_0 NET 'BF_DIN' U1-L10 # DIN_0 NET 'BF_DOUT_BUSY' U1-AK10 # DOUT_BUSY_0 NET 'BF_CSI_B' U1-T10 # CSI_B_0 NET 'BF_RDWR_B' U1-J10 # RDWR_B_0 # # System Monitor Nets NET 'BF_SM_AVDD' U1-Y22 # AVDD_0 NET 'BF_SM_AVSS' U1-Y21 # AVSS_0 NET 'BF_SM_VP' U1-AA22 # VP_0 NET 'BF_SM_VN' U1-AB21 # VN_0 NET 'BF_SM_VREFP' U1-AB22 # VREFP_0 NET 'BF_SM_AVSS' U1-AA21 # VREFN_0 # # Silicon Temperature Nets NET 'BF_SI_TEMP_DXP' U1-AC22 # DXP_0 NET 'BF_SI_TEMP_DXN' U1-AC21 # DXN_0 # # Other Special "Bank 0" Nets NET 'BF_HSWAPEN' U1-P10 # HSWAPEN_0 # VBATT is a power supply pin for the Decryptor Key memory. # The book says that when VBATT is not used to connect # this pin to either VccAUX or to GROUND. CMX will not # use the Decryptor Key VBATT supply. CMX will # permanently and irrevocably Ground this pin. # ## NET 'BF_VBATT' U1-R10 # VBATT_0 NET 'GROUND' U1-R10 # VBATT_0 # VFS is a power supply pin for programming the EFUSE. # The book says to Ground the VFS pin when it is not # being used. CMX will not use the EFUSE. Thus CMX # will permanently and irrevocably Ground this pin. # ## NET 'BF_VFS' U1-AH10 # VFS_0 NET 'GROUND' U1-AH10 # VFS_0 # # Special Non-Bank 0 Nets # # CMX FF1759 Package NET-to-Pin File # -------------------------------------- # # # Original Rev. 1-Feb-2012 # Most Recent Rev. 21-Dec-2012 # # # # This is the N2P file is for Virtex-6 VCCAUX and VCCINT Nets # in the FF1759 Package. # # This file is for the Base Function FPGA on the CMX card. # # The following 20 pins are the Virtex-6 VCCAUX power pins. # On the CMX card the VCCAUX power will come from the BULK_2V5 # power distribution bus. NET 'BULK_2V5' U1-AA10 U1-AA28 U1-AB11 U1-AB29 U1-AC10 U1-AC28 NET 'BULK_2V5' U1-AD11 U1-AD29 U1-AE10 U1-AE28 U1-AF27 U1-AF29 U1-T29 U1-U28 U1-V11 U1-V29 NET 'BULK_2V5' U1-W10 U1-W28 U1-Y11 U1-Y29 # The following 104 pins are the Virtex-6 VCCINT power pins. # On the CMX card the VCCINT power for the Base Function FPGA # will come from the BF_CORE power distribution bus. NET 'BF_CORE' U1-AA12 U1-AA14 U1-AA16 U1-AA18 U1-AA20 U1-AA24 NET 'BF_CORE' U1-AA26 U1-AB13 U1-AB15 U1-AB17 U1-AB19 U1-AB23 U1-AB25 U1-AB27 U1-AC12 U1-AC14 NET 'BF_CORE' U1-AC16 U1-AC18 U1-AC20 U1-AC24 U1-AC26 U1-AD13 U1-AD15 U1-AD17 U1-AD19 U1-AD21 NET 'BF_CORE' U1-AD23 U1-AD25 U1-AD27 U1-AE12 U1-AE14 U1-AE16 U1-AE18 U1-AE20 U1-AE22 U1-AE24 NET 'BF_CORE' U1-AE26 U1-AF13 U1-AF15 U1-AF17 U1-AF19 U1-AF21 U1-AF23 U1-AF25 U1-AG12 U1-AG14 NET 'BF_CORE' U1-AG16 U1-AG18 U1-AG20 U1-AG22 U1-AG24 U1-AG26 U1-AH13 U1-AH15 U1-AH19 U1-AH21 NET 'BF_CORE' U1-AH23 U1-P13 U1-P15 U1-R12 U1-R14 U1-R18 U1-R20 U1-R22 U1-R24 U1-T13 NET 'BF_CORE' U1-T15 U1-T17 U1-T19 U1-T21 U1-T23 U1-T25 U1-T27 U1-U12 U1-U14 U1-U16 NET 'BF_CORE' U1-U18 U1-U20 U1-U22 U1-U24 U1-U26 U1-V13 U1-V15 U1-V17 U1-V19 U1-V21 NET 'BF_CORE' U1-V23 U1-V25 U1-V27 U1-W12 U1-W14 U1-W16 U1-W18 U1-W20 U1-W22 U1-W24 NET 'BF_CORE' U1-W26 U1-Y13 U1-Y15 U1-Y17 U1-Y19 U1-Y23 U1-Y25 U1-Y27