############################################################################################ # # CMX Net-to-Resource File for the # TP Function FPGA IO signals used for Front Panel CTP Output # -=============------------------------------------------------ # # # Original Rev. 19-Nov-2012 Place holder # Rev: 11-Dec-2012 Copy Base FPGA pin assignment # Rev: 14-Jan-2013 Assign outer pins from IO banks 36, 37, 38 and route on layers 2,3,4,5 # Rev: 05-Apr-2013 Tentatively flag these signals to belong to layer 6 # Most Recent Rev: 04-Jun-2013 Update position of signal #65 after final location of 5th translator # # # Signal Nets referenced in this file: # ------------------------------------ # # There are 0, 1 or 2 CTP cables connected to a given CMX card. # A Crate CMX with only Base CMX functionality does not send any data to the CTP # A System CMX in a CPM crate sends information to the CTP over one cable # A System CMX in a JEM crate sends information to the CTP over two cables # A Crate CMX with TP functionality would probably send information to the CTP over two cables # # 'TP_DOUT_CTP_xx' are the CTP output signals from the TP FPGA with xx=00 to 65. # Each CTP output cable carries 33 LVDS signals consisting of 31 data bits, one clock # and one parity bit. # xx=0 to 30 carry data bits on cable #1 # xx=31 carry the clock on cable #1 # xx=64 carry the parity on cable #1 # xx=32 to 62 carry data bits on cable #2 # xx=63 carry the clock on cable #2 # xx=65 carry the parity on cable #2 # Note that regional clock signals are assigned to CTP output signals # 31 and 63 # for flexibility, so that the CTP output cables could be used as inputs instead. # # These CTP output signals are assigned here to resources in IO banks ??2 and ?? # # The rest of the circuitry used to drive the LVDS cables is in the file front_panel_ctp_driver_n2p.txt # in the Net_Lists/Front_Panel_CTP_IO_Nets directory # # # Note: Trace layer information is appended as comments below. # ----- # # NET 'TP_DOUT_CTP_00' U2- #> F02 #> T02 00 D22 # # ^ ^ ^ ^ ^ # | | | | | # Tailored comment flag to help with string searches -----------------+ | | | | # | | | | # Target Trace Layer number to use for this net --------------------------+ | | | # as it exits the FPGA (to reach a nearby via if needed) | | | # F01 is top layer, F02 the first inner layer, etc | | | # | | | # Target Trace Layer number to use for this net ---------------------------------+ | | # as it reaches the level translator near the front of the card | | # T01 is top layer, T02 the first inner layer, etc | | # | | # Signal number is repeated to help manual entry of Pin Number ---------------------+ | # | # Target Pin Number read from paper study -----------------------------------------------+ # and cross-checked after Match_Res2Pin # ############################################################################################ # # CTP Cable #1 # NET 'TP_DOUT_CTP_00' U2- #> F02 #> T06 00 D22 NET 'TP_DOUT_CTP_01' U2- #> F02 #> T06 01 B22 NET 'TP_DOUT_CTP_02' U2- #> F02 #> T06 02 A22 NET 'TP_DOUT_CTP_03' U2- #> F02 #> T06 03 B23 NET 'TP_DOUT_CTP_04' U2- #> F02 #> T06 04 C23 NET 'TP_DOUT_CTP_05' U2- #> F02 #> T06 05 A24 NET 'TP_DOUT_CTP_06' U2- #> F02 #> T06 06 B24 NET 'TP_DOUT_CTP_07' U2- #> F02 #> T06 07 A25 NET 'TP_DOUT_CTP_08' U2- #> F02 #> T06 08 C25 NET 'TP_DOUT_CTP_09' U2- #> F02 #> T06 09 A26 NET 'TP_DOUT_CTP_10' U2- #> F02 #> T06 10 B26 NET 'TP_DOUT_CTP_11' U2- #> F02 #> T06 11 A27 NET 'TP_DOUT_CTP_12' U2- #> F02 #> T06 12 B27 NET 'TP_DOUT_CTP_13' U2- #> F02 #> T06 13 B28 NET 'TP_DOUT_CTP_14' U2- #> F03 #> T06 14 F22 NET 'TP_DOUT_CTP_15' U2- #> F03 #> T06 15 E22 NET 'TP_DOUT_CTP_16' U2- #> F03 #> T06 16 D23 NET 'TP_DOUT_CTP_17' U2- #> F03 #> T06 17 E24 NET 'TP_DOUT_CTP_18' U2- #> F03 #> T06 18 C24 NET 'TP_DOUT_CTP_19' U2- #> F03 #> T06 19 D25 NET 'TP_DOUT_CTP_20' U2- #> F03 #> T06 20 C26 NET 'TP_DOUT_CTP_21' U2- #> F03 #> T06 21 D27 NET 'TP_DOUT_CTP_22' U2- #> F03 #> T06 22 C28 NET 'TP_DOUT_CTP_23' U2- #> F04 #> T06 23 K22 NET 'TP_DOUT_CTP_24' U2- #> F04 #> T06 24 G22 NET 'TP_DOUT_CTP_25' U2- #> F04 #> T06 25 E23 NET 'TP_DOUT_CTP_26' U2- #> F04 #> T06 26 F24 NET 'TP_DOUT_CTP_27' U2- #> F04 #> T06 27 F25 NET 'TP_DOUT_CTP_28' U2- #> F04 #> T06 28 E25 NET 'TP_DOUT_CTP_29' U2- #> F04 #> T06 29 D26 NET 'TP_DOUT_CTP_30' U2- #> F04 #> T06 30 E27 NET 'TP_DOUT_CTP_31' U2- #> F05 #> T06 31 J22 NET 'TP_DOUT_CTP_64' U2- #> F05 #> T06 64 F26 # # CTP Cable #2 # NET 'TP_DOUT_CTP_32' U2- #> F02 #> T06 32 B17 NET 'TP_DOUT_CTP_33' U2- #> F02 #> T06 33 A17 NET 'TP_DOUT_CTP_34' U2- #> F02 #> T06 34 B18 NET 'TP_DOUT_CTP_35' U2- #> F02 #> T06 35 B19 NET 'TP_DOUT_CTP_36' U2- #> F02 #> T06 36 A19 NET 'TP_DOUT_CTP_37' U2- #> F02 #> T06 37 C20 NET 'TP_DOUT_CTP_38' U2- #> F02 #> T06 38 A20 NET 'TP_DOUT_CTP_39' U2- #> F02 #> T06 39 D20 NET 'TP_DOUT_CTP_40' U2- #> F02 #> T06 40 A21 NET 'TP_DOUT_CTP_41' U2- #> F02 #> T06 41 B21 NET 'TP_DOUT_CTP_42' U2- #> F02 #> T06 42 C21 NET 'TP_DOUT_CTP_43' U2- #> F03 #> T06 43 D17 NET 'TP_DOUT_CTP_44' U2- #> F03 #> T06 44 C18 NET 'TP_DOUT_CTP_45' U2- #> F03 #> T06 45 C19 NET 'TP_DOUT_CTP_46' U2- #> F03 #> T06 46 E19 NET 'TP_DOUT_CTP_47' U2- #> F03 #> T06 47 E20 NET 'TP_DOUT_CTP_48' U2- #> F03 #> T06 48 D21 NET 'TP_DOUT_CTP_49' U2- #> F03 #> T06 49 F21 NET 'TP_DOUT_CTP_50' U2- #> F04 #> T06 50 E17 NET 'TP_DOUT_CTP_51' U2- #> F04 #> T06 51 D18 NET 'TP_DOUT_CTP_52' U2- #> F04 #> T06 52 E18 NET 'TP_DOUT_CTP_53' U2- #> F04 #> T06 53 F19 NET 'TP_DOUT_CTP_54' U2- #> F04 #> T06 54 F20 NET 'TP_DOUT_CTP_55' U2- #> F04 #> T06 55 G21 NET 'TP_DOUT_CTP_56' U2- #> F04 #> T06 56 H21 NET 'TP_DOUT_CTP_57' U2- #> F05 #> T06 57 F16 NET 'TP_DOUT_CTP_58' U2- #> F05 #> T06 58 F17 NET 'TP_DOUT_CTP_59' U2- #> F05 #> T06 59 G17 NET 'TP_DOUT_CTP_60' U2- #> F05 #> T06 60 G18 NET 'TP_DOUT_CTP_61' U2- #> F05 #> T06 61 G19 NET 'TP_DOUT_CTP_62' U2- #> F05 #> T06 62 H20 NET 'TP_DOUT_CTP_63' U2- #> F05 #> T06 63 L22 NET 'TP_DOUT_CTP_65' U2- #> F05 #> T06 65 J21 ############################################################################################ # # CMX Net-to-Resource File for the # TP Function FPGA IO signals used the highspeed GTX Receivers # -=============------------------------------------------------- # # # Original Rev. 16-Mar-2012 # Rev. 5-Dec-2012 Rename nets and add termination resistors # Rev: 11-Dec-2012 File name changed for uniformity and consistency # between Base and TP files # Rev: 31-Dec-2012 Change the net-name on the MGTAVTTRCAL_115 # Calibration Resistor pin. # Rev: 23-May-2013 Assign full net names, including fiber number, to the # GTX Receivers in Quads 113, 114, 115, i.e. MiniPOD MP4. # Rev: 24-May-2013 Assign full net names, including fiber number, to the # GTX Receivers in Quads 110, 111, 112, i.e. MiniPOD MP3 # and to Quads 116, 117, 118, i.e. MiniPOD MP5. # Most Recent Rev: 8-Oct-2013 Change some GTX Transceiver - MiniPOD Fiber assignments # to allow better trace length match of DIR and CMP traces. # # # Receiver 1 MiniPOD MP3 # --------===----------===== NET 'MP3_F01_QUAD_110_REC_0_DIR' U2- NET 'MP3_F01_QUAD_110_REC_0_CMP' U2- NET 'MP3_F07_QUAD_110_REC_1_DIR' U2- NET 'MP3_F07_QUAD_110_REC_1_CMP' U2- NET 'MP3_F05_QUAD_110_REC_2_DIR' U2- NET 'MP3_F05_QUAD_110_REC_2_CMP' U2- NET 'MP3_F03_QUAD_110_REC_3_DIR' U2- NET 'MP3_F03_QUAD_110_REC_3_CMP' U2- NET 'MP3_F09_QUAD_111_REC_0_DIR' U2- NET 'MP3_F09_QUAD_111_REC_0_CMP' U2- NET 'MP3_F11_QUAD_111_REC_1_DIR' U2- NET 'MP3_F11_QUAD_111_REC_1_CMP' U2- NET 'MP3_F10_QUAD_111_REC_2_DIR' U2- NET 'MP3_F10_QUAD_111_REC_2_CMP' U2- NET 'MP3_F08_QUAD_111_REC_3_DIR' U2- NET 'MP3_F08_QUAD_111_REC_3_CMP' U2- NET 'MP3_F00_QUAD_112_REC_0_DIR' U2- NET 'MP3_F00_QUAD_112_REC_0_CMP' U2- NET 'MP3_F04_QUAD_112_REC_1_DIR' U2- NET 'MP3_F04_QUAD_112_REC_1_CMP' U2- NET 'MP3_F06_QUAD_112_REC_2_DIR' U2- NET 'MP3_F06_QUAD_112_REC_2_CMP' U2- NET 'MP3_F02_QUAD_112_REC_3_DIR' U2- NET 'MP3_F02_QUAD_112_REC_3_CMP' U2- # Receiver 2 MiniPOD MP4 # --------===----------===== NET 'MP4_F01_QUAD_113_REC_0_DIR' U2- NET 'MP4_F01_QUAD_113_REC_0_CMP' U2- NET 'MP4_F03_QUAD_113_REC_3_DIR' U2- NET 'MP4_F03_QUAD_113_REC_3_CMP' U2- NET 'MP4_F05_QUAD_113_REC_2_DIR' U2- NET 'MP4_F05_QUAD_113_REC_2_CMP' U2- NET 'MP4_F07_QUAD_113_REC_1_DIR' U2- NET 'MP4_F07_QUAD_113_REC_1_CMP' U2- NET 'MP4_F09_QUAD_114_REC_0_DIR' U2- NET 'MP4_F09_QUAD_114_REC_0_CMP' U2- NET 'MP4_F11_QUAD_114_REC_1_DIR' U2- NET 'MP4_F11_QUAD_114_REC_1_CMP' U2- NET 'MP4_F10_QUAD_114_REC_2_DIR' U2- NET 'MP4_F10_QUAD_114_REC_2_CMP' U2- NET 'MP4_F08_QUAD_114_REC_3_DIR' U2- NET 'MP4_F08_QUAD_114_REC_3_CMP' U2- NET 'MP4_F02_QUAD_115_REC_0_DIR' U2- NET 'MP4_F02_QUAD_115_REC_0_CMP' U2- NET 'MP4_F04_QUAD_115_REC_1_DIR' U2- NET 'MP4_F04_QUAD_115_REC_1_CMP' U2- NET 'MP4_F06_QUAD_115_REC_2_DIR' U2- NET 'MP4_F06_QUAD_115_REC_2_CMP' U2- NET 'MP4_F00_QUAD_115_REC_3_DIR' U2- NET 'MP4_F00_QUAD_115_REC_3_CMP' U2- # Receiver 3 MiniPOD MP5 # --------===----------===== NET 'MP5_F01_QUAD_116_REC_0_DIR' U2- NET 'MP5_F01_QUAD_116_REC_0_CMP' U2- NET 'MP5_F03_QUAD_116_REC_1_DIR' U2- NET 'MP5_F03_QUAD_116_REC_1_CMP' U2- NET 'MP5_F05_QUAD_116_REC_2_DIR' U2- NET 'MP5_F05_QUAD_116_REC_2_CMP' U2- NET 'MP5_F07_QUAD_116_REC_3_DIR' U2- NET 'MP5_F07_QUAD_116_REC_3_CMP' U2- NET 'MP5_F09_QUAD_117_REC_0_DIR' U2- NET 'MP5_F09_QUAD_117_REC_0_CMP' U2- NET 'MP5_F11_QUAD_117_REC_1_DIR' U2- NET 'MP5_F11_QUAD_117_REC_1_CMP' U2- NET 'MP5_F10_QUAD_117_REC_2_DIR' U2- NET 'MP5_F10_QUAD_117_REC_2_CMP' U2- NET 'MP5_F08_QUAD_117_REC_3_DIR' U2- NET 'MP5_F08_QUAD_117_REC_3_CMP' U2- NET 'MP5_F02_QUAD_118_REC_0_DIR' U2- NET 'MP5_F02_QUAD_118_REC_0_CMP' U2- NET 'MP5_F04_QUAD_118_REC_1_DIR' U2- NET 'MP5_F04_QUAD_118_REC_1_CMP' U2- NET 'MP5_F06_QUAD_118_REC_2_DIR' U2- NET 'MP5_F06_QUAD_118_REC_2_CMP' U2- NET 'MP5_F00_QUAD_118_REC_3_DIR' U2- NET 'MP5_F00_QUAD_118_REC_3_CMP' U2- # Now connect the GTX Termination Calibration Resistor # This is a precision 100 Ohm resistor. # See Chapter 5 page 274 of the # Virtex-6 GTX User Guide. # # The other half of these connections is in: # # ..../Everything_Else/dci_gtx_res_nets_n2p.txt # NET 'TP_MGTRREF' U2- # B11 Topological MGTRREF pin NET 'TP_GTX_AVTT' U2- # A12 Topological MGTAVTTRCAL # connected to the TP_GTX_AVTT bus # as indicated in the User Guide ############################################################################################ # # CMX Net-to-Resource File for the # TP Function FPGA IO signals used for the Low-Speed DAQ & ROI Data Output # -=============-------------------------------------------------------------- # # # Original Rev. 17-Jan-2013 # Most Recent Rev. 17-Jan-2013 Assign lowest Two channels # # # TP Function FPGA # # DAQ and ROI Data Outputs to SFP Optical Transmitters # # SFP3 TP Function DAQ SFP Optical Output # SFP4 TP Function RIO SFP Optical Output # NET 'TP_DAQ_DATA_OUT_DIR' U2- # BA1 DAQ Data Output Direct NET 'TP_DAQ_DATA_OUT_CMP' U2- # BA2 DAQ Data Output Complement NET 'TP_ROI_DATA_OUT_DIR' U2- # BB3 ROI Data Output Direct NET 'TP_ROI_DATA_OUT_CMP' U2- # BB4 ROI Data Output Complement ############################################################################################ # # CMX Net-to-Resource File for the # TP Function FPGA IO signals used for the On-Card VME bus signals # -=============----------------------------------------------------- # # # Original Rev. 11-Dec-2012 Copy Base FPGA pin assignment # Most Recent Rev: 14-Jan-2013 Assign outer pins from IO banks 15, 16 &17 and route on layers 7 (most) & 6 (with via) # # # Signal Nets referenced in this file: # ------------------------------------ # # 'OCB_Axx' are the On-Card Bus Address lines to the Base FPGA with xx=01 to 23 # (note there is no "A00" signal) # # 'OCB_Dyy' are the On-Card Bus Data lines to the Base FPGA with yy=00 to 15 # # 'OCB_GEO_ADRS_z' are the On-Card Bus Geographic Section Address lines with z=0 to 6 # # # 'OCB_SYS_RESET_B' is the On-Card Bus VME SYS_RESET signal # The "_B" postfix is used to indicate that the reset request is active # when the electrical signal is low # # 'OCB_DS_B' is the On-Card Bus Data strobe. # The "_B" postfix is used to indicate that the data strobe signal is on the # falling edge of the electrical signal. # # 'OCB_WRITE_B' is the On-Card Bus Data Direction # The "_B" postfix is used to indicate that the Write direction is # requested when the electrical signal is low. # # # IO Banks used # ------------- # # Most signal nets are assigned to IO Bank 14 and a few to Io Bank 13 # - All address line nets are in IO Bank 14 # - All data line nets are in IO Bank 14 # - The Data Strobe net is assigned to a regional clock pin in IO Bank 14 # - The Board Select net is assigned to a regional clock pin in IO Bank 13 # - The Write Net is assigned to an IO input pin in Bank 13 # - The Sys_Reset net is assigned to an IO input pin in Bank 13 # # The bulk of IO Bank 13 is used for the CTP output signals # # Note: Trace layer information is appended as comments below. # ----- # # NET 'OCB_A01' U2- #> F07 #> T07 A01 AF41 # # ^ ^ ^ ^ ^ # | | | | | # Tailored comment flag to help with string searches ------------------+ | | | | # | | | | # Target Trace Layer number to use for this net --------------------------+ | | | # as it exits the FPGA (to reach a nearby via if needed) | | | # F01 is top layer, F02 the first inner layer, etc | | | # | | | # Target Trace Layer number to use for this net ---------------------------------+ | | # as it connects the VME bus transceiver section to the two FPGAs | | # T01 is top layer, T02 the first inner layer, etc | | # | | # Signal number is repeated to help manual entry of Pin Number ---------------------+ | # | # Target Pin Number read from paper drawing ---------------------------------------------+ # and cross-checked after Match_Res2Pin # ############################################################################################ # The lower Address (1:16), all Data lines, and the Data Strobe, will come in directly (no via) # The data strobe is assigned to a regional clock input pin (but probably not used as a clock) NET 'OCB_A01' U2- #> F07 #> T07 A01 AF41 NET 'OCB_A02' U2- #> F07 #> T07 A02 AF42 NET 'OCB_A03' U2- #> F07 #> T07 A03 AE40 NET 'OCB_A04' U2- #> F07 #> T07 A04 AE42 NET 'OCB_A05' U2- #> F07 #> T07 A05 AD41 NET 'OCB_A06' U2- #> F07 #> T07 A06 AD42 NET 'OCB_A07' U2- #> F07 #> T07 A07 AC41 NET 'OCB_A08' U2- #> F07 #> T07 A08 AC40 NET 'OCB_A09' U2- #> F07 #> T07 A09 AB42 NET 'OCB_A10' U2- #> F07 #> T07 A10 AB41 NET 'OCB_A11' U2- #> F07 #> T07 A11 AB39 NET 'OCB_A12' U2- #> F07 #> T07 A12 AA40 NET 'OCB_A13' U2- #> F07 #> T07 A13 AA41 NET 'OCB_A14' U2- #> F07 #> T07 A14 AA42 NET 'OCB_A15' U2- #> F07 #> T07 A15 Y40 NET 'OCB_A16' U2- #> F07 #> T07 A16 Y42 NET 'OCB_D00' U2- #> F07 #> T07 D00 L41 NET 'OCB_D01' U2- #> F07 #> T07 D01 L42 NET 'OCB_D02' U2- #> F07 #> T07 D02 M41 NET 'OCB_D03' U2- #> F07 #> T07 D03 M42 NET 'OCB_D04' U2- #> F07 #> T07 D04 N41 NET 'OCB_D05' U2- #> F07 #> T07 D05 P41 NET 'OCB_D06' U2- #> F07 #> T07 D06 P42 NET 'OCB_D07' U2- #> F07 #> T07 D07 R40 NET 'OCB_D08' U2- #> F07 #> T07 D08 R42 NET 'OCB_D09' U2- #> F07 #> T07 D09 T41 NET 'OCB_D10' U2- #> F07 #> T07 D10 T42 NET 'OCB_D11' U2- #> F07 #> T07 D11 U41 NET 'OCB_D12' U2- #> F07 #> T07 D12 U42 NET 'OCB_D13' U2- #> F07 #> T07 D13 V41 NET 'OCB_D14' U2- #> F07 #> T07 D14 W41 NET 'OCB_D15' U2- #> F07 #> T07 D15 W42 NET 'OCB_DS_B' U2- #> F07 #> T07 DS W32 # The upper Address (17:23), the Direction, SysReset, and all Geographic Address signals # will need to transition to another trace layer (tentatively trace layer 2) NET 'OCB_A17' U2- #> F02 #> T07 A17 W38 NET 'OCB_A18' U2- #> F02 #> T07 A18 W40 NET 'OCB_A19' U2- #> F02 #> T07 A19 V40 NET 'OCB_A20' U2- #> F02 #> T07 A20 U39 NET 'OCB_A21' U2- #> F02 #> T07 A21 T40 NET 'OCB_A22' U2- #> F02 #> T07 A22 R39 NET 'OCB_A23' U2- #> F02 #> T07 A23 P40 NET 'OCB_WRITE_B' U2- #> F02 #> T07 WRI Y39 NET 'OCB_SYS_RESET_B' U2- #> F02 #> T07 RES AA39 NET 'OCB_GEO_ADRS_0' U2- #> F02 #> T07 GA0 AB38 NET 'OCB_GEO_ADRS_1' U2- #> F02 #> T07 GA1 L40 NET 'OCB_GEO_ADRS_2' U2- #> F02 #> T07 GA2 M39 NET 'OCB_GEO_ADRS_3' U2- #> F02 #> T07 GA3 N40 NET 'OCB_GEO_ADRS_4' U2- #> F02 #> T07 GA4 AC39 NET 'OCB_GEO_ADRS_5' U2- #> F02 #> T07 GA5 AD40 NET 'OCB_GEO_ADRS_6' U2- #> F02 #> T07 GA6 AE39 ############################################################################################ # # CMX Net-to-Resource File for the # # # TP Function FPGA Clock Connections # -=============-----=======------------- # # # Original Rev. 24-AUG-2012 # Rev. 9-Dec-2012 # Rev: 11-Dec-2012 File name changed for uniformity and consistency between Base and TP files # Rev: 29-Dec-2012 Remove the JTAG nets from this file. Remove "jtag" from the filename. # Rev: 16-Jan-2013 Change "Not_Used_" to "No_Conn_". # Most Recent Rev: 2-May-2013 Change Logic and GTX clock net names to # reflect the 40.08 or 320.64 MHz LHC clocks # and the 40.000 or 100.000 MHz Crystal clocks # # # # Topological Processor FPGA Clocks Logic and Transceiver # -----------------------------======------------------------ # # # LHC Locked Logic Clocks # # Connect the 40.08 MHz and 320.64 MHz Logic Clocks to # the Topological Processor FPGA. These are LHC locked LVDS # clock signals to the Logic in the Topological Processor FPGA. # # A Global Clock input in I/O Bank 34 receives the DeSkew #1 40.08 MHz Logic clock. # # A Global Clock input in I/O Bank 25 receives the DeSkew #2 40.08 MHz Logic clock. # # A Global Clock input in I/O Bank 34 receives the 320.64 MHz Logic clock. # NET 'CLK_40MHz08_DSKW_1_TP_LOGIC_DIR' U2- # AY14 40.08 MHz DeSkew-1 LHC Logic NET 'CLK_40MHz08_DSKW_1_TP_LOGIC_CMP' U2- # AY13 Clk to the Topological FPGA NET 'CLK_40MHz08_DSKW_2_TP_LOGIC_DIR' U2- # J42 40.08 MHz DeSkew-2 LHC Logic NET 'CLK_40MHz08_DSKW_2_TP_LOGIC_CMP' U2- # K42 Clk to the Topological FPGA NET 'CLK_320MHz64_LHC_TP_LOGIC_DIR' U2- # AP12 320.64 MHz LHC Logic Clock NET 'CLK_320MHz64_LHC_TP_LOGIC_CMP' U2- # AP11 to the Topological FPGA # # Crystal Oscillator #2 GTX Clock # # Now to the Topological Processor FPGA connect the 40.000 MHz # or 100.000 Mhz Crystal Oscillator #2 LVPECL clock to the # clock "0" input of the GTX Transceiver Quad 110. # # This is the clock to the GTX Transcievers that # transmit the DAQ and ROI data either by G-Link # or by S-Link. # NET 'CLK_100MHz000_XTAL_2_TP_TRNCV_DIR' U2- # BA10 100.000 MHz Crystal Osc #2 NET 'CLK_100MHz000_XTAL_2_TP_TRNCV_CMP' U2- # BA9 GTX Clk to the TP FPGA. # This could also be 40.000 MHz # # LHC Locked GTX Clocks # # Now on the Topological Processor FPGA connect the # 320.64 MHz LHC locked LVPECL clocks to the clock # inputs of the GTX Transceivers. # # We will use the "0" clock inputs to the Quad Banks # 111, 114, and 117 to receive these Transceiver clocks. # These are the Topological Processor GTX Transceivers # that receive the 6.4 Gbps L1Topo data. # NET 'CLK_320MHz64_LHC_TP_QUAD_111_DIR' U2- # AU10 320.64 MHz LHC GTX Clk #1 NET 'CLK_320MHz64_LHC_TP_QUAD_111_CMP' U2- # AU9 to the Topological FPGA NET 'CLK_320MHz64_LHC_TP_QUAD_114_DIR' U2- # AB8 320.64 MHz LHC GTX Clk #2 NET 'CLK_320MHz64_LHC_TP_QUAD_114_CMP' U2- # AB7 to the Topological FPGA NET 'CLK_320MHz64_LHC_TP_QUAD_117_DIR' U2- # G10 320.64 MHz LHC GTX Clk #3 NET 'CLK_320MHz64_LHC_TP_QUAD_117_CMP' U2- # G9 to the Topological FPGA # # Now on the Topological Processor FPGA connect ALL of the # UN-Used Tranceiver Clock Inputs to single point nets. # # Not Used Bank 110 Clock Input NET 'No_Conn_TP_GTX_CLK_1_110_DIR' U2- # pin AW10 NET 'No_Conn_TP_GTX_CLK_1_110_CMP' U2- # pin AW9 # Not Used Bank 111 Clock Input NET 'No_Conn_TP_GTX_CLK_1_111_DIR' U2- # pin AT8 NET 'No_Conn_TP_GTX_CLK_1_111_CMP' U2- # pin AT7 # Not Used Bank 112 Clock Inputs NET 'No_Conn_TP_GTX_CLK_0_112_DIR' U2- # pin AK8 NET 'No_Conn_TP_GTX_CLK_0_112_CMP' U2- # pin AK7 NET 'No_Conn_TP_GTX_CLK_1_112_DIR' U2- # pin AH8 NET 'No_Conn_TP_GTX_CLK_1_112_CMP' U2- # pin AH7 # Not Used Bank 113 Clock Inputs NET 'No_Conn_TP_GTX_CLK_0_113_DIR' U2- # pin AF8 NET 'No_Conn_TP_GTX_CLK_0_113_CMP' U2- # pin AF7 NET 'No_Conn_TP_GTX_CLK_1_113_DIR' U2- # pin AD8 NET 'No_Conn_TP_GTX_CLK_1_113_CMP' U2- # pin AD7 # Not Used Bank 114 Clock Input NET 'No_Conn_TP_GTX_CLK_1_114_DIR' U2- # pin Y8 NET 'No_Conn_TP_GTX_CLK_1_114_CMP' U2- # pin Y7 # Not Used Bank 115 Clock Inputs NET 'No_Conn_TP_GTX_CLK_0_115_DIR' U2- # pin V8 NET 'No_Conn_TP_GTX_CLK_0_115_CMP' U2- # pin V7 NET 'No_Conn_TP_GTX_CLK_1_115_DIR' U2- # pin T8 NET 'No_Conn_TP_GTX_CLK_1_115_CMP' U2- # pin T7 # Not Used Bank 116 Clock Inputs NET 'No_Conn_TP_GTX_CLK_0_116_DIR' U2- # pin M8 NET 'No_Conn_TP_GTX_CLK_0_116_CMP' U2- # pin M7 NET 'No_Conn_TP_GTX_CLK_1_116_DIR' U2- # pin K8 NET 'No_Conn_TP_GTX_CLK_1_116_CMP' U2- # pin K7 # Not Used Bank 117 Clock Input NET 'No_Conn_TP_GTX_CLK_1_117_DIR' U2- # pin E10 NET 'No_Conn_TP_GTX_CLK_1_117_CMP' U2- # pin E9 # Not Used Bank 118 Clock Inputs NET 'No_Conn_TP_GTX_CLK_0_118_DIR' U2- # pin C10 NET 'No_Conn_TP_GTX_CLK_0_118_CMP' U2- # pin C9 NET 'No_Conn_TP_GTX_CLK_1_118_DIR' U2- # pin A10 NET 'No_Conn_TP_GTX_CLK_1_118_CMP' U2- # pin A9 ############################################################################################ # # CMX Net-to-Resource File for the # Topo Function FPGA IO signals used for the connections to the TTC signals # -=============------------------------------------------================== # # # Original Rev. 28-Mar-2012 # Most Recent Rev. 04-Apr-2013 find location for these 53x signals # # ############################################################################################ # 53x signals are connecting to the buffered version of the TTCdec signals NET 'BUF_TTC_BRCST_2' U2- #> F07 #> T07 BB34 NET 'BUF_TTC_BRCST_3' U2- #> F07 #> T07 BA34 NET 'BUF_TTC_BRCST_4' U2- #> F07 #> T07 BA35 NET 'BUF_TTC_BRCST_5' U2- #> F07 #> T07 BB36 NET 'BUF_TTC_BRCST_6' U2- #> F07 #> T07 BA36 NET 'BUF_TTC_BRCST_7' U2- #> F07 #> T07 BB37 NET 'BUF_TTC_BRCST_STR_1' U2- #> F07 #> T07 BA37 NET 'BUF_TTC_BRCST_STR_2' U2- #> F07 #> T07 BB38 NET 'BUF_TTC_SIN_ERR_STR' U2- #> F07 #> T07 AY38 NET 'BUF_TTC_DB_ERR_STR' U2- #> F07 #> T07 BB39 NET 'BUF_TTC_CLK_40_L1A' U2- #> F07 #> T07 BA39 NET 'BUF_TTC_BNCH_CNT_RES' U2- #> F07 #> T07 BA40 NET 'BUF_TTC_EV_CNT_RES' U2- #> F07 #> T07 BB41 NET 'BUF_TTC_EV_CNT_H_STR' U2- #> F07 #> T07 BA41 NET 'BUF_TTC_EV_CNT_L_STR' U2- #> F07 #> T07 BA42 NET 'BUF_TTC_BNCH_CNT_STR' U2- #> F07 #> T07 AY39 NET 'BUF_TTC_B_CNT_0' U2- #> F07 #> T07 AY40 NET 'BUF_TTC_B_CNT_1' U2- #> F07 #> T07 AY42 NET 'BUF_TTC_B_CNT_2' U2- #> F07 #> T07 AW40 NET 'BUF_TTC_B_CNT_3' U2- #> F07 #> T07 AW41 NET 'BUF_TTC_B_CNT_4' U2- #> F07 #> T07 AW42 NET 'BUF_TTC_B_CNT_5' U2- #> F07 #> T07 AV40 NET 'BUF_TTC_B_CNT_6' U2- #> F07 #> T07 AV41 NET 'BUF_TTC_B_CNT_7' U2- #> F07 #> T07 AU39 NET 'BUF_TTC_B_CNT_8' U2- #> F07 #> T07 AU41 NET 'BUF_TTC_B_CNT_9' U2- #> F07 #> T07 AU42 NET 'BUF_TTC_B_CNT_10' U2- #> F07 #> T07 AT40 NET 'BUF_TTC_B_CNT_11' U2- #> F07 #> T07 AT41 NET 'BUF_TTC_DQ_0' U2- #> F07 #> T07 AT42 NET 'BUF_TTC_DQ_1' U2- #> F07 #> T07 AR39 NET 'BUF_TTC_DQ_2' U2- #> F07 #> T07 AR40 NET 'BUF_TTC_DQ_3' U2- #> F07 #> T07 AR42 NET 'BUF_TTC_L1_ACCEPT' U2- #> F07 #> T07 AP40 NET 'BUF_TTC_SER_B_CH' U2- #> F07 #> T07 AP41 NET 'BUF_TTC_D_OUT_STR' U2- #> F07 #> T07 AP42 NET 'BUF_TTC_READY' U2- #> F07 #> T07 AN40 NET 'BUF_TTC_STATUS_2' U2- #> F07 #> T07 AN41 NET 'BUF_TTC_D_OUT_0' U2- #> F07 #> T07 AM39 NET 'BUF_TTC_D_OUT_1' U2- #> F07 #> T07 AM41 NET 'BUF_TTC_D_OUT_2' U2- #> F07 #> T07 AM42 NET 'BUF_TTC_D_OUT_3' U2- #> F07 #> T07 AL40 NET 'BUF_TTC_D_OUT_4' U2- #> F07 #> T07 AL41 NET 'BUF_TTC_D_OUT_5' U2- #> F07 #> T07 AL42 NET 'BUF_TTC_D_OUT_6' U2- #> F07 #> T07 AK39 NET 'BUF_TTC_D_OUT_7' U2- #> F07 #> T07 AK40 NET 'BUF_TTC_SUB_ADRS_0' U2- #> F07 #> T07 AK42 NET 'BUF_TTC_SUB_ADRS_1' U2- #> F07 #> T07 AJ40 NET 'BUF_TTC_SUB_ADRS_2' U2- #> F07 #> T07 AJ41 NET 'BUF_TTC_SUB_ADRS_3' U2- #> F07 #> T07 AJ42 NET 'BUF_TTC_SUB_ADRS_4' U2- #> F07 #> T07 AH40 NET 'BUF_TTC_SUB_ADRS_5' U2- #> F07 #> T07 AH41 NET 'BUF_TTC_SUB_ADRS_6' U2- #> F07 #> T07 AG41 NET 'BUF_TTC_SUB_ADRS_7' U2- #> F07 #> T07 AG42 ############################################################################################ # # CMX Net-to-Resource File for the # Topo Function FPGA IO signals used for the connections to the TP FPGA # -=============------------------------------------------================ # # Original Rev. 02-Apr-2012 # Rev. 03-Apr-2013 find location for these signals # Most Recent Rev. 20-Jun-2013 swap the two channels to ease trace routing # # BF to TP connections for support of S-link return channels # ========----------------------------====================== # # If the TP function needs to support S-link protocol (rather than G-link) # the CMX will need to receive the return channel of the Duplex S-link. # # The SFP optical receiver from the 2x S-link connections (DAQ and ROI) # cannot be directly received in the TP FPGA because all 36x MGT receivers # of the TP FPGA are already used with the 3x12 Avago optical receivers. # # The SFP optical receivers are instead routed to MGT receivers located # on the BF FPGA and the serial signal received is sent from the BF FPGA # to the TP FPGA via two differential Select IO signals. # # Signal Nets referenced in this file: # ------------------------------------ # # BF_TO_TP_DAQ_SLINK_RETURN_DIR Direct signal # BF_TO_TP_DAQ_SLINK_RETURN_CMP Complement signal # for the return S-link channel for DAQ readout # # BF_TO_TP_ROI_SLINK_RETURN_DIR Direct signal # BF_TO_TP_ROI_SLINK_RETURN_CMP Complement signal # for the return S-link channel for ROI readout # ############################################################################################ # 4x Select IO pins forming 2x differential signals going to the TP FPGA # This is IO Bank 26 and the signals will be routed north on trace layer 6. NET 'BF_TO_TP_DAQ_SLINK_RETURN_DIR' U2- #> F06 #> T06 A40 NET 'BF_TO_TP_DAQ_SLINK_RETURN_CMP' U2- #> F06 #> T06 A41 NET 'BF_TO_TP_ROI_SLINK_RETURN_DIR' U2- #> F06 #> T06 B38 NET 'BF_TO_TP_ROI_SLINK_RETURN_CMP' U2- #> F06 #> T06 A39 ############################################################################################ # # CMX Net-to-Resource File for the # Topo Function FPGA IO signals used for the connections to the Board Support FPGA # -=============------------------------------------------========================== # # # Original Rev. 28-Mar-2012 # Rev. 03-Apr-2013 find location for these 15x signals # Most Recent Rev. 20-Jun-2013 Swap TP_TO_FROM_BSPT_6 and _7 to help trace layout # # Signal Nets referenced in this file: # ------------------------------------ # # TP_REQ_CTP_n_INPUT (n=1:2) 2x direction request for CTP cable n sent to BSPT FPGA # # TP_LED_REQ_n (n=0:4) 5x LED state request sent to BSPT FPGA # # TP_TO_FROM_BSPT_n (n=0:7) 8x un-assigned Input or Ouput connections to BSPT FPGA # ############################################################################################ # 15x signals are going to the Board Support FPGA on layer 7 # These signals are listed in west to east order as they leave the FPGA area on layer 7 NET 'TP_REQ_CTP_1_INPUT' U2- #> F07 #> T07 A32 NET 'TP_REQ_CTP_2_INPUT' U2- #> F07 #> T07 B32 NET 'TP_LED_REQ_0' U2- #> F07 #> T07 B33 NET 'TP_LED_REQ_1' U2- #> F07 #> T07 A34 NET 'TP_LED_REQ_2' U2- #> F01 #> T07 B34 NET 'TP_LED_REQ_3' U2- #> F01 #> T07 A35 NET 'TP_LED_REQ_4' U2- #> F01 #> T07 C35 NET 'TP_TO_FROM_BSPT_0' U2- #> F06 #> T07 A36 NET 'TP_TO_FROM_BSPT_1' U2- #> F06 #> T07 B36 NET 'TP_TO_FROM_BSPT_2' U2- #> F01 #> T07 A37 NET 'TP_TO_FROM_BSPT_3' U2- #> F01 #> T07 B37 NET 'TP_TO_FROM_BSPT_4' U2- #> F01 #> T07 C38 NET 'TP_TO_FROM_BSPT_5' U2- #> F07 #> T07 B39 NET 'TP_TO_FROM_BSPT_6' U2- #> F07 #> T07 B41 NET 'TP_TO_FROM_BSPT_7' U2- #> F07 #> T07 C40 ############################################################################################ # # CMX Net-to-Resource File for the # Topo Function FPGA IO signals used for the connections to the Debug Connector # -=============------------------------------------------====================== # # # Original Rev. 28-Mar-2012 # Rev. 03-Apr-2013 find location for these 10x signals without interfering with backplane inputs # Most Recent Rev: 10-Jul-2013 Reorder pin assignment for straight route near debug connector # # Signal Nets referenced in this file: # ------------------------------------ # # TP_DEBUG_n (n=0:9) 10x spare connections from the BF FPGA to debug connector J14 # ############################################################################################ # 10x signals are going to the Debug Connector on layer 6 NET 'TP_DEBUG_0' U2- #> F06 #> T06 F42 NET 'TP_DEBUG_1' U2- #> F06 #> T06 D41 NET 'TP_DEBUG_2' U2- #> F06 #> T06 F41 NET 'TP_DEBUG_3' U2- #> F06 #> T06 D42 NET 'TP_DEBUG_4' U2- #> F06 #> T06 E42 NET 'TP_DEBUG_5' U2- #> F06 #> T06 E40 NET 'TP_DEBUG_6' U2- #> F06 #> T06 G41 NET 'TP_DEBUG_7' U2- #> F06 #> T06 C41 NET 'TP_DEBUG_8' U2- #> F06 #> T06 G42 NET 'TP_DEBUG_9' U2- #> F06 #> T06 B42 ############################################################################################ # # CMX Net-to-Resource File for the # TP Function FPGA IO signals used for all unused and Not Connected MGT IO pins # -=============-----------------------------------------====================---------- # # # Original Rev. 17-Jan-2013 # Most Recent Rev. 17-Jan-2013 Initial roundup # # # On the TP Function FPGA connect ALL of the # UN-Used Tranceiver IO Pins to single point nets. # # Signal Nets referenced in this file: # ------------------------------------ # # 'No_Conn_TP_xxxx' are the unique net names assigned to these MGT IO signals # where "xxxx" is the fpga MGT IO signal name # ############################################################################################ ################ # Receivers ################ # All Receiver Channels from MGT Quad 110 to 118 are used to field the miniPOD recievers # Those nets are defined in tp_function_gtx_receivers_n2r.txt # ################ # Transmitters ################ # Two of the Tramsmitter channels from MGT Quad 110 are used for the g-link output # Those nets are defined in base_function_low_speed_daq_roi_data_out_n2r.txt # The other two channels are unused NET 'No_Conn_TP_MGTTXP2_110' U2- # 110 AY3 NET 'No_Conn_TP_MGTTXN2_110' U2- # 110 AY4 NET 'No_Conn_TP_MGTTXP3_110' U2- # 110 AW1 NET 'No_Conn_TP_MGTTXN3_110' U2- # 110 AW2 # All Tramsmitter Channels from MGT Quad 111 are unused NET 'No_Conn_TP_MGTTXP0_111' U2- # 111 AV3 NET 'No_Conn_TP_MGTTXN0_111' U2- # 111 AV4 NET 'No_Conn_TP_MGTTXP1_111' U2- # 111 AU1 NET 'No_Conn_TP_MGTTXN1_111' U2- # 111 AU2 NET 'No_Conn_TP_MGTTXP2_111' U2- # 111 AT3 NET 'No_Conn_TP_MGTTXN2_111' U2- # 111 AT4 NET 'No_Conn_TP_MGTTXP3_111' U2- # 111 AR1 NET 'No_Conn_TP_MGTTXN3_111' U2- # 111 AR2 # All Tramsmitter Channels from MGT Quad 112 are unused NET 'No_Conn_TP_MGTTXP0_112' U2- # 112 AP3 NET 'No_Conn_TP_MGTTXN0_112' U2- # 112 AP4 NET 'No_Conn_TP_MGTTXP1_112' U2- # 112 AN1 NET 'No_Conn_TP_MGTTXN1_112' U2- # 112 AN2 NET 'No_Conn_TP_MGTTXP2_112' U2- # 112 AM3 NET 'No_Conn_TP_MGTTXN2_112' U2- # 112 AM4 NET 'No_Conn_TP_MGTTXP3_112' U2- # 112 AL1 NET 'No_Conn_TP_MGTTXN3_112' U2- # 112 AL2 # All Tramsmitter Channels from MGT Quad 113 are unused NET 'No_Conn_TP_MGTTXP0_113' U2- # 113 AK3 NET 'No_Conn_TP_MGTTXN0_113' U2- # 113 AK4 NET 'No_Conn_TP_MGTTXP1_113' U2- # 113 AJ1 NET 'No_Conn_TP_MGTTXN1_113' U2- # 113 AJ2 NET 'No_Conn_TP_MGTTXP2_113' U2- # 113 AH3 NET 'No_Conn_TP_MGTTXN2_113' U2- # 113 AH4 NET 'No_Conn_TP_MGTTXP3_113' U2- # 113 AG1 NET 'No_Conn_TP_MGTTXN3_113' U2- # 113 AG2 # All Tramsmitter Channels from MGT Quad 114 are unused NET 'No_Conn_TP_MGTTXP0_114' U2- # 114 AE1 NET 'No_Conn_TP_MGTTXN0_114' U2- # 114 AE2 NET 'No_Conn_TP_MGTTXP1_114' U2- # 114 AC1 NET 'No_Conn_TP_MGTTXN1_114' U2- # 114 AC2 NET 'No_Conn_TP_MGTTXP2_114' U2- # 114 AA1 NET 'No_Conn_TP_MGTTXN2_114' U2- # 114 AA2 NET 'No_Conn_TP_MGTTXP3_114' U2- # 114 W1 NET 'No_Conn_TP_MGTTXN3_114' U2- # 114 W2 # All Tramsmitter Channels from MGT Quad 115 are unused NET 'No_Conn_TP_MGTTXP0_115' U2- # 115 U1 NET 'No_Conn_TP_MGTTXN0_115' U2- # 115 U2 NET 'No_Conn_TP_MGTTXP1_115' U2- # 115 T3 NET 'No_Conn_TP_MGTTXN1_115' U2- # 115 T4 NET 'No_Conn_TP_MGTTXP2_115' U2- # 115 R1 NET 'No_Conn_TP_MGTTXN2_115' U2- # 115 R2 NET 'No_Conn_TP_MGTTXP3_115' U2- # 115 P3 NET 'No_Conn_TP_MGTTXN3_115' U2- # 115 P4 # All Tramsmitter Channels from MGT Quad 116 are unused NET 'No_Conn_TP_MGTTXP0_116' U2- # 116 N1 NET 'No_Conn_TP_MGTTXN0_116' U2- # 116 N2 NET 'No_Conn_TP_MGTTXP1_116' U2- # 116 M3 NET 'No_Conn_TP_MGTTXN1_116' U2- # 116 M4 NET 'No_Conn_TP_MGTTXP2_116' U2- # 116 L1 NET 'No_Conn_TP_MGTTXN2_116' U2- # 116 L2 NET 'No_Conn_TP_MGTTXP3_116' U2- # 116 K3 NET 'No_Conn_TP_MGTTXN3_116' U2- # 116 K4 # All Tramsmitter Channels from MGT Quad 117 are unused NET 'No_Conn_TP_MGTTXP0_117' U2- # 117 J1 NET 'No_Conn_TP_MGTTXN0_117' U2- # 117 J2 NET 'No_Conn_TP_MGTTXP1_117' U2- # 117 H3 NET 'No_Conn_TP_MGTTXN1_117' U2- # 117 H4 NET 'No_Conn_TP_MGTTXP2_117' U2- # 117 G1 NET 'No_Conn_TP_MGTTXN2_117' U2- # 117 G2 NET 'No_Conn_TP_MGTTXP3_117' U2- # 117 F3 NET 'No_Conn_TP_MGTTXN3_117' U2- # 117 F4 # All Tramsmitter Channels from MGT Quad 118 are unused NET 'No_Conn_TP_MGTTXP0_118' U2- # 118 E1 NET 'No_Conn_TP_MGTTXN0_118' U2- # 118 E2 NET 'No_Conn_TP_MGTTXP1_118' U2- # 118 D3 NET 'No_Conn_TP_MGTTXN1_118' U2- # 118 D4 NET 'No_Conn_TP_MGTTXP2_118' U2- # 118 C1 NET 'No_Conn_TP_MGTTXN2_118' U2- # 118 C2 NET 'No_Conn_TP_MGTTXP3_118' U2- # 118 B3 NET 'No_Conn_TP_MGTTXN3_118' U2- # 118 B4 ############################################################################################ # # CMX Net-to-Resource File for the # TP Function FPGA IO signals used for all unused and Not Connected Select IO pins # -=============-----------------------------------------=======================------- # # # Original Rev. 17-Jan-2013 # Rev. 17-Jan-2013 Initial roundup # Most Recent Rev. 04-Apr-2013 Remove pins now assigned to connections to Board Support FPGA, # Debug Connector, BF to TP S-Link, and TTC signals. # # Signal Nets referenced in this file: # ------------------------------------ # # 'No_Conn_TP_xxxx' are the unique net names assigned to these Select IO signals # where "xxxx" is the fpga Select IO signal name # ############################################################################################ # Unused pins from IO bank 12 ############################# # note: This bank is otherwise used for TTC connections NET 'No_Conn_TP_IO_L9P_MRCC_12' U2- # 12 AN35 NET 'No_Conn_TP_IO_L9N_MRCC_12' U2- # 12 AN36 NET 'No_Conn_TP_IO_L10N_MRCC_12' U2- # 12 AP35 NET 'No_Conn_TP_IO_L10P_MRCC_12' U2- # 12 AP36 NET 'No_Conn_TP_IO_L2P_12' U2- # 12 AP37 NET 'No_Conn_TP_IO_L12P_VRN_12' U2- # 12 AR35 NET 'No_Conn_TP_IO_L2N_12' U2- # 12 AR37 NET 'No_Conn_TP_IO_L0N_12' U2- # 12 AR38 NET 'No_Conn_TP_IO_L16N_12' U2- # 12 AT34 NET 'No_Conn_TP_IO_L12N_VRP_12' U2- # 12 AT35 NET 'No_Conn_TP_IO_L6N_12' U2- # 12 AT36 NET 'No_Conn_TP_IO_L0P_12' U2- # 12 AT37 NET 'No_Conn_TP_IO_L16P_12' U2- # 12 AU34 NET 'No_Conn_TP_IO_L6P_12' U2- # 12 AU36 NET 'No_Conn_TP_IO_L4P_12' U2- # 12 AU37 NET 'No_Conn_TP_IO_L4N_VREF_12' U2- # 12 AU38 NET 'No_Conn_TP_IO_L18P_12' U2- # 12 AV34 NET 'No_Conn_TP_IO_L18N_12' U2- # 12 AV35 NET 'No_Conn_TP_IO_L14N_VREF_12' U2- # 12 AV36 NET 'No_Conn_TP_IO_L1N_12' U2- # 12 AV38 NET 'No_Conn_TP_IO_L1P_12' U2- # 12 AV39 NET 'No_Conn_TP_IO_L19N_12' U2- # 12 AW35 NET 'No_Conn_TP_IO_L14P_12' U2- # 12 AW36 NET 'No_Conn_TP_IO_L8P_SRCC_12' U2- # 12 AW37 NET 'No_Conn_TP_IO_L8N_SRCC_12' U2- # 12 AW38 NET 'No_Conn_TP_IO_L19P_12' U2- # 12 AY34 NET 'No_Conn_TP_IO_L17N_12' U2- # 12 AY35 NET 'No_Conn_TP_IO_L5N_12' U2- # 12 AY37 # Unused pins from IO bank 13 ############################# # note: This bank is otherwise used for TTC connections NET 'No_Conn_TP_IO_L9N_MRCC_13' U2- # 13 AK34 NET 'No_Conn_TP_IO_L18P_13' U2- # 13 AK35 NET 'No_Conn_TP_IO_L9P_MRCC_13' U2- # 13 AL34 NET 'No_Conn_TP_IO_L6N_13' U2- # 13 AL35 NET 'No_Conn_TP_IO_L18N_13' U2- # 13 AL36 NET 'No_Conn_TP_IO_L4P_13' U2- # 13 AL37 NET 'No_Conn_TP_IO_L6P_13' U2- # 13 AM34 NET 'No_Conn_TP_IO_L16N_13' U2- # 13 AM36 NET 'No_Conn_TP_IO_L16P_13' U2- # 13 AM37 NET 'No_Conn_TP_IO_L4N_VREF_13' U2- # 13 AM38 NET 'No_Conn_TP_IO_L12P_VRN_13' U2- # 13 AN38 NET 'No_Conn_TP_IO_L2P_13' U2- # 13 AN39 NET 'No_Conn_TP_IO_L12N_VRP_13' U2- # 13 AP38 NET 'No_Conn_TP_IO_L14N_VREF_13' U2- # 13 AT39 # Unused pins from IO bank 14 ############################# # note: This bank is otherwise used for TTC connections NET 'No_Conn_TP_IO_L18P_14' U2- # 14 AF32 NET 'No_Conn_TP_IO_L0N_14' U2- # 14 AF34 NET 'No_Conn_TP_IO_L16P_14' U2- # 14 AF35 NET 'No_Conn_TP_IO_L16N_14' U2- # 14 AF36 NET 'No_Conn_TP_IO_L6P_14' U2- # 14 AF37 NET 'No_Conn_TP_IO_L2P_14' U2- # 14 AF39 NET 'No_Conn_TP_IO_L1P_14' U2- # 14 AF40 NET 'No_Conn_TP_IO_L18N_14' U2- # 14 AG33 NET 'No_Conn_TP_IO_L0P_14' U2- # 14 AG34 NET 'No_Conn_TP_IO_L14P_14' U2- # 14 AG36 NET 'No_Conn_TP_IO_L6N_14' U2- # 14 AG37 NET 'No_Conn_TP_IO_L4P_14' U2- # 14 AG38 NET 'No_Conn_TP_IO_L2N_14' U2- # 14 AG39 NET 'No_Conn_TP_IO_L9P_MRCC_14' U2- # 14 AH34 NET 'No_Conn_TP_IO_L12N_VRP_14' U2- # 14 AH35 NET 'No_Conn_TP_IO_L14N_VREF_14' U2- # 14 AH36 NET 'No_Conn_TP_IO_L4N_VREF_14' U2- # 14 AH38 NET 'No_Conn_TP_IO_L11P_SRCC_14' U2- # 14 AH39 NET 'No_Conn_TP_IO_L9N_MRCC_14' U2- # 14 AJ35 NET 'No_Conn_TP_IO_L12P_VRN_14' U2- # 14 AJ36 NET 'No_Conn_TP_IO_L10P_MRCC_14' U2- # 14 AJ37 NET 'No_Conn_TP_IO_L8N_SRCC_14' U2- # 14 AJ38 NET 'No_Conn_TP_IO_L10N_MRCC_14' U2- # 14 AK37 NET 'No_Conn_TP_IO_L8P_SRCC_14' U2- # 14 AK38 NET 'No_Conn_TP_IO_L19N_14' U2- # 14 AL39 # Unused pins from IO bank 15 ############################# # note: some pins from this bank are used for the On-Card Bus NET 'No_Conn_TP_IO_L12P_SM13P_15' U2- # 15 AB32 NET 'No_Conn_TP_IO_L12N_SM13N_15' U2- # 15 AB33 NET 'No_Conn_TP_IO_L16N_VRP_15' U2- # 15 AB34 NET 'No_Conn_TP_IO_L8N_SRCC_15' U2- # 15 AB36 NET 'No_Conn_TP_IO_L1P_15' U2- # 15 AB37 NET 'No_Conn_TP_IO_L18N_15' U2- # 15 AC33 NET 'No_Conn_TP_IO_L18P_15' U2- # 15 AC34 NET 'No_Conn_TP_IO_L16P_VRN_15' U2- # 15 AC35 NET 'No_Conn_TP_IO_L8P_SRCC_15' U2- # 15 AC36 NET 'No_Conn_TP_IO_L4P_15' U2- # 15 AC38 NET 'No_Conn_TP_IO_L9P_MRCC_15' U2- # 15 AD32 NET 'No_Conn_TP_IO_L2N_SM8N_15' U2- # 15 AD33 NET 'No_Conn_TP_IO_L14N_VREF_15' U2- # 15 AD35 NET 'No_Conn_TP_IO_L14P_15' U2- # 15 AD36 NET 'No_Conn_TP_IO_L10N_MRCC_15' U2- # 15 AD37 NET 'No_Conn_TP_IO_L6N_SM11N_15' U2- # 15 AD38 NET 'No_Conn_TP_IO_L9N_MRCC_15' U2- # 15 AE32 NET 'No_Conn_TP_IO_L2P_SM8P_15' U2- # 15 AE33 NET 'No_Conn_TP_IO_L0P_15' U2- # 15 AE34 NET 'No_Conn_TP_IO_L0N_15' U2- # 15 AE35 NET 'No_Conn_TP_IO_L10P_MRCC_15' U2- # 15 AE37 NET 'No_Conn_TP_IO_L6P_SM11P_15' U2- # 15 AE38 # Unused pins from IO bank 16 ############################# # note: some pins from this bank are used for the On-Card Bus NET 'No_Conn_TP_IO_L16P_16' U2- # 16 U32 NET 'No_Conn_TP_IO_L16N_16' U2- # 16 U33 NET 'No_Conn_TP_IO_L10N_MRCC_16' U2- # 16 U34 NET 'No_Conn_TP_IO_L1P_16' U2- # 16 U37 NET 'No_Conn_TP_IO_L1N_16' U2- # 16 U38 NET 'No_Conn_TP_IO_L18P_16' U2- # 16 V33 NET 'No_Conn_TP_IO_L10P_MRCC_16' U2- # 16 V34 NET 'No_Conn_TP_IO_L6N_16' U2- # 16 V35 NET 'No_Conn_TP_IO_L2N_16' U2- # 16 V36 NET 'No_Conn_TP_IO_L7P_16' U2- # 16 V38 NET 'No_Conn_TP_IO_L5N_16' U2- # 16 V39 NET 'No_Conn_TP_IO_L18N_16' U2- # 16 W33 NET 'No_Conn_TP_IO_L6P_16' U2- # 16 W35 NET 'No_Conn_TP_IO_L2P_16' U2- # 16 W36 NET 'No_Conn_TP_IO_L0P_16' U2- # 16 W37 NET 'No_Conn_TP_IO_L12N_VRP_16' U2- # 16 Y32 NET 'No_Conn_TP_IO_L9N_MRCC_16' U2- # 16 Y33 NET 'No_Conn_TP_IO_L14N_VREF_16' U2- # 16 Y34 NET 'No_Conn_TP_IO_L8N_SRCC_16' U2- # 16 Y35 NET 'No_Conn_TP_IO_L0N_16' U2- # 16 Y37 NET 'No_Conn_TP_IO_L19P_16' U2- # 16 Y38 NET 'No_Conn_TP_IO_L12P_VRN_16' U2- # 16 AA32 NET 'No_Conn_TP_IO_L14P_16' U2- # 16 AA34 NET 'No_Conn_TP_IO_L8P_SRCC_16' U2- # 16 AA35 NET 'No_Conn_TP_IO_L4P_16' U2- # 16 AA36 NET 'No_Conn_TP_IO_L4N_VREF_16' U2- # 16 AA37 # Unused pins from IO bank 17 ############################# # note: some pins from this bank are used for the On-Card Bus NET 'No_Conn_TP_IO_L1P_17' U2- # 17 L39 NET 'No_Conn_TP_IO_L0P_17' U2- # 17 M36 NET 'No_Conn_TP_IO_L0N_17' U2- # 17 M37 NET 'No_Conn_TP_IO_L2P_17' U2- # 17 M38 NET 'No_Conn_TP_IO_L4N_VREF_17' U2- # 17 N34 NET 'No_Conn_TP_IO_L4P_17' U2- # 17 N35 NET 'No_Conn_TP_IO_L6P_17' U2- # 17 N36 NET 'No_Conn_TP_IO_L5P_17' U2- # 17 N38 NET 'No_Conn_TP_IO_L5N_17' U2- # 17 N39 NET 'No_Conn_TP_IO_L9N_MRCC_17' U2- # 17 P35 NET 'No_Conn_TP_IO_L9P_MRCC_17' U2- # 17 P36 NET 'No_Conn_TP_IO_L6N_17' U2- # 17 P37 NET 'No_Conn_TP_IO_L8N_SRCC_17' U2- # 17 P38 NET 'No_Conn_TP_IO_L14N_VREF_17' U2- # 17 R34 NET 'No_Conn_TP_IO_L14P_17' U2- # 17 R35 NET 'No_Conn_TP_IO_L12P_VRN_17' U2- # 17 R37 NET 'No_Conn_TP_IO_L10N_MRCC_17' U2- # 17 R38 NET 'No_Conn_TP_IO_L18P_17' U2- # 17 T34 NET 'No_Conn_TP_IO_L18N_17' U2- # 17 T35 NET 'No_Conn_TP_IO_L16N_17' U2- # 17 T36 NET 'No_Conn_TP_IO_L12N_VRP_17' U2- # 17 T37 NET 'No_Conn_TP_IO_L10P_MRCC_17' U2- # 17 T39 NET 'No_Conn_TP_IO_L16P_17' U2- # 17 U36 # Unused pins from IO bank 21 ############################# NET 'No_Conn_TP_IO_L1N_21' U2- # 21 AJ22 NET 'No_Conn_TP_IO_L5P_21' U2- # 21 AJ23 NET 'No_Conn_TP_IO_L1P_21' U2- # 21 AK22 NET 'No_Conn_TP_IO_L5N_21' U2- # 21 AK23 NET 'No_Conn_TP_IO_L10P_MRCC_21' U2- # 21 AK24 NET 'No_Conn_TP_IO_L3N_21' U2- # 21 AL22 NET 'No_Conn_TP_IO_L13N_21' U2- # 21 AL24 NET 'No_Conn_TP_IO_L10N_MRCC_21' U2- # 21 AL25 NET 'No_Conn_TP_IO_L3P_21' U2- # 21 AM22 NET 'No_Conn_TP_IO_L7P_21' U2- # 21 AM23 NET 'No_Conn_TP_IO_L13P_21' U2- # 21 AM24 NET 'No_Conn_TP_IO_L7N_21' U2- # 21 AN23 NET 'No_Conn_TP_IO_L15P_21' U2- # 21 AN24 NET 'No_Conn_TP_IO_L15N_21' U2- # 21 AN25 NET 'No_Conn_TP_IO_L11P_SRCC_21' U2- # 21 AP23 NET 'No_Conn_TP_IO_L9P_MRCC_21' U2- # 21 AP25 NET 'No_Conn_TP_IO_L9N_MRCC_21' U2- # 21 AP26 NET 'No_Conn_TP_IO_L11N_SRCC_21' U2- # 21 AR23 NET 'No_Conn_TP_IO_L17P_21' U2- # 21 AR24 NET 'No_Conn_TP_IO_L19N_21' U2- # 21 AR25 NET 'No_Conn_TP_IO_L17N_21' U2- # 21 AT24 NET 'No_Conn_TP_IO_L19P_21' U2- # 21 AT25 NET 'No_Conn_TP_IO_L0P_21' U2- # 21 AT26 NET 'No_Conn_TP_IO_L8P_SRCC_21' U2- # 21 AU23 NET 'No_Conn_TP_IO_L8N_SRCC_21' U2- # 21 AU24 NET 'No_Conn_TP_IO_L16N_21' U2- # 21 AU26 NET 'No_Conn_TP_IO_L0N_21' U2- # 21 AU27 NET 'No_Conn_TP_IO_L12P_VRN_21' U2- # 21 AV24 NET 'No_Conn_TP_IO_L12N_VRP_21' U2- # 21 AV25 NET 'No_Conn_TP_IO_L16P_21' U2- # 21 AV26 NET 'No_Conn_TP_IO_L18P_21' U2- # 21 AW25 NET 'No_Conn_TP_IO_L18N_21' U2- # 21 AW26 NET 'No_Conn_TP_IO_L2N_21' U2- # 21 AW27 NET 'No_Conn_TP_IO_L14N_VREF_21' U2- # 21 AY25 NET 'No_Conn_TP_IO_L2P_21' U2- # 21 AY27 NET 'No_Conn_TP_IO_L14P_21' U2- # 21 BA25 NET 'No_Conn_TP_IO_L4P_21' U2- # 21 BA26 NET 'No_Conn_TP_IO_L4N_VREF_21' U2- # 21 BA27 NET 'No_Conn_TP_IO_L6P_21' U2- # 21 BB26 NET 'No_Conn_TP_IO_L6N_21' U2- # 21 BB27 # Unused pins from IO bank 22 ############################# NET 'No_Conn_TP_IO_L9N_MRCC_22' U2- # 22 AL26 NET 'No_Conn_TP_IO_L9P_MRCC_22' U2- # 22 AM26 NET 'No_Conn_TP_IO_L10N_MRCC_22' U2- # 22 AM27 NET 'No_Conn_TP_IO_L1P_22' U2- # 22 AN26 NET 'No_Conn_TP_IO_L10P_MRCC_22' U2- # 22 AN28 NET 'No_Conn_TP_IO_L1N_22' U2- # 22 AP27 NET 'No_Conn_TP_IO_L3N_22' U2- # 22 AP28 NET 'No_Conn_TP_IO_L11P_SRCC_22' U2- # 22 AR27 NET 'No_Conn_TP_IO_L3P_22' U2- # 22 AR28 NET 'No_Conn_TP_IO_L5N_22' U2- # 22 AR29 NET 'No_Conn_TP_IO_L7N_22' U2- # 22 AR30 NET 'No_Conn_TP_IO_L11N_SRCC_22' U2- # 22 AT27 NET 'No_Conn_TP_IO_L5P_22' U2- # 22 AT29 NET 'No_Conn_TP_IO_L7P_22' U2- # 22 AT30 NET 'No_Conn_TP_IO_L13P_22' U2- # 22 AT31 NET 'No_Conn_TP_IO_L17P_22' U2- # 22 AU28 NET 'No_Conn_TP_IO_L15P_22' U2- # 22 AU29 NET 'No_Conn_TP_IO_L13N_22' U2- # 22 AU31 NET 'No_Conn_TP_IO_L17N_22' U2- # 22 AV28 NET 'No_Conn_TP_IO_L15N_22' U2- # 22 AV29 NET 'No_Conn_TP_IO_L0N_22' U2- # 22 AV30 NET 'No_Conn_TP_IO_L2N_22' U2- # 22 AV31 NET 'No_Conn_TP_IO_L19P_22' U2- # 22 AW28 NET 'No_Conn_TP_IO_L0P_22' U2- # 22 AW30 NET 'No_Conn_TP_IO_L2P_22' U2- # 22 AW31 NET 'No_Conn_TP_IO_L4N_VREF_22' U2- # 22 AW32 NET 'No_Conn_TP_IO_L19N_22' U2- # 22 AY28 NET 'No_Conn_TP_IO_L12P_VRN_22' U2- # 22 AY29 NET 'No_Conn_TP_IO_L8N_SRCC_22' U2- # 22 AY30 NET 'No_Conn_TP_IO_L4P_22' U2- # 22 AY32 NET 'No_Conn_TP_IO_L6N_22' U2- # 22 AY33 NET 'No_Conn_TP_IO_L12N_VRP_22' U2- # 22 BA29 NET 'No_Conn_TP_IO_L8P_SRCC_22' U2- # 22 BA30 NET 'No_Conn_TP_IO_L16P_22' U2- # 22 BA31 NET 'No_Conn_TP_IO_L6P_22' U2- # 22 BA32 NET 'No_Conn_TP_IO_L18N_22' U2- # 22 BB28 NET 'No_Conn_TP_IO_L18P_22' U2- # 22 BB29 NET 'No_Conn_TP_IO_L16N_22' U2- # 22 BB31 NET 'No_Conn_TP_IO_L14N_VREF_22' U2- # 22 BB32 NET 'No_Conn_TP_IO_L14P_22' U2- # 22 BB33 # Unused pins from IO bank 23 ############################# NET 'No_Conn_TP_IO_L14N_VREF_23' U2- # 23 AG27 NET 'No_Conn_TP_IO_L14P_23' U2- # 23 AG28 NET 'No_Conn_TP_IO_L10P_MRCC_23' U2- # 23 AH24 NET 'No_Conn_TP_IO_L10N_MRCC_23' U2- # 23 AH25 NET 'No_Conn_TP_IO_L18N_23' U2- # 23 AH26 NET 'No_Conn_TP_IO_L12P_VRN_23' U2- # 23 AH28 NET 'No_Conn_TP_IO_L9P_MRCC_23' U2- # 23 AJ25 NET 'No_Conn_TP_IO_L18P_23' U2- # 23 AJ26 NET 'No_Conn_TP_IO_L16N_23' U2- # 23 AJ27 NET 'No_Conn_TP_IO_L12N_VRP_23' U2- # 23 AJ28 NET 'No_Conn_TP_IO_L9N_MRCC_23' U2- # 23 AK25 NET 'No_Conn_TP_IO_L16P_23' U2- # 23 AK27 NET 'No_Conn_TP_IO_L8P_SRCC_23' U2- # 23 AK28 NET 'No_Conn_TP_IO_L8N_SRCC_23' U2- # 23 AK29 NET 'No_Conn_TP_IO_L6P_23' U2- # 23 AL27 NET 'No_Conn_TP_IO_L2P_23' U2- # 23 AL29 NET 'No_Conn_TP_IO_L2N_23' U2- # 23 AL30 NET 'No_Conn_TP_IO_L1N_23' U2- # 23 AL31 NET 'No_Conn_TP_IO_L6N_23' U2- # 23 AM28 NET 'No_Conn_TP_IO_L4N_VREF_23' U2- # 23 AM29 NET 'No_Conn_TP_IO_L1P_23' U2- # 23 AM31 NET 'No_Conn_TP_IO_L3N_23' U2- # 23 AM32 NET 'No_Conn_TP_IO_L3P_23' U2- # 23 AM33 NET 'No_Conn_TP_IO_L4P_23' U2- # 23 AN29 NET 'No_Conn_TP_IO_L0N_23' U2- # 23 AN30 NET 'No_Conn_TP_IO_L7N_23' U2- # 23 AN31 NET 'No_Conn_TP_IO_L5P_23' U2- # 23 AN33 NET 'No_Conn_TP_IO_L5N_23' U2- # 23 AN34 NET 'No_Conn_TP_IO_L0P_23' U2- # 23 AP30 NET 'No_Conn_TP_IO_L7P_23' U2- # 23 AP31 NET 'No_Conn_TP_IO_L13P_23' U2- # 23 AP32 NET 'No_Conn_TP_IO_L11N_SRCC_23' U2- # 23 AP33 NET 'No_Conn_TP_IO_L13N_23' U2- # 23 AR32 NET 'No_Conn_TP_IO_L15P_23' U2- # 23 AR33 NET 'No_Conn_TP_IO_L11P_SRCC_23' U2- # 23 AR34 NET 'No_Conn_TP_IO_L15N_23' U2- # 23 AT32 NET 'No_Conn_TP_IO_L17N_23' U2- # 23 AU32 NET 'No_Conn_TP_IO_L17P_23' U2- # 23 AU33 NET 'No_Conn_TP_IO_L19P_23' U2- # 23 AV33 NET 'No_Conn_TP_IO_L19N_23' U2- # 23 AW33 # Unused pins from IO bank 24 ############################# NET 'No_Conn_TP_IO_L5P_D9_24' U2- # 24 N33 NET 'No_Conn_TP_IO_L7P_D5_24' U2- # 24 P32 NET 'No_Conn_TP_IO_L5N_D8_24' U2- # 24 P33 NET 'No_Conn_TP_IO_L3N_D12_24' U2- # 24 R30 NET 'No_Conn_TP_IO_L11P_SRCC_24' U2- # 24 R32 NET 'No_Conn_TP_IO_L7N_D4_24' U2- # 24 R33 NET 'No_Conn_TP_IO_L3P_D13_24' U2- # 24 T30 NET 'No_Conn_TP_IO_L13P_D1_FS1_24' U2- # 24 T31 NET 'No_Conn_TP_IO_L11N_SRCC_24' U2- # 24 T32 NET 'No_Conn_TP_IO_L13N_D0_FS0_24' U2- # 24 U31 NET 'No_Conn_TP_IO_L1N_GC_24' U2- # 24 V30 NET 'No_Conn_TP_IO_L15P_FWE_B_24' U2- # 24 V31 NET 'No_Conn_TP_IO_L1P_GC_24' U2- # 24 W30 NET 'No_Conn_TP_IO_L15N_RS1_24' U2- # 24 W31 NET 'No_Conn_TP_IO_L9P_MRCC_24' U2- # 24 Y30 NET 'No_Conn_TP_IO_L9N_MRCC_24' U2- # 24 AA30 NET 'No_Conn_TP_IO_L10P_MRCC_24' U2- # 24 AA31 NET 'No_Conn_TP_IO_L10N_MRCC_24' U2- # 24 AB31 NET 'No_Conn_TP_IO_L17N_VRP_24' U2- # 24 AC30 NET 'No_Conn_TP_IO_L17P_VRN_24' U2- # 24 AC31 NET 'No_Conn_TP_IO_L19N_24' U2- # 24 AD30 NET 'No_Conn_TP_IO_L19P_24' U2- # 24 AD31 NET 'No_Conn_TP_IO_L0P_GC_24' U2- # 24 AE30 NET 'No_Conn_TP_IO_L0N_GC_24' U2- # 24 AF30 NET 'No_Conn_TP_IO_L2N_D14_24' U2- # 24 AF31 NET 'No_Conn_TP_IO_L18N_24' U2- # 24 AG29 NET 'No_Conn_TP_IO_L4N_VREF_D10_24' U2- # 24 AG31 NET 'No_Conn_TP_IO_L2P_D15_24' U2- # 24 AG32 NET 'No_Conn_TP_IO_L18P_24' U2- # 24 AH29 NET 'No_Conn_TP_IO_L14P_FCS_B_24' U2- # 24 AH30 NET 'No_Conn_TP_IO_L4P_D11_24' U2- # 24 AH31 NET 'No_Conn_TP_IO_L6N_D6_24' U2- # 24 AH33 NET 'No_Conn_TP_IO_L14N_VREF_FOE_B_MOSI_24' U2- # 24 AJ30 NET 'No_Conn_TP_IO_L16P_RS0_24' U2- # 24 AJ31 NET 'No_Conn_TP_IO_L8N_SRCC_24' U2- # 24 AJ32 NET 'No_Conn_TP_IO_L6P_D7_24' U2- # 24 AJ33 NET 'No_Conn_TP_IO_L16N_CSO_B_24' U2- # 24 AK30 NET 'No_Conn_TP_IO_L12P_D3_24' U2- # 24 AK32 NET 'No_Conn_TP_IO_L8P_SRCC_24' U2- # 24 AK33 NET 'No_Conn_TP_IO_L12N_D2_FS2_24' U2- # 24 AL32 # Unused pins from IO bank 25 ############################# # note: 2 pins from this bank are used for the 40 MHz Logic Clock NET 'No_Conn_TP_IO_L6N_25' U2- # 25 H38 NET 'No_Conn_TP_IO_L6P_25' U2- # 25 H39 NET 'No_Conn_TP_IO_L12P_25' U2- # 25 H40 NET 'No_Conn_TP_IO_L12N_25' U2- # 25 H41 NET 'No_Conn_TP_IO_L4N_VREF_25' U2- # 25 J36 NET 'No_Conn_TP_IO_L4P_25' U2- # 25 J37 NET 'No_Conn_TP_IO_L8N_SRCC_25' U2- # 25 J38 NET 'No_Conn_TP_IO_L14P_25' U2- # 25 J40 NET 'No_Conn_TP_IO_L14N_VREF_25' U2- # 25 J41 NET 'No_Conn_TP_IO_L0N_25' U2- # 25 K32 NET 'No_Conn_TP_IO_L0P_25' U2- # 25 K33 NET 'No_Conn_TP_IO_L2N_25' U2- # 25 K34 NET 'No_Conn_TP_IO_L2P_25' U2- # 25 K35 NET 'No_Conn_TP_IO_L11P_SRCC_25' U2- # 25 K37 NET 'No_Conn_TP_IO_L8P_SRCC_25' U2- # 25 K38 NET 'No_Conn_TP_IO_L16P_VRN_25' U2- # 25 K39 NET 'No_Conn_TP_IO_L16N_VRP_25' U2- # 25 K40 NET 'No_Conn_TP_IO_L3P_25' U2- # 25 L31 NET 'No_Conn_TP_IO_L3N_25' U2- # 25 L32 NET 'No_Conn_TP_IO_L13P_25' U2- # 25 L34 NET 'No_Conn_TP_IO_L7P_25' U2- # 25 L35 NET 'No_Conn_TP_IO_L7N_25' U2- # 25 L36 NET 'No_Conn_TP_IO_L11N_SRCC_25' U2- # 25 L37 NET 'No_Conn_TP_IO_L17P_25' U2- # 25 M31 NET 'No_Conn_TP_IO_L15N_25' U2- # 25 M32 NET 'No_Conn_TP_IO_L15P_25' U2- # 25 M33 NET 'No_Conn_TP_IO_L13N_25' U2- # 25 M34 NET 'No_Conn_TP_IO_L1P_25' U2- # 25 N28 NET 'No_Conn_TP_IO_L5P_25' U2- # 25 N29 NET 'No_Conn_TP_IO_L5N_25' U2- # 25 N30 NET 'No_Conn_TP_IO_L17N_25' U2- # 25 N31 NET 'No_Conn_TP_IO_L9P_MRCC_25' U2- # 25 P27 NET 'No_Conn_TP_IO_L1N_25' U2- # 25 P28 NET 'No_Conn_TP_IO_L19P_GC_25' U2- # 25 P30 NET 'No_Conn_TP_IO_L19N_GC_25' U2- # 25 P31 NET 'No_Conn_TP_IO_L9N_MRCC_25' U2- # 25 R27 NET 'No_Conn_TP_IO_L10P_MRCC_25' U2- # 25 R28 NET 'No_Conn_TP_IO_L10N_MRCC_25' U2- # 25 R29 # Unused pins from IO bank 26 ############################# # note: this bank is otherwise used for BF to TP S-link connection, and Debug connector connections NET 'No_Conn_TP_IO_L5N_26' U2- # 26 C39 NET 'No_Conn_TP_IO_L6P_26' U2- # 26 D38 NET 'No_Conn_TP_IO_L17P_26' U2- # 26 D40 NET 'No_Conn_TP_IO_L4N_VREF_26' U2- # 26 E37 NET 'No_Conn_TP_IO_L8N_SRCC_26' U2- # 26 E38 NET 'No_Conn_TP_IO_L8P_SRCC_26' U2- # 26 E39 NET 'No_Conn_TP_IO_L10P_MRCC_26' U2- # 26 F35 NET 'No_Conn_TP_IO_L10N_MRCC_26' U2- # 26 F36 NET 'No_Conn_TP_IO_L4P_26' U2- # 26 F37 NET 'No_Conn_TP_IO_L12P_VRN_26' U2- # 26 F39 NET 'No_Conn_TP_IO_L16P_26' U2- # 26 F40 NET 'No_Conn_TP_IO_L9P_MRCC_26' U2- # 26 G34 NET 'No_Conn_TP_IO_L0N_26' U2- # 26 G36 NET 'No_Conn_TP_IO_L14P_26' U2- # 26 G37 NET 'No_Conn_TP_IO_L14N_VREF_26' U2- # 26 G38 NET 'No_Conn_TP_IO_L12N_VRP_26' U2- # 26 G39 NET 'No_Conn_TP_IO_L9N_MRCC_26' U2- # 26 H34 NET 'No_Conn_TP_IO_L2N_26' U2- # 26 H35 NET 'No_Conn_TP_IO_L0P_26' U2- # 26 H36 NET 'No_Conn_TP_IO_L2P_26' U2- # 26 J35 # Unused pins from IO bank 27 ############################# # note: this bank is otherwise used for TP to BSPT connections NET 'No_Conn_TP_IO_L3N_27' U2- # 27 C33 NET 'No_Conn_TP_IO_L7N_27' U2- # 27 C34 NET 'No_Conn_TP_IO_L15N_27' U2- # 27 C36 NET 'No_Conn_TP_IO_L0N_27' U2- # 27 D32 NET 'No_Conn_TP_IO_L11P_SRCC_27' U2- # 27 D33 NET 'No_Conn_TP_IO_L4N_VREF_27' U2- # 27 D35 NET 'No_Conn_TP_IO_L19P_27' U2- # 27 D36 NET 'No_Conn_TP_IO_L19N_27' U2- # 27 D37 NET 'No_Conn_TP_IO_L0P_27' U2- # 27 E32 NET 'No_Conn_TP_IO_L11N_SRCC_27' U2- # 27 E33 NET 'No_Conn_TP_IO_L17P_27' U2- # 27 E34 NET 'No_Conn_TP_IO_L4P_27' U2- # 27 E35 NET 'No_Conn_TP_IO_L2N_27' U2- # 27 F31 NET 'No_Conn_TP_IO_L2P_27' U2- # 27 F32 NET 'No_Conn_TP_IO_L17N_27' U2- # 27 F34 NET 'No_Conn_TP_IO_L6N_27' U2- # 27 G31 NET 'No_Conn_TP_IO_L8N_SRCC_27' U2- # 27 G32 NET 'No_Conn_TP_IO_L8P_SRCC_27' U2- # 27 G33 NET 'No_Conn_TP_IO_L16P_27' U2- # 27 H30 NET 'No_Conn_TP_IO_L6P_27' U2- # 27 H31 NET 'No_Conn_TP_IO_L12P_VRN_27' U2- # 27 H33 NET 'No_Conn_TP_IO_L16N_27' U2- # 27 J30 NET 'No_Conn_TP_IO_L14N_VREF_27' U2- # 27 J31 NET 'No_Conn_TP_IO_L14P_27' U2- # 27 J32 NET 'No_Conn_TP_IO_L12N_VRP_27' U2- # 27 J33 NET 'No_Conn_TP_IO_L18P_27' U2- # 27 K29 NET 'No_Conn_TP_IO_L18N_27' U2- # 27 K30 NET 'No_Conn_TP_IO_L9P_MRCC_27' U2- # 27 L29 NET 'No_Conn_TP_IO_L9N_MRCC_27' U2- # 27 L30 NET 'No_Conn_TP_IO_L10P_MRCC_27' U2- # 27 M28 NET 'No_Conn_TP_IO_L10N_MRCC_27' U2- # 27 M29 # Unused pins from IO bank 28 ############################# NET 'No_Conn_TP_IO_L17P_28' U2- # 28 A29 NET 'No_Conn_TP_IO_L17N_28' U2- # 28 A30 NET 'No_Conn_TP_IO_L13P_28' U2- # 28 A31 NET 'No_Conn_TP_IO_L15P_28' U2- # 28 B29 NET 'No_Conn_TP_IO_L13N_28' U2- # 28 B31 NET 'No_Conn_TP_IO_L15N_28' U2- # 28 C29 NET 'No_Conn_TP_IO_L7P_28' U2- # 28 C30 NET 'No_Conn_TP_IO_L5P_28' U2- # 28 C31 NET 'No_Conn_TP_IO_L1P_28' U2- # 28 D28 NET 'No_Conn_TP_IO_L7N_28' U2- # 28 D30 NET 'No_Conn_TP_IO_L5N_28' U2- # 28 D31 NET 'No_Conn_TP_IO_L11N_SRCC_28' U2- # 28 E28 NET 'No_Conn_TP_IO_L1N_28' U2- # 28 E29 NET 'No_Conn_TP_IO_L3P_28' U2- # 28 E30 NET 'No_Conn_TP_IO_L11P_SRCC_28' U2- # 28 F27 NET 'No_Conn_TP_IO_L4N_VREF_28' U2- # 28 F29 NET 'No_Conn_TP_IO_L3N_28' U2- # 28 F30 NET 'No_Conn_TP_IO_L2N_28' U2- # 28 G27 NET 'No_Conn_TP_IO_L2P_28' U2- # 28 G28 NET 'No_Conn_TP_IO_L4P_28' U2- # 28 G29 NET 'No_Conn_TP_IO_L14P_28' U2- # 28 H28 NET 'No_Conn_TP_IO_L14N_VREF_28' U2- # 28 H29 NET 'No_Conn_TP_IO_L0N_28' U2- # 28 J26 NET 'No_Conn_TP_IO_L0P_28' U2- # 28 J27 NET 'No_Conn_TP_IO_L16P_28' U2- # 28 J28 NET 'No_Conn_TP_IO_L18N_28' U2- # 28 K27 NET 'No_Conn_TP_IO_L16N_28' U2- # 28 K28 NET 'No_Conn_TP_IO_L9N_MRCC_28' U2- # 28 L25 NET 'No_Conn_TP_IO_L9P_MRCC_28' U2- # 28 L26 NET 'No_Conn_TP_IO_L18P_28' U2- # 28 L27 NET 'No_Conn_TP_IO_L19P_28' U2- # 28 M26 NET 'No_Conn_TP_IO_L19N_28' U2- # 28 M27 NET 'No_Conn_TP_IO_L10P_MRCC_28' U2- # 28 N24 NET 'No_Conn_TP_IO_L10N_MRCC_28' U2- # 28 N25 NET 'No_Conn_TP_IO_L12N_VRP_28' U2- # 28 N26 NET 'No_Conn_TP_IO_L6N_28' U2- # 28 P23 NET 'No_Conn_TP_IO_L8N_SRCC_28' U2- # 28 P25 NET 'No_Conn_TP_IO_L12P_VRN_28' U2- # 28 P26 NET 'No_Conn_TP_IO_L6P_28' U2- # 28 R23 NET 'No_Conn_TP_IO_L8P_SRCC_28' U2- # 28 R25 # Unused pins from IO bank 32 ############################# NET 'No_Conn_TP_IO_L9N_MRCC_32' U2- # 32 AJ20 NET 'No_Conn_TP_IO_L9P_MRCC_32' U2- # 32 AJ21 NET 'No_Conn_TP_IO_L10N_MRCC_32' U2- # 32 AK19 NET 'No_Conn_TP_IO_L10P_MRCC_32' U2- # 32 AK20 NET 'No_Conn_TP_IO_L1P_32' U2- # 32 AL19 NET 'No_Conn_TP_IO_L5P_32' U2- # 32 AL20 NET 'No_Conn_TP_IO_L5N_32' U2- # 32 AL21 NET 'No_Conn_TP_IO_L1N_32' U2- # 32 AM19 NET 'No_Conn_TP_IO_L11P_SRCC_32' U2- # 32 AM21 NET 'No_Conn_TP_IO_L7P_32' U2- # 32 AN20 NET 'No_Conn_TP_IO_L11N_SRCC_32' U2- # 32 AN21 NET 'No_Conn_TP_IO_L7N_32' U2- # 32 AP20 NET 'No_Conn_TP_IO_L19P_32' U2- # 32 AP21 NET 'No_Conn_TP_IO_L19N_32' U2- # 32 AP22 NET 'No_Conn_TP_IO_L3N_32' U2- # 32 AR20 NET 'No_Conn_TP_IO_L17N_32' U2- # 32 AR22 NET 'No_Conn_TP_IO_L3P_32' U2- # 32 AT20 NET 'No_Conn_TP_IO_L15N_32' U2- # 32 AT21 NET 'No_Conn_TP_IO_L17P_32' U2- # 32 AT22 NET 'No_Conn_TP_IO_L15P_32' U2- # 32 AU21 NET 'No_Conn_TP_IO_L2N_32' U2- # 32 AU22 NET 'No_Conn_TP_IO_L13P_32' U2- # 32 AV20 NET 'No_Conn_TP_IO_L12P_VRN_32' U2- # 32 AV21 NET 'No_Conn_TP_IO_L2P_32' U2- # 32 AV23 NET 'No_Conn_TP_IO_L13N_32' U2- # 32 AW20 NET 'No_Conn_TP_IO_L12N_VRP_32' U2- # 32 AW21 NET 'No_Conn_TP_IO_L16P_32' U2- # 32 AW22 NET 'No_Conn_TP_IO_L4P_32' U2- # 32 AW23 NET 'No_Conn_TP_IO_L8P_SRCC_32' U2- # 32 AY20 NET 'No_Conn_TP_IO_L16N_32' U2- # 32 AY22 NET 'No_Conn_TP_IO_L4N_VREF_32' U2- # 32 AY23 NET 'No_Conn_TP_IO_L0P_32' U2- # 32 AY24 NET 'No_Conn_TP_IO_L8N_SRCC_32' U2- # 32 BA20 NET 'No_Conn_TP_IO_L14N_VREF_32' U2- # 32 BA21 NET 'No_Conn_TP_IO_L14P_32' U2- # 32 BA22 NET 'No_Conn_TP_IO_L0N_32' U2- # 32 BA24 NET 'No_Conn_TP_IO_L18N_32' U2- # 32 BB21 NET 'No_Conn_TP_IO_L18P_32' U2- # 32 BB22 NET 'No_Conn_TP_IO_L6N_32' U2- # 32 BB23 NET 'No_Conn_TP_IO_L6P_32' U2- # 32 BB24 # Unused pins from IO bank 33 ############################# NET 'No_Conn_TP_IO_L10N_MRCC_33' U2- # 33 AJ15 NET 'No_Conn_TP_IO_L10P_MRCC_33' U2- # 33 AJ16 NET 'No_Conn_TP_IO_L6P_33' U2- # 33 AJ17 NET 'No_Conn_TP_IO_L18N_33' U2- # 33 AJ18 NET 'No_Conn_TP_IO_L9N_MRCC_33' U2- # 33 AK14 NET 'No_Conn_TP_IO_L9P_MRCC_33' U2- # 33 AK15 NET 'No_Conn_TP_IO_L6N_33' U2- # 33 AK17 NET 'No_Conn_TP_IO_L18P_33' U2- # 33 AK18 NET 'No_Conn_TP_IO_L0N_33' U2- # 33 AL14 NET 'No_Conn_TP_IO_L0P_33' U2- # 33 AL15 NET 'No_Conn_TP_IO_L4N_VREF_33' U2- # 33 AL16 NET 'No_Conn_TP_IO_L4P_33' U2- # 33 AL17 NET 'No_Conn_TP_IO_L2N_33' U2- # 33 AM14 NET 'No_Conn_TP_IO_L8N_SRCC_33' U2- # 33 AM16 NET 'No_Conn_TP_IO_L14P_33' U2- # 33 AM17 NET 'No_Conn_TP_IO_L14N_VREF_33' U2- # 33 AM18 NET 'No_Conn_TP_IO_L2P_33' U2- # 33 AN15 NET 'No_Conn_TP_IO_L8P_SRCC_33' U2- # 33 AN16 NET 'No_Conn_TP_IO_L16P_33' U2- # 33 AN18 NET 'No_Conn_TP_IO_L16N_33' U2- # 33 AN19 NET 'No_Conn_TP_IO_L12P_VRN_33' U2- # 33 AP16 NET 'No_Conn_TP_IO_L12N_VRP_33' U2- # 33 AP17 NET 'No_Conn_TP_IO_L11P_SRCC_33' U2- # 33 AP18 NET 'No_Conn_TP_IO_L1P_33' U2- # 33 AR17 NET 'No_Conn_TP_IO_L1N_33' U2- # 33 AR18 NET 'No_Conn_TP_IO_L11N_SRCC_33' U2- # 33 AR19 NET 'No_Conn_TP_IO_L3P_33' U2- # 33 AT16 NET 'No_Conn_TP_IO_L5P_33' U2- # 33 AT17 NET 'No_Conn_TP_IO_L19N_33' U2- # 33 AT19 NET 'No_Conn_TP_IO_L3N_33' U2- # 33 AU17 NET 'No_Conn_TP_IO_L5N_33' U2- # 33 AU18 NET 'No_Conn_TP_IO_L19P_33' U2- # 33 AU19 NET 'No_Conn_TP_IO_L13P_33' U2- # 33 AV18 NET 'No_Conn_TP_IO_L13N_33' U2- # 33 AV19 NET 'No_Conn_TP_IO_L7N_33' U2- # 33 AW18 NET 'No_Conn_TP_IO_L7P_33' U2- # 33 AY18 NET 'No_Conn_TP_IO_L17N_33' U2- # 33 AY19 NET 'No_Conn_TP_IO_L17P_33' U2- # 33 BA19 NET 'No_Conn_TP_IO_L15P_33' U2- # 33 BB18 NET 'No_Conn_TP_IO_L15N_33' U2- # 33 BB19 # Unused pins from IO bank 34 ############################# # note: 4 pins from this bank are used for 40MHz and 320 MHz Logic Clocks NET 'No_Conn_TP_IO_L9N_MRCC_34' U2- # 34 AM12 NET 'No_Conn_TP_IO_L9P_MRCC_34' U2- # 34 AM13 NET 'No_Conn_TP_IO_L10N_MRCC_34' U2- # 34 AN13 NET 'No_Conn_TP_IO_L10P_MRCC_34' U2- # 34 AN14 NET 'No_Conn_TP_IO_L5P_A09_D25_34' U2- # 34 AP13 NET 'No_Conn_TP_IO_L17P_A19_34' U2- # 34 AP15 NET 'No_Conn_TP_IO_L3P_A13_D29_34' U2- # 34 AR12 NET 'No_Conn_TP_IO_L5N_A08_D24_34' U2- # 34 AR13 NET 'No_Conn_TP_IO_L15P_A23_34' U2- # 34 AR14 NET 'No_Conn_TP_IO_L17N_A18_34' U2- # 34 AR15 NET 'No_Conn_TP_IO_L3N_A12_D28_34' U2- # 34 AT12 NET 'No_Conn_TP_IO_L15N_A22_34' U2- # 34 AT14 NET 'No_Conn_TP_IO_L19P_VRN_34' U2- # 34 AT15 NET 'No_Conn_TP_IO_L7P_A05_D21_34' U2- # 34 AU12 NET 'No_Conn_TP_IO_L7N_A04_D20_34' U2- # 34 AU13 NET 'No_Conn_TP_IO_L4N_VREF_A10_D26_34' U2- # 34 AU14 NET 'No_Conn_TP_IO_L19N_VRP_34' U2- # 34 AU16 NET 'No_Conn_TP_IO_L11P_SRCC_34' U2- # 34 AV13 NET 'No_Conn_TP_IO_L11N_SRCC_34' U2- # 34 AV14 NET 'No_Conn_TP_IO_L4P_A11_D27_34' U2- # 34 AV15 NET 'No_Conn_TP_IO_L8P_SRCC_34' U2- # 34 AV16 NET 'No_Conn_TP_IO_L13P_A01_D17_34' U2- # 34 AW12 NET 'No_Conn_TP_IO_L13N_A00_D16_34' U2- # 34 AW13 NET 'No_Conn_TP_IO_L6N_A06_D22_34' U2- # 34 AW15 NET 'No_Conn_TP_IO_L8N_SRCC_34' U2- # 34 AW16 NET 'No_Conn_TP_IO_L18N_A16_34' U2- # 34 AW17 NET 'No_Conn_TP_IO_L6P_A07_D23_34' U2- # 34 AY15 NET 'No_Conn_TP_IO_L18P_A17_34' U2- # 34 AY17 NET 'No_Conn_TP_IO_L2N_A14_D30_34' U2- # 34 BA14 NET 'No_Conn_TP_IO_L2P_A15_D31_34' U2- # 34 BA15 NET 'No_Conn_TP_IO_L14P_A25_34' U2- # 34 BA16 NET 'No_Conn_TP_IO_L14N_VREF_A24_34' U2- # 34 BA17 NET 'No_Conn_TP_IO_L12P_A03_D19_34' U2- # 34 BB13 NET 'No_Conn_TP_IO_L12N_A02_D18_34' U2- # 34 BB14 NET 'No_Conn_TP_IO_L16P_A21_34' U2- # 34 BB16 NET 'No_Conn_TP_IO_L16N_A20_34' U2- # 34 BB17 # Unused pins from IO bank 35 ############################# NET 'No_Conn_TP_IO_L5N_SM2N_35' U2- # 35 A14 NET 'No_Conn_TP_IO_L5P_SM2P_35' U2- # 35 A15 NET 'No_Conn_TP_IO_L1P_35' U2- # 35 A16 NET 'No_Conn_TP_IO_L13P_SM6P_35' U2- # 35 B14 NET 'No_Conn_TP_IO_L1N_35' U2- # 35 B16 NET 'No_Conn_TP_IO_L15P_SM7P_35' U2- # 35 C13 NET 'No_Conn_TP_IO_L13N_SM6N_35' U2- # 35 C14 NET 'No_Conn_TP_IO_L7P_SM4P_35' U2- # 35 C15 NET 'No_Conn_TP_IO_L3N_SM1N_35' U2- # 35 C16 NET 'No_Conn_TP_IO_L15N_SM7N_35' U2- # 35 D12 NET 'No_Conn_TP_IO_L17P_35' U2- # 35 D13 NET 'No_Conn_TP_IO_L7N_SM4N_35' U2- # 35 D15 NET 'No_Conn_TP_IO_L3P_SM1P_35' U2- # 35 D16 NET 'No_Conn_TP_IO_L0N_35' U2- # 35 E12 NET 'No_Conn_TP_IO_L17N_35' U2- # 35 E13 NET 'No_Conn_TP_IO_L19P_GC_35' U2- # 35 E14 NET 'No_Conn_TP_IO_L11P_SRCC_35' U2- # 35 E15 NET 'No_Conn_TP_IO_L0P_35' U2- # 35 F12 NET 'No_Conn_TP_IO_L19N_GC_35' U2- # 35 F14 NET 'No_Conn_TP_IO_L11N_SRCC_35' U2- # 35 F15 NET 'No_Conn_TP_IO_L6N_SM3N_35' U2- # 35 G12 NET 'No_Conn_TP_IO_L4N_VREF_35' U2- # 35 G13 NET 'No_Conn_TP_IO_L2N_SM0N_35' U2- # 35 G14 NET 'No_Conn_TP_IO_L6P_SM3P_35' U2- # 35 H13 NET 'No_Conn_TP_IO_L4P_35' U2- # 35 H14 NET 'No_Conn_TP_IO_L2P_SM0P_35' U2- # 35 H15 NET 'No_Conn_TP_IO_L8N_SRCC_35' U2- # 35 J11 NET 'No_Conn_TP_IO_L8P_SRCC_35' U2- # 35 J12 NET 'No_Conn_TP_IO_L12P_SM5P_35' U2- # 35 J13 NET 'No_Conn_TP_IO_L16P_VRN_35' U2- # 35 K12 NET 'No_Conn_TP_IO_L12N_SM5N_35' U2- # 35 K13 NET 'No_Conn_TP_IO_L14P_35' U2- # 35 K14 NET 'No_Conn_TP_IO_L16N_VRP_35' U2- # 35 L11 NET 'No_Conn_TP_IO_L18P_GC_35' U2- # 35 L12 NET 'No_Conn_TP_IO_L14N_VREF_35' U2- # 35 L14 NET 'No_Conn_TP_IO_L18N_GC_35' U2- # 35 M12 NET 'No_Conn_TP_IO_L10P_MRCC_35' U2- # 35 M13 NET 'No_Conn_TP_IO_L9P_MRCC_35' U2- # 35 M14 NET 'No_Conn_TP_IO_L10N_MRCC_35' U2- # 35 N13 NET 'No_Conn_TP_IO_L9N_MRCC_35' U2- # 35 N14 # Unused pins from IO bank 36 ############################# # note: some pins from this bank are used for the CTP Output NET 'No_Conn_TP_IO_L2P_36' U2- # 36 G16 NET 'No_Conn_TP_IO_L4N_VREF_36' U2- # 36 H16 NET 'No_Conn_TP_IO_L1P_36' U2- # 36 H18 NET 'No_Conn_TP_IO_L14P_36' U2- # 36 J15 NET 'No_Conn_TP_IO_L4P_36' U2- # 36 J16 NET 'No_Conn_TP_IO_L6N_36' U2- # 36 J17 NET 'No_Conn_TP_IO_L0N_36' U2- # 36 J18 NET 'No_Conn_TP_IO_L14N_VREF_36' U2- # 36 K15 NET 'No_Conn_TP_IO_L6P_36' U2- # 36 K17 NET 'No_Conn_TP_IO_L0P_36' U2- # 36 K18 NET 'No_Conn_TP_IO_L16N_36' U2- # 36 L15 NET 'No_Conn_TP_IO_L16P_36' U2- # 36 L16 NET 'No_Conn_TP_IO_L12P_VRN_36' U2- # 36 L17 NET 'No_Conn_TP_IO_L18P_36' U2- # 36 M16 NET 'No_Conn_TP_IO_L12N_VRP_36' U2- # 36 M17 NET 'No_Conn_TP_IO_L8P_SRCC_36' U2- # 36 M18 NET 'No_Conn_TP_IO_L18N_36' U2- # 36 N15 NET 'No_Conn_TP_IO_L10P_MRCC_36' U2- # 36 N16 NET 'No_Conn_TP_IO_L8N_SRCC_36' U2- # 36 N18 NET 'No_Conn_TP_IO_L10N_MRCC_36' U2- # 36 P16 NET 'No_Conn_TP_IO_L9N_MRCC_36' U2- # 36 P17 NET 'No_Conn_TP_IO_L9P_MRCC_36' U2- # 36 P18 # Unused pins from IO bank 37 ############################# # note: some pins from this bank are used for the CTP Output NET 'No_Conn_TP_IO_L0P_37' U2- # 37 G23 NET 'No_Conn_TP_IO_L14N_VREF_37' U2- # 37 H19 NET 'No_Conn_TP_IO_L0N_37' U2- # 37 H23 NET 'No_Conn_TP_IO_L14P_37' U2- # 37 J20 NET 'No_Conn_TP_IO_L18P_37' U2- # 37 K19 NET 'No_Conn_TP_IO_L16P_37' U2- # 37 K20 NET 'No_Conn_TP_IO_L18N_37' U2- # 37 L19 NET 'No_Conn_TP_IO_L16N_37' U2- # 37 L20 NET 'No_Conn_TP_IO_L9N_MRCC_37' U2- # 37 L21 # Unused pins from IO bank 38 ############################# # note: some pins from this bank are used for the CTP Output NET 'No_Conn_TP_IO_L0N_38' U2- # 38 G24 NET 'No_Conn_TP_IO_L5P_38' U2- # 38 G26 NET 'No_Conn_TP_IO_L0P_38' U2- # 38 H24 NET 'No_Conn_TP_IO_L4N_VREF_38' U2- # 38 H25 NET 'No_Conn_TP_IO_L4P_38' U2- # 38 H26 NET 'No_Conn_TP_IO_L8P_SRCC_38' U2- # 38 J23 NET 'No_Conn_TP_IO_L6N_38' U2- # 38 J25 NET 'No_Conn_TP_IO_L8N_SRCC_38' U2- # 38 K23 NET 'No_Conn_TP_IO_L12N_VRP_38' U2- # 38 K24 NET 'No_Conn_TP_IO_L6P_38' U2- # 38 K25 NET 'No_Conn_TP_IO_L12P_VRN_38' U2- # 38 L24 NET 'No_Conn_TP_IO_L9P_MRCC_38' U2- # 38 M19 NET 'No_Conn_TP_IO_L10N_MRCC_38' U2- # 38 M21 NET 'No_Conn_TP_IO_L14P_38' U2- # 38 M22 NET 'No_Conn_TP_IO_L14N_VREF_38' U2- # 38 M23 NET 'No_Conn_TP_IO_L16N_38' U2- # 38 M24 NET 'No_Conn_TP_IO_L9N_MRCC_38' U2- # 38 N19 NET 'No_Conn_TP_IO_L19N_38' U2- # 38 N20 NET 'No_Conn_TP_IO_L10P_MRCC_38' U2- # 38 N21 NET 'No_Conn_TP_IO_L16P_38' U2- # 38 N23 NET 'No_Conn_TP_IO_L19P_38' U2- # 38 P20 NET 'No_Conn_TP_IO_L18P_38' U2- # 38 P21 NET 'No_Conn_TP_IO_L18N_38' U2- # 38 P22