# # File created by Match_Resource_to_Pin V3.1 at Thu Oct 10 12:05:44 2013 # derived from input Netlist file # and Resource to Pin dictionary # ############################################################################################ # # CMX Net-to-Resource File for the # TP Function FPGA IO signals used for Front Panel CTP Output # -=============------------------------------------------------ # # # Original Rev. 19-Nov-2012 Place holder # Rev: 11-Dec-2012 Copy Base FPGA pin assignment # Rev: 14-Jan-2013 Assign outer pins from IO banks 36, 37, 38 and route on layers 2,3,4,5 # Rev: 05-Apr-2013 Tentatively flag these signals to belong to layer 6 # Most Recent Rev: 04-Jun-2013 Update position of signal #65 after final location of 5th translator # # # Signal Nets referenced in this file: # ------------------------------------ # # There are 0, 1 or 2 CTP cables connected to a given CMX card. # A Crate CMX with only Base CMX functionality does not send any data to the CTP # A System CMX in a CPM crate sends information to the CTP over one cable # A System CMX in a JEM crate sends information to the CTP over two cables # A Crate CMX with TP functionality would probably send information to the CTP over two cables # # 'TP_DOUT_CTP_xx' are the CTP output signals from the TP FPGA with xx=00 to 65. # Each CTP output cable carries 33 LVDS signals consisting of 31 data bits, one clock # and one parity bit. # xx=0 to 30 carry data bits on cable #1 # xx=31 carry the clock on cable #1 # xx=64 carry the parity on cable #1 # xx=32 to 62 carry data bits on cable #2 # xx=63 carry the clock on cable #2 # xx=65 carry the parity on cable #2 # Note that regional clock signals are assigned to CTP output signals # 31 and 63 # for flexibility, so that the CTP output cables could be used as inputs instead. # # These CTP output signals are assigned here to resources in IO banks ??2 and ?? # # The rest of the circuitry used to drive the LVDS cables is in the file front_panel_ctp_driver_n2p.txt # in the Net_Lists/Front_Panel_CTP_IO_Nets directory # # # Note: Trace layer information is appended as comments below. # ----- # # NET 'TP_DOUT_CTP_00' U2- #> F02 #> T02 00 D22 # # ^ ^ ^ ^ ^ # | | | | | # Tailored comment flag to help with string searches -----------------+ | | | | # | | | | # Target Trace Layer number to use for this net --------------------------+ | | | # as it exits the FPGA (to reach a nearby via if needed) | | | # F01 is top layer, F02 the first inner layer, etc | | | # | | | # Target Trace Layer number to use for this net ---------------------------------+ | | # as it reaches the level translator near the front of the card | | # T01 is top layer, T02 the first inner layer, etc | | # | | # Signal number is repeated to help manual entry of Pin Number ---------------------+ | # | # Target Pin Number read from paper study -----------------------------------------------+ # and cross-checked after Match_Res2Pin # ############################################################################################ # # CTP Cable #1 # NET 'TP_DOUT_CTP_00' U2-D22 #> F02 #> T06 00 D22 IO_L11N_SRCC_37 NET 'TP_DOUT_CTP_01' U2-B22 #> F02 #> T06 01 B22 IO_L5N_37 NET 'TP_DOUT_CTP_02' U2-A22 #> F02 #> T06 02 A22 IO_L13P_37 NET 'TP_DOUT_CTP_03' U2-B23 #> F02 #> T06 03 B23 IO_L5P_37 NET 'TP_DOUT_CTP_04' U2-C23 #> F02 #> T06 04 C23 IO_L3N_37 NET 'TP_DOUT_CTP_05' U2-A24 #> F02 #> T06 05 A24 IO_L1N_37 NET 'TP_DOUT_CTP_06' U2-B24 #> F02 #> T06 06 B24 IO_L1P_37 NET 'TP_DOUT_CTP_07' U2-A25 #> F02 #> T06 07 A25 IO_L11N_SRCC_38 NET 'TP_DOUT_CTP_08' U2-C25 #> F02 #> T06 08 C25 IO_L15N_38 NET 'TP_DOUT_CTP_09' U2-A26 #> F02 #> T06 09 A26 IO_L11P_SRCC_38 NET 'TP_DOUT_CTP_10' U2-B26 #> F02 #> T06 10 B26 IO_L15P_38 NET 'TP_DOUT_CTP_11' U2-A27 #> F02 #> T06 11 A27 IO_L7N_38 NET 'TP_DOUT_CTP_12' U2-B27 #> F02 #> T06 12 B27 IO_L7P_38 NET 'TP_DOUT_CTP_13' U2-B28 #> F02 #> T06 13 B28 IO_L3N_38 NET 'TP_DOUT_CTP_14' U2-F22 #> F03 #> T06 14 F22 IO_L2N_37 NET 'TP_DOUT_CTP_15' U2-E22 #> F03 #> T06 15 E22 IO_L4N_VREF_37 NET 'TP_DOUT_CTP_16' U2-D23 #> F03 #> T06 16 D23 IO_L11P_SRCC_37 NET 'TP_DOUT_CTP_17' U2-E24 #> F03 #> T06 17 E24 IO_L7P_37 NET 'TP_DOUT_CTP_18' U2-C24 #> F03 #> T06 18 C24 IO_L3P_37 NET 'TP_DOUT_CTP_19' U2-D25 #> F03 #> T06 19 D25 IO_L17P_38 NET 'TP_DOUT_CTP_20' U2-C26 #> F03 #> T06 20 C26 IO_L13P_38 NET 'TP_DOUT_CTP_21' U2-D27 #> F03 #> T06 21 D27 IO_L1N_38 NET 'TP_DOUT_CTP_22' U2-C28 #> F03 #> T06 22 C28 IO_L3P_38 NET 'TP_DOUT_CTP_23' U2-K22 #> F04 #> T06 23 K22 IO_L10N_MRCC_37 NET 'TP_DOUT_CTP_24' U2-G22 #> F04 #> T06 24 G22 IO_L2P_37 NET 'TP_DOUT_CTP_25' U2-E23 #> F04 #> T06 25 E23 IO_L7N_37 NET 'TP_DOUT_CTP_26' U2-F24 #> F04 #> T06 26 F24 IO_L2N_38 NET 'TP_DOUT_CTP_27' U2-F25 #> F04 #> T06 27 F25 IO_L2P_38 NET 'TP_DOUT_CTP_28' U2-E25 #> F04 #> T06 28 E25 IO_L17N_38 NET 'TP_DOUT_CTP_29' U2-D26 #> F04 #> T06 29 D26 IO_L13N_38 NET 'TP_DOUT_CTP_30' U2-E27 #> F04 #> T06 30 E27 IO_L1P_38 NET 'TP_DOUT_CTP_31' U2-J22 #> F05 #> T06 31 J22 IO_L10P_MRCC_37 NET 'TP_DOUT_CTP_64' U2-F26 #> F05 #> T06 64 F26 IO_L5N_38 # # CTP Cable #2 # NET 'TP_DOUT_CTP_32' U2-B17 #> F02 #> T06 32 B17 IO_L17N_36 NET 'TP_DOUT_CTP_33' U2-A17 #> F02 #> T06 33 A17 IO_L17P_36 NET 'TP_DOUT_CTP_34' U2-B18 #> F02 #> T06 34 B18 IO_L15P_36 NET 'TP_DOUT_CTP_35' U2-B19 #> F02 #> T06 35 B19 IO_L7N_36 NET 'TP_DOUT_CTP_36' U2-A19 #> F02 #> T06 36 A19 IO_L15N_36 NET 'TP_DOUT_CTP_37' U2-C20 #> F02 #> T06 37 C20 IO_L19P_37 NET 'TP_DOUT_CTP_38' U2-A20 #> F02 #> T06 38 A20 IO_L15N_37 NET 'TP_DOUT_CTP_39' U2-D20 #> F02 #> T06 39 D20 IO_L19N_37 NET 'TP_DOUT_CTP_40' U2-A21 #> F02 #> T06 40 A21 IO_L13N_37 NET 'TP_DOUT_CTP_41' U2-B21 #> F02 #> T06 41 B21 IO_L15P_37 NET 'TP_DOUT_CTP_42' U2-C21 #> F02 #> T06 42 C21 IO_L17P_37 NET 'TP_DOUT_CTP_43' U2-D17 #> F03 #> T06 43 D17 IO_L19P_36 NET 'TP_DOUT_CTP_44' U2-C18 #> F03 #> T06 44 C18 IO_L13N_36 NET 'TP_DOUT_CTP_45' U2-C19 #> F03 #> T06 45 C19 IO_L7P_36 NET 'TP_DOUT_CTP_46' U2-E19 #> F03 #> T06 46 E19 IO_L5P_36 NET 'TP_DOUT_CTP_47' U2-E20 #> F03 #> T06 47 E20 IO_L12P_VRN_37 NET 'TP_DOUT_CTP_48' U2-D21 #> F03 #> T06 48 D21 IO_L17N_37 NET 'TP_DOUT_CTP_49' U2-F21 #> F03 #> T06 49 F21 IO_L4P_37 NET 'TP_DOUT_CTP_50' U2-E17 #> F04 #> T06 50 E17 IO_L19N_36 NET 'TP_DOUT_CTP_51' U2-D18 #> F04 #> T06 51 D18 IO_L13P_36 NET 'TP_DOUT_CTP_52' U2-E18 #> F04 #> T06 52 E18 IO_L5N_36 NET 'TP_DOUT_CTP_53' U2-F19 #> F04 #> T06 53 F19 IO_L3N_36 NET 'TP_DOUT_CTP_54' U2-F20 #> F04 #> T06 54 F20 IO_L12N_VRP_37 NET 'TP_DOUT_CTP_55' U2-G21 #> F04 #> T06 55 G21 IO_L8N_SRCC_37 NET 'TP_DOUT_CTP_56' U2-H21 #> F04 #> T06 56 H21 IO_L6P_37 NET 'TP_DOUT_CTP_57' U2-F16 #> F05 #> T06 57 F16 IO_L2N_36 NET 'TP_DOUT_CTP_58' U2-F17 #> F05 #> T06 58 F17 IO_L11P_SRCC_36 NET 'TP_DOUT_CTP_59' U2-G17 #> F05 #> T06 59 G17 IO_L11N_SRCC_36 NET 'TP_DOUT_CTP_60' U2-G18 #> F05 #> T06 60 G18 IO_L1N_36 NET 'TP_DOUT_CTP_61' U2-G19 #> F05 #> T06 61 G19 IO_L3P_36 NET 'TP_DOUT_CTP_62' U2-H20 #> F05 #> T06 62 H20 IO_L8P_SRCC_37 NET 'TP_DOUT_CTP_63' U2-L22 #> F05 #> T06 63 L22 IO_L9P_MRCC_37 NET 'TP_DOUT_CTP_65' U2-J21 #> F05 #> T06 65 J21 IO_L6N_37 ############################################################################################ # # CMX Net-to-Resource File for the # TP Function FPGA IO signals used the highspeed GTX Receivers # -=============------------------------------------------------- # # # Original Rev. 16-Mar-2012 # Rev. 5-Dec-2012 Rename nets and add termination resistors # Rev: 11-Dec-2012 File name changed for uniformity and consistency # between Base and TP files # Rev: 31-Dec-2012 Change the net-name on the MGTAVTTRCAL_115 # Calibration Resistor pin. # Rev: 23-May-2013 Assign full net names, including fiber number, to the # GTX Receivers in Quads 113, 114, 115, i.e. MiniPOD MP4. # Rev: 24-May-2013 Assign full net names, including fiber number, to the # GTX Receivers in Quads 110, 111, 112, i.e. MiniPOD MP3 # and to Quads 116, 117, 118, i.e. MiniPOD MP5. # Most Recent Rev: 8-Oct-2013 Change some GTX Transceiver - MiniPOD Fiber assignments # to allow better trace length match of DIR and CMP traces. # # # Receiver 1 MiniPOD MP3 # --------===----------===== NET 'MP3_F01_QUAD_110_REC_0_DIR' U2-BB7 # MGTRXP0_110 NET 'MP3_F01_QUAD_110_REC_0_CMP' U2-BB8 # MGTRXN0_110 NET 'MP3_F07_QUAD_110_REC_1_DIR' U2-BA5 # MGTRXP1_110 NET 'MP3_F07_QUAD_110_REC_1_CMP' U2-BA6 # MGTRXN1_110 NET 'MP3_F05_QUAD_110_REC_2_DIR' U2-AY7 # MGTRXP2_110 NET 'MP3_F05_QUAD_110_REC_2_CMP' U2-AY8 # MGTRXN2_110 NET 'MP3_F03_QUAD_110_REC_3_DIR' U2-AW5 # MGTRXP3_110 NET 'MP3_F03_QUAD_110_REC_3_CMP' U2-AW6 # MGTRXN3_110 NET 'MP3_F09_QUAD_111_REC_0_DIR' U2-AV7 # MGTRXP0_111 NET 'MP3_F09_QUAD_111_REC_0_CMP' U2-AV8 # MGTRXN0_111 NET 'MP3_F11_QUAD_111_REC_1_DIR' U2-AU5 # MGTRXP1_111 NET 'MP3_F11_QUAD_111_REC_1_CMP' U2-AU6 # MGTRXN1_111 NET 'MP3_F10_QUAD_111_REC_2_DIR' U2-AR5 # MGTRXP2_111 NET 'MP3_F10_QUAD_111_REC_2_CMP' U2-AR6 # MGTRXN2_111 NET 'MP3_F08_QUAD_111_REC_3_DIR' U2-AP7 # MGTRXP3_111 NET 'MP3_F08_QUAD_111_REC_3_CMP' U2-AP8 # MGTRXN3_111 NET 'MP3_F00_QUAD_112_REC_0_DIR' U2-AN5 # MGTRXP0_112 NET 'MP3_F00_QUAD_112_REC_0_CMP' U2-AN6 # MGTRXN0_112 NET 'MP3_F04_QUAD_112_REC_1_DIR' U2-AM7 # MGTRXP1_112 NET 'MP3_F04_QUAD_112_REC_1_CMP' U2-AM8 # MGTRXN1_112 NET 'MP3_F06_QUAD_112_REC_2_DIR' U2-AL5 # MGTRXP2_112 NET 'MP3_F06_QUAD_112_REC_2_CMP' U2-AL6 # MGTRXN2_112 NET 'MP3_F02_QUAD_112_REC_3_DIR' U2-AJ5 # MGTRXP3_112 NET 'MP3_F02_QUAD_112_REC_3_CMP' U2-AJ6 # MGTRXN3_112 # Receiver 2 MiniPOD MP4 # --------===----------===== NET 'MP4_F01_QUAD_113_REC_0_DIR' U2-AG5 # MGTRXP0_113 NET 'MP4_F01_QUAD_113_REC_0_CMP' U2-AG6 # MGTRXN0_113 NET 'MP4_F03_QUAD_113_REC_3_DIR' U2-AD3 # MGTRXP3_113 NET 'MP4_F03_QUAD_113_REC_3_CMP' U2-AD4 # MGTRXN3_113 NET 'MP4_F05_QUAD_113_REC_2_DIR' U2-AE5 # MGTRXP2_113 NET 'MP4_F05_QUAD_113_REC_2_CMP' U2-AE6 # MGTRXN2_113 NET 'MP4_F07_QUAD_113_REC_1_DIR' U2-AF3 # MGTRXP1_113 NET 'MP4_F07_QUAD_113_REC_1_CMP' U2-AF4 # MGTRXN1_113 NET 'MP4_F09_QUAD_114_REC_0_DIR' U2-AC5 # MGTRXP0_114 NET 'MP4_F09_QUAD_114_REC_0_CMP' U2-AC6 # MGTRXN0_114 NET 'MP4_F11_QUAD_114_REC_1_DIR' U2-AB3 # MGTRXP1_114 NET 'MP4_F11_QUAD_114_REC_1_CMP' U2-AB4 # MGTRXN1_114 NET 'MP4_F10_QUAD_114_REC_2_DIR' U2-AA5 # MGTRXP2_114 NET 'MP4_F10_QUAD_114_REC_2_CMP' U2-AA6 # MGTRXN2_114 NET 'MP4_F08_QUAD_114_REC_3_DIR' U2-Y3 # MGTRXP3_114 NET 'MP4_F08_QUAD_114_REC_3_CMP' U2-Y4 # MGTRXN3_114 NET 'MP4_F02_QUAD_115_REC_0_DIR' U2-W5 # MGTRXP0_115 NET 'MP4_F02_QUAD_115_REC_0_CMP' U2-W6 # MGTRXN0_115 NET 'MP4_F04_QUAD_115_REC_1_DIR' U2-V3 # MGTRXP1_115 NET 'MP4_F04_QUAD_115_REC_1_CMP' U2-V4 # MGTRXN1_115 NET 'MP4_F06_QUAD_115_REC_2_DIR' U2-U5 # MGTRXP2_115 NET 'MP4_F06_QUAD_115_REC_2_CMP' U2-U6 # MGTRXN2_115 NET 'MP4_F00_QUAD_115_REC_3_DIR' U2-R5 # MGTRXP3_115 NET 'MP4_F00_QUAD_115_REC_3_CMP' U2-R6 # MGTRXN3_115 # Receiver 3 MiniPOD MP5 # --------===----------===== NET 'MP5_F01_QUAD_116_REC_0_DIR' U2-P7 # MGTRXP0_116 NET 'MP5_F01_QUAD_116_REC_0_CMP' U2-P8 # MGTRXN0_116 NET 'MP5_F03_QUAD_116_REC_1_DIR' U2-N5 # MGTRXP1_116 NET 'MP5_F03_QUAD_116_REC_1_CMP' U2-N6 # MGTRXN1_116 NET 'MP5_F05_QUAD_116_REC_2_DIR' U2-L5 # MGTRXP2_116 NET 'MP5_F05_QUAD_116_REC_2_CMP' U2-L6 # MGTRXN2_116 NET 'MP5_F07_QUAD_116_REC_3_DIR' U2-J5 # MGTRXP3_116 NET 'MP5_F07_QUAD_116_REC_3_CMP' U2-J6 # MGTRXN3_116 NET 'MP5_F09_QUAD_117_REC_0_DIR' U2-H7 # MGTRXP0_117 NET 'MP5_F09_QUAD_117_REC_0_CMP' U2-H8 # MGTRXN0_117 NET 'MP5_F11_QUAD_117_REC_1_DIR' U2-G5 # MGTRXP1_117 NET 'MP5_F11_QUAD_117_REC_1_CMP' U2-G6 # MGTRXN1_117 NET 'MP5_F10_QUAD_117_REC_2_DIR' U2-F7 # MGTRXP2_117 NET 'MP5_F10_QUAD_117_REC_2_CMP' U2-F8 # MGTRXN2_117 NET 'MP5_F08_QUAD_117_REC_3_DIR' U2-E5 # MGTRXP3_117 NET 'MP5_F08_QUAD_117_REC_3_CMP' U2-E6 # MGTRXN3_117 NET 'MP5_F02_QUAD_118_REC_0_DIR' U2-D7 # MGTRXP0_118 NET 'MP5_F02_QUAD_118_REC_0_CMP' U2-D8 # MGTRXN0_118 NET 'MP5_F04_QUAD_118_REC_1_DIR' U2-C5 # MGTRXP1_118 NET 'MP5_F04_QUAD_118_REC_1_CMP' U2-C6 # MGTRXN1_118 NET 'MP5_F06_QUAD_118_REC_2_DIR' U2-B7 # MGTRXP2_118 NET 'MP5_F06_QUAD_118_REC_2_CMP' U2-B8 # MGTRXN2_118 NET 'MP5_F00_QUAD_118_REC_3_DIR' U2-A5 # MGTRXP3_118 NET 'MP5_F00_QUAD_118_REC_3_CMP' U2-A6 # MGTRXN3_118 # Now connect the GTX Termination Calibration Resistor # This is a precision 100 Ohm resistor. # See Chapter 5 page 274 of the # Virtex-6 GTX User Guide. # # The other half of these connections is in: # # ..../Everything_Else/dci_gtx_res_nets_n2p.txt # NET 'TP_MGTRREF' U2-B11 # B11 Topological MGTRREF pin MGTRREF_115 NET 'TP_GTX_AVTT' U2-A12 # A12 Topological MGTAVTTRCAL MGTAVTTRCAL_115 # connected to the TP_GTX_AVTT bus # as indicated in the User Guide ############################################################################################ # # CMX Net-to-Resource File for the # TP Function FPGA IO signals used for the Low-Speed DAQ & ROI Data Output # -=============-------------------------------------------------------------- # # # Original Rev. 17-Jan-2013 # Most Recent Rev. 17-Jan-2013 Assign lowest Two channels # # # TP Function FPGA # # DAQ and ROI Data Outputs to SFP Optical Transmitters # # SFP3 TP Function DAQ SFP Optical Output # SFP4 TP Function RIO SFP Optical Output # NET 'TP_DAQ_DATA_OUT_DIR' U2-BA1 # BA1 DAQ Data Output Direct MGTTXP1_110 NET 'TP_DAQ_DATA_OUT_CMP' U2-BA2 # BA2 DAQ Data Output Complement MGTTXN1_110 NET 'TP_ROI_DATA_OUT_DIR' U2-BB3 # BB3 ROI Data Output Direct MGTTXP0_110 NET 'TP_ROI_DATA_OUT_CMP' U2-BB4 # BB4 ROI Data Output Complement MGTTXN0_110 ############################################################################################ # # CMX Net-to-Resource File for the # TP Function FPGA IO signals used for the On-Card VME bus signals # -=============----------------------------------------------------- # # # Original Rev. 11-Dec-2012 Copy Base FPGA pin assignment # Most Recent Rev: 14-Jan-2013 Assign outer pins from IO banks 15, 16 &17 and route on layers 7 (most) & 6 (with via) # # # Signal Nets referenced in this file: # ------------------------------------ # # 'OCB_Axx' are the On-Card Bus Address lines to the Base FPGA with xx=01 to 23 # (note there is no "A00" signal) # # 'OCB_Dyy' are the On-Card Bus Data lines to the Base FPGA with yy=00 to 15 # # 'OCB_GEO_ADRS_z' are the On-Card Bus Geographic Section Address lines with z=0 to 6 # # # 'OCB_SYS_RESET_B' is the On-Card Bus VME SYS_RESET signal # The "_B" postfix is used to indicate that the reset request is active # when the electrical signal is low # # 'OCB_DS_B' is the On-Card Bus Data strobe. # The "_B" postfix is used to indicate that the data strobe signal is on the # falling edge of the electrical signal. # # 'OCB_WRITE_B' is the On-Card Bus Data Direction # The "_B" postfix is used to indicate that the Write direction is # requested when the electrical signal is low. # # # IO Banks used # ------------- # # Most signal nets are assigned to IO Bank 14 and a few to Io Bank 13 # - All address line nets are in IO Bank 14 # - All data line nets are in IO Bank 14 # - The Data Strobe net is assigned to a regional clock pin in IO Bank 14 # - The Board Select net is assigned to a regional clock pin in IO Bank 13 # - The Write Net is assigned to an IO input pin in Bank 13 # - The Sys_Reset net is assigned to an IO input pin in Bank 13 # # The bulk of IO Bank 13 is used for the CTP output signals # # Note: Trace layer information is appended as comments below. # ----- # # NET 'OCB_A01' U2- #> F07 #> T07 A01 AF41 # # ^ ^ ^ ^ ^ # | | | | | # Tailored comment flag to help with string searches ------------------+ | | | | # | | | | # Target Trace Layer number to use for this net --------------------------+ | | | # as it exits the FPGA (to reach a nearby via if needed) | | | # F01 is top layer, F02 the first inner layer, etc | | | # | | | # Target Trace Layer number to use for this net ---------------------------------+ | | # as it connects the VME bus transceiver section to the two FPGAs | | # T01 is top layer, T02 the first inner layer, etc | | # | | # Signal number is repeated to help manual entry of Pin Number ---------------------+ | # | # Target Pin Number read from paper drawing ---------------------------------------------+ # and cross-checked after Match_Res2Pin # ############################################################################################ # The lower Address (1:16), all Data lines, and the Data Strobe, will come in directly (no via) # The data strobe is assigned to a regional clock input pin (but probably not used as a clock) NET 'OCB_A01' U2-AF41 #> F07 #> T07 A01 AF41 IO_L17N_15 NET 'OCB_A02' U2-AF42 #> F07 #> T07 A02 AF42 IO_L17P_15 NET 'OCB_A03' U2-AE40 #> F07 #> T07 A03 AE40 IO_L19P_15 NET 'OCB_A04' U2-AE42 #> F07 #> T07 A04 AE42 IO_L15N_SM15N_15 NET 'OCB_A05' U2-AD41 #> F07 #> T07 A05 AD41 IO_L11N_SRCC_15 NET 'OCB_A06' U2-AD42 #> F07 #> T07 A06 AD42 IO_L15P_SM15P_15 NET 'OCB_A07' U2-AC41 #> F07 #> T07 A07 AC41 IO_L11P_SRCC_15 NET 'OCB_A08' U2-AC40 #> F07 #> T07 A08 AC40 IO_L13P_SM14P_15 NET 'OCB_A09' U2-AB42 #> F07 #> T07 A09 AB42 IO_L7N_SM12N_15 NET 'OCB_A10' U2-AB41 #> F07 #> T07 A10 AB41 IO_L5N_SM10N_15 NET 'OCB_A11' U2-AB39 #> F07 #> T07 A11 AB39 IO_L3P_SM9P_15 NET 'OCB_A12' U2-AA40 #> F07 #> T07 A12 AA40 IO_L3N_SM9N_15 NET 'OCB_A13' U2-AA41 #> F07 #> T07 A13 AA41 IO_L5P_SM10P_15 NET 'OCB_A14' U2-AA42 #> F07 #> T07 A14 AA42 IO_L7P_SM12P_15 NET 'OCB_A15' U2-Y40 #> F07 #> T07 A15 Y40 IO_L17P_16 NET 'OCB_A16' U2-Y42 #> F07 #> T07 A16 Y42 IO_L15N_16 NET 'OCB_D00' U2-L41 #> F07 #> T07 D00 L41 IO_L3P_17 NET 'OCB_D01' U2-L42 #> F07 #> T07 D01 L42 IO_L3N_17 NET 'OCB_D02' U2-M41 #> F07 #> T07 D02 M41 IO_L7P_17 NET 'OCB_D03' U2-M42 #> F07 #> T07 D03 M42 IO_L7N_17 NET 'OCB_D04' U2-N41 #> F07 #> T07 D04 N41 IO_L11N_SRCC_17 NET 'OCB_D05' U2-P41 #> F07 #> T07 D05 P41 IO_L13N_17 NET 'OCB_D06' U2-P42 #> F07 #> T07 D06 P42 IO_L15P_17 NET 'OCB_D07' U2-R40 #> F07 #> T07 D07 R40 IO_L17P_17 NET 'OCB_D08' U2-R42 #> F07 #> T07 D08 R42 IO_L15N_17 NET 'OCB_D09' U2-T41 #> F07 #> T07 D09 T41 IO_L19P_17 NET 'OCB_D10' U2-T42 #> F07 #> T07 D10 T42 IO_L19N_17 NET 'OCB_D11' U2-U41 #> F07 #> T07 D11 U41 IO_L3N_16 NET 'OCB_D12' U2-U42 #> F07 #> T07 D12 U42 IO_L3P_16 NET 'OCB_D13' U2-V41 #> F07 #> T07 D13 V41 IO_L13P_16 NET 'OCB_D14' U2-W41 #> F07 #> T07 D14 W41 IO_L13N_16 NET 'OCB_D15' U2-W42 #> F07 #> T07 D15 W42 IO_L15P_16 NET 'OCB_DS_B' U2-W32 #> F07 #> T07 DS W32 IO_L9P_MRCC_16 # The upper Address (17:23), the Direction, SysReset, and all Geographic Address signals # will need to transition to another trace layer (tentatively trace layer 2) NET 'OCB_A17' U2-W38 #> F02 #> T07 A17 W38 IO_L7N_16 NET 'OCB_A18' U2-W40 #> F02 #> T07 A18 W40 IO_L11N_SRCC_16 NET 'OCB_A19' U2-V40 #> F02 #> T07 A19 V40 IO_L11P_SRCC_16 NET 'OCB_A20' U2-U39 #> F02 #> T07 A20 U39 IO_L5P_16 NET 'OCB_A21' U2-T40 #> F02 #> T07 A21 T40 IO_L17N_17 NET 'OCB_A22' U2-R39 #> F02 #> T07 A22 R39 IO_L8P_SRCC_17 NET 'OCB_A23' U2-P40 #> F02 #> T07 A23 P40 IO_L13P_17 NET 'OCB_WRITE_B' U2-Y39 #> F02 #> T07 WRI Y39 IO_L17N_16 NET 'OCB_SYS_RESET_B' U2-AA39 #> F02 #> T07 RES AA39 IO_L19N_16 NET 'OCB_GEO_ADRS_0' U2-AB38 #> F02 #> T07 GA0 AB38 IO_L1N_15 NET 'OCB_GEO_ADRS_1' U2-L40 #> F02 #> T07 GA1 L40 IO_L1N_17 NET 'OCB_GEO_ADRS_2' U2-M39 #> F02 #> T07 GA2 M39 IO_L2N_17 NET 'OCB_GEO_ADRS_3' U2-N40 #> F02 #> T07 GA3 N40 IO_L11P_SRCC_17 NET 'OCB_GEO_ADRS_4' U2-AC39 #> F02 #> T07 GA4 AC39 IO_L4N_VREF_15 NET 'OCB_GEO_ADRS_5' U2-AD40 #> F02 #> T07 GA5 AD40 IO_L13N_SM14N_15 NET 'OCB_GEO_ADRS_6' U2-AE39 #> F02 #> T07 GA6 AE39 IO_L19N_15 ############################################################################################ # # CMX Net-to-Resource File for the # # # TP Function FPGA Clock Connections # -=============-----=======------------- # # # Original Rev. 24-AUG-2012 # Rev. 9-Dec-2012 # Rev: 11-Dec-2012 File name changed for uniformity and consistency between Base and TP files # Rev: 29-Dec-2012 Remove the JTAG nets from this file. Remove "jtag" from the filename. # Rev: 16-Jan-2013 Change "Not_Used_" to "No_Conn_". # Most Recent Rev: 2-May-2013 Change Logic and GTX clock net names to # reflect the 40.08 or 320.64 MHz LHC clocks # and the 40.000 or 100.000 MHz Crystal clocks # # # # Topological Processor FPGA Clocks Logic and Transceiver # -----------------------------======------------------------ # # # LHC Locked Logic Clocks # # Connect the 40.08 MHz and 320.64 MHz Logic Clocks to # the Topological Processor FPGA. These are LHC locked LVDS # clock signals to the Logic in the Topological Processor FPGA. # # A Global Clock input in I/O Bank 34 receives the DeSkew #1 40.08 MHz Logic clock. # # A Global Clock input in I/O Bank 25 receives the DeSkew #2 40.08 MHz Logic clock. # # A Global Clock input in I/O Bank 34 receives the 320.64 MHz Logic clock. # NET 'CLK_40MHz08_DSKW_1_TP_LOGIC_DIR' U2-AY14 # AY14 40.08 MHz DeSkew-1 LHC Logic IO_L0P_GC_34 NET 'CLK_40MHz08_DSKW_1_TP_LOGIC_CMP' U2-AY13 # AY13 Clk to the Topological FPGA IO_L0N_GC_34 NET 'CLK_40MHz08_DSKW_2_TP_LOGIC_DIR' U2-J42 # J42 40.08 MHz DeSkew-2 LHC Logic IO_L18P_GC_25 NET 'CLK_40MHz08_DSKW_2_TP_LOGIC_CMP' U2-K42 # K42 Clk to the Topological FPGA IO_L18N_GC_25 NET 'CLK_320MHz64_LHC_TP_LOGIC_DIR' U2-AP12 # AP12 320.64 MHz LHC Logic Clock IO_L1N_GC_34 NET 'CLK_320MHz64_LHC_TP_LOGIC_CMP' U2-AP11 # AP11 to the Topological FPGA IO_L1P_GC_34 # # Crystal Oscillator #2 GTX Clock # # Now to the Topological Processor FPGA connect the 40.000 MHz # or 100.000 Mhz Crystal Oscillator #2 LVPECL clock to the # clock "0" input of the GTX Transceiver Quad 110. # # This is the clock to the GTX Transcievers that # transmit the DAQ and ROI data either by G-Link # or by S-Link. # NET 'CLK_100MHz000_XTAL_2_TP_TRNCV_DIR' U2-BA10 # BA10 100.000 MHz Crystal Osc #2 MGTREFCLK0P_110 NET 'CLK_100MHz000_XTAL_2_TP_TRNCV_CMP' U2-BA9 # BA9 GTX Clk to the TP FPGA. MGTREFCLK0N_110 # This could also be 40.000 MHz # # LHC Locked GTX Clocks # # Now on the Topological Processor FPGA connect the # 320.64 MHz LHC locked LVPECL clocks to the clock # inputs of the GTX Transceivers. # # We will use the "0" clock inputs to the Quad Banks # 111, 114, and 117 to receive these Transceiver clocks. # These are the Topological Processor GTX Transceivers # that receive the 6.4 Gbps L1Topo data. # NET 'CLK_320MHz64_LHC_TP_QUAD_111_DIR' U2-AU10 # AU10 320.64 MHz LHC GTX Clk #1 MGTREFCLK0P_111 NET 'CLK_320MHz64_LHC_TP_QUAD_111_CMP' U2-AU9 # AU9 to the Topological FPGA MGTREFCLK0N_111 NET 'CLK_320MHz64_LHC_TP_QUAD_114_DIR' U2-AB8 # AB8 320.64 MHz LHC GTX Clk #2 MGTREFCLK0P_114 NET 'CLK_320MHz64_LHC_TP_QUAD_114_CMP' U2-AB7 # AB7 to the Topological FPGA MGTREFCLK0N_114 NET 'CLK_320MHz64_LHC_TP_QUAD_117_DIR' U2-G10 # G10 320.64 MHz LHC GTX Clk #3 MGTREFCLK0P_117 NET 'CLK_320MHz64_LHC_TP_QUAD_117_CMP' U2-G9 # G9 to the Topological FPGA MGTREFCLK0N_117 # # Now on the Topological Processor FPGA connect ALL of the # UN-Used Tranceiver Clock Inputs to single point nets. # # Not Used Bank 110 Clock Input NET 'No_Conn_TP_GTX_CLK_1_110_DIR' U2-AW10 # pin AW10 MGTREFCLK1P_110 NET 'No_Conn_TP_GTX_CLK_1_110_CMP' U2-AW9 # pin AW9 MGTREFCLK1N_110 # Not Used Bank 111 Clock Input NET 'No_Conn_TP_GTX_CLK_1_111_DIR' U2-AT8 # pin AT8 MGTREFCLK1P_111 NET 'No_Conn_TP_GTX_CLK_1_111_CMP' U2-AT7 # pin AT7 MGTREFCLK1N_111 # Not Used Bank 112 Clock Inputs NET 'No_Conn_TP_GTX_CLK_0_112_DIR' U2-AK8 # pin AK8 MGTREFCLK0P_112 NET 'No_Conn_TP_GTX_CLK_0_112_CMP' U2-AK7 # pin AK7 MGTREFCLK0N_112 NET 'No_Conn_TP_GTX_CLK_1_112_DIR' U2-AH8 # pin AH8 MGTREFCLK1P_112 NET 'No_Conn_TP_GTX_CLK_1_112_CMP' U2-AH7 # pin AH7 MGTREFCLK1N_112 # Not Used Bank 113 Clock Inputs NET 'No_Conn_TP_GTX_CLK_0_113_DIR' U2-AF8 # pin AF8 MGTREFCLK0P_113 NET 'No_Conn_TP_GTX_CLK_0_113_CMP' U2-AF7 # pin AF7 MGTREFCLK0N_113 NET 'No_Conn_TP_GTX_CLK_1_113_DIR' U2-AD8 # pin AD8 MGTREFCLK1P_113 NET 'No_Conn_TP_GTX_CLK_1_113_CMP' U2-AD7 # pin AD7 MGTREFCLK1N_113 # Not Used Bank 114 Clock Input NET 'No_Conn_TP_GTX_CLK_1_114_DIR' U2-Y8 # pin Y8 MGTREFCLK1P_114 NET 'No_Conn_TP_GTX_CLK_1_114_CMP' U2-Y7 # pin Y7 MGTREFCLK1N_114 # Not Used Bank 115 Clock Inputs NET 'No_Conn_TP_GTX_CLK_0_115_DIR' U2-V8 # pin V8 MGTREFCLK0P_115 NET 'No_Conn_TP_GTX_CLK_0_115_CMP' U2-V7 # pin V7 MGTREFCLK0N_115 NET 'No_Conn_TP_GTX_CLK_1_115_DIR' U2-T8 # pin T8 MGTREFCLK1P_115 NET 'No_Conn_TP_GTX_CLK_1_115_CMP' U2-T7 # pin T7 MGTREFCLK1N_115 # Not Used Bank 116 Clock Inputs NET 'No_Conn_TP_GTX_CLK_0_116_DIR' U2-M8 # pin M8 MGTREFCLK0P_116 NET 'No_Conn_TP_GTX_CLK_0_116_CMP' U2-M7 # pin M7 MGTREFCLK0N_116 NET 'No_Conn_TP_GTX_CLK_1_116_DIR' U2-K8 # pin K8 MGTREFCLK1P_116 NET 'No_Conn_TP_GTX_CLK_1_116_CMP' U2-K7 # pin K7 MGTREFCLK1N_116 # Not Used Bank 117 Clock Input NET 'No_Conn_TP_GTX_CLK_1_117_DIR' U2-E10 # pin E10 MGTREFCLK1P_117 NET 'No_Conn_TP_GTX_CLK_1_117_CMP' U2-E9 # pin E9 MGTREFCLK1N_117 # Not Used Bank 118 Clock Inputs NET 'No_Conn_TP_GTX_CLK_0_118_DIR' U2-C10 # pin C10 MGTREFCLK0P_118 NET 'No_Conn_TP_GTX_CLK_0_118_CMP' U2-C9 # pin C9 MGTREFCLK0N_118 NET 'No_Conn_TP_GTX_CLK_1_118_DIR' U2-A10 # pin A10 MGTREFCLK1P_118 NET 'No_Conn_TP_GTX_CLK_1_118_CMP' U2-A9 # pin A9 MGTREFCLK1N_118 ############################################################################################ # # CMX Net-to-Resource File for the # Topo Function FPGA IO signals used for the connections to the TTC signals # -=============------------------------------------------================== # # # Original Rev. 28-Mar-2012 # Most Recent Rev. 04-Apr-2013 find location for these 53x signals # # ############################################################################################ # 53x signals are connecting to the buffered version of the TTCdec signals NET 'BUF_TTC_BRCST_2' U2-BB34 #> F07 #> T07 BB34 IO_L15P_12 NET 'BUF_TTC_BRCST_3' U2-BA34 #> F07 #> T07 BA34 IO_L15N_12 NET 'BUF_TTC_BRCST_4' U2-BA35 #> F07 #> T07 BA35 IO_L17P_12 NET 'BUF_TTC_BRCST_5' U2-BB36 #> F07 #> T07 BB36 IO_L13P_12 NET 'BUF_TTC_BRCST_6' U2-BA36 #> F07 #> T07 BA36 IO_L13N_12 NET 'BUF_TTC_BRCST_7' U2-BB37 #> F07 #> T07 BB37 IO_L11N_SRCC_12 NET 'BUF_TTC_BRCST_STR_1' U2-BA37 #> F07 #> T07 BA37 IO_L11P_SRCC_12 NET 'BUF_TTC_BRCST_STR_2' U2-BB38 #> F07 #> T07 BB38 IO_L7N_12 NET 'BUF_TTC_SIN_ERR_STR' U2-AY38 #> F07 #> T07 AY38 IO_L5P_12 NET 'BUF_TTC_DB_ERR_STR' U2-BB39 #> F07 #> T07 BB39 IO_L7P_12 NET 'BUF_TTC_CLK_40_L1A' U2-BA39 #> F07 #> T07 BA39 IO_L3N_12 NET 'BUF_TTC_BNCH_CNT_RES' U2-BA40 #> F07 #> T07 BA40 IO_L17P_13 NET 'BUF_TTC_EV_CNT_RES' U2-BB41 #> F07 #> T07 BB41 IO_L15N_13 NET 'BUF_TTC_EV_CNT_H_STR' U2-BA41 #> F07 #> T07 BA41 IO_L15P_13 NET 'BUF_TTC_EV_CNT_L_STR' U2-BA42 #> F07 #> T07 BA42 IO_L13N_13 NET 'BUF_TTC_BNCH_CNT_STR' U2-AY39 #> F07 #> T07 AY39 IO_L3P_12 NET 'BUF_TTC_B_CNT_0' U2-AY40 #> F07 #> T07 AY40 IO_L17N_13 NET 'BUF_TTC_B_CNT_1' U2-AY42 #> F07 #> T07 AY42 IO_L13P_13 NET 'BUF_TTC_B_CNT_2' U2-AW40 #> F07 #> T07 AW40 IO_L19N_13 NET 'BUF_TTC_B_CNT_3' U2-AW41 #> F07 #> T07 AW41 IO_L7N_13 NET 'BUF_TTC_B_CNT_4' U2-AW42 #> F07 #> T07 AW42 IO_L7P_13 NET 'BUF_TTC_B_CNT_5' U2-AV40 #> F07 #> T07 AV40 IO_L19P_13 NET 'BUF_TTC_B_CNT_6' U2-AV41 #> F07 #> T07 AV41 IO_L11P_SRCC_13 NET 'BUF_TTC_B_CNT_7' U2-AU39 #> F07 #> T07 AU39 IO_L10N_MRCC_13 NET 'BUF_TTC_B_CNT_8' U2-AU41 #> F07 #> T07 AU41 IO_L11N_SRCC_13 NET 'BUF_TTC_B_CNT_9' U2-AU42 #> F07 #> T07 AU42 IO_L5N_13 NET 'BUF_TTC_B_CNT_10' U2-AT40 #> F07 #> T07 AT40 IO_L10P_MRCC_13 NET 'BUF_TTC_B_CNT_11' U2-AT41 #> F07 #> T07 AT41 IO_L8N_SRCC_13 NET 'BUF_TTC_DQ_0' U2-AT42 #> F07 #> T07 AT42 IO_L5P_13 NET 'BUF_TTC_DQ_1' U2-AR39 #> F07 #> T07 AR39 IO_L14P_13 NET 'BUF_TTC_DQ_2' U2-AR40 #> F07 #> T07 AR40 IO_L8P_SRCC_13 NET 'BUF_TTC_DQ_3' U2-AR42 #> F07 #> T07 AR42 IO_L3N_13 NET 'BUF_TTC_L1_ACCEPT' U2-AP40 #> F07 #> T07 AP40 IO_L0N_13 NET 'BUF_TTC_SER_B_CH' U2-AP41 #> F07 #> T07 AP41 IO_L1N_13 NET 'BUF_TTC_D_OUT_STR' U2-AP42 #> F07 #> T07 AP42 IO_L3P_13 NET 'BUF_TTC_READY' U2-AN40 #> F07 #> T07 AN40 IO_L0P_13 NET 'BUF_TTC_STATUS_2' U2-AN41 #> F07 #> T07 AN41 IO_L1P_13 NET 'BUF_TTC_D_OUT_0' U2-AM39 #> F07 #> T07 AM39 IO_L2N_13 NET 'BUF_TTC_D_OUT_1' U2-AM41 #> F07 #> T07 AM41 IO_L15N_14 NET 'BUF_TTC_D_OUT_2' U2-AM42 #> F07 #> T07 AM42 IO_L13N_14 NET 'BUF_TTC_D_OUT_3' U2-AL40 #> F07 #> T07 AL40 IO_L17N_14 NET 'BUF_TTC_D_OUT_4' U2-AL41 #> F07 #> T07 AL41 IO_L15P_14 NET 'BUF_TTC_D_OUT_5' U2-AL42 #> F07 #> T07 AL42 IO_L13P_14 NET 'BUF_TTC_D_OUT_6' U2-AK39 #> F07 #> T07 AK39 IO_L19P_14 NET 'BUF_TTC_D_OUT_7' U2-AK40 #> F07 #> T07 AK40 IO_L17P_14 NET 'BUF_TTC_SUB_ADRS_0' U2-AK42 #> F07 #> T07 AK42 IO_L7N_14 NET 'BUF_TTC_SUB_ADRS_1' U2-AJ40 #> F07 #> T07 AJ40 IO_L11N_SRCC_14 NET 'BUF_TTC_SUB_ADRS_2' U2-AJ41 #> F07 #> T07 AJ41 IO_L5N_14 NET 'BUF_TTC_SUB_ADRS_3' U2-AJ42 #> F07 #> T07 AJ42 IO_L7P_14 NET 'BUF_TTC_SUB_ADRS_4' U2-AH40 #> F07 #> T07 AH40 IO_L5P_14 NET 'BUF_TTC_SUB_ADRS_5' U2-AH41 #> F07 #> T07 AH41 IO_L3N_14 NET 'BUF_TTC_SUB_ADRS_6' U2-AG41 #> F07 #> T07 AG41 IO_L1N_14 NET 'BUF_TTC_SUB_ADRS_7' U2-AG42 #> F07 #> T07 AG42 IO_L3P_14 ############################################################################################ # # CMX Net-to-Resource File for the # Topo Function FPGA IO signals used for the connections to the TP FPGA # -=============------------------------------------------================ # # Original Rev. 02-Apr-2012 # Rev. 03-Apr-2013 find location for these signals # Most Recent Rev. 20-Jun-2013 swap the two channels to ease trace routing # # BF to TP connections for support of S-link return channels # ========----------------------------====================== # # If the TP function needs to support S-link protocol (rather than G-link) # the CMX will need to receive the return channel of the Duplex S-link. # # The SFP optical receiver from the 2x S-link connections (DAQ and ROI) # cannot be directly received in the TP FPGA because all 36x MGT receivers # of the TP FPGA are already used with the 3x12 Avago optical receivers. # # The SFP optical receivers are instead routed to MGT receivers located # on the BF FPGA and the serial signal received is sent from the BF FPGA # to the TP FPGA via two differential Select IO signals. # # Signal Nets referenced in this file: # ------------------------------------ # # BF_TO_TP_DAQ_SLINK_RETURN_DIR Direct signal # BF_TO_TP_DAQ_SLINK_RETURN_CMP Complement signal # for the return S-link channel for DAQ readout # # BF_TO_TP_ROI_SLINK_RETURN_DIR Direct signal # BF_TO_TP_ROI_SLINK_RETURN_CMP Complement signal # for the return S-link channel for ROI readout # ############################################################################################ # 4x Select IO pins forming 2x differential signals going to the TP FPGA # This is IO Bank 26 and the signals will be routed north on trace layer 6. NET 'BF_TO_TP_DAQ_SLINK_RETURN_DIR' U2-A40 #> F06 #> T06 A40 IO_L7P_26 NET 'BF_TO_TP_DAQ_SLINK_RETURN_CMP' U2-A41 #> F06 #> T06 A41 IO_L7N_26 NET 'BF_TO_TP_ROI_SLINK_RETURN_DIR' U2-B38 #> F06 #> T06 B38 IO_L3P_26 NET 'BF_TO_TP_ROI_SLINK_RETURN_CMP' U2-A39 #> F06 #> T06 A39 IO_L3N_26 ############################################################################################ # # CMX Net-to-Resource File for the # Topo Function FPGA IO signals used for the connections to the Board Support FPGA # -=============------------------------------------------========================== # # # Original Rev. 28-Mar-2012 # Rev. 03-Apr-2013 find location for these 15x signals # Most Recent Rev. 20-Jun-2013 Swap TP_TO_FROM_BSPT_6 and _7 to help trace layout # # Signal Nets referenced in this file: # ------------------------------------ # # TP_REQ_CTP_n_INPUT (n=1:2) 2x direction request for CTP cable n sent to BSPT FPGA # # TP_LED_REQ_n (n=0:4) 5x LED state request sent to BSPT FPGA # # TP_TO_FROM_BSPT_n (n=0:7) 8x un-assigned Input or Ouput connections to BSPT FPGA # ############################################################################################ # 15x signals are going to the Board Support FPGA on layer 7 # These signals are listed in west to east order as they leave the FPGA area on layer 7 NET 'TP_REQ_CTP_1_INPUT' U2-A32 #> F07 #> T07 A32 IO_L1P_27 NET 'TP_REQ_CTP_2_INPUT' U2-B32 #> F07 #> T07 B32 IO_L1N_27 NET 'TP_LED_REQ_0' U2-B33 #> F07 #> T07 B33 IO_L3P_27 NET 'TP_LED_REQ_1' U2-A34 #> F07 #> T07 A34 IO_L5P_27 NET 'TP_LED_REQ_2' U2-B34 #> F01 #> T07 B34 IO_L7P_27 NET 'TP_LED_REQ_3' U2-A35 #> F01 #> T07 A35 IO_L5N_27 NET 'TP_LED_REQ_4' U2-C35 #> F01 #> T07 C35 IO_L15P_27 NET 'TP_TO_FROM_BSPT_0' U2-A36 #> F06 #> T07 A36 IO_L13P_27 NET 'TP_TO_FROM_BSPT_1' U2-B36 #> F06 #> T07 B36 IO_L13N_27 NET 'TP_TO_FROM_BSPT_2' U2-A37 #> F01 #> T07 A37 IO_L1N_26 NET 'TP_TO_FROM_BSPT_3' U2-B37 #> F01 #> T07 B37 IO_L1P_26 NET 'TP_TO_FROM_BSPT_4' U2-C38 #> F01 #> T07 C38 IO_L6N_26 NET 'TP_TO_FROM_BSPT_5' U2-B39 #> F07 #> T07 B39 IO_L5P_26 NET 'TP_TO_FROM_BSPT_6' U2-B41 #> F07 #> T07 B41 IO_L11P_SRCC_26 NET 'TP_TO_FROM_BSPT_7' U2-C40 #> F07 #> T07 C40 IO_L13P_26 ############################################################################################ # # CMX Net-to-Resource File for the # Topo Function FPGA IO signals used for the connections to the Debug Connector # -=============------------------------------------------====================== # # # Original Rev. 28-Mar-2012 # Rev. 03-Apr-2013 find location for these 10x signals without interfering with backplane inputs # Most Recent Rev: 10-Jul-2013 Reorder pin assignment for straight route near debug connector # # Signal Nets referenced in this file: # ------------------------------------ # # TP_DEBUG_n (n=0:9) 10x spare connections from the BF FPGA to debug connector J14 # ############################################################################################ # 10x signals are going to the Debug Connector on layer 6 NET 'TP_DEBUG_0' U2-F42 #> F06 #> T06 F42 IO_L19N_26 NET 'TP_DEBUG_1' U2-D41 #> F06 #> T06 D41 IO_L15N_26 NET 'TP_DEBUG_2' U2-F41 #> F06 #> T06 F41 IO_L16N_26 NET 'TP_DEBUG_3' U2-D42 #> F06 #> T06 D42 IO_L15P_26 NET 'TP_DEBUG_4' U2-E42 #> F06 #> T06 E42 IO_L19P_26 NET 'TP_DEBUG_5' U2-E40 #> F06 #> T06 E40 IO_L17N_26 NET 'TP_DEBUG_6' U2-G41 #> F06 #> T06 G41 IO_L18P_26 NET 'TP_DEBUG_7' U2-C41 #> F06 #> T06 C41 IO_L13N_26 NET 'TP_DEBUG_8' U2-G42 #> F06 #> T06 G42 IO_L18N_26 NET 'TP_DEBUG_9' U2-B42 #> F06 #> T06 B42 IO_L11N_SRCC_26 ############################################################################################ # # CMX Net-to-Resource File for the # TP Function FPGA IO signals used for all unused and Not Connected MGT IO pins # -=============-----------------------------------------====================---------- # # # Original Rev. 17-Jan-2013 # Most Recent Rev. 17-Jan-2013 Initial roundup # # # On the TP Function FPGA connect ALL of the # UN-Used Tranceiver IO Pins to single point nets. # # Signal Nets referenced in this file: # ------------------------------------ # # 'No_Conn_TP_xxxx' are the unique net names assigned to these MGT IO signals # where "xxxx" is the fpga MGT IO signal name # ############################################################################################ ################ # Receivers ################ # All Receiver Channels from MGT Quad 110 to 118 are used to field the miniPOD recievers # Those nets are defined in tp_function_gtx_receivers_n2r.txt # ################ # Transmitters ################ # Two of the Tramsmitter channels from MGT Quad 110 are used for the g-link output # Those nets are defined in base_function_low_speed_daq_roi_data_out_n2r.txt # The other two channels are unused NET 'No_Conn_TP_MGTTXP2_110' U2-AY3 # 110 AY3 MGTTXP2_110 NET 'No_Conn_TP_MGTTXN2_110' U2-AY4 # 110 AY4 MGTTXN2_110 NET 'No_Conn_TP_MGTTXP3_110' U2-AW1 # 110 AW1 MGTTXP3_110 NET 'No_Conn_TP_MGTTXN3_110' U2-AW2 # 110 AW2 MGTTXN3_110 # All Tramsmitter Channels from MGT Quad 111 are unused NET 'No_Conn_TP_MGTTXP0_111' U2-AV3 # 111 AV3 MGTTXP0_111 NET 'No_Conn_TP_MGTTXN0_111' U2-AV4 # 111 AV4 MGTTXN0_111 NET 'No_Conn_TP_MGTTXP1_111' U2-AU1 # 111 AU1 MGTTXP1_111 NET 'No_Conn_TP_MGTTXN1_111' U2-AU2 # 111 AU2 MGTTXN1_111 NET 'No_Conn_TP_MGTTXP2_111' U2-AT3 # 111 AT3 MGTTXP2_111 NET 'No_Conn_TP_MGTTXN2_111' U2-AT4 # 111 AT4 MGTTXN2_111 NET 'No_Conn_TP_MGTTXP3_111' U2-AR1 # 111 AR1 MGTTXP3_111 NET 'No_Conn_TP_MGTTXN3_111' U2-AR2 # 111 AR2 MGTTXN3_111 # All Tramsmitter Channels from MGT Quad 112 are unused NET 'No_Conn_TP_MGTTXP0_112' U2-AP3 # 112 AP3 MGTTXP0_112 NET 'No_Conn_TP_MGTTXN0_112' U2-AP4 # 112 AP4 MGTTXN0_112 NET 'No_Conn_TP_MGTTXP1_112' U2-AN1 # 112 AN1 MGTTXP1_112 NET 'No_Conn_TP_MGTTXN1_112' U2-AN2 # 112 AN2 MGTTXN1_112 NET 'No_Conn_TP_MGTTXP2_112' U2-AM3 # 112 AM3 MGTTXP2_112 NET 'No_Conn_TP_MGTTXN2_112' U2-AM4 # 112 AM4 MGTTXN2_112 NET 'No_Conn_TP_MGTTXP3_112' U2-AL1 # 112 AL1 MGTTXP3_112 NET 'No_Conn_TP_MGTTXN3_112' U2-AL2 # 112 AL2 MGTTXN3_112 # All Tramsmitter Channels from MGT Quad 113 are unused NET 'No_Conn_TP_MGTTXP0_113' U2-AK3 # 113 AK3 MGTTXP0_113 NET 'No_Conn_TP_MGTTXN0_113' U2-AK4 # 113 AK4 MGTTXN0_113 NET 'No_Conn_TP_MGTTXP1_113' U2-AJ1 # 113 AJ1 MGTTXP1_113 NET 'No_Conn_TP_MGTTXN1_113' U2-AJ2 # 113 AJ2 MGTTXN1_113 NET 'No_Conn_TP_MGTTXP2_113' U2-AH3 # 113 AH3 MGTTXP2_113 NET 'No_Conn_TP_MGTTXN2_113' U2-AH4 # 113 AH4 MGTTXN2_113 NET 'No_Conn_TP_MGTTXP3_113' U2-AG1 # 113 AG1 MGTTXP3_113 NET 'No_Conn_TP_MGTTXN3_113' U2-AG2 # 113 AG2 MGTTXN3_113 # All Tramsmitter Channels from MGT Quad 114 are unused NET 'No_Conn_TP_MGTTXP0_114' U2-AE1 # 114 AE1 MGTTXP0_114 NET 'No_Conn_TP_MGTTXN0_114' U2-AE2 # 114 AE2 MGTTXN0_114 NET 'No_Conn_TP_MGTTXP1_114' U2-AC1 # 114 AC1 MGTTXP1_114 NET 'No_Conn_TP_MGTTXN1_114' U2-AC2 # 114 AC2 MGTTXN1_114 NET 'No_Conn_TP_MGTTXP2_114' U2-AA1 # 114 AA1 MGTTXP2_114 NET 'No_Conn_TP_MGTTXN2_114' U2-AA2 # 114 AA2 MGTTXN2_114 NET 'No_Conn_TP_MGTTXP3_114' U2-W1 # 114 W1 MGTTXP3_114 NET 'No_Conn_TP_MGTTXN3_114' U2-W2 # 114 W2 MGTTXN3_114 # All Tramsmitter Channels from MGT Quad 115 are unused NET 'No_Conn_TP_MGTTXP0_115' U2-U1 # 115 U1 MGTTXP0_115 NET 'No_Conn_TP_MGTTXN0_115' U2-U2 # 115 U2 MGTTXN0_115 NET 'No_Conn_TP_MGTTXP1_115' U2-T3 # 115 T3 MGTTXP1_115 NET 'No_Conn_TP_MGTTXN1_115' U2-T4 # 115 T4 MGTTXN1_115 NET 'No_Conn_TP_MGTTXP2_115' U2-R1 # 115 R1 MGTTXP2_115 NET 'No_Conn_TP_MGTTXN2_115' U2-R2 # 115 R2 MGTTXN2_115 NET 'No_Conn_TP_MGTTXP3_115' U2-P3 # 115 P3 MGTTXP3_115 NET 'No_Conn_TP_MGTTXN3_115' U2-P4 # 115 P4 MGTTXN3_115 # All Tramsmitter Channels from MGT Quad 116 are unused NET 'No_Conn_TP_MGTTXP0_116' U2-N1 # 116 N1 MGTTXP0_116 NET 'No_Conn_TP_MGTTXN0_116' U2-N2 # 116 N2 MGTTXN0_116 NET 'No_Conn_TP_MGTTXP1_116' U2-M3 # 116 M3 MGTTXP1_116 NET 'No_Conn_TP_MGTTXN1_116' U2-M4 # 116 M4 MGTTXN1_116 NET 'No_Conn_TP_MGTTXP2_116' U2-L1 # 116 L1 MGTTXP2_116 NET 'No_Conn_TP_MGTTXN2_116' U2-L2 # 116 L2 MGTTXN2_116 NET 'No_Conn_TP_MGTTXP3_116' U2-K3 # 116 K3 MGTTXP3_116 NET 'No_Conn_TP_MGTTXN3_116' U2-K4 # 116 K4 MGTTXN3_116 # All Tramsmitter Channels from MGT Quad 117 are unused NET 'No_Conn_TP_MGTTXP0_117' U2-J1 # 117 J1 MGTTXP0_117 NET 'No_Conn_TP_MGTTXN0_117' U2-J2 # 117 J2 MGTTXN0_117 NET 'No_Conn_TP_MGTTXP1_117' U2-H3 # 117 H3 MGTTXP1_117 NET 'No_Conn_TP_MGTTXN1_117' U2-H4 # 117 H4 MGTTXN1_117 NET 'No_Conn_TP_MGTTXP2_117' U2-G1 # 117 G1 MGTTXP2_117 NET 'No_Conn_TP_MGTTXN2_117' U2-G2 # 117 G2 MGTTXN2_117 NET 'No_Conn_TP_MGTTXP3_117' U2-F3 # 117 F3 MGTTXP3_117 NET 'No_Conn_TP_MGTTXN3_117' U2-F4 # 117 F4 MGTTXN3_117 # All Tramsmitter Channels from MGT Quad 118 are unused NET 'No_Conn_TP_MGTTXP0_118' U2-E1 # 118 E1 MGTTXP0_118 NET 'No_Conn_TP_MGTTXN0_118' U2-E2 # 118 E2 MGTTXN0_118 NET 'No_Conn_TP_MGTTXP1_118' U2-D3 # 118 D3 MGTTXP1_118 NET 'No_Conn_TP_MGTTXN1_118' U2-D4 # 118 D4 MGTTXN1_118 NET 'No_Conn_TP_MGTTXP2_118' U2-C1 # 118 C1 MGTTXP2_118 NET 'No_Conn_TP_MGTTXN2_118' U2-C2 # 118 C2 MGTTXN2_118 NET 'No_Conn_TP_MGTTXP3_118' U2-B3 # 118 B3 MGTTXP3_118 NET 'No_Conn_TP_MGTTXN3_118' U2-B4 # 118 B4 MGTTXN3_118 ############################################################################################ # # CMX Net-to-Resource File for the # TP Function FPGA IO signals used for all unused and Not Connected Select IO pins # -=============-----------------------------------------=======================------- # # # Original Rev. 17-Jan-2013 # Rev. 17-Jan-2013 Initial roundup # Most Recent Rev. 04-Apr-2013 Remove pins now assigned to connections to Board Support FPGA, # Debug Connector, BF to TP S-Link, and TTC signals. # # Signal Nets referenced in this file: # ------------------------------------ # # 'No_Conn_TP_xxxx' are the unique net names assigned to these Select IO signals # where "xxxx" is the fpga Select IO signal name # ############################################################################################ # Unused pins from IO bank 12 ############################# # note: This bank is otherwise used for TTC connections NET 'No_Conn_TP_IO_L9P_MRCC_12' U2-AN35 # 12 AN35 IO_L9P_MRCC_12 NET 'No_Conn_TP_IO_L9N_MRCC_12' U2-AN36 # 12 AN36 IO_L9N_MRCC_12 NET 'No_Conn_TP_IO_L10N_MRCC_12' U2-AP35 # 12 AP35 IO_L10N_MRCC_12 NET 'No_Conn_TP_IO_L10P_MRCC_12' U2-AP36 # 12 AP36 IO_L10P_MRCC_12 NET 'No_Conn_TP_IO_L2P_12' U2-AP37 # 12 AP37 IO_L2P_12 NET 'No_Conn_TP_IO_L12P_VRN_12' U2-AR35 # 12 AR35 IO_L12P_VRN_12 NET 'No_Conn_TP_IO_L2N_12' U2-AR37 # 12 AR37 IO_L2N_12 NET 'No_Conn_TP_IO_L0N_12' U2-AR38 # 12 AR38 IO_L0N_12 NET 'No_Conn_TP_IO_L16N_12' U2-AT34 # 12 AT34 IO_L16N_12 NET 'No_Conn_TP_IO_L12N_VRP_12' U2-AT35 # 12 AT35 IO_L12N_VRP_12 NET 'No_Conn_TP_IO_L6N_12' U2-AT36 # 12 AT36 IO_L6N_12 NET 'No_Conn_TP_IO_L0P_12' U2-AT37 # 12 AT37 IO_L0P_12 NET 'No_Conn_TP_IO_L16P_12' U2-AU34 # 12 AU34 IO_L16P_12 NET 'No_Conn_TP_IO_L6P_12' U2-AU36 # 12 AU36 IO_L6P_12 NET 'No_Conn_TP_IO_L4P_12' U2-AU37 # 12 AU37 IO_L4P_12 NET 'No_Conn_TP_IO_L4N_VREF_12' U2-AU38 # 12 AU38 IO_L4N_VREF_12 NET 'No_Conn_TP_IO_L18P_12' U2-AV34 # 12 AV34 IO_L18P_12 NET 'No_Conn_TP_IO_L18N_12' U2-AV35 # 12 AV35 IO_L18N_12 NET 'No_Conn_TP_IO_L14N_VREF_12' U2-AV36 # 12 AV36 IO_L14N_VREF_12 NET 'No_Conn_TP_IO_L1N_12' U2-AV38 # 12 AV38 IO_L1N_12 NET 'No_Conn_TP_IO_L1P_12' U2-AV39 # 12 AV39 IO_L1P_12 NET 'No_Conn_TP_IO_L19N_12' U2-AW35 # 12 AW35 IO_L19N_12 NET 'No_Conn_TP_IO_L14P_12' U2-AW36 # 12 AW36 IO_L14P_12 NET 'No_Conn_TP_IO_L8P_SRCC_12' U2-AW37 # 12 AW37 IO_L8P_SRCC_12 NET 'No_Conn_TP_IO_L8N_SRCC_12' U2-AW38 # 12 AW38 IO_L8N_SRCC_12 NET 'No_Conn_TP_IO_L19P_12' U2-AY34 # 12 AY34 IO_L19P_12 NET 'No_Conn_TP_IO_L17N_12' U2-AY35 # 12 AY35 IO_L17N_12 NET 'No_Conn_TP_IO_L5N_12' U2-AY37 # 12 AY37 IO_L5N_12 # Unused pins from IO bank 13 ############################# # note: This bank is otherwise used for TTC connections NET 'No_Conn_TP_IO_L9N_MRCC_13' U2-AK34 # 13 AK34 IO_L9N_MRCC_13 NET 'No_Conn_TP_IO_L18P_13' U2-AK35 # 13 AK35 IO_L18P_13 NET 'No_Conn_TP_IO_L9P_MRCC_13' U2-AL34 # 13 AL34 IO_L9P_MRCC_13 NET 'No_Conn_TP_IO_L6N_13' U2-AL35 # 13 AL35 IO_L6N_13 NET 'No_Conn_TP_IO_L18N_13' U2-AL36 # 13 AL36 IO_L18N_13 NET 'No_Conn_TP_IO_L4P_13' U2-AL37 # 13 AL37 IO_L4P_13 NET 'No_Conn_TP_IO_L6P_13' U2-AM34 # 13 AM34 IO_L6P_13 NET 'No_Conn_TP_IO_L16N_13' U2-AM36 # 13 AM36 IO_L16N_13 NET 'No_Conn_TP_IO_L16P_13' U2-AM37 # 13 AM37 IO_L16P_13 NET 'No_Conn_TP_IO_L4N_VREF_13' U2-AM38 # 13 AM38 IO_L4N_VREF_13 NET 'No_Conn_TP_IO_L12P_VRN_13' U2-AN38 # 13 AN38 IO_L12P_VRN_13 NET 'No_Conn_TP_IO_L2P_13' U2-AN39 # 13 AN39 IO_L2P_13 NET 'No_Conn_TP_IO_L12N_VRP_13' U2-AP38 # 13 AP38 IO_L12N_VRP_13 NET 'No_Conn_TP_IO_L14N_VREF_13' U2-AT39 # 13 AT39 IO_L14N_VREF_13 # Unused pins from IO bank 14 ############################# # note: This bank is otherwise used for TTC connections NET 'No_Conn_TP_IO_L18P_14' U2-AF32 # 14 AF32 IO_L18P_14 NET 'No_Conn_TP_IO_L0N_14' U2-AF34 # 14 AF34 IO_L0N_14 NET 'No_Conn_TP_IO_L16P_14' U2-AF35 # 14 AF35 IO_L16P_14 NET 'No_Conn_TP_IO_L16N_14' U2-AF36 # 14 AF36 IO_L16N_14 NET 'No_Conn_TP_IO_L6P_14' U2-AF37 # 14 AF37 IO_L6P_14 NET 'No_Conn_TP_IO_L2P_14' U2-AF39 # 14 AF39 IO_L2P_14 NET 'No_Conn_TP_IO_L1P_14' U2-AF40 # 14 AF40 IO_L1P_14 NET 'No_Conn_TP_IO_L18N_14' U2-AG33 # 14 AG33 IO_L18N_14 NET 'No_Conn_TP_IO_L0P_14' U2-AG34 # 14 AG34 IO_L0P_14 NET 'No_Conn_TP_IO_L14P_14' U2-AG36 # 14 AG36 IO_L14P_14 NET 'No_Conn_TP_IO_L6N_14' U2-AG37 # 14 AG37 IO_L6N_14 NET 'No_Conn_TP_IO_L4P_14' U2-AG38 # 14 AG38 IO_L4P_14 NET 'No_Conn_TP_IO_L2N_14' U2-AG39 # 14 AG39 IO_L2N_14 NET 'No_Conn_TP_IO_L9P_MRCC_14' U2-AH34 # 14 AH34 IO_L9P_MRCC_14 NET 'No_Conn_TP_IO_L12N_VRP_14' U2-AH35 # 14 AH35 IO_L12N_VRP_14 NET 'No_Conn_TP_IO_L14N_VREF_14' U2-AH36 # 14 AH36 IO_L14N_VREF_14 NET 'No_Conn_TP_IO_L4N_VREF_14' U2-AH38 # 14 AH38 IO_L4N_VREF_14 NET 'No_Conn_TP_IO_L11P_SRCC_14' U2-AH39 # 14 AH39 IO_L11P_SRCC_14 NET 'No_Conn_TP_IO_L9N_MRCC_14' U2-AJ35 # 14 AJ35 IO_L9N_MRCC_14 NET 'No_Conn_TP_IO_L12P_VRN_14' U2-AJ36 # 14 AJ36 IO_L12P_VRN_14 NET 'No_Conn_TP_IO_L10P_MRCC_14' U2-AJ37 # 14 AJ37 IO_L10P_MRCC_14 NET 'No_Conn_TP_IO_L8N_SRCC_14' U2-AJ38 # 14 AJ38 IO_L8N_SRCC_14 NET 'No_Conn_TP_IO_L10N_MRCC_14' U2-AK37 # 14 AK37 IO_L10N_MRCC_14 NET 'No_Conn_TP_IO_L8P_SRCC_14' U2-AK38 # 14 AK38 IO_L8P_SRCC_14 NET 'No_Conn_TP_IO_L19N_14' U2-AL39 # 14 AL39 IO_L19N_14 # Unused pins from IO bank 15 ############################# # note: some pins from this bank are used for the On-Card Bus NET 'No_Conn_TP_IO_L12P_SM13P_15' U2-AB32 # 15 AB32 IO_L12P_SM13P_15 NET 'No_Conn_TP_IO_L12N_SM13N_15' U2-AB33 # 15 AB33 IO_L12N_SM13N_15 NET 'No_Conn_TP_IO_L16N_VRP_15' U2-AB34 # 15 AB34 IO_L16N_VRP_15 NET 'No_Conn_TP_IO_L8N_SRCC_15' U2-AB36 # 15 AB36 IO_L8N_SRCC_15 NET 'No_Conn_TP_IO_L1P_15' U2-AB37 # 15 AB37 IO_L1P_15 NET 'No_Conn_TP_IO_L18N_15' U2-AC33 # 15 AC33 IO_L18N_15 NET 'No_Conn_TP_IO_L18P_15' U2-AC34 # 15 AC34 IO_L18P_15 NET 'No_Conn_TP_IO_L16P_VRN_15' U2-AC35 # 15 AC35 IO_L16P_VRN_15 NET 'No_Conn_TP_IO_L8P_SRCC_15' U2-AC36 # 15 AC36 IO_L8P_SRCC_15 NET 'No_Conn_TP_IO_L4P_15' U2-AC38 # 15 AC38 IO_L4P_15 NET 'No_Conn_TP_IO_L9P_MRCC_15' U2-AD32 # 15 AD32 IO_L9P_MRCC_15 NET 'No_Conn_TP_IO_L2N_SM8N_15' U2-AD33 # 15 AD33 IO_L2N_SM8N_15 NET 'No_Conn_TP_IO_L14N_VREF_15' U2-AD35 # 15 AD35 IO_L14N_VREF_15 NET 'No_Conn_TP_IO_L14P_15' U2-AD36 # 15 AD36 IO_L14P_15 NET 'No_Conn_TP_IO_L10N_MRCC_15' U2-AD37 # 15 AD37 IO_L10N_MRCC_15 NET 'No_Conn_TP_IO_L6N_SM11N_15' U2-AD38 # 15 AD38 IO_L6N_SM11N_15 NET 'No_Conn_TP_IO_L9N_MRCC_15' U2-AE32 # 15 AE32 IO_L9N_MRCC_15 NET 'No_Conn_TP_IO_L2P_SM8P_15' U2-AE33 # 15 AE33 IO_L2P_SM8P_15 NET 'No_Conn_TP_IO_L0P_15' U2-AE34 # 15 AE34 IO_L0P_15 NET 'No_Conn_TP_IO_L0N_15' U2-AE35 # 15 AE35 IO_L0N_15 NET 'No_Conn_TP_IO_L10P_MRCC_15' U2-AE37 # 15 AE37 IO_L10P_MRCC_15 NET 'No_Conn_TP_IO_L6P_SM11P_15' U2-AE38 # 15 AE38 IO_L6P_SM11P_15 # Unused pins from IO bank 16 ############################# # note: some pins from this bank are used for the On-Card Bus NET 'No_Conn_TP_IO_L16P_16' U2-U32 # 16 U32 IO_L16P_16 NET 'No_Conn_TP_IO_L16N_16' U2-U33 # 16 U33 IO_L16N_16 NET 'No_Conn_TP_IO_L10N_MRCC_16' U2-U34 # 16 U34 IO_L10N_MRCC_16 NET 'No_Conn_TP_IO_L1P_16' U2-U37 # 16 U37 IO_L1P_16 NET 'No_Conn_TP_IO_L1N_16' U2-U38 # 16 U38 IO_L1N_16 NET 'No_Conn_TP_IO_L18P_16' U2-V33 # 16 V33 IO_L18P_16 NET 'No_Conn_TP_IO_L10P_MRCC_16' U2-V34 # 16 V34 IO_L10P_MRCC_16 NET 'No_Conn_TP_IO_L6N_16' U2-V35 # 16 V35 IO_L6N_16 NET 'No_Conn_TP_IO_L2N_16' U2-V36 # 16 V36 IO_L2N_16 NET 'No_Conn_TP_IO_L7P_16' U2-V38 # 16 V38 IO_L7P_16 NET 'No_Conn_TP_IO_L5N_16' U2-V39 # 16 V39 IO_L5N_16 NET 'No_Conn_TP_IO_L18N_16' U2-W33 # 16 W33 IO_L18N_16 NET 'No_Conn_TP_IO_L6P_16' U2-W35 # 16 W35 IO_L6P_16 NET 'No_Conn_TP_IO_L2P_16' U2-W36 # 16 W36 IO_L2P_16 NET 'No_Conn_TP_IO_L0P_16' U2-W37 # 16 W37 IO_L0P_16 NET 'No_Conn_TP_IO_L12N_VRP_16' U2-Y32 # 16 Y32 IO_L12N_VRP_16 NET 'No_Conn_TP_IO_L9N_MRCC_16' U2-Y33 # 16 Y33 IO_L9N_MRCC_16 NET 'No_Conn_TP_IO_L14N_VREF_16' U2-Y34 # 16 Y34 IO_L14N_VREF_16 NET 'No_Conn_TP_IO_L8N_SRCC_16' U2-Y35 # 16 Y35 IO_L8N_SRCC_16 NET 'No_Conn_TP_IO_L0N_16' U2-Y37 # 16 Y37 IO_L0N_16 NET 'No_Conn_TP_IO_L19P_16' U2-Y38 # 16 Y38 IO_L19P_16 NET 'No_Conn_TP_IO_L12P_VRN_16' U2-AA32 # 16 AA32 IO_L12P_VRN_16 NET 'No_Conn_TP_IO_L14P_16' U2-AA34 # 16 AA34 IO_L14P_16 NET 'No_Conn_TP_IO_L8P_SRCC_16' U2-AA35 # 16 AA35 IO_L8P_SRCC_16 NET 'No_Conn_TP_IO_L4P_16' U2-AA36 # 16 AA36 IO_L4P_16 NET 'No_Conn_TP_IO_L4N_VREF_16' U2-AA37 # 16 AA37 IO_L4N_VREF_16 # Unused pins from IO bank 17 ############################# # note: some pins from this bank are used for the On-Card Bus NET 'No_Conn_TP_IO_L1P_17' U2-L39 # 17 L39 IO_L1P_17 NET 'No_Conn_TP_IO_L0P_17' U2-M36 # 17 M36 IO_L0P_17 NET 'No_Conn_TP_IO_L0N_17' U2-M37 # 17 M37 IO_L0N_17 NET 'No_Conn_TP_IO_L2P_17' U2-M38 # 17 M38 IO_L2P_17 NET 'No_Conn_TP_IO_L4N_VREF_17' U2-N34 # 17 N34 IO_L4N_VREF_17 NET 'No_Conn_TP_IO_L4P_17' U2-N35 # 17 N35 IO_L4P_17 NET 'No_Conn_TP_IO_L6P_17' U2-N36 # 17 N36 IO_L6P_17 NET 'No_Conn_TP_IO_L5P_17' U2-N38 # 17 N38 IO_L5P_17 NET 'No_Conn_TP_IO_L5N_17' U2-N39 # 17 N39 IO_L5N_17 NET 'No_Conn_TP_IO_L9N_MRCC_17' U2-P35 # 17 P35 IO_L9N_MRCC_17 NET 'No_Conn_TP_IO_L9P_MRCC_17' U2-P36 # 17 P36 IO_L9P_MRCC_17 NET 'No_Conn_TP_IO_L6N_17' U2-P37 # 17 P37 IO_L6N_17 NET 'No_Conn_TP_IO_L8N_SRCC_17' U2-P38 # 17 P38 IO_L8N_SRCC_17 NET 'No_Conn_TP_IO_L14N_VREF_17' U2-R34 # 17 R34 IO_L14N_VREF_17 NET 'No_Conn_TP_IO_L14P_17' U2-R35 # 17 R35 IO_L14P_17 NET 'No_Conn_TP_IO_L12P_VRN_17' U2-R37 # 17 R37 IO_L12P_VRN_17 NET 'No_Conn_TP_IO_L10N_MRCC_17' U2-R38 # 17 R38 IO_L10N_MRCC_17 NET 'No_Conn_TP_IO_L18P_17' U2-T34 # 17 T34 IO_L18P_17 NET 'No_Conn_TP_IO_L18N_17' U2-T35 # 17 T35 IO_L18N_17 NET 'No_Conn_TP_IO_L16N_17' U2-T36 # 17 T36 IO_L16N_17 NET 'No_Conn_TP_IO_L12N_VRP_17' U2-T37 # 17 T37 IO_L12N_VRP_17 NET 'No_Conn_TP_IO_L10P_MRCC_17' U2-T39 # 17 T39 IO_L10P_MRCC_17 NET 'No_Conn_TP_IO_L16P_17' U2-U36 # 17 U36 IO_L16P_17 # Unused pins from IO bank 21 ############################# NET 'No_Conn_TP_IO_L1N_21' U2-AJ22 # 21 AJ22 IO_L1N_21 NET 'No_Conn_TP_IO_L5P_21' U2-AJ23 # 21 AJ23 IO_L5P_21 NET 'No_Conn_TP_IO_L1P_21' U2-AK22 # 21 AK22 IO_L1P_21 NET 'No_Conn_TP_IO_L5N_21' U2-AK23 # 21 AK23 IO_L5N_21 NET 'No_Conn_TP_IO_L10P_MRCC_21' U2-AK24 # 21 AK24 IO_L10P_MRCC_21 NET 'No_Conn_TP_IO_L3N_21' U2-AL22 # 21 AL22 IO_L3N_21 NET 'No_Conn_TP_IO_L13N_21' U2-AL24 # 21 AL24 IO_L13N_21 NET 'No_Conn_TP_IO_L10N_MRCC_21' U2-AL25 # 21 AL25 IO_L10N_MRCC_21 NET 'No_Conn_TP_IO_L3P_21' U2-AM22 # 21 AM22 IO_L3P_21 NET 'No_Conn_TP_IO_L7P_21' U2-AM23 # 21 AM23 IO_L7P_21 NET 'No_Conn_TP_IO_L13P_21' U2-AM24 # 21 AM24 IO_L13P_21 NET 'No_Conn_TP_IO_L7N_21' U2-AN23 # 21 AN23 IO_L7N_21 NET 'No_Conn_TP_IO_L15P_21' U2-AN24 # 21 AN24 IO_L15P_21 NET 'No_Conn_TP_IO_L15N_21' U2-AN25 # 21 AN25 IO_L15N_21 NET 'No_Conn_TP_IO_L11P_SRCC_21' U2-AP23 # 21 AP23 IO_L11P_SRCC_21 NET 'No_Conn_TP_IO_L9P_MRCC_21' U2-AP25 # 21 AP25 IO_L9P_MRCC_21 NET 'No_Conn_TP_IO_L9N_MRCC_21' U2-AP26 # 21 AP26 IO_L9N_MRCC_21 NET 'No_Conn_TP_IO_L11N_SRCC_21' U2-AR23 # 21 AR23 IO_L11N_SRCC_21 NET 'No_Conn_TP_IO_L17P_21' U2-AR24 # 21 AR24 IO_L17P_21 NET 'No_Conn_TP_IO_L19N_21' U2-AR25 # 21 AR25 IO_L19N_21 NET 'No_Conn_TP_IO_L17N_21' U2-AT24 # 21 AT24 IO_L17N_21 NET 'No_Conn_TP_IO_L19P_21' U2-AT25 # 21 AT25 IO_L19P_21 NET 'No_Conn_TP_IO_L0P_21' U2-AT26 # 21 AT26 IO_L0P_21 NET 'No_Conn_TP_IO_L8P_SRCC_21' U2-AU23 # 21 AU23 IO_L8P_SRCC_21 NET 'No_Conn_TP_IO_L8N_SRCC_21' U2-AU24 # 21 AU24 IO_L8N_SRCC_21 NET 'No_Conn_TP_IO_L16N_21' U2-AU26 # 21 AU26 IO_L16N_21 NET 'No_Conn_TP_IO_L0N_21' U2-AU27 # 21 AU27 IO_L0N_21 NET 'No_Conn_TP_IO_L12P_VRN_21' U2-AV24 # 21 AV24 IO_L12P_VRN_21 NET 'No_Conn_TP_IO_L12N_VRP_21' U2-AV25 # 21 AV25 IO_L12N_VRP_21 NET 'No_Conn_TP_IO_L16P_21' U2-AV26 # 21 AV26 IO_L16P_21 NET 'No_Conn_TP_IO_L18P_21' U2-AW25 # 21 AW25 IO_L18P_21 NET 'No_Conn_TP_IO_L18N_21' U2-AW26 # 21 AW26 IO_L18N_21 NET 'No_Conn_TP_IO_L2N_21' U2-AW27 # 21 AW27 IO_L2N_21 NET 'No_Conn_TP_IO_L14N_VREF_21' U2-AY25 # 21 AY25 IO_L14N_VREF_21 NET 'No_Conn_TP_IO_L2P_21' U2-AY27 # 21 AY27 IO_L2P_21 NET 'No_Conn_TP_IO_L14P_21' U2-BA25 # 21 BA25 IO_L14P_21 NET 'No_Conn_TP_IO_L4P_21' U2-BA26 # 21 BA26 IO_L4P_21 NET 'No_Conn_TP_IO_L4N_VREF_21' U2-BA27 # 21 BA27 IO_L4N_VREF_21 NET 'No_Conn_TP_IO_L6P_21' U2-BB26 # 21 BB26 IO_L6P_21 NET 'No_Conn_TP_IO_L6N_21' U2-BB27 # 21 BB27 IO_L6N_21 # Unused pins from IO bank 22 ############################# NET 'No_Conn_TP_IO_L9N_MRCC_22' U2-AL26 # 22 AL26 IO_L9N_MRCC_22 NET 'No_Conn_TP_IO_L9P_MRCC_22' U2-AM26 # 22 AM26 IO_L9P_MRCC_22 NET 'No_Conn_TP_IO_L10N_MRCC_22' U2-AM27 # 22 AM27 IO_L10N_MRCC_22 NET 'No_Conn_TP_IO_L1P_22' U2-AN26 # 22 AN26 IO_L1P_22 NET 'No_Conn_TP_IO_L10P_MRCC_22' U2-AN28 # 22 AN28 IO_L10P_MRCC_22 NET 'No_Conn_TP_IO_L1N_22' U2-AP27 # 22 AP27 IO_L1N_22 NET 'No_Conn_TP_IO_L3N_22' U2-AP28 # 22 AP28 IO_L3N_22 NET 'No_Conn_TP_IO_L11P_SRCC_22' U2-AR27 # 22 AR27 IO_L11P_SRCC_22 NET 'No_Conn_TP_IO_L3P_22' U2-AR28 # 22 AR28 IO_L3P_22 NET 'No_Conn_TP_IO_L5N_22' U2-AR29 # 22 AR29 IO_L5N_22 NET 'No_Conn_TP_IO_L7N_22' U2-AR30 # 22 AR30 IO_L7N_22 NET 'No_Conn_TP_IO_L11N_SRCC_22' U2-AT27 # 22 AT27 IO_L11N_SRCC_22 NET 'No_Conn_TP_IO_L5P_22' U2-AT29 # 22 AT29 IO_L5P_22 NET 'No_Conn_TP_IO_L7P_22' U2-AT30 # 22 AT30 IO_L7P_22 NET 'No_Conn_TP_IO_L13P_22' U2-AT31 # 22 AT31 IO_L13P_22 NET 'No_Conn_TP_IO_L17P_22' U2-AU28 # 22 AU28 IO_L17P_22 NET 'No_Conn_TP_IO_L15P_22' U2-AU29 # 22 AU29 IO_L15P_22 NET 'No_Conn_TP_IO_L13N_22' U2-AU31 # 22 AU31 IO_L13N_22 NET 'No_Conn_TP_IO_L17N_22' U2-AV28 # 22 AV28 IO_L17N_22 NET 'No_Conn_TP_IO_L15N_22' U2-AV29 # 22 AV29 IO_L15N_22 NET 'No_Conn_TP_IO_L0N_22' U2-AV30 # 22 AV30 IO_L0N_22 NET 'No_Conn_TP_IO_L2N_22' U2-AV31 # 22 AV31 IO_L2N_22 NET 'No_Conn_TP_IO_L19P_22' U2-AW28 # 22 AW28 IO_L19P_22 NET 'No_Conn_TP_IO_L0P_22' U2-AW30 # 22 AW30 IO_L0P_22 NET 'No_Conn_TP_IO_L2P_22' U2-AW31 # 22 AW31 IO_L2P_22 NET 'No_Conn_TP_IO_L4N_VREF_22' U2-AW32 # 22 AW32 IO_L4N_VREF_22 NET 'No_Conn_TP_IO_L19N_22' U2-AY28 # 22 AY28 IO_L19N_22 NET 'No_Conn_TP_IO_L12P_VRN_22' U2-AY29 # 22 AY29 IO_L12P_VRN_22 NET 'No_Conn_TP_IO_L8N_SRCC_22' U2-AY30 # 22 AY30 IO_L8N_SRCC_22 NET 'No_Conn_TP_IO_L4P_22' U2-AY32 # 22 AY32 IO_L4P_22 NET 'No_Conn_TP_IO_L6N_22' U2-AY33 # 22 AY33 IO_L6N_22 NET 'No_Conn_TP_IO_L12N_VRP_22' U2-BA29 # 22 BA29 IO_L12N_VRP_22 NET 'No_Conn_TP_IO_L8P_SRCC_22' U2-BA30 # 22 BA30 IO_L8P_SRCC_22 NET 'No_Conn_TP_IO_L16P_22' U2-BA31 # 22 BA31 IO_L16P_22 NET 'No_Conn_TP_IO_L6P_22' U2-BA32 # 22 BA32 IO_L6P_22 NET 'No_Conn_TP_IO_L18N_22' U2-BB28 # 22 BB28 IO_L18N_22 NET 'No_Conn_TP_IO_L18P_22' U2-BB29 # 22 BB29 IO_L18P_22 NET 'No_Conn_TP_IO_L16N_22' U2-BB31 # 22 BB31 IO_L16N_22 NET 'No_Conn_TP_IO_L14N_VREF_22' U2-BB32 # 22 BB32 IO_L14N_VREF_22 NET 'No_Conn_TP_IO_L14P_22' U2-BB33 # 22 BB33 IO_L14P_22 # Unused pins from IO bank 23 ############################# NET 'No_Conn_TP_IO_L14N_VREF_23' U2-AG27 # 23 AG27 IO_L14N_VREF_23 NET 'No_Conn_TP_IO_L14P_23' U2-AG28 # 23 AG28 IO_L14P_23 NET 'No_Conn_TP_IO_L10P_MRCC_23' U2-AH24 # 23 AH24 IO_L10P_MRCC_23 NET 'No_Conn_TP_IO_L10N_MRCC_23' U2-AH25 # 23 AH25 IO_L10N_MRCC_23 NET 'No_Conn_TP_IO_L18N_23' U2-AH26 # 23 AH26 IO_L18N_23 NET 'No_Conn_TP_IO_L12P_VRN_23' U2-AH28 # 23 AH28 IO_L12P_VRN_23 NET 'No_Conn_TP_IO_L9P_MRCC_23' U2-AJ25 # 23 AJ25 IO_L9P_MRCC_23 NET 'No_Conn_TP_IO_L18P_23' U2-AJ26 # 23 AJ26 IO_L18P_23 NET 'No_Conn_TP_IO_L16N_23' U2-AJ27 # 23 AJ27 IO_L16N_23 NET 'No_Conn_TP_IO_L12N_VRP_23' U2-AJ28 # 23 AJ28 IO_L12N_VRP_23 NET 'No_Conn_TP_IO_L9N_MRCC_23' U2-AK25 # 23 AK25 IO_L9N_MRCC_23 NET 'No_Conn_TP_IO_L16P_23' U2-AK27 # 23 AK27 IO_L16P_23 NET 'No_Conn_TP_IO_L8P_SRCC_23' U2-AK28 # 23 AK28 IO_L8P_SRCC_23 NET 'No_Conn_TP_IO_L8N_SRCC_23' U2-AK29 # 23 AK29 IO_L8N_SRCC_23 NET 'No_Conn_TP_IO_L6P_23' U2-AL27 # 23 AL27 IO_L6P_23 NET 'No_Conn_TP_IO_L2P_23' U2-AL29 # 23 AL29 IO_L2P_23 NET 'No_Conn_TP_IO_L2N_23' U2-AL30 # 23 AL30 IO_L2N_23 NET 'No_Conn_TP_IO_L1N_23' U2-AL31 # 23 AL31 IO_L1N_23 NET 'No_Conn_TP_IO_L6N_23' U2-AM28 # 23 AM28 IO_L6N_23 NET 'No_Conn_TP_IO_L4N_VREF_23' U2-AM29 # 23 AM29 IO_L4N_VREF_23 NET 'No_Conn_TP_IO_L1P_23' U2-AM31 # 23 AM31 IO_L1P_23 NET 'No_Conn_TP_IO_L3N_23' U2-AM32 # 23 AM32 IO_L3N_23 NET 'No_Conn_TP_IO_L3P_23' U2-AM33 # 23 AM33 IO_L3P_23 NET 'No_Conn_TP_IO_L4P_23' U2-AN29 # 23 AN29 IO_L4P_23 NET 'No_Conn_TP_IO_L0N_23' U2-AN30 # 23 AN30 IO_L0N_23 NET 'No_Conn_TP_IO_L7N_23' U2-AN31 # 23 AN31 IO_L7N_23 NET 'No_Conn_TP_IO_L5P_23' U2-AN33 # 23 AN33 IO_L5P_23 NET 'No_Conn_TP_IO_L5N_23' U2-AN34 # 23 AN34 IO_L5N_23 NET 'No_Conn_TP_IO_L0P_23' U2-AP30 # 23 AP30 IO_L0P_23 NET 'No_Conn_TP_IO_L7P_23' U2-AP31 # 23 AP31 IO_L7P_23 NET 'No_Conn_TP_IO_L13P_23' U2-AP32 # 23 AP32 IO_L13P_23 NET 'No_Conn_TP_IO_L11N_SRCC_23' U2-AP33 # 23 AP33 IO_L11N_SRCC_23 NET 'No_Conn_TP_IO_L13N_23' U2-AR32 # 23 AR32 IO_L13N_23 NET 'No_Conn_TP_IO_L15P_23' U2-AR33 # 23 AR33 IO_L15P_23 NET 'No_Conn_TP_IO_L11P_SRCC_23' U2-AR34 # 23 AR34 IO_L11P_SRCC_23 NET 'No_Conn_TP_IO_L15N_23' U2-AT32 # 23 AT32 IO_L15N_23 NET 'No_Conn_TP_IO_L17N_23' U2-AU32 # 23 AU32 IO_L17N_23 NET 'No_Conn_TP_IO_L17P_23' U2-AU33 # 23 AU33 IO_L17P_23 NET 'No_Conn_TP_IO_L19P_23' U2-AV33 # 23 AV33 IO_L19P_23 NET 'No_Conn_TP_IO_L19N_23' U2-AW33 # 23 AW33 IO_L19N_23 # Unused pins from IO bank 24 ############################# NET 'No_Conn_TP_IO_L5P_D9_24' U2-N33 # 24 N33 IO_L5P_D9_24 NET 'No_Conn_TP_IO_L7P_D5_24' U2-P32 # 24 P32 IO_L7P_D5_24 NET 'No_Conn_TP_IO_L5N_D8_24' U2-P33 # 24 P33 IO_L5N_D8_24 NET 'No_Conn_TP_IO_L3N_D12_24' U2-R30 # 24 R30 IO_L3N_D12_24 NET 'No_Conn_TP_IO_L11P_SRCC_24' U2-R32 # 24 R32 IO_L11P_SRCC_24 NET 'No_Conn_TP_IO_L7N_D4_24' U2-R33 # 24 R33 IO_L7N_D4_24 NET 'No_Conn_TP_IO_L3P_D13_24' U2-T30 # 24 T30 IO_L3P_D13_24 NET 'No_Conn_TP_IO_L13P_D1_FS1_24' U2-T31 # 24 T31 IO_L13P_D1_FS1_24 NET 'No_Conn_TP_IO_L11N_SRCC_24' U2-T32 # 24 T32 IO_L11N_SRCC_24 NET 'No_Conn_TP_IO_L13N_D0_FS0_24' U2-U31 # 24 U31 IO_L13N_D0_FS0_24 NET 'No_Conn_TP_IO_L1N_GC_24' U2-V30 # 24 V30 IO_L1N_GC_24 NET 'No_Conn_TP_IO_L15P_FWE_B_24' U2-V31 # 24 V31 IO_L15P_FWE_B_24 NET 'No_Conn_TP_IO_L1P_GC_24' U2-W30 # 24 W30 IO_L1P_GC_24 NET 'No_Conn_TP_IO_L15N_RS1_24' U2-W31 # 24 W31 IO_L15N_RS1_24 NET 'No_Conn_TP_IO_L9P_MRCC_24' U2-Y30 # 24 Y30 IO_L9P_MRCC_24 NET 'No_Conn_TP_IO_L9N_MRCC_24' U2-AA30 # 24 AA30 IO_L9N_MRCC_24 NET 'No_Conn_TP_IO_L10P_MRCC_24' U2-AA31 # 24 AA31 IO_L10P_MRCC_24 NET 'No_Conn_TP_IO_L10N_MRCC_24' U2-AB31 # 24 AB31 IO_L10N_MRCC_24 NET 'No_Conn_TP_IO_L17N_VRP_24' U2-AC30 # 24 AC30 IO_L17N_VRP_24 NET 'No_Conn_TP_IO_L17P_VRN_24' U2-AC31 # 24 AC31 IO_L17P_VRN_24 NET 'No_Conn_TP_IO_L19N_24' U2-AD30 # 24 AD30 IO_L19N_24 NET 'No_Conn_TP_IO_L19P_24' U2-AD31 # 24 AD31 IO_L19P_24 NET 'No_Conn_TP_IO_L0P_GC_24' U2-AE30 # 24 AE30 IO_L0P_GC_24 NET 'No_Conn_TP_IO_L0N_GC_24' U2-AF30 # 24 AF30 IO_L0N_GC_24 NET 'No_Conn_TP_IO_L2N_D14_24' U2-AF31 # 24 AF31 IO_L2N_D14_24 NET 'No_Conn_TP_IO_L18N_24' U2-AG29 # 24 AG29 IO_L18N_24 NET 'No_Conn_TP_IO_L4N_VREF_D10_24' U2-AG31 # 24 AG31 IO_L4N_VREF_D10_24 NET 'No_Conn_TP_IO_L2P_D15_24' U2-AG32 # 24 AG32 IO_L2P_D15_24 NET 'No_Conn_TP_IO_L18P_24' U2-AH29 # 24 AH29 IO_L18P_24 NET 'No_Conn_TP_IO_L14P_FCS_B_24' U2-AH30 # 24 AH30 IO_L14P_FCS_B_24 NET 'No_Conn_TP_IO_L4P_D11_24' U2-AH31 # 24 AH31 IO_L4P_D11_24 NET 'No_Conn_TP_IO_L6N_D6_24' U2-AH33 # 24 AH33 IO_L6N_D6_24 NET 'No_Conn_TP_IO_L14N_VREF_FOE_B_MOSI_24' U2-AJ30 # 24 AJ30 IO_L14N_VREF_FOE_B_MOSI_24 NET 'No_Conn_TP_IO_L16P_RS0_24' U2-AJ31 # 24 AJ31 IO_L16P_RS0_24 NET 'No_Conn_TP_IO_L8N_SRCC_24' U2-AJ32 # 24 AJ32 IO_L8N_SRCC_24 NET 'No_Conn_TP_IO_L6P_D7_24' U2-AJ33 # 24 AJ33 IO_L6P_D7_24 NET 'No_Conn_TP_IO_L16N_CSO_B_24' U2-AK30 # 24 AK30 IO_L16N_CSO_B_24 NET 'No_Conn_TP_IO_L12P_D3_24' U2-AK32 # 24 AK32 IO_L12P_D3_24 NET 'No_Conn_TP_IO_L8P_SRCC_24' U2-AK33 # 24 AK33 IO_L8P_SRCC_24 NET 'No_Conn_TP_IO_L12N_D2_FS2_24' U2-AL32 # 24 AL32 IO_L12N_D2_FS2_24 # Unused pins from IO bank 25 ############################# # note: 2 pins from this bank are used for the 40 MHz Logic Clock NET 'No_Conn_TP_IO_L6N_25' U2-H38 # 25 H38 IO_L6N_25 NET 'No_Conn_TP_IO_L6P_25' U2-H39 # 25 H39 IO_L6P_25 NET 'No_Conn_TP_IO_L12P_25' U2-H40 # 25 H40 IO_L12P_25 NET 'No_Conn_TP_IO_L12N_25' U2-H41 # 25 H41 IO_L12N_25 NET 'No_Conn_TP_IO_L4N_VREF_25' U2-J36 # 25 J36 IO_L4N_VREF_25 NET 'No_Conn_TP_IO_L4P_25' U2-J37 # 25 J37 IO_L4P_25 NET 'No_Conn_TP_IO_L8N_SRCC_25' U2-J38 # 25 J38 IO_L8N_SRCC_25 NET 'No_Conn_TP_IO_L14P_25' U2-J40 # 25 J40 IO_L14P_25 NET 'No_Conn_TP_IO_L14N_VREF_25' U2-J41 # 25 J41 IO_L14N_VREF_25 NET 'No_Conn_TP_IO_L0N_25' U2-K32 # 25 K32 IO_L0N_25 NET 'No_Conn_TP_IO_L0P_25' U2-K33 # 25 K33 IO_L0P_25 NET 'No_Conn_TP_IO_L2N_25' U2-K34 # 25 K34 IO_L2N_25 NET 'No_Conn_TP_IO_L2P_25' U2-K35 # 25 K35 IO_L2P_25 NET 'No_Conn_TP_IO_L11P_SRCC_25' U2-K37 # 25 K37 IO_L11P_SRCC_25 NET 'No_Conn_TP_IO_L8P_SRCC_25' U2-K38 # 25 K38 IO_L8P_SRCC_25 NET 'No_Conn_TP_IO_L16P_VRN_25' U2-K39 # 25 K39 IO_L16P_VRN_25 NET 'No_Conn_TP_IO_L16N_VRP_25' U2-K40 # 25 K40 IO_L16N_VRP_25 NET 'No_Conn_TP_IO_L3P_25' U2-L31 # 25 L31 IO_L3P_25 NET 'No_Conn_TP_IO_L3N_25' U2-L32 # 25 L32 IO_L3N_25 NET 'No_Conn_TP_IO_L13P_25' U2-L34 # 25 L34 IO_L13P_25 NET 'No_Conn_TP_IO_L7P_25' U2-L35 # 25 L35 IO_L7P_25 NET 'No_Conn_TP_IO_L7N_25' U2-L36 # 25 L36 IO_L7N_25 NET 'No_Conn_TP_IO_L11N_SRCC_25' U2-L37 # 25 L37 IO_L11N_SRCC_25 NET 'No_Conn_TP_IO_L17P_25' U2-M31 # 25 M31 IO_L17P_25 NET 'No_Conn_TP_IO_L15N_25' U2-M32 # 25 M32 IO_L15N_25 NET 'No_Conn_TP_IO_L15P_25' U2-M33 # 25 M33 IO_L15P_25 NET 'No_Conn_TP_IO_L13N_25' U2-M34 # 25 M34 IO_L13N_25 NET 'No_Conn_TP_IO_L1P_25' U2-N28 # 25 N28 IO_L1P_25 NET 'No_Conn_TP_IO_L5P_25' U2-N29 # 25 N29 IO_L5P_25 NET 'No_Conn_TP_IO_L5N_25' U2-N30 # 25 N30 IO_L5N_25 NET 'No_Conn_TP_IO_L17N_25' U2-N31 # 25 N31 IO_L17N_25 NET 'No_Conn_TP_IO_L9P_MRCC_25' U2-P27 # 25 P27 IO_L9P_MRCC_25 NET 'No_Conn_TP_IO_L1N_25' U2-P28 # 25 P28 IO_L1N_25 NET 'No_Conn_TP_IO_L19P_GC_25' U2-P30 # 25 P30 IO_L19P_GC_25 NET 'No_Conn_TP_IO_L19N_GC_25' U2-P31 # 25 P31 IO_L19N_GC_25 NET 'No_Conn_TP_IO_L9N_MRCC_25' U2-R27 # 25 R27 IO_L9N_MRCC_25 NET 'No_Conn_TP_IO_L10P_MRCC_25' U2-R28 # 25 R28 IO_L10P_MRCC_25 NET 'No_Conn_TP_IO_L10N_MRCC_25' U2-R29 # 25 R29 IO_L10N_MRCC_25 # Unused pins from IO bank 26 ############################# # note: this bank is otherwise used for BF to TP S-link connection, and Debug connector connections NET 'No_Conn_TP_IO_L5N_26' U2-C39 # 26 C39 IO_L5N_26 NET 'No_Conn_TP_IO_L6P_26' U2-D38 # 26 D38 IO_L6P_26 NET 'No_Conn_TP_IO_L17P_26' U2-D40 # 26 D40 IO_L17P_26 NET 'No_Conn_TP_IO_L4N_VREF_26' U2-E37 # 26 E37 IO_L4N_VREF_26 NET 'No_Conn_TP_IO_L8N_SRCC_26' U2-E38 # 26 E38 IO_L8N_SRCC_26 NET 'No_Conn_TP_IO_L8P_SRCC_26' U2-E39 # 26 E39 IO_L8P_SRCC_26 NET 'No_Conn_TP_IO_L10P_MRCC_26' U2-F35 # 26 F35 IO_L10P_MRCC_26 NET 'No_Conn_TP_IO_L10N_MRCC_26' U2-F36 # 26 F36 IO_L10N_MRCC_26 NET 'No_Conn_TP_IO_L4P_26' U2-F37 # 26 F37 IO_L4P_26 NET 'No_Conn_TP_IO_L12P_VRN_26' U2-F39 # 26 F39 IO_L12P_VRN_26 NET 'No_Conn_TP_IO_L16P_26' U2-F40 # 26 F40 IO_L16P_26 NET 'No_Conn_TP_IO_L9P_MRCC_26' U2-G34 # 26 G34 IO_L9P_MRCC_26 NET 'No_Conn_TP_IO_L0N_26' U2-G36 # 26 G36 IO_L0N_26 NET 'No_Conn_TP_IO_L14P_26' U2-G37 # 26 G37 IO_L14P_26 NET 'No_Conn_TP_IO_L14N_VREF_26' U2-G38 # 26 G38 IO_L14N_VREF_26 NET 'No_Conn_TP_IO_L12N_VRP_26' U2-G39 # 26 G39 IO_L12N_VRP_26 NET 'No_Conn_TP_IO_L9N_MRCC_26' U2-H34 # 26 H34 IO_L9N_MRCC_26 NET 'No_Conn_TP_IO_L2N_26' U2-H35 # 26 H35 IO_L2N_26 NET 'No_Conn_TP_IO_L0P_26' U2-H36 # 26 H36 IO_L0P_26 NET 'No_Conn_TP_IO_L2P_26' U2-J35 # 26 J35 IO_L2P_26 # Unused pins from IO bank 27 ############################# # note: this bank is otherwise used for TP to BSPT connections NET 'No_Conn_TP_IO_L3N_27' U2-C33 # 27 C33 IO_L3N_27 NET 'No_Conn_TP_IO_L7N_27' U2-C34 # 27 C34 IO_L7N_27 NET 'No_Conn_TP_IO_L15N_27' U2-C36 # 27 C36 IO_L15N_27 NET 'No_Conn_TP_IO_L0N_27' U2-D32 # 27 D32 IO_L0N_27 NET 'No_Conn_TP_IO_L11P_SRCC_27' U2-D33 # 27 D33 IO_L11P_SRCC_27 NET 'No_Conn_TP_IO_L4N_VREF_27' U2-D35 # 27 D35 IO_L4N_VREF_27 NET 'No_Conn_TP_IO_L19P_27' U2-D36 # 27 D36 IO_L19P_27 NET 'No_Conn_TP_IO_L19N_27' U2-D37 # 27 D37 IO_L19N_27 NET 'No_Conn_TP_IO_L0P_27' U2-E32 # 27 E32 IO_L0P_27 NET 'No_Conn_TP_IO_L11N_SRCC_27' U2-E33 # 27 E33 IO_L11N_SRCC_27 NET 'No_Conn_TP_IO_L17P_27' U2-E34 # 27 E34 IO_L17P_27 NET 'No_Conn_TP_IO_L4P_27' U2-E35 # 27 E35 IO_L4P_27 NET 'No_Conn_TP_IO_L2N_27' U2-F31 # 27 F31 IO_L2N_27 NET 'No_Conn_TP_IO_L2P_27' U2-F32 # 27 F32 IO_L2P_27 NET 'No_Conn_TP_IO_L17N_27' U2-F34 # 27 F34 IO_L17N_27 NET 'No_Conn_TP_IO_L6N_27' U2-G31 # 27 G31 IO_L6N_27 NET 'No_Conn_TP_IO_L8N_SRCC_27' U2-G32 # 27 G32 IO_L8N_SRCC_27 NET 'No_Conn_TP_IO_L8P_SRCC_27' U2-G33 # 27 G33 IO_L8P_SRCC_27 NET 'No_Conn_TP_IO_L16P_27' U2-H30 # 27 H30 IO_L16P_27 NET 'No_Conn_TP_IO_L6P_27' U2-H31 # 27 H31 IO_L6P_27 NET 'No_Conn_TP_IO_L12P_VRN_27' U2-H33 # 27 H33 IO_L12P_VRN_27 NET 'No_Conn_TP_IO_L16N_27' U2-J30 # 27 J30 IO_L16N_27 NET 'No_Conn_TP_IO_L14N_VREF_27' U2-J31 # 27 J31 IO_L14N_VREF_27 NET 'No_Conn_TP_IO_L14P_27' U2-J32 # 27 J32 IO_L14P_27 NET 'No_Conn_TP_IO_L12N_VRP_27' U2-J33 # 27 J33 IO_L12N_VRP_27 NET 'No_Conn_TP_IO_L18P_27' U2-K29 # 27 K29 IO_L18P_27 NET 'No_Conn_TP_IO_L18N_27' U2-K30 # 27 K30 IO_L18N_27 NET 'No_Conn_TP_IO_L9P_MRCC_27' U2-L29 # 27 L29 IO_L9P_MRCC_27 NET 'No_Conn_TP_IO_L9N_MRCC_27' U2-L30 # 27 L30 IO_L9N_MRCC_27 NET 'No_Conn_TP_IO_L10P_MRCC_27' U2-M28 # 27 M28 IO_L10P_MRCC_27 NET 'No_Conn_TP_IO_L10N_MRCC_27' U2-M29 # 27 M29 IO_L10N_MRCC_27 # Unused pins from IO bank 28 ############################# NET 'No_Conn_TP_IO_L17P_28' U2-A29 # 28 A29 IO_L17P_28 NET 'No_Conn_TP_IO_L17N_28' U2-A30 # 28 A30 IO_L17N_28 NET 'No_Conn_TP_IO_L13P_28' U2-A31 # 28 A31 IO_L13P_28 NET 'No_Conn_TP_IO_L15P_28' U2-B29 # 28 B29 IO_L15P_28 NET 'No_Conn_TP_IO_L13N_28' U2-B31 # 28 B31 IO_L13N_28 NET 'No_Conn_TP_IO_L15N_28' U2-C29 # 28 C29 IO_L15N_28 NET 'No_Conn_TP_IO_L7P_28' U2-C30 # 28 C30 IO_L7P_28 NET 'No_Conn_TP_IO_L5P_28' U2-C31 # 28 C31 IO_L5P_28 NET 'No_Conn_TP_IO_L1P_28' U2-D28 # 28 D28 IO_L1P_28 NET 'No_Conn_TP_IO_L7N_28' U2-D30 # 28 D30 IO_L7N_28 NET 'No_Conn_TP_IO_L5N_28' U2-D31 # 28 D31 IO_L5N_28 NET 'No_Conn_TP_IO_L11N_SRCC_28' U2-E28 # 28 E28 IO_L11N_SRCC_28 NET 'No_Conn_TP_IO_L1N_28' U2-E29 # 28 E29 IO_L1N_28 NET 'No_Conn_TP_IO_L3P_28' U2-E30 # 28 E30 IO_L3P_28 NET 'No_Conn_TP_IO_L11P_SRCC_28' U2-F27 # 28 F27 IO_L11P_SRCC_28 NET 'No_Conn_TP_IO_L4N_VREF_28' U2-F29 # 28 F29 IO_L4N_VREF_28 NET 'No_Conn_TP_IO_L3N_28' U2-F30 # 28 F30 IO_L3N_28 NET 'No_Conn_TP_IO_L2N_28' U2-G27 # 28 G27 IO_L2N_28 NET 'No_Conn_TP_IO_L2P_28' U2-G28 # 28 G28 IO_L2P_28 NET 'No_Conn_TP_IO_L4P_28' U2-G29 # 28 G29 IO_L4P_28 NET 'No_Conn_TP_IO_L14P_28' U2-H28 # 28 H28 IO_L14P_28 NET 'No_Conn_TP_IO_L14N_VREF_28' U2-H29 # 28 H29 IO_L14N_VREF_28 NET 'No_Conn_TP_IO_L0N_28' U2-J26 # 28 J26 IO_L0N_28 NET 'No_Conn_TP_IO_L0P_28' U2-J27 # 28 J27 IO_L0P_28 NET 'No_Conn_TP_IO_L16P_28' U2-J28 # 28 J28 IO_L16P_28 NET 'No_Conn_TP_IO_L18N_28' U2-K27 # 28 K27 IO_L18N_28 NET 'No_Conn_TP_IO_L16N_28' U2-K28 # 28 K28 IO_L16N_28 NET 'No_Conn_TP_IO_L9N_MRCC_28' U2-L25 # 28 L25 IO_L9N_MRCC_28 NET 'No_Conn_TP_IO_L9P_MRCC_28' U2-L26 # 28 L26 IO_L9P_MRCC_28 NET 'No_Conn_TP_IO_L18P_28' U2-L27 # 28 L27 IO_L18P_28 NET 'No_Conn_TP_IO_L19P_28' U2-M26 # 28 M26 IO_L19P_28 NET 'No_Conn_TP_IO_L19N_28' U2-M27 # 28 M27 IO_L19N_28 NET 'No_Conn_TP_IO_L10P_MRCC_28' U2-N24 # 28 N24 IO_L10P_MRCC_28 NET 'No_Conn_TP_IO_L10N_MRCC_28' U2-N25 # 28 N25 IO_L10N_MRCC_28 NET 'No_Conn_TP_IO_L12N_VRP_28' U2-N26 # 28 N26 IO_L12N_VRP_28 NET 'No_Conn_TP_IO_L6N_28' U2-P23 # 28 P23 IO_L6N_28 NET 'No_Conn_TP_IO_L8N_SRCC_28' U2-P25 # 28 P25 IO_L8N_SRCC_28 NET 'No_Conn_TP_IO_L12P_VRN_28' U2-P26 # 28 P26 IO_L12P_VRN_28 NET 'No_Conn_TP_IO_L6P_28' U2-R23 # 28 R23 IO_L6P_28 NET 'No_Conn_TP_IO_L8P_SRCC_28' U2-R25 # 28 R25 IO_L8P_SRCC_28 # Unused pins from IO bank 32 ############################# NET 'No_Conn_TP_IO_L9N_MRCC_32' U2-AJ20 # 32 AJ20 IO_L9N_MRCC_32 NET 'No_Conn_TP_IO_L9P_MRCC_32' U2-AJ21 # 32 AJ21 IO_L9P_MRCC_32 NET 'No_Conn_TP_IO_L10N_MRCC_32' U2-AK19 # 32 AK19 IO_L10N_MRCC_32 NET 'No_Conn_TP_IO_L10P_MRCC_32' U2-AK20 # 32 AK20 IO_L10P_MRCC_32 NET 'No_Conn_TP_IO_L1P_32' U2-AL19 # 32 AL19 IO_L1P_32 NET 'No_Conn_TP_IO_L5P_32' U2-AL20 # 32 AL20 IO_L5P_32 NET 'No_Conn_TP_IO_L5N_32' U2-AL21 # 32 AL21 IO_L5N_32 NET 'No_Conn_TP_IO_L1N_32' U2-AM19 # 32 AM19 IO_L1N_32 NET 'No_Conn_TP_IO_L11P_SRCC_32' U2-AM21 # 32 AM21 IO_L11P_SRCC_32 NET 'No_Conn_TP_IO_L7P_32' U2-AN20 # 32 AN20 IO_L7P_32 NET 'No_Conn_TP_IO_L11N_SRCC_32' U2-AN21 # 32 AN21 IO_L11N_SRCC_32 NET 'No_Conn_TP_IO_L7N_32' U2-AP20 # 32 AP20 IO_L7N_32 NET 'No_Conn_TP_IO_L19P_32' U2-AP21 # 32 AP21 IO_L19P_32 NET 'No_Conn_TP_IO_L19N_32' U2-AP22 # 32 AP22 IO_L19N_32 NET 'No_Conn_TP_IO_L3N_32' U2-AR20 # 32 AR20 IO_L3N_32 NET 'No_Conn_TP_IO_L17N_32' U2-AR22 # 32 AR22 IO_L17N_32 NET 'No_Conn_TP_IO_L3P_32' U2-AT20 # 32 AT20 IO_L3P_32 NET 'No_Conn_TP_IO_L15N_32' U2-AT21 # 32 AT21 IO_L15N_32 NET 'No_Conn_TP_IO_L17P_32' U2-AT22 # 32 AT22 IO_L17P_32 NET 'No_Conn_TP_IO_L15P_32' U2-AU21 # 32 AU21 IO_L15P_32 NET 'No_Conn_TP_IO_L2N_32' U2-AU22 # 32 AU22 IO_L2N_32 NET 'No_Conn_TP_IO_L13P_32' U2-AV20 # 32 AV20 IO_L13P_32 NET 'No_Conn_TP_IO_L12P_VRN_32' U2-AV21 # 32 AV21 IO_L12P_VRN_32 NET 'No_Conn_TP_IO_L2P_32' U2-AV23 # 32 AV23 IO_L2P_32 NET 'No_Conn_TP_IO_L13N_32' U2-AW20 # 32 AW20 IO_L13N_32 NET 'No_Conn_TP_IO_L12N_VRP_32' U2-AW21 # 32 AW21 IO_L12N_VRP_32 NET 'No_Conn_TP_IO_L16P_32' U2-AW22 # 32 AW22 IO_L16P_32 NET 'No_Conn_TP_IO_L4P_32' U2-AW23 # 32 AW23 IO_L4P_32 NET 'No_Conn_TP_IO_L8P_SRCC_32' U2-AY20 # 32 AY20 IO_L8P_SRCC_32 NET 'No_Conn_TP_IO_L16N_32' U2-AY22 # 32 AY22 IO_L16N_32 NET 'No_Conn_TP_IO_L4N_VREF_32' U2-AY23 # 32 AY23 IO_L4N_VREF_32 NET 'No_Conn_TP_IO_L0P_32' U2-AY24 # 32 AY24 IO_L0P_32 NET 'No_Conn_TP_IO_L8N_SRCC_32' U2-BA20 # 32 BA20 IO_L8N_SRCC_32 NET 'No_Conn_TP_IO_L14N_VREF_32' U2-BA21 # 32 BA21 IO_L14N_VREF_32 NET 'No_Conn_TP_IO_L14P_32' U2-BA22 # 32 BA22 IO_L14P_32 NET 'No_Conn_TP_IO_L0N_32' U2-BA24 # 32 BA24 IO_L0N_32 NET 'No_Conn_TP_IO_L18N_32' U2-BB21 # 32 BB21 IO_L18N_32 NET 'No_Conn_TP_IO_L18P_32' U2-BB22 # 32 BB22 IO_L18P_32 NET 'No_Conn_TP_IO_L6N_32' U2-BB23 # 32 BB23 IO_L6N_32 NET 'No_Conn_TP_IO_L6P_32' U2-BB24 # 32 BB24 IO_L6P_32 # Unused pins from IO bank 33 ############################# NET 'No_Conn_TP_IO_L10N_MRCC_33' U2-AJ15 # 33 AJ15 IO_L10N_MRCC_33 NET 'No_Conn_TP_IO_L10P_MRCC_33' U2-AJ16 # 33 AJ16 IO_L10P_MRCC_33 NET 'No_Conn_TP_IO_L6P_33' U2-AJ17 # 33 AJ17 IO_L6P_33 NET 'No_Conn_TP_IO_L18N_33' U2-AJ18 # 33 AJ18 IO_L18N_33 NET 'No_Conn_TP_IO_L9N_MRCC_33' U2-AK14 # 33 AK14 IO_L9N_MRCC_33 NET 'No_Conn_TP_IO_L9P_MRCC_33' U2-AK15 # 33 AK15 IO_L9P_MRCC_33 NET 'No_Conn_TP_IO_L6N_33' U2-AK17 # 33 AK17 IO_L6N_33 NET 'No_Conn_TP_IO_L18P_33' U2-AK18 # 33 AK18 IO_L18P_33 NET 'No_Conn_TP_IO_L0N_33' U2-AL14 # 33 AL14 IO_L0N_33 NET 'No_Conn_TP_IO_L0P_33' U2-AL15 # 33 AL15 IO_L0P_33 NET 'No_Conn_TP_IO_L4N_VREF_33' U2-AL16 # 33 AL16 IO_L4N_VREF_33 NET 'No_Conn_TP_IO_L4P_33' U2-AL17 # 33 AL17 IO_L4P_33 NET 'No_Conn_TP_IO_L2N_33' U2-AM14 # 33 AM14 IO_L2N_33 NET 'No_Conn_TP_IO_L8N_SRCC_33' U2-AM16 # 33 AM16 IO_L8N_SRCC_33 NET 'No_Conn_TP_IO_L14P_33' U2-AM17 # 33 AM17 IO_L14P_33 NET 'No_Conn_TP_IO_L14N_VREF_33' U2-AM18 # 33 AM18 IO_L14N_VREF_33 NET 'No_Conn_TP_IO_L2P_33' U2-AN15 # 33 AN15 IO_L2P_33 NET 'No_Conn_TP_IO_L8P_SRCC_33' U2-AN16 # 33 AN16 IO_L8P_SRCC_33 NET 'No_Conn_TP_IO_L16P_33' U2-AN18 # 33 AN18 IO_L16P_33 NET 'No_Conn_TP_IO_L16N_33' U2-AN19 # 33 AN19 IO_L16N_33 NET 'No_Conn_TP_IO_L12P_VRN_33' U2-AP16 # 33 AP16 IO_L12P_VRN_33 NET 'No_Conn_TP_IO_L12N_VRP_33' U2-AP17 # 33 AP17 IO_L12N_VRP_33 NET 'No_Conn_TP_IO_L11P_SRCC_33' U2-AP18 # 33 AP18 IO_L11P_SRCC_33 NET 'No_Conn_TP_IO_L1P_33' U2-AR17 # 33 AR17 IO_L1P_33 NET 'No_Conn_TP_IO_L1N_33' U2-AR18 # 33 AR18 IO_L1N_33 NET 'No_Conn_TP_IO_L11N_SRCC_33' U2-AR19 # 33 AR19 IO_L11N_SRCC_33 NET 'No_Conn_TP_IO_L3P_33' U2-AT16 # 33 AT16 IO_L3P_33 NET 'No_Conn_TP_IO_L5P_33' U2-AT17 # 33 AT17 IO_L5P_33 NET 'No_Conn_TP_IO_L19N_33' U2-AT19 # 33 AT19 IO_L19N_33 NET 'No_Conn_TP_IO_L3N_33' U2-AU17 # 33 AU17 IO_L3N_33 NET 'No_Conn_TP_IO_L5N_33' U2-AU18 # 33 AU18 IO_L5N_33 NET 'No_Conn_TP_IO_L19P_33' U2-AU19 # 33 AU19 IO_L19P_33 NET 'No_Conn_TP_IO_L13P_33' U2-AV18 # 33 AV18 IO_L13P_33 NET 'No_Conn_TP_IO_L13N_33' U2-AV19 # 33 AV19 IO_L13N_33 NET 'No_Conn_TP_IO_L7N_33' U2-AW18 # 33 AW18 IO_L7N_33 NET 'No_Conn_TP_IO_L7P_33' U2-AY18 # 33 AY18 IO_L7P_33 NET 'No_Conn_TP_IO_L17N_33' U2-AY19 # 33 AY19 IO_L17N_33 NET 'No_Conn_TP_IO_L17P_33' U2-BA19 # 33 BA19 IO_L17P_33 NET 'No_Conn_TP_IO_L15P_33' U2-BB18 # 33 BB18 IO_L15P_33 NET 'No_Conn_TP_IO_L15N_33' U2-BB19 # 33 BB19 IO_L15N_33 # Unused pins from IO bank 34 ############################# # note: 4 pins from this bank are used for 40MHz and 320 MHz Logic Clocks NET 'No_Conn_TP_IO_L9N_MRCC_34' U2-AM12 # 34 AM12 IO_L9N_MRCC_34 NET 'No_Conn_TP_IO_L9P_MRCC_34' U2-AM13 # 34 AM13 IO_L9P_MRCC_34 NET 'No_Conn_TP_IO_L10N_MRCC_34' U2-AN13 # 34 AN13 IO_L10N_MRCC_34 NET 'No_Conn_TP_IO_L10P_MRCC_34' U2-AN14 # 34 AN14 IO_L10P_MRCC_34 NET 'No_Conn_TP_IO_L5P_A09_D25_34' U2-AP13 # 34 AP13 IO_L5P_A09_D25_34 NET 'No_Conn_TP_IO_L17P_A19_34' U2-AP15 # 34 AP15 IO_L17P_A19_34 NET 'No_Conn_TP_IO_L3P_A13_D29_34' U2-AR12 # 34 AR12 IO_L3P_A13_D29_34 NET 'No_Conn_TP_IO_L5N_A08_D24_34' U2-AR13 # 34 AR13 IO_L5N_A08_D24_34 NET 'No_Conn_TP_IO_L15P_A23_34' U2-AR14 # 34 AR14 IO_L15P_A23_34 NET 'No_Conn_TP_IO_L17N_A18_34' U2-AR15 # 34 AR15 IO_L17N_A18_34 NET 'No_Conn_TP_IO_L3N_A12_D28_34' U2-AT12 # 34 AT12 IO_L3N_A12_D28_34 NET 'No_Conn_TP_IO_L15N_A22_34' U2-AT14 # 34 AT14 IO_L15N_A22_34 NET 'No_Conn_TP_IO_L19P_VRN_34' U2-AT15 # 34 AT15 IO_L19P_VRN_34 NET 'No_Conn_TP_IO_L7P_A05_D21_34' U2-AU12 # 34 AU12 IO_L7P_A05_D21_34 NET 'No_Conn_TP_IO_L7N_A04_D20_34' U2-AU13 # 34 AU13 IO_L7N_A04_D20_34 NET 'No_Conn_TP_IO_L4N_VREF_A10_D26_34' U2-AU14 # 34 AU14 IO_L4N_VREF_A10_D26_34 NET 'No_Conn_TP_IO_L19N_VRP_34' U2-AU16 # 34 AU16 IO_L19N_VRP_34 NET 'No_Conn_TP_IO_L11P_SRCC_34' U2-AV13 # 34 AV13 IO_L11P_SRCC_34 NET 'No_Conn_TP_IO_L11N_SRCC_34' U2-AV14 # 34 AV14 IO_L11N_SRCC_34 NET 'No_Conn_TP_IO_L4P_A11_D27_34' U2-AV15 # 34 AV15 IO_L4P_A11_D27_34 NET 'No_Conn_TP_IO_L8P_SRCC_34' U2-AV16 # 34 AV16 IO_L8P_SRCC_34 NET 'No_Conn_TP_IO_L13P_A01_D17_34' U2-AW12 # 34 AW12 IO_L13P_A01_D17_34 NET 'No_Conn_TP_IO_L13N_A00_D16_34' U2-AW13 # 34 AW13 IO_L13N_A00_D16_34 NET 'No_Conn_TP_IO_L6N_A06_D22_34' U2-AW15 # 34 AW15 IO_L6N_A06_D22_34 NET 'No_Conn_TP_IO_L8N_SRCC_34' U2-AW16 # 34 AW16 IO_L8N_SRCC_34 NET 'No_Conn_TP_IO_L18N_A16_34' U2-AW17 # 34 AW17 IO_L18N_A16_34 NET 'No_Conn_TP_IO_L6P_A07_D23_34' U2-AY15 # 34 AY15 IO_L6P_A07_D23_34 NET 'No_Conn_TP_IO_L18P_A17_34' U2-AY17 # 34 AY17 IO_L18P_A17_34 NET 'No_Conn_TP_IO_L2N_A14_D30_34' U2-BA14 # 34 BA14 IO_L2N_A14_D30_34 NET 'No_Conn_TP_IO_L2P_A15_D31_34' U2-BA15 # 34 BA15 IO_L2P_A15_D31_34 NET 'No_Conn_TP_IO_L14P_A25_34' U2-BA16 # 34 BA16 IO_L14P_A25_34 NET 'No_Conn_TP_IO_L14N_VREF_A24_34' U2-BA17 # 34 BA17 IO_L14N_VREF_A24_34 NET 'No_Conn_TP_IO_L12P_A03_D19_34' U2-BB13 # 34 BB13 IO_L12P_A03_D19_34 NET 'No_Conn_TP_IO_L12N_A02_D18_34' U2-BB14 # 34 BB14 IO_L12N_A02_D18_34 NET 'No_Conn_TP_IO_L16P_A21_34' U2-BB16 # 34 BB16 IO_L16P_A21_34 NET 'No_Conn_TP_IO_L16N_A20_34' U2-BB17 # 34 BB17 IO_L16N_A20_34 # Unused pins from IO bank 35 ############################# NET 'No_Conn_TP_IO_L5N_SM2N_35' U2-A14 # 35 A14 IO_L5N_SM2N_35 NET 'No_Conn_TP_IO_L5P_SM2P_35' U2-A15 # 35 A15 IO_L5P_SM2P_35 NET 'No_Conn_TP_IO_L1P_35' U2-A16 # 35 A16 IO_L1P_35 NET 'No_Conn_TP_IO_L13P_SM6P_35' U2-B14 # 35 B14 IO_L13P_SM6P_35 NET 'No_Conn_TP_IO_L1N_35' U2-B16 # 35 B16 IO_L1N_35 NET 'No_Conn_TP_IO_L15P_SM7P_35' U2-C13 # 35 C13 IO_L15P_SM7P_35 NET 'No_Conn_TP_IO_L13N_SM6N_35' U2-C14 # 35 C14 IO_L13N_SM6N_35 NET 'No_Conn_TP_IO_L7P_SM4P_35' U2-C15 # 35 C15 IO_L7P_SM4P_35 NET 'No_Conn_TP_IO_L3N_SM1N_35' U2-C16 # 35 C16 IO_L3N_SM1N_35 NET 'No_Conn_TP_IO_L15N_SM7N_35' U2-D12 # 35 D12 IO_L15N_SM7N_35 NET 'No_Conn_TP_IO_L17P_35' U2-D13 # 35 D13 IO_L17P_35 NET 'No_Conn_TP_IO_L7N_SM4N_35' U2-D15 # 35 D15 IO_L7N_SM4N_35 NET 'No_Conn_TP_IO_L3P_SM1P_35' U2-D16 # 35 D16 IO_L3P_SM1P_35 NET 'No_Conn_TP_IO_L0N_35' U2-E12 # 35 E12 IO_L0N_35 NET 'No_Conn_TP_IO_L17N_35' U2-E13 # 35 E13 IO_L17N_35 NET 'No_Conn_TP_IO_L19P_GC_35' U2-E14 # 35 E14 IO_L19P_GC_35 NET 'No_Conn_TP_IO_L11P_SRCC_35' U2-E15 # 35 E15 IO_L11P_SRCC_35 NET 'No_Conn_TP_IO_L0P_35' U2-F12 # 35 F12 IO_L0P_35 NET 'No_Conn_TP_IO_L19N_GC_35' U2-F14 # 35 F14 IO_L19N_GC_35 NET 'No_Conn_TP_IO_L11N_SRCC_35' U2-F15 # 35 F15 IO_L11N_SRCC_35 NET 'No_Conn_TP_IO_L6N_SM3N_35' U2-G12 # 35 G12 IO_L6N_SM3N_35 NET 'No_Conn_TP_IO_L4N_VREF_35' U2-G13 # 35 G13 IO_L4N_VREF_35 NET 'No_Conn_TP_IO_L2N_SM0N_35' U2-G14 # 35 G14 IO_L2N_SM0N_35 NET 'No_Conn_TP_IO_L6P_SM3P_35' U2-H13 # 35 H13 IO_L6P_SM3P_35 NET 'No_Conn_TP_IO_L4P_35' U2-H14 # 35 H14 IO_L4P_35 NET 'No_Conn_TP_IO_L2P_SM0P_35' U2-H15 # 35 H15 IO_L2P_SM0P_35 NET 'No_Conn_TP_IO_L8N_SRCC_35' U2-J11 # 35 J11 IO_L8N_SRCC_35 NET 'No_Conn_TP_IO_L8P_SRCC_35' U2-J12 # 35 J12 IO_L8P_SRCC_35 NET 'No_Conn_TP_IO_L12P_SM5P_35' U2-J13 # 35 J13 IO_L12P_SM5P_35 NET 'No_Conn_TP_IO_L16P_VRN_35' U2-K12 # 35 K12 IO_L16P_VRN_35 NET 'No_Conn_TP_IO_L12N_SM5N_35' U2-K13 # 35 K13 IO_L12N_SM5N_35 NET 'No_Conn_TP_IO_L14P_35' U2-K14 # 35 K14 IO_L14P_35 NET 'No_Conn_TP_IO_L16N_VRP_35' U2-L11 # 35 L11 IO_L16N_VRP_35 NET 'No_Conn_TP_IO_L18P_GC_35' U2-L12 # 35 L12 IO_L18P_GC_35 NET 'No_Conn_TP_IO_L14N_VREF_35' U2-L14 # 35 L14 IO_L14N_VREF_35 NET 'No_Conn_TP_IO_L18N_GC_35' U2-M12 # 35 M12 IO_L18N_GC_35 NET 'No_Conn_TP_IO_L10P_MRCC_35' U2-M13 # 35 M13 IO_L10P_MRCC_35 NET 'No_Conn_TP_IO_L9P_MRCC_35' U2-M14 # 35 M14 IO_L9P_MRCC_35 NET 'No_Conn_TP_IO_L10N_MRCC_35' U2-N13 # 35 N13 IO_L10N_MRCC_35 NET 'No_Conn_TP_IO_L9N_MRCC_35' U2-N14 # 35 N14 IO_L9N_MRCC_35 # Unused pins from IO bank 36 ############################# # note: some pins from this bank are used for the CTP Output NET 'No_Conn_TP_IO_L2P_36' U2-G16 # 36 G16 IO_L2P_36 NET 'No_Conn_TP_IO_L4N_VREF_36' U2-H16 # 36 H16 IO_L4N_VREF_36 NET 'No_Conn_TP_IO_L1P_36' U2-H18 # 36 H18 IO_L1P_36 NET 'No_Conn_TP_IO_L14P_36' U2-J15 # 36 J15 IO_L14P_36 NET 'No_Conn_TP_IO_L4P_36' U2-J16 # 36 J16 IO_L4P_36 NET 'No_Conn_TP_IO_L6N_36' U2-J17 # 36 J17 IO_L6N_36 NET 'No_Conn_TP_IO_L0N_36' U2-J18 # 36 J18 IO_L0N_36 NET 'No_Conn_TP_IO_L14N_VREF_36' U2-K15 # 36 K15 IO_L14N_VREF_36 NET 'No_Conn_TP_IO_L6P_36' U2-K17 # 36 K17 IO_L6P_36 NET 'No_Conn_TP_IO_L0P_36' U2-K18 # 36 K18 IO_L0P_36 NET 'No_Conn_TP_IO_L16N_36' U2-L15 # 36 L15 IO_L16N_36 NET 'No_Conn_TP_IO_L16P_36' U2-L16 # 36 L16 IO_L16P_36 NET 'No_Conn_TP_IO_L12P_VRN_36' U2-L17 # 36 L17 IO_L12P_VRN_36 NET 'No_Conn_TP_IO_L18P_36' U2-M16 # 36 M16 IO_L18P_36 NET 'No_Conn_TP_IO_L12N_VRP_36' U2-M17 # 36 M17 IO_L12N_VRP_36 NET 'No_Conn_TP_IO_L8P_SRCC_36' U2-M18 # 36 M18 IO_L8P_SRCC_36 NET 'No_Conn_TP_IO_L18N_36' U2-N15 # 36 N15 IO_L18N_36 NET 'No_Conn_TP_IO_L10P_MRCC_36' U2-N16 # 36 N16 IO_L10P_MRCC_36 NET 'No_Conn_TP_IO_L8N_SRCC_36' U2-N18 # 36 N18 IO_L8N_SRCC_36 NET 'No_Conn_TP_IO_L10N_MRCC_36' U2-P16 # 36 P16 IO_L10N_MRCC_36 NET 'No_Conn_TP_IO_L9N_MRCC_36' U2-P17 # 36 P17 IO_L9N_MRCC_36 NET 'No_Conn_TP_IO_L9P_MRCC_36' U2-P18 # 36 P18 IO_L9P_MRCC_36 # Unused pins from IO bank 37 ############################# # note: some pins from this bank are used for the CTP Output NET 'No_Conn_TP_IO_L0P_37' U2-G23 # 37 G23 IO_L0P_37 NET 'No_Conn_TP_IO_L14N_VREF_37' U2-H19 # 37 H19 IO_L14N_VREF_37 NET 'No_Conn_TP_IO_L0N_37' U2-H23 # 37 H23 IO_L0N_37 NET 'No_Conn_TP_IO_L14P_37' U2-J20 # 37 J20 IO_L14P_37 NET 'No_Conn_TP_IO_L18P_37' U2-K19 # 37 K19 IO_L18P_37 NET 'No_Conn_TP_IO_L16P_37' U2-K20 # 37 K20 IO_L16P_37 NET 'No_Conn_TP_IO_L18N_37' U2-L19 # 37 L19 IO_L18N_37 NET 'No_Conn_TP_IO_L16N_37' U2-L20 # 37 L20 IO_L16N_37 NET 'No_Conn_TP_IO_L9N_MRCC_37' U2-L21 # 37 L21 IO_L9N_MRCC_37 # Unused pins from IO bank 38 ############################# # note: some pins from this bank are used for the CTP Output NET 'No_Conn_TP_IO_L0N_38' U2-G24 # 38 G24 IO_L0N_38 NET 'No_Conn_TP_IO_L5P_38' U2-G26 # 38 G26 IO_L5P_38 NET 'No_Conn_TP_IO_L0P_38' U2-H24 # 38 H24 IO_L0P_38 NET 'No_Conn_TP_IO_L4N_VREF_38' U2-H25 # 38 H25 IO_L4N_VREF_38 NET 'No_Conn_TP_IO_L4P_38' U2-H26 # 38 H26 IO_L4P_38 NET 'No_Conn_TP_IO_L8P_SRCC_38' U2-J23 # 38 J23 IO_L8P_SRCC_38 NET 'No_Conn_TP_IO_L6N_38' U2-J25 # 38 J25 IO_L6N_38 NET 'No_Conn_TP_IO_L8N_SRCC_38' U2-K23 # 38 K23 IO_L8N_SRCC_38 NET 'No_Conn_TP_IO_L12N_VRP_38' U2-K24 # 38 K24 IO_L12N_VRP_38 NET 'No_Conn_TP_IO_L6P_38' U2-K25 # 38 K25 IO_L6P_38 NET 'No_Conn_TP_IO_L12P_VRN_38' U2-L24 # 38 L24 IO_L12P_VRN_38 NET 'No_Conn_TP_IO_L9P_MRCC_38' U2-M19 # 38 M19 IO_L9P_MRCC_38 NET 'No_Conn_TP_IO_L10N_MRCC_38' U2-M21 # 38 M21 IO_L10N_MRCC_38 NET 'No_Conn_TP_IO_L14P_38' U2-M22 # 38 M22 IO_L14P_38 NET 'No_Conn_TP_IO_L14N_VREF_38' U2-M23 # 38 M23 IO_L14N_VREF_38 NET 'No_Conn_TP_IO_L16N_38' U2-M24 # 38 M24 IO_L16N_38 NET 'No_Conn_TP_IO_L9N_MRCC_38' U2-N19 # 38 N19 IO_L9N_MRCC_38 NET 'No_Conn_TP_IO_L19N_38' U2-N20 # 38 N20 IO_L19N_38 NET 'No_Conn_TP_IO_L10P_MRCC_38' U2-N21 # 38 N21 IO_L10P_MRCC_38 NET 'No_Conn_TP_IO_L16P_38' U2-N23 # 38 N23 IO_L16P_38 NET 'No_Conn_TP_IO_L19P_38' U2-P20 # 38 P20 IO_L19P_38 NET 'No_Conn_TP_IO_L18P_38' U2-P21 # 38 P21 IO_L18P_38 NET 'No_Conn_TP_IO_L18N_38' U2-P22 # 38 P22 IO_L18N_38