# # CMX FF1759 Package NET-to-Pin File # -------------------------------------- # # # Original Rev. 1-Feb-2012 # Most Recent Rev. 14-Nov-2012 # # # # This is the N2P file is for Virtex-6 VCCAUX and VCCINT Nets # in the FF1759 Package. # # This file is for the TP FPGA on the CMX card. # # The following 20 pins are the Virtex-6 VCCAUX power pins. # On the CMX card the VCCAUX power will come from the BULK_2V5 # power distribution bus. NET 'BULK_2V5' U2-AA10 U2-AA28 U2-AB11 U2-AB29 U2-AC10 U2-AC28 NET 'BULK_2V5' U2-AD11 U2-AD29 U2-AE10 U2-AE28 U2-AF27 U2-AF29 U2-T29 U2-U28 U2-V11 U2-V29 NET 'BULK_2V5' U2-W10 U2-W28 U2-Y11 U2-Y29 # The following 104 pins are the Virtex-6 VCCINT power pins. # On the CMX card the VCCINT power for the Base Function FPGA # will come from the BASE_CORE power distribution bus. NET 'TP_CORE' U2-AA12 U2-AA14 U2-AA16 U2-AA18 U2-AA20 U2-AA24 NET 'TP_CORE' U2-AA26 U2-AB13 U2-AB15 U2-AB17 U2-AB19 U2-AB23 U2-AB25 U2-AB27 U2-AC12 U2-AC14 NET 'TP_CORE' U2-AC16 U2-AC18 U2-AC20 U2-AC24 U2-AC26 U2-AD13 U2-AD15 U2-AD17 U2-AD19 U2-AD21 NET 'TP_CORE' U2-AD23 U2-AD25 U2-AD27 U2-AE12 U2-AE14 U2-AE16 U2-AE18 U2-AE20 U2-AE22 U2-AE24 NET 'TP_CORE' U2-AE26 U2-AF13 U2-AF15 U2-AF17 U2-AF19 U2-AF21 U2-AF23 U2-AF25 U2-AG12 U2-AG14 NET 'TP_CORE' U2-AG16 U2-AG18 U2-AG20 U2-AG22 U2-AG24 U2-AG26 U2-AH13 U2-AH15 U2-AH19 U2-AH21 NET 'TP_CORE' U2-AH23 U2-P13 U2-P15 U2-R12 U2-R14 U2-R18 U2-R20 U2-R22 U2-R24 U2-T13 NET 'TP_CORE' U2-T15 U2-T17 U2-T19 U2-T21 U2-T23 U2-T25 U2-T27 U2-U12 U2-U14 U2-U16 NET 'TP_CORE' U2-U18 U2-U20 U2-U22 U2-U24 U2-U26 U2-V13 U2-V15 U2-V17 U2-V19 U2-V21 NET 'TP_CORE' U2-V23 U2-V25 U2-V27 U2-W12 U2-W14 U2-W16 U2-W18 U2-W20 U2-W22 U2-W24 NET 'TP_CORE' U2-W26 U2-Y13 U2-Y15 U2-Y17 U2-Y19 U2-Y23 U2-Y25 U2-Y27 # # CMX FF1759 Package NET-to-Pin File # -------------------------------------- # # # Bank 0 and Special Pins # ------===--------------------- # # # # Original Rev. 29-Dec-2012 # Most Recent Rev. 18-Mar-2012 # # # # This is the N2P file for Virtex-6 "Bank 0" and Special # Nets for the CMX Topological Function FPGA. # # Pins with many and completely different functions are # included in what Xilinx calls "Bank 0". These are not # Select I/O pins. Rather these pins include those that # are involved with thinks like Configuration, System # Monitor, JTAG, Power Management, Si temperature # measurement, ... # # These are all special one of a kind fixed location pins. # # Other "special" pins, besides those in "Bank 0" should # be included in this Net to Pin file. Recall, we want # to assign a net to every one of the 1760 pins on this # component. # # # This file is for the Topological Function FPGA on the CMX card. # -------------------- # # # JTAG connections to the Topological Function FPGA # # On the CMX's Virtex-6 FPGAs the JTAG connections # are pins in "Bank 0" NET 'CFG_TMS_from_ACE' U2-AN11 # TMS_0 CFG JTAG TMS from ACE pin 85 NET 'CFG_TCK_from_ACE' U2-AN10 # TCK_0 CFG JTAG TCK from ACE pin 80 NET 'CFG_TP_TDI' U2-AP10 # TDI_0 CFG JTAG Data from BF to TP NET 'CFG_TP_TDO' U2-AR10 # TDO_0 CFG JTAG Data from TP to ACE # # Configuration Nets NET 'TP_PROGRAM_B' U2-M11 # PROGRAM_B_0 NET 'TP_INIT_B' U2-N11 # INIT_B_0 NET 'TP_CONFIG_DONE' U2-N10 # DONE_0 NET 'TP_M0' U2-AL11 # M0_0 NET 'TP_M1' U2-AM11 # M1_0 NET 'TP_M2' U2-AL10 # M2_0 NET 'TP_CCLK' U2-K10 # CCLK_0 NET 'TP_DIN' U2-L10 # DIN_0 NET 'TP_DOUT_BUSY' U2-AK10 # DOUT_BUSY_0 NET 'TP_CSI_B' U2-T10 # CSI_B_0 NET 'TP_RDWR_B' U2-J10 # RDWR_B_0 # # System Monitor Nets NET 'TP_SM_AVDD' U2-Y22 # AVDD_0 NET 'TP_SM_AVSS' U2-Y21 # AVSS_0 NET 'TP_SM_VP' U2-AA22 # VP_0 NET 'TP_SM_VN' U2-AB21 # VN_0 NET 'TP_SM_VREFP' U2-AB22 # VREFP_0 NET 'TP_SM_AVSS' U2-AA21 # VREFN_0 # # Silicon Temperature Nets NET 'TP_SI_TEMP_DXP' U2-AC22 # DXP_0 NET 'TP_SI_TEMP_DXN' U2-AC21 # DXN_0 # # Other Special "Bank 0" Nets NET 'TP_HSWAPEN' U2-P10 # HSWAPEN_0 # VBATT is a power supply pin for the Decryptor Key memory. # The book says that when VBATT is not used to connect # this pin to either VccAUX or to GROUND. CMX will not # use the Decryptor Key VBATT supply. CMX will # permanently and irrevocably Ground this pin. # ## NET 'TP_VBATT' U2-R10 # VBATT_0 NET 'GROUND' U2-R10 # VBATT_0 # VFS is a power supply pin for programming the EFUSE. # The book says to Ground the VFS pin when it is not # being used. CMX will not use the EFUSE. Thus CMX # will permanently and irrevocably Ground this pin. # ## NET 'TP_VFS' U2-AH10 # VFS_0 NET 'GROUND' U2-AH10 # VFS_0 # # Special Non-Bank 0 Nets # # CMX FF1759 Package NET-to-Pin File # -------------------------------------- # # # Original Rev. 30-Jan-2012 # Most Recent Rev. 14-Nov-2012 # # # This is the N2P file is for Virtex-6 Ground Nets in the FF1759 Package. # # This file is for the TP FPGA on the CMX card. # # This file has 431 Ground Pins. # NET 'GROUND' U2-A2 U2-A3 U2-A4 U2-A7 U2-A8 U2-A11 U2-A13 U2-A18 U2-A28 NET 'GROUND' U2-A38 U2-AA3 U2-AA7 U2-AA9 U2-AA11 U2-AA13 U2-AA15 U2-AA17 U2-AA19 U2-AA23 NET 'GROUND' U2-AA25 U2-AA27 U2-AA29 U2-AA38 U2-AB1 U2-AB2 U2-AB5 U2-AB6 U2-AB9 U2-AB10 NET 'GROUND' U2-AB12 U2-AB14 U2-AB16 U2-AB18 U2-AB20 U2-AB24 U2-AB26 U2-AB28 U2-AB35 U2-AC3 NET 'GROUND' U2-AC7 U2-AC9 U2-AC11 U2-AC13 U2-AC15 U2-AC17 U2-AC19 U2-AC23 U2-AC25 U2-AC27 NET 'GROUND' U2-AC29 U2-AC32 U2-AC42 U2-AD1 U2-AD2 U2-AD5 U2-AD6 U2-AD9 U2-AD10 U2-AD12 NET 'GROUND' U2-AD14 U2-AD16 U2-AD18 U2-AD20 U2-AD22 U2-AD24 U2-AD26 U2-AD28 U2-AD39 U2-AE3 NET 'GROUND' U2-AE7 U2-AE9 U2-AE11 U2-AE13 U2-AE15 U2-AE17 U2-AE19 U2-AE21 U2-AE23 U2-AE25 NET 'GROUND' U2-AE27 U2-AE29 U2-AE36 U2-AF1 U2-AF2 U2-AF5 U2-AF6 U2-AF9 U2-AF10 U2-AF11 NET 'GROUND' U2-AF12 U2-AF14 U2-AF16 U2-AF18 U2-AF20 U2-AF22 U2-AF24 U2-AF26 U2-AF28 U2-AF33 NET 'GROUND' U2-AG3 U2-AG4 U2-AG7 U2-AG8 U2-AG9 U2-AG10 U2-AG11 U2-AG13 U2-AG15 U2-AG17 NET 'GROUND' U2-AG19 U2-AG21 U2-AG23 U2-AG30 U2-AG40 U2-AH1 U2-AH2 U2-AH5 U2-AH6 U2-AH9 NET 'GROUND' U2-AH11 U2-AH12 U2-AH14 U2-AH16 U2-AH17 U2-AH18 U2-AH20 U2-AH27 U2-AH37 U2-AJ3 NET 'GROUND' U2-AJ7 U2-AJ9 U2-AJ11 U2-AJ12 U2-AJ13 U2-AJ14 U2-AJ24 U2-AJ34 U2-AK1 U2-AK2 NET 'GROUND' U2-AK5 U2-AK6 U2-AK9 U2-AK11 U2-AK12 U2-AK13 U2-AK21 U2-AK31 U2-AK41 U2-AL3 NET 'GROUND' U2-AL7 U2-AL9 U2-AL12 U2-AL18 U2-AL28 U2-AL38 U2-AM1 U2-AM2 U2-AM5 U2-AM9 NET 'GROUND' U2-AM10 U2-AM15 U2-AM25 U2-AM35 U2-AN3 U2-AN7 U2-AN9 U2-AN12 U2-AN22 U2-AN32 NET 'GROUND' U2-AN42 U2-AP1 U2-AP2 U2-AP5 U2-AP9 U2-AP19 U2-AP29 U2-AP39 U2-AR3 U2-AR7 NET 'GROUND' U2-AR9 U2-AR16 U2-AR26 U2-AR36 U2-AT1 U2-AT2 U2-AT5 U2-AT6 U2-AT9 U2-AT10 NET 'GROUND' U2-AT11 U2-AT13 U2-AT23 U2-AT33 U2-AU3 U2-AU7 U2-AU11 U2-AU20 U2-AU30 U2-AU40 NET 'GROUND' U2-AV1 U2-AV2 U2-AV5 U2-AV9 U2-AV10 U2-AV11 U2-AV17 U2-AV27 U2-AV37 U2-AW3 NET 'GROUND' U2-AW7 U2-AW11 U2-AW14 U2-AW24 U2-AW34 U2-AY1 U2-AY2 U2-AY5 U2-AY9 U2-AY10 NET 'GROUND' U2-AY11 U2-AY12 U2-AY21 U2-AY31 U2-AY41 U2-B1 U2-B2 U2-B5 U2-B9 U2-B10 NET 'GROUND' U2-B12 U2-B13 U2-B15 U2-B25 U2-B35 U2-BA3 U2-BA7 U2-BA11 U2-BA12 U2-BA18 NET 'GROUND' U2-BA28 U2-BA38 U2-BB2 U2-BB5 U2-BB6 U2-BB9 U2-BB10 U2-BB11 U2-BB12 U2-BB15 NET 'GROUND' U2-BB25 U2-BB35 U2-C3 U2-C7 U2-C11 U2-C12 U2-C22 U2-C32 U2-C42 U2-D1 NET 'GROUND' U2-D2 U2-D5 U2-D9 U2-D10 U2-D11 U2-D19 U2-D29 U2-D39 U2-E3 U2-E7 NET 'GROUND' U2-E11 U2-E16 U2-E26 U2-E36 U2-F1 U2-F2 U2-F5 U2-F9 U2-F10 U2-F11 NET 'GROUND' U2-F13 U2-F23 U2-F33 U2-G3 U2-G7 U2-G11 U2-G20 U2-G30 U2-G40 U2-H1 NET 'GROUND' U2-H2 U2-H5 U2-H9 U2-H10 U2-H11 U2-H17 U2-H27 U2-H37 U2-J3 U2-J7 NET 'GROUND' U2-J9 U2-J14 U2-J24 U2-J34 U2-K1 U2-K2 U2-K5 U2-K6 U2-K9 U2-K11 NET 'GROUND' U2-K21 U2-K31 U2-K41 U2-L3 U2-L7 U2-L9 U2-L18 U2-L28 U2-L38 U2-M1 NET 'GROUND' U2-M2 U2-M5 U2-M6 U2-M9 U2-M15 U2-M25 U2-M35 U2-N3 U2-N7 U2-N9 NET 'GROUND' U2-N12 U2-N22 U2-N32 U2-N42 U2-P1 U2-P2 U2-P5 U2-P9 U2-P11 U2-P12 NET 'GROUND' U2-P19 U2-P29 U2-P39 U2-R3 U2-R7 U2-R9 U2-R13 U2-R15 U2-R16 U2-R17 NET 'GROUND' U2-R19 U2-R26 U2-R36 U2-T1 U2-T2 U2-T5 U2-T6 U2-T9 U2-T11 U2-T12 NET 'GROUND' U2-T14 U2-T16 U2-T18 U2-T20 U2-T22 U2-T24 U2-T26 U2-T33 U2-U3 U2-U4 NET 'GROUND' U2-U7 U2-U8 U2-U9 U2-U10 U2-U11 U2-U13 U2-U15 U2-U17 U2-U19 U2-U21 NET 'GROUND' U2-U23 U2-U25 U2-U27 U2-U29 U2-U30 U2-U40 U2-V1 U2-V2 U2-V5 U2-V6 NET 'GROUND' U2-V9 U2-V10 U2-V12 U2-V14 U2-V16 U2-V18 U2-V20 U2-V22 U2-V24 U2-V26 NET 'GROUND' U2-V28 U2-V37 U2-W3 U2-W7 U2-W9 U2-W11 U2-W13 U2-W15 U2-W17 U2-W19 NET 'GROUND' U2-W21 U2-W23 U2-W25 U2-W27 U2-W34 U2-Y1 U2-Y2 U2-Y5 U2-Y6 U2-Y9 NET 'GROUND' U2-Y10 U2-Y12 U2-Y14 U2-Y16 U2-Y18 U2-Y20 U2-Y24 U2-Y26 U2-Y28 U2-Y31 NET 'GROUND' U2-Y41 U2-AJ10 # # CMX FF1759 Package NET-to-Pin File # -------------------------------------- # # # Original Rev. 30-Jan-2012 # Most Recent Rev. 31-Dec-2012 # # # # This is the N2P file is for Virtex-6 MGTAVCC and MGTAVTT Nets # in the FF1759 Package. These are the analog power nets for # the high speed serial transceivers. # # This file is for the Topological Processor FPGA on the CMX card. # ----------------------- # # The following 18 pins are the Virtex-6 MGTAVCC power pins. # On the CMX card the MGTAVCC power will come from the GTX_AVTT # power distribution bus. NET 'TP_GTX_AVCC' U2-AA8 U2-C8 U2-E8 U2-G8 U2-J8 U2-L8 U2-N8 U2-R8 U2-W8 # MGTAVCC_N NET 'TP_GTX_AVCC' U2-AC8 U2-AE8 U2-AJ8 U2-AL8 U2-AN8 U2-AR8 U2-AU8 U2-AW8 U2-BA8 # MGTAVCC_S # The following 27 pins are the Virtex-6 MGTAVTT power pins. # On the CMX card the MGTAVTT power will come from the GTX_AVCC # power distribution bus. NET 'TP_GTX_AVTT' U2-B6 U2-C4 U2-D6 U2-E4 U2-F6 U2-G4 U2-H6 U2-J4 U2-L4 # MGTAVTT_N NET 'TP_GTX_AVTT' U2-N4 U2-P6 U2-R4 U2-W4 # MGTAVTT_N NET 'TP_GTX_AVTT' U2-AA4 U2-AC4 U2-AE4 U2-AJ4 U2-AL4 U2-AM6 U2-AN4 U2-AP6 # MGTAVTT_S NET 'TP_GTX_AVTT' U2-AR4 U2-AU4 U2-AV6 U2-AW4 U2-AY6 U2-BA4 # MGTAVTT_S # # CMX FF1759 Package NET-to-Pin File # -------------------------------------- # # # Original Rev. 30-Jan-2012 # Most Recent Rev. 14-Nov-2012 # # # # This is the N2P file is for Virtex-6 VCCO_xy Nets # in the FF1759 Package. # # This file is for the TP FPGA on the CMX card. # # The following 112 pins are the Virtex-6 VCCO power pins. # On the CMX card the VCCO power will come from the BULK_2V5 # power distribution bus. All TP FPGA I/O Banks will have # 2.5V signal levels. # NET 'BULK_2V5' U2-M10 U2-R11 # VCCO_0 NET 'BULK_2V5' U2-AP34 U2-AT38 U2-AU35 U2-AW39 U2-AY36 # VCCO_12 NET 'BULK_2V5' U2-AK36 U2-AN37 U2-AR41 U2-AV42 U2-BB40 # VCCO_13 NET 'BULK_2V5' U2-AF38 U2-AG35 U2-AH42 U2-AJ39 U2-AM40 # VCCO_14 NET 'BULK_2V5' U2-AA33 U2-AB40 U2-AC37 U2-AD34 U2-AE41 # VCCO_15 NET 'BULK_2V5' U2-U35 U2-V32 U2-V42 U2-W39 U2-Y36 # VCCO_16 NET 'BULK_2V5' U2-M40 U2-N37 U2-P34 U2-R41 U2-T38 # VCCO_17 NET 'BULK_2V5' U2-AH22 U2-AL23 U2-AP24 U2-AU25 U2-AY26 # VCCO_21 NET 'BULK_2V5' U2-AN27 U2-AT28 U2-AW29 U2-BA33 U2-BB30 # VCCO_22 NET 'BULK_2V5' U2-AG25 U2-AK26 U2-AL33 U2-AM30 U2-AR31 U2-AV32 # VCCO_23 NET 'BULK_2V5' U2-AB30 U2-AE31 U2-AH32 U2-AJ29 U2-R31 U2-W29 # VCCO_24 NET 'BULK_2V5' U2-H42 U2-J39 U2-K36 U2-L33 U2-M30 U2-T28 # VCCO_25 NET 'BULK_2V5' U2-B40 U2-C37 U2-E41 U2-F38 U2-G35 # VCCO_26 NET 'BULK_2V5' U2-A33 U2-D34 U2-E31 U2-H32 U2-J29 # VCCO_27 NET 'BULK_2V5' U2-B30 U2-F28 U2-K26 U2-N27 U2-P24 # VCCO_28 NET 'BULK_2V5' U2-AJ19 U2-AM20 U2-AR21 U2-AV22 U2-BA23 # VCCO_32 NET 'BULK_2V5' U2-AK16 U2-AL13 U2-AN17 U2-AT18 U2-AW19 U2-BB20 # VCCO_33 NET 'BULK_2V5' U2-AP14 U2-AR11 U2-AU15 U2-AV12 U2-AY16 U2-BA13 # VCCO_34 NET 'BULK_2V5' U2-C17 U2-D14 U2-G15 U2-H12 U2-L13 # VCCO_35 NET 'BULK_2V5' U2-B20 U2-F18 U2-K16 U2-N17 U2-P14 # VCCO_36 NET 'BULK_2V5' U2-A23 U2-D24 U2-E21 U2-H22 U2-J19 # VCCO_37 NET 'BULK_2V5' U2-C27 U2-G25 U2-L23 U2-M20 U2-R21 # VCCO_38