# # CMX Backplane Connector #1 Net-to-Pin File # ------------------------------------------------ # # # Original Rev. 29-Aug-2011 # Rev: 11-Apr-2012 (added backplane linear rank "bxxx") # Rev: 06-Sep-2011 remove the linear rank and add comments # Most Recent Rev: 30-Oct-2012 Add "_" to the VME signal names and # make the VME Control Signal names fit # the VME-- document. # # # This is the N2P file for Backplane Connector #1 on the CMX card. # This is a 2mm hard metric 5 Column x 19 Row type "B-19" connector # with ground shield. # # This is connector J1 in the CMX card design. # # This connector carries the "VME--" signals (a custom subset # of VME for A24/D16 transfers only): # # VME_Dnn are the 16 data signals nn=00 to 15 # VME_App are the 23 address signal with pp=01 to 23 # VME_DS_B is the control signal for data strobe # VME_WRITE_B is the control signal for direction control # VME_DTACK_B is the control signal for data transfer acknowledgement # VME_SYS_RESET_B is the control signal for VME reset # # # 'Pxx_yy' are the single ended signals (series terminated at the source) # coming from the JEM or CPM Processor cards in the crate # There are (up to) 16 Processor cards in a crate and xx = 0 to 15 # Each Processor sends 25 signals to the CMX card and yy = 0 to 24 # ## no net on pin J1-A1 . NET 'GROUND' J1-B1 NET 'VME_D00' J1-C1 NET 'VME_D08' J1-D1 NET 'VME_D09' J1-E1 ## no net on pin J1-A2 . NET 'VME_D01' J1-B2 NET 'VME_D02' J1-C2 NET 'VME_D10' J1-D2 NET 'VME_D11' J1-E2 ## no net on pin J1-A3 . NET 'GROUND' J1-B3 NET 'VME_D03' J1-C3 NET 'VME_D12' J1-D3 NET 'VME_D13' J1-E3 ## no net on pin J1-A4 . NET 'VME_D04' J1-B4 NET 'VME_D05' J1-C4 NET 'VME_D14' J1-D4 NET 'VME_D15' J1-E4 ## no net on pin J1-A5 . NET 'GROUND' J1-B5 NET 'VME_D06' J1-C5 NET 'VME_A23' J1-D5 NET 'VME_A22' J1-E5 ## no net on pin J1-A6 . NET 'VME_D07' J1-B6 NET 'GROUND' J1-C6 NET 'VME_A21' J1-D6 NET 'VME_A20' J1-E6 ## no net on pin J1-A7 . NET 'GROUND' J1-B7 NET 'VME_DS_B' J1-C7 NET 'GROUND' J1-D7 NET 'GROUND' J1-E7 ## no net on pin J1-A8 . NET 'VME_WRITE_B' J1-B8 NET 'GROUND' J1-C8 NET 'VME_A18' J1-D8 NET 'VME_A19' J1-E8 ## no net on pin J1-A9 . NET 'GROUND' J1-B9 NET 'VME_DTACK_B' J1-C9 NET 'VME_A16' J1-D9 NET 'VME_A17' J1-E9 NET 'GROUND' J1-A10 NET 'VME_A07' J1-B10 NET 'VME_A06' J1-C10 NET 'VME_A14' J1-D10 NET 'VME_A15' J1-E10 NET 'P0_0' J1-A11 NET 'GROUND' J1-B11 NET 'VME_A05' J1-C11 NET 'VME_A12' J1-D11 NET 'VME_A13' J1-E11 NET 'P0_1' J1-A12 NET 'VME_A04' J1-B12 NET 'VME_A03' J1-C12 NET 'VME_A10' J1-D12 NET 'VME_A11' J1-E12 NET 'P0_2' J1-A13 NET 'GROUND' J1-B13 NET 'VME_A02' J1-C13 NET 'VME_A08' J1-D13 NET 'VME_A09' J1-E13 NET 'P0_3' J1-A14 NET 'VME_SYS_RESET_B' J1-B14 NET 'VME_A01' J1-C14 NET 'GROUND' J1-D14 NET 'GROUND' J1-E14 NET 'P0_4' J1-A15 NET 'P1_0' J1-B15 NET 'GROUND' J1-C15 NET 'P2_0' J1-D15 NET 'P3_0' J1-E15 NET 'P0_5' J1-A16 NET 'GROUND' J1-B16 NET 'P1_1' J1-C16 NET 'P2_1' J1-D16 NET 'P3_1' J1-E16 NET 'P0_6' J1-A17 NET 'P1_2' J1-B17 NET 'P2_2' J1-C17 NET 'GROUND' J1-D17 NET 'P3_2' J1-E17 NET 'P0_7' J1-A18 NET 'GROUND' J1-B18 NET 'P1_3' J1-C18 NET 'P2_3' J1-D18 NET 'P3_3' J1-E18 NET 'P0_8' J1-A19 NET 'P1_4' J1-B19 NET 'P2_4' J1-C19 NET 'GROUND' J1-D19 NET 'P3_4' J1-E19 NET 'GROUND' J1-F1 NET 'GROUND' J1-F3 NET 'GROUND' J1-F5 NET 'GROUND' J1-F7 NET 'GROUND' J1-F9 NET 'GROUND' J1-F11 NET 'GROUND' J1-F13 NET 'GROUND' J1-F15 NET 'GROUND' J1-F17 NET 'GROUND' J1-F19 # # CMX Backplane Connector #2 Net-to-Pin File # ------------------------------------------------ # # # Original Rev. 30-Aug-2011 # Rev: 11-Apr-2012 (added backplane linear rank "bxxx") # Rev: 06-Sep-2011 remove the linear rank and add comments # Most Recent Rev: 30-Oct-2012 Standardize the names of the Geographic # Address signals to indicate that they # come from the VME Backplane Bus. # # # This is the N2P file for Backplane Connector #2 on the CMX card. # This is a 2mm hard metric 5 Column x 19 Row type "B-19" connector # with ground shield. # # This is connector J2 in the CMX card design. # # This connector includes the 4 Geographic Address signals: # VME_Geo_ADRS_0, VME_Geo_ADRS_4, VME_Geo_ADRS_5, VME_Geo_ADRS_6 # # 'Pxx_yy' are the single ended signals (series terminated at the source) # coming from the JEM or CPM Processor cards in the crate # There are (up to) 16 Processor cards in a crate and xx = 0 to 15 # Each Processor sends 25 signals to the CMX card and yy = 0 to 24 # NET 'P0_9' J2-A1 NET 'GROUND' J2-B1 NET 'P1_5' J2-C1 NET 'P2_5' J2-D1 NET 'P3_5' J2-E1 NET 'P0_10' J2-A2 NET 'P1_6' J2-B2 NET 'P2_6' J2-C2 NET 'GROUND' J2-D2 NET 'P3_6' J2-E2 NET 'P0_11' J2-A3 NET 'GROUND' J2-B3 NET 'P1_7' J2-C3 NET 'P2_7' J2-D3 NET 'P3_7' J2-E3 NET 'P0_12' J2-A4 NET 'P1_8' J2-B4 NET 'P2_8' J2-C4 NET 'GROUND' J2-D4 NET 'P3_8' J2-E4 NET 'P0_13' J2-A5 NET 'GROUND' J2-B5 NET 'P1_9' J2-C5 NET 'P2_9' J2-D5 NET 'P3_9' J2-E5 NET 'P0_14' J2-A6 NET 'P1_10' J2-B6 NET 'P2_10' J2-C6 NET 'GROUND' J2-D6 NET 'P3_10' J2-E6 NET 'P0_15' J2-A7 NET 'GROUND' J2-B7 NET 'P1_11' J2-C7 NET 'P2_11' J2-D7 NET 'P3_11' J2-E7 NET 'P0_16' J2-A8 NET 'P1_12' J2-B8 NET 'P2_12' J2-C8 NET 'GROUND' J2-D8 NET 'P3_12' J2-E8 NET 'P0_17' J2-A9 NET 'GROUND' J2-B9 NET 'P1_13' J2-C9 NET 'P2_13' J2-D9 NET 'P3_13' J2-E9 NET 'P0_18' J2-A10 NET 'P1_14' J2-B10 NET 'P2_14' J2-C10 NET 'GROUND' J2-D10 NET 'P3_14' J2-E10 NET 'P0_19' J2-A11 NET 'GROUND' J2-B11 NET 'P1_15' J2-C11 NET 'P2_15' J2-D11 NET 'P3_15' J2-E11 NET 'P0_20' J2-A12 NET 'P1_16' J2-B12 NET 'P2_16' J2-C12 NET 'GROUND' J2-D12 NET 'P3_16' J2-E12 NET 'P0_21' J2-A13 NET 'GROUND' J2-B13 NET 'P1_17' J2-C13 NET 'P2_17' J2-D13 NET 'P3_17' J2-E13 NET 'P0_22' J2-A14 NET 'P1_18' J2-B14 NET 'P2_18' J2-C14 NET 'GROUND' J2-D14 NET 'P3_18' J2-E14 NET 'P0_23' J2-A15 NET 'GROUND' J2-B15 NET 'P1_19' J2-C15 NET 'P2_19' J2-D15 NET 'P3_19' J2-E15 NET 'P0_24' J2-A16 NET 'P1_20' J2-B16 NET 'P2_20' J2-C16 NET 'GROUND' J2-D16 NET 'P3_20' J2-E16 NET 'VME_GEO_ADRS_5' J2-A17 NET 'P1_21' J2-B17 NET 'VME_GEO_ADRS_4' J2-C17 NET 'P2_21' J2-D17 NET 'P3_21' J2-E17 NET 'VME_GEO_ADRS_6' J2-A18 NET 'P1_22' J2-B18 NET 'P2_22' J2-C18 NET 'GROUND' J2-D18 NET 'P3_22' J2-E18 NET 'VME_GEO_ADRS_0' J2-A19 NET 'GROUND' J2-B19 NET 'P1_23' J2-C19 NET 'P2_23' J2-D19 NET 'P3_23' J2-E19 NET 'GROUND' J2-F1 NET 'GROUND' J2-F3 NET 'GROUND' J2-F5 NET 'GROUND' J2-F7 NET 'GROUND' J2-F9 NET 'GROUND' J2-F11 NET 'GROUND' J2-F13 NET 'GROUND' J2-F15 NET 'GROUND' J2-F17 NET 'GROUND' J2-F19 # # CMX Backplane Connector #3 Net-to-Pin File # ------------------------------------------------ # # # Original Rev. 07-Sep-2011 # Rev: 11-Apr-2012 (added backplane linear rank "bxxx") # Most Recent Rev: 06-Sep-2011 remove the linear rank and add comments # # # This is the N2P file for Backplane Connector #3 on the CMX card. # This is a 2mm hard metric 5 Column x 19 Row type "B-19" connector # with ground shield. # # This is connector J3 in the CMX card design. # # 'Pxx_yy' are the single ended signals (series terminated at the source) # coming from the JEM or CPM Processor cards in the crate # There are (up to) 16 Processor cards in a crate and xx = 0 to 15 # Each Processor sends 25 signals to the CMX card and yy = 0 to 24 # NET 'P4_0' J3-A1 NET 'P1_24' J3-B1 NET 'P2_24' J3-C1 NET 'GROUND' J3-D1 NET 'P3_24' J3-E1 NET 'P4_1' J3-A2 NET 'GROUND' J3-B2 NET 'P5_0' J3-C2 NET 'P6_0' J3-D2 NET 'P7_0' J3-E2 NET 'P4_2' J3-A3 NET 'P5_1' J3-B3 NET 'P6_1' J3-C3 NET 'GROUND' J3-D3 NET 'P7_1' J3-E3 NET 'P4_3' J3-A4 NET 'GROUND' J3-B4 NET 'P5_2' J3-C4 NET 'P6_2' J3-D4 NET 'P7_2' J3-E4 NET 'P4_4' J3-A5 NET 'P5_3' J3-B5 NET 'P6_3' J3-C5 NET 'GROUND' J3-D5 NET 'P7_3' J3-E5 NET 'P4_5' J3-A6 NET 'GROUND' J3-B6 NET 'P5_4' J3-C6 NET 'P6_4' J3-D6 NET 'P7_4' J3-E6 NET 'P4_6' J3-A7 NET 'P5_5' J3-B7 NET 'P6_5' J3-C7 NET 'GROUND' J3-D7 NET 'P7_5' J3-E7 NET 'P4_7' J3-A8 NET 'GROUND' J3-B8 NET 'P5_6' J3-C8 NET 'P6_6' J3-D8 NET 'P7_6' J3-E8 NET 'P4_8' J3-A9 NET 'P5_7' J3-B9 NET 'P6_7' J3-C9 NET 'GROUND' J3-D9 NET 'P7_7' J3-E9 NET 'P4_9' J3-A10 NET 'GROUND' J3-B10 NET 'P5_8' J3-C10 NET 'P6_8' J3-D10 NET 'P7_8' J3-E10 NET 'P4_10' J3-A11 NET 'P5_9' J3-B11 NET 'P6_9' J3-C11 NET 'GROUND' J3-D11 NET 'P7_9' J3-E11 NET 'P4_11' J3-A12 NET 'GROUND' J3-B12 NET 'P5_10' J3-C12 NET 'P6_10' J3-D12 NET 'P7_10' J3-E12 NET 'P4_12' J3-A13 NET 'P5_11' J3-B13 NET 'P6_11' J3-C13 NET 'GROUND' J3-D13 NET 'P7_11' J3-E13 NET 'P4_13' J3-A14 NET 'GROUND' J3-B14 NET 'P5_12' J3-C14 NET 'P6_12' J3-D14 NET 'P7_12' J3-E14 NET 'P4_14' J3-A15 NET 'P5_13' J3-B15 NET 'P6_13' J3-C15 NET 'GROUND' J3-D15 NET 'P7_13' J3-E15 NET 'P4_15' J3-A16 NET 'GROUND' J3-B16 NET 'P5_14' J3-C16 NET 'P6_14' J3-D16 NET 'P7_14' J3-E16 NET 'P4_16' J3-A17 NET 'P5_15' J3-B17 NET 'P6_15' J3-C17 NET 'GROUND' J3-D17 NET 'P7_15' J3-E17 NET 'P4_17' J3-A18 NET 'GROUND' J3-B18 NET 'P5_16' J3-C18 NET 'P6_16' J3-D18 NET 'P7_16' J3-E18 NET 'P4_18' J3-A19 NET 'P5_17' J3-B19 NET 'P6_17' J3-C19 NET 'GROUND' J3-D19 NET 'P7_17' J3-E19 NET 'GROUND' J3-F1 NET 'GROUND' J3-F3 NET 'GROUND' J3-F5 NET 'GROUND' J3-F7 NET 'GROUND' J3-F9 NET 'GROUND' J3-F11 NET 'GROUND' J3-F13 NET 'GROUND' J3-F15 NET 'GROUND' J3-F17 NET 'GROUND' J3-F19 # # CMX Backplane Connector #4 Net-to-Pin File # ------------------------------------------------ # # # Original Rev. 07-Sep-2011 # Rev: 11-Apr-2012 (added backplane linear rank "bxxx") # Rev: 06-Sep-2011 remove the linear rank and add comments # Most Recent Rev: 22-July-2013 Until now the pins have # been connected to the GROUND net. Now # connect them to the REAR_CG_GND net. # There are 6 of the pins in connector J4. # # # # # This is the N2P file for Backplane Connector #4 on the CMX card. # This is a 2mm hard metric 5 Column x 19 Row type "B-19" connector # with ground shield. # # This is connector J4 in the CMX card design. # # 'Pxx_yy' are the single ended signals (series terminated at the source) # coming from the JEM or CPM Processor cards in the crate # There are (up to) 16 Processor cards in a crate and xx = 0 to 15 # Each Processor sends 25 signals to the CMX card and yy = 0 to 24 # # 'M_zz_POS' and 'M_zz_NEG' are the LVDS signal used for Cable IO # from a Crate CMX card to a System CMX card. 'M_zz_POS' is the # non-inverted signal and 'M_zz_NEG' is the inverted signal. # There are up to 3 cables used for a given CMX card. # A Crate CMX card uses one cable as output only, while a System CMX # card receives 2 or 3 cables as input. # A Rear Transition Module (RTM) card provides the interface to the # three 34-signal LVDS connectors. # Only 27 signals from each connector are routed on the current RTM cards. # zz=0 to 26 correspond to the first cable, # zz=27 to 53 correspond to the second cable, and # zz=54 to 80 correspond to the third cable. # Additionally, 3 more sets of signals are labelled on the backplane # but are not routed on the RTM: zz= 31 to 83 # NET 'P4_19' J4-A1 NET 'GROUND' J4-B1 NET 'P5_18' J4-C1 NET 'P6_18' J4-D1 NET 'P7_18' J4-E1 NET 'P4_20' J4-A2 NET 'P5_19' J4-B2 NET 'P6_19' J4-C2 NET 'GROUND' J4-D2 NET 'P7_19' J4-E2 NET 'P4_21' J4-A3 NET 'GROUND' J4-B3 NET 'P5_20' J4-C3 NET 'P6_20' J4-D3 NET 'P7_20' J4-E3 NET 'P4_22' J4-A4 NET 'P5_21' J4-B4 NET 'P6_21' J4-C4 NET 'GROUND' J4-D4 NET 'P7_21' J4-E4 NET 'P4_23' J4-A5 NET 'GROUND' J4-B5 NET 'P5_22' J4-C5 NET 'P6_22' J4-D5 NET 'P7_22' J4-E5 NET 'P4_24' J4-A6 NET 'P5_23' J4-B6 NET 'P6_23' J4-C6 NET 'GROUND' J4-D6 NET 'P7_23' J4-E6 NET 'GROUND' J4-A7 NET 'GROUND' J4-B7 NET 'P5_24' J4-C7 NET 'P6_24' J4-D7 NET 'P7_24' J4-E7 NET 'M_00_POS' J4-A8 NET 'M_01_POS' J4-B8 NET 'M_02_POS' J4-C8 NET 'M_03_POS' J4-D8 NET 'M_04_POS' J4-E8 NET 'M_00_NEG' J4-A9 NET 'M_01_NEG' J4-B9 NET 'M_02_NEG' J4-C9 NET 'M_03_NEG' J4-D9 NET 'M_04_NEG' J4-E9 NET 'M_05_POS' J4-A10 NET 'M_06_POS' J4-B10 NET 'M_07_POS' J4-C10 NET 'REAR_CG_GND' J4-D10 # this is a cable ground NET 'M_08_POS' J4-E10 NET 'M_05_NEG' J4-A11 NET 'M_06_NEG' J4-B11 NET 'M_07_NEG' J4-C11 NET 'REAR_CG_GND' J4-D11 # this is a cable ground NET 'M_08_NEG' J4-E11 NET 'M_09_POS' J4-A12 NET 'M_10_POS' J4-B12 NET 'M_11_POS' J4-C12 NET 'M_12_POS' J4-D12 NET 'M_13_POS' J4-E12 NET 'M_09_NEG' J4-A13 NET 'M_10_NEG' J4-B13 NET 'M_11_NEG' J4-C13 NET 'M_12_NEG' J4-D13 NET 'M_13_NEG' J4-E13 NET 'M_14_POS' J4-A14 NET 'REAR_CG_GND' J4-B14 # this is a cable ground NET 'M_15_POS' J4-C14 NET 'M_16_POS' J4-D14 NET 'M_17_POS' J4-E14 NET 'M_14_NEG' J4-A15 NET 'REAR_CG_GND' J4-B15 # this is a cable ground NET 'M_15_NEG' J4-C15 NET 'M_16_NEG' J4-D15 NET 'M_17_NEG' J4-E15 NET 'M_18_POS' J4-A16 NET 'M_19_POS' J4-B16 NET 'M_20_POS' J4-C16 NET 'M_21_POS' J4-D16 NET 'M_22_POS' J4-E16 NET 'M_18_NEG' J4-A17 NET 'M_19_NEG' J4-B17 NET 'M_20_NEG' J4-C17 NET 'M_21_NEG' J4-D17 NET 'M_22_NEG' J4-E17 NET 'M_23_POS' J4-A18 NET 'M_24_POS' J4-B18 NET 'M_25_POS' J4-C18 NET 'REAR_CG_GND' J4-D18 # this is a cable ground NET 'M_26_POS' J4-E18 NET 'M_23_NEG' J4-A19 NET 'M_24_NEG' J4-B19 NET 'M_25_NEG' J4-C19 NET 'REAR_CG_GND' J4-D19 # this is a cable ground NET 'M_26_NEG' J4-E19 NET 'GROUND' J4-F1 NET 'GROUND' J4-F3 NET 'GROUND' J4-F5 NET 'GROUND' J4-F7 NET 'GROUND' J4-F9 NET 'GROUND' J4-F11 NET 'GROUND' J4-F13 NET 'GROUND' J4-F15 NET 'GROUND' J4-F17 NET 'GROUND' J4-F19 # # CMX Backplane Connector #5 Net-to-Pin File # ------------------------------------------------ # # # Original Rev. 08-Sep-2011 # Rev: 11-Apr-2012 (added backplane linear rank "bxxx") # Rev: 06-Sep-2011 remove the linear rank and add comments # Most Recent Rev: 22-July-2013 Until now the pins have # been connected to the GROUND net. Now # connect them to the REAR_CG_GND net. # There are 9 of the pins in connector J5. # # # # # This is the N2P file for Backplane Connector #5 on the CMX card. # This is a 2mm hard metric 5 Column x 25 Row type "B-25" connector # with ground shield. # # This is connector J5 in the CMX card design. # # 'Pxx_yy' are the single ended signals (series terminated at the source) # coming from the JEM or CPM Processor cards in the crate # There are (up to) 16 Processor cards in a crate and xx = 0 to 15 # Each Processor sends 25 signals to the CMX card and yy = 0 to 24 # # 'M_zz_POS' and 'M_zz_NEG' are the LVDS signal used for Cable IO # from a Crate CMX card to a System CMX card. 'M_zz_POS' is the # non-inverted signal and 'M_zz_NEG' is the inverted signal. # There are up to 3 cables used for a given CMX card. # A Crate CMX card uses one cable as output only, while a System CMX # card receives 2 or 3 cables as input. # A Rear Transition Module (RTM) card provides the interface to the # three 34-signal LVDS connectors. # Only 27 signals from each connector are routed on the current RTM cards. # zz=0 to 26 correspond to the first cable, # zz=27 to 53 correspond to the second cable, and # zz=54 to 80 correspond to the third cable. # Additionally, 3 more sets of signals are labelled on the backplane # but are not routed on the RTM: zz= 31 to 83 # NET 'M_27_POS' J5-A1 NET 'M_28_POS' J5-B1 NET 'M_29_POS' J5-C1 NET 'M_30_POS' J5-D1 NET 'M_31_POS' J5-E1 NET 'M_27_NEG' J5-A2 NET 'M_28_NEG' J5-B2 NET 'M_29_NEG' J5-C2 NET 'M_30_NEG' J5-D2 NET 'M_31_NEG' J5-E2 NET 'M_32_POS' J5-A3 NET 'REAR_CG_GND' J5-B3 # this is a cable ground NET 'M_33_POS' J5-C3 NET 'M_34_POS' J5-D3 NET 'M_35_POS' J5-E3 NET 'M_32_NEG' J5-A4 NET 'REAR_CG_GND' J5-B4 # this is a cable ground NET 'M_33_NEG' J5-C4 NET 'M_34_NEG' J5-D4 NET 'M_35_NEG' J5-E4 NET 'M_36_POS' J5-A5 NET 'M_37_POS' J5-B5 NET 'M_38_POS' J5-C5 NET 'M_39_POS' J5-D5 NET 'M_40_POS' J5-E5 NET 'M_36_NEG' J5-A6 NET 'M_37_NEG' J5-B6 NET 'M_38_NEG' J5-C6 NET 'M_39_NEG' J5-D6 NET 'M_40_NEG' J5-E6 NET 'M_41_POS' J5-A7 NET 'M_42_POS' J5-B7 NET 'M_43_POS' J5-C7 NET 'REAR_CG_GND' J5-D7 # this is a cable ground NET 'M_44_POS' J5-E7 NET 'M_41_NEG' J5-A8 NET 'M_42_NEG' J5-B8 NET 'M_43_NEG' J5-C8 NET 'REAR_CG_GND' J5-D8 # this is a cable ground NET 'M_44_NEG' J5-E8 NET 'M_45_POS' J5-A9 NET 'M_46_POS' J5-B9 NET 'M_47_POS' J5-C9 NET 'M_48_POS' J5-D9 NET 'M_49_POS' J5-E9 NET 'M_45_NEG' J5-A10 NET 'M_46_NEG' J5-B10 NET 'M_47_NEG' J5-C10 NET 'M_48_NEG' J5-D10 NET 'M_49_NEG' J5-E10 NET 'M_50_POS' J5-A11 NET 'M_51_POS' J5-B11 NET 'REAR_CG_GND' J5-C11 # this is a cable ground NET 'M_52_POS' J5-D11 NET 'M_53_POS' J5-E11 NET 'M_50_NEG' J5-A12 NET 'M_51_NEG' J5-B12 NET 'REAR_CG_GND' J5-C12 # this is a cable ground NET 'M_52_NEG' J5-D12 NET 'M_53_NEG' J5-E12 NET 'GROUND' J5-A13 NET 'M_54_POS' J5-B13 NET 'M_55_POS' J5-C13 NET 'M_56_POS' J5-D13 NET 'M_57_POS' J5-E13 NET 'P8_0' J5-A14 NET 'M_54_NEG' J5-B14 NET 'M_55_NEG' J5-C14 NET 'M_56_NEG' J5-D14 NET 'M_57_NEG' J5-E14 NET 'P8_1' J5-A15 NET 'GROUND' J5-B15 NET 'REAR_CG_GND' J5-C15 # this is a cable ground NET 'M_59_POS' J5-D15 NET 'M_60_POS' J5-E15 NET 'P8_2' J5-A16 NET 'M_58_POS' J5-B16 NET 'REAR_CG_GND' J5-C16 # this is a cable ground NET 'M_59_NEG' J5-D16 NET 'M_60_NEG' J5-E16 NET 'P8_3' J5-A17 NET 'M_58_NEG' J5-B17 NET 'M_61_POS' J5-C17 NET 'M_62_POS' J5-D17 NET 'M_63_POS' J5-E17 NET 'P8_4' J5-A18 NET 'GROUND' J5-B18 NET 'M_61_NEG' J5-C18 NET 'M_62_NEG' J5-D18 NET 'M_63_NEG' J5-E18 NET 'P8_5' J5-A19 NET 'M_64_POS' J5-B19 NET 'M_65_POS' J5-C19 NET 'REAR_CG_GND' J5-D19 # this is a cable ground NET 'M_66_POS' J5-E19 NET 'P8_6' J5-A20 NET 'M_64_NEG' J5-B20 NET 'M_65_NEG' J5-C20 NET 'M_68_POS' J5-D20 NET 'M_66_NEG' J5-E20 NET 'P8_7' J5-A21 NET 'GROUND' J5-B21 NET 'M_67_POS' J5-C21 NET 'M_68_NEG' J5-D21 NET 'M_69_POS' J5-E21 NET 'P8_8' J5-A22 NET 'GROUND' J5-B22 NET 'M_67_NEG' J5-C22 NET 'M_71_POS' J5-D22 NET 'M_69_NEG' J5-E22 NET 'P8_9' J5-A23 NET 'P9_0' J5-B23 NET 'M_70_POS' J5-C23 NET 'M_71_NEG' J5-D23 NET 'M_72_POS' J5-E23 NET 'P8_10' J5-A24 NET 'P9_1' J5-B24 NET 'M_70_NEG' J5-C24 NET 'M_73_POS' J5-D24 NET 'M_72_NEG' J5-E24 NET 'P8_11' J5-A25 NET 'P9_2' J5-B25 NET 'GROUND' J5-C25 NET 'M_73_NEG' J5-D25 NET 'M_74_POS' J5-E25 NET 'GROUND' J5-F1 NET 'GROUND' J5-F3 NET 'GROUND' J5-F5 NET 'GROUND' J5-F7 NET 'GROUND' J5-F9 NET 'GROUND' J5-F11 NET 'GROUND' J5-F13 NET 'GROUND' J5-F15 NET 'GROUND' J5-F17 NET 'GROUND' J5-F19 NET 'GROUND' J5-F21 NET 'GROUND' J5-F23 NET 'GROUND' J5-F25 # # CMX Backplane Connector #6 Net-to-Pin File # ------------------------------------------------ # # # Original Rev. 08-Sep-2011 # Rev: 11-Apr-2012 (added backplane linear rank "bxxx") # Rev: 06-Sep-2011 remove the linear rank and add comments # Most Recent Rev: 22-July-2013 Until now the pins have # been connected to the GROUND net. Now # connect them to the REAR_CG_GND net. # There are 3 of the pins in connector J6. # # # # This is the N2P file for Backplane Connector #6 on the CMX card. # This is a 2mm hard metric 5 Column x 19 Row type "B-19" connector # with ground shield. # # This is connector J6 in the CMX card design. # # 'Pxx_yy' are the single ended signals (series terminated at the source) # coming from the JEM or CPM Processor cards in the crate # There are (up to) 16 Processor cards in a crate and xx = 0 to 15 # Each Processor sends 25 signals to the CMX card and yy = 0 to 24 # # 'M_zz_POS' and 'M_zz_NEG' are the LVDS signal used for Cable IO # from a Crate CMX card to a System CMX card. 'M_zz_POS' is the # non-inverted signal and 'M_zz_NEG' is the inverted signal. # There are up to 3 cables used for a given CMX card. # A Crate CMX card uses one cable as output only, while a System CMX # card receives 2 or 3 cables as input. # A Rear Transition Module (RTM) card provides the interface to the # three 34-signal LVDS connectors. # Only 27 signals from each connector are routed on the current RTM cards. # zz=0 to 26 correspond to the first cable, # zz=27 to 53 correspond to the second cable, and # zz=54 to 80 correspond to the third cable. # Additionally, 3 more sets of signals are labelled on the backplane # but are not routed on the RTM: zz= 31 to 83 # NET 'P8_12' J6-A1 NET 'GROUND' J6-B1 NET 'P9_3' J6-C1 NET 'M_75_POS' J6-D1 NET 'M_74_NEG' J6-E1 NET 'P8_13' J6-A2 NET 'P9_4' J6-B2 NET 'GROUND' J6-C2 NET 'M_75_NEG' J6-D2 NET 'REAR_CG_GND' J6-E2 # this is a cable ground NET 'P8_14' J6-A3 NET 'GROUND' J6-B3 NET 'P9_5' J6-C3 NET 'M_76_POS' J6-D3 NET 'REAR_CG_GND' J6-E3 # this is a cable ground NET 'P8_15' J6-A4 NET 'P9_6' J6-B4 NET 'GROUND' J6-C4 NET 'M_76_NEG' J6-D4 NET 'M_77_POS' J6-E4 NET 'P8_16' J6-A5 NET 'GROUND' J6-B5 NET 'P9_7' J6-C5 NET 'GROUND' J6-D5 NET 'M_77_NEG' J6-E5 NET 'P8_17' J6-A6 NET 'P9_8' J6-B6 NET 'GROUND' J6-C6 NET 'P10_0' J6-D6 NET 'M_78_POS' J6-E6 NET 'P8_18' J6-A7 NET 'GROUND' J6-B7 NET 'P9_9' J6-C7 NET 'P10_1' J6-D7 NET 'M_78_NEG' J6-E7 NET 'P8_19' J6-A8 NET 'P9_10' J6-B8 NET 'GROUND' J6-C8 NET 'P10_2' J6-D8 NET 'REAR_CG_GND' J6-E8 # this is a cable ground NET 'P8_20' J6-A9 NET 'GROUND' J6-B9 NET 'P9_11' J6-C9 NET 'P10_3' J6-D9 NET 'M_79_POS' J6-E9 NET 'P8_21' J6-A10 NET 'P9_12' J6-B10 NET 'P10_4' J6-C10 NET 'GROUND' J6-D10 NET 'M_79_NEG' J6-E10 NET 'P8_22' J6-A11 NET 'GROUND' J6-B11 NET 'P9_13' J6-C11 NET 'P10_5' J6-D11 NET 'M_80_POS' J6-E11 NET 'P8_23' J6-A12 NET 'P9_14' J6-B12 NET 'P10_6' J6-C12 NET 'GROUND' J6-D12 NET 'M_80_NEG' J6-E12 NET 'P8_24' J6-A13 NET 'GROUND' J6-B13 NET 'P9_15' J6-C13 NET 'P10_7' J6-D13 NET 'GROUND' J6-E13 NET 'M_81_POS' J6-A14 NET 'P9_16' J6-B14 NET 'P10_8' J6-C14 NET 'GROUND' J6-D14 NET 'P11_0' J6-E14 NET 'M_81_NEG' J6-A15 NET 'GROUND' J6-B15 NET 'P9_17' J6-C15 NET 'P10_9' J6-D15 NET 'P11_1' J6-E15 NET 'M_82_POS' J6-A16 NET 'P9_18' J6-B16 NET 'P10_10' J6-C16 NET 'GROUND' J6-D16 NET 'P11_2' J6-E16 NET 'M_82_NEG' J6-A17 NET 'GROUND' J6-B17 NET 'P9_19' J6-C17 NET 'P10_11' J6-D17 NET 'P11_3' J6-E17 NET 'M_83_POS' J6-A18 NET 'P9_20' J6-B18 NET 'P10_12' J6-C18 NET 'GROUND' J6-D18 NET 'P11_4' J6-E18 NET 'M_83_NEG' J6-A19 NET 'GROUND' J6-B19 NET 'P9_21' J6-C19 NET 'P10_13' J6-D19 NET 'P11_5' J6-E19 NET 'GROUND' J6-F1 NET 'GROUND' J6-F3 NET 'GROUND' J6-F5 NET 'GROUND' J6-F7 NET 'GROUND' J6-F9 NET 'GROUND' J6-F11 NET 'GROUND' J6-F13 NET 'GROUND' J6-F15 NET 'GROUND' J6-F17 NET 'GROUND' J6-F19 # # CMX Backplane Connector #7 Net-to-Pin File # ------------------------------------------------ # # # Original Rev. 08-Sep-2011 # Rev: 11-Apr-2012 (added backplane linear rank "bxxx") # Most Recent Rev: 06-Sep-2011 remove the linear rank and add comments # # # This is the N2P file for Backplane Connector #7 on the CMX card. # This is a 2mm hard metric 5 Column x 19 Row type "B-19" connector # with ground shield. # # This is connector J7 in the CMX card design. # # 'Pxx_yy' are the single ended signals (series terminated at the source) # coming from the JEM or CPM Processor cards in the crate # There are (up to) 16 Processor cards in a crate and xx = 0 to 15 # Each Processor sends 25 signals to the CMX card and yy = 0 to 24 # NET 'GROUND' J7-A1 NET 'P9_22' J7-B1 NET 'GROUND' J7-C1 NET 'P10_14' J7-D1 NET 'P11_6' J7-E1 NET 'GROUND' J7-A2 NET 'P9_23' J7-B2 NET 'P10_15' J7-C2 NET 'GROUND' J7-D2 NET 'P11_7' J7-E2 ## no net on pin J7-A3 NET 'P9_24' J7-B3 NET 'GROUND' J7-C3 NET 'P10_16' J7-D3 NET 'P11_8' J7-E3 ## no net on pin J7-A4 ## no net on pin J7-B4 NET 'P10_17' J7-C4 NET 'GROUND' J7-D4 NET 'P11_9' J7-E4 ## no net on pin J7-A5 ## no net on pin J7-B5 NET 'GROUND' J7-C5 NET 'P10_18' J7-D5 NET 'P11_10' J7-E5 ## no net on pin J7-A6 ## no net on pin J7-B6 NET 'P10_19' J7-C6 NET 'GROUND' J7-D6 NET 'P11_11' J7-E6 ## no net on pin J7-A7 ## no net on pin J7-B7 NET 'GROUND' J7-C7 NET 'P10_20' J7-D7 NET 'P11_12' J7-E7 ## no net on pin J7-A8 ## no net on pin J7-B8 NET 'P10_21' J7-C8 NET 'GROUND' J7-D8 NET 'P11_13' J7-E8 NET 'GROUND' J7-A9 NET 'GROUND' J7-B9 NET 'GROUND' J7-C9 NET 'P10_22' J7-D9 NET 'P11_14' J7-E9 NET 'P12_0' J7-A10 NET 'P13_0' J7-B10 NET 'P10_23' J7-C10 NET 'GROUND' J7-D10 NET 'P11_15' J7-E10 NET 'P12_1' J7-A11 NET 'GROUND' J7-B11 NET 'P13_1' J7-C11 NET 'P10_24' J7-D11 NET 'P11_16' J7-E11 NET 'P12_2' J7-A12 NET 'P13_2' J7-B12 NET 'P14_0' J7-C12 NET 'GROUND' J7-D12 NET 'P11_17' J7-E12 NET 'P12_3' J7-A13 NET 'GROUND' J7-B13 NET 'P13_3' J7-C13 NET 'P14_1' J7-D13 NET 'P11_18' J7-E13 NET 'P12_4' J7-A14 NET 'P13_4' J7-B14 NET 'P14_2' J7-C14 NET 'GROUND' J7-D14 NET 'P11_19' J7-E14 NET 'P12_5' J7-A15 NET 'GROUND' J7-B15 NET 'P13_5' J7-C15 NET 'P14_3' J7-D15 NET 'P11_20' J7-E15 NET 'P12_6' J7-A16 NET 'P13_6' J7-B16 NET 'P14_4' J7-C16 NET 'GROUND' J7-D16 NET 'P11_21' J7-E16 NET 'P12_7' J7-A17 NET 'GROUND' J7-B17 NET 'P13_7' J7-C17 NET 'P14_5' J7-D17 NET 'P11_22' J7-E17 NET 'P12_8' J7-A18 NET 'P13_8' J7-B18 NET 'P14_6' J7-C18 NET 'GROUND' J7-D18 NET 'P11_23' J7-E18 NET 'P12_9' J7-A19 NET 'GROUND' J7-B19 NET 'P13_9' J7-C19 NET 'P14_7' J7-D19 NET 'P11_24' J7-E19 NET 'GROUND' J7-F1 NET 'GROUND' J7-F3 NET 'GROUND' J7-F5 NET 'GROUND' J7-F7 NET 'GROUND' J7-F9 NET 'GROUND' J7-F11 NET 'GROUND' J7-F13 NET 'GROUND' J7-F15 NET 'GROUND' J7-F17 NET 'GROUND' J7-F19 # # CMX Backplane Connector #8 Net-to-Pin File # ------------------------------------------------ # # # Original Rev. 08-Sep-2011 # Rev: 11-Apr-2012 (added backplane linear rank "bxxx") # Most Recent Rev: 06-Sep-2011 remove the linear rank and add comments # # # This is the N2P file for Backplane Connector #8 on the CMX card. # This is a 2mm hard metric 5 Column x 25 Row type "B-25" connector # with ground shield. # # This is connector J8 in the CMX card design. # # 'Pxx_yy' are the single ended signals (series terminated at the source) # coming from the JEM or CPM Processor cards in the crate # There are (up to) 16 Processor cards in a crate and xx = 0 to 15 # Each Processor sends 25 signals to the CMX card and yy = 0 to 24 # # TTC_POS and TTC_NEG is the differential input for the Timing, Trigger and Control signal # # CAN_POS and CAN_NEG is the differential CANbus signal # NET 'P12_10' J8-A1 NET 'P13_10' J8-B1 NET 'P14_8' J8-C1 NET 'GROUND' J8-D1 NET 'P15_0' J8-E1 NET 'P12_11' J8-A2 NET 'GROUND' J8-B2 NET 'P13_11' J8-C2 NET 'P14_9' J8-D2 NET 'P15_1' J8-E2 NET 'P12_12' J8-A3 NET 'P13_12' J8-B3 NET 'P14_10' J8-C3 NET 'GROUND' J8-D3 NET 'P15_2' J8-E3 NET 'P12_13' J8-A4 NET 'GROUND' J8-B4 NET 'P13_13' J8-C4 NET 'P14_11' J8-D4 NET 'P15_3' J8-E4 NET 'P12_14' J8-A5 NET 'P13_14' J8-B5 NET 'P14_12' J8-C5 NET 'GROUND' J8-D5 NET 'P15_4' J8-E5 NET 'P12_15' J8-A6 NET 'GROUND' J8-B6 NET 'P13_15' J8-C6 NET 'P14_13' J8-D6 NET 'P15_5' J8-E6 NET 'P12_16' J8-A7 NET 'P13_16' J8-B7 NET 'P14_14' J8-C7 NET 'GROUND' J8-D7 NET 'P15_6' J8-E7 NET 'P12_17' J8-A8 NET 'GROUND' J8-B8 NET 'P13_17' J8-C8 NET 'P14_15' J8-D8 NET 'P15_7' J8-E8 NET 'P12_18' J8-A9 NET 'P13_18' J8-B9 NET 'P14_16' J8-C9 NET 'GROUND' J8-D9 NET 'P15_8' J8-E9 NET 'P12_19' J8-A10 NET 'GROUND' J8-B10 NET 'P13_19' J8-C10 NET 'P14_17' J8-D10 NET 'P15_9' J8-E10 NET 'P12_20' J8-A11 NET 'P13_20' J8-B11 NET 'P14_18' J8-C11 NET 'GROUND' J8-D11 NET 'P15_10' J8-E11 NET 'P12_21' J8-A12 NET 'GROUND' J8-B12 NET 'P13_21' J8-C12 NET 'P14_19' J8-D12 NET 'P15_11' J8-E12 NET 'P12_22' J8-A13 NET 'P13_22' J8-B13 NET 'P14_20' J8-C13 NET 'GROUND' J8-D13 NET 'P15_12' J8-E13 NET 'P12_23' J8-A14 NET 'GROUND' J8-B14 NET 'P13_23' J8-C14 NET 'P14_21' J8-D14 NET 'P15_13' J8-E14 NET 'P12_24' J8-A15 NET 'P13_24' J8-B15 NET 'P14_22' J8-C15 NET 'GROUND' J8-D15 NET 'P15_14' J8-E15 ## no net on pin J8-A16 ## no net on pin J8-B16 NET 'GROUND' J8-C16 NET 'P14_23' J8-D16 NET 'P15_15' J8-E16 ## no net on pin J8-A17 ## no net on pin J8-B17 NET 'P14_24' J8-C17 NET 'GROUND' J8-D17 NET 'P15_16' J8-E17 ## no net on pin J8-A18 ## no net on pin J8-B18 ## no net on pin J8-C18 ## no net on pin J8-D18 NET 'P15_17' J8-E18 ## no net on pin J8-A19 ## no net on pin J8-B19 ## no net on pin J8-C19 NET 'GROUND' J8-D19 NET 'P15_18' J8-E19 ## no net on pin J8-A20 ## no net on pin J8-B20 ## no net on pin J8-C20 ## no net on pin J8-D20 NET 'P15_19' J8-E20 ## no net on pin J8-A21 ## no net on pin J8-B21 ## no net on pin J8-C21 NET 'GROUND' J8-D21 NET 'P15_20' J8-E21 ## no net on pin J8-A22 ## no net on pin J8-B22 ## no net on pin J8-C22 ## no net on pin J8-D22 NET 'P15_21' J8-E22 NET 'GROUND' J8-A23 NET 'GROUND' J8-B23 NET 'GROUND' J8-C23 NET 'GROUND' J8-D23 NET 'P15_22' J8-E23 NET 'CAN_POS' J8-A24 NET 'GROUND' J8-B24 NET 'TTC_POS' J8-C24 NET 'GROUND' J8-D24 NET 'P15_23' J8-E24 NET 'CAN_NEG' J8-A25 NET 'GROUND' J8-B25 NET 'TTC_NEG' J8-C25 NET 'GROUND' J8-D25 NET 'P15_24' J8-E25 NET 'GROUND' J8-F1 NET 'GROUND' J8-F3 NET 'GROUND' J8-F5 NET 'GROUND' J8-F7 NET 'GROUND' J8-F9 NET 'GROUND' J8-F11 NET 'GROUND' J8-F13 NET 'GROUND' J8-F15 NET 'GROUND' J8-F17 NET 'GROUND' J8-F19 NET 'GROUND' J8-F21 NET 'GROUND' J8-F23 NET 'GROUND' J8-F25 # # CMX Backplane Connector J9 Net-to-Pin File # ------------------------------------------------- # # # Original Rev. 08-Sep-2011 # Most Recent Rev. 16-Jan-2013 # # # This is the N2P file for Backplane Connector J9. # This is the power connector at the bottom of the CMX card. # # Connector J9 is geometry conn_power_zpack in the CMX card design. # # Define the nets going to each contact in this power connector. # # The upper contact, i.e. contact #2, is pin numbers # 1, 3, 4, 5. This is the 3.3 Volt backplane bus and # is not used on the CMX card. These will be NO_CONN # single point nets in the overall CMX net list. # # The middle contact, i.e. contact #6, is pin numbers # 8, 9, 11, 12. This is the power ground connection # (return) on the CMX card. # # The bottom contact, i.e. contact #10, is pin numbers # 14, 15, 16, 17. This is the backplane 5.0 Volt power # bus supply to the CMX card. # NET 'No_Conn_J9_PIN_1' J9-1 # No Connection to J9 Pin 1 NET 'No_Conn_J9_PIN_3' J9-3 # No Connection to J9 Pin 3 NET 'No_Conn_J9_PIN_4' J9-4 # No Connection to J9 Pin 4 NET 'No_Conn_J9_PIN_5' J9-5 # No Connection to J9 Pin 5 NET 'GROUND' J9-8 J9-9 J9-11 J9-12 NET 'BK_PLN_5V0' J9-14 J9-15 J9-16 J9-17 # # CMX Front Panel Connector #10 Net-to-Pin File # ------------------------------------------------- # # # Original Rev. 16-Aug-2011 # Most Recent Rev. 20-July-2013 # # # This is the N2P file for Front Panel Connector #10 # on the CMX card. This is a 68 pin MDR connector # to the CTP. # # This is connector J10 in the CMX card design. # # Define the nets going to each pin. # NET 'CN_CTP_00_POS' J10-1 NET 'CN_CTP_00_NEG' J10-35 NET 'CN_CTP_01_POS' J10-2 NET 'CN_CTP_01_NEG' J10-36 NET 'CN_CTP_02_POS' J10-3 NET 'CN_CTP_02_NEG' J10-37 NET 'CN_CTP_03_POS' J10-4 NET 'CN_CTP_03_NEG' J10-38 NET 'CN_CTP_04_POS' J10-5 NET 'CN_CTP_04_NEG' J10-39 NET 'CN_CTP_05_POS' J10-6 NET 'CN_CTP_05_NEG' J10-40 NET 'CN_CTP_06_POS' J10-7 NET 'CN_CTP_06_NEG' J10-41 NET 'CN_CTP_07_POS' J10-8 NET 'CN_CTP_07_NEG' J10-42 NET 'CN_CTP_08_POS' J10-9 NET 'CN_CTP_08_NEG' J10-43 NET 'CN_CTP_09_POS' J10-10 NET 'CN_CTP_09_NEG' J10-44 NET 'CN_CTP_10_POS' J10-11 NET 'CN_CTP_10_NEG' J10-45 NET 'CN_CTP_11_POS' J10-12 NET 'CN_CTP_11_NEG' J10-46 NET 'CN_CTP_12_POS' J10-13 NET 'CN_CTP_12_NEG' J10-47 NET 'CN_CTP_13_POS' J10-14 NET 'CN_CTP_13_NEG' J10-48 NET 'CN_CTP_14_POS' J10-15 NET 'CN_CTP_14_NEG' J10-49 NET 'CN_CTP_15_POS' J10-16 NET 'CN_CTP_15_NEG' J10-50 NET 'CN_CTP_16_POS' J10-17 NET 'CN_CTP_16_NEG' J10-51 NET 'CN_CTP_17_POS' J10-18 NET 'CN_CTP_17_NEG' J10-52 NET 'CN_CTP_18_POS' J10-19 NET 'CN_CTP_18_NEG' J10-53 NET 'CN_CTP_19_POS' J10-20 NET 'CN_CTP_19_NEG' J10-54 NET 'CN_CTP_20_POS' J10-21 NET 'CN_CTP_20_NEG' J10-55 NET 'CN_CTP_21_POS' J10-22 NET 'CN_CTP_21_NEG' J10-56 NET 'CN_CTP_22_POS' J10-23 NET 'CN_CTP_22_NEG' J10-57 NET 'CN_CTP_23_POS' J10-24 NET 'CN_CTP_23_NEG' J10-58 NET 'CN_CTP_24_POS' J10-25 NET 'CN_CTP_24_NEG' J10-59 NET 'CN_CTP_25_POS' J10-26 NET 'CN_CTP_25_NEG' J10-60 NET 'CN_CTP_26_POS' J10-27 NET 'CN_CTP_26_NEG' J10-61 NET 'CN_CTP_27_POS' J10-28 NET 'CN_CTP_27_NEG' J10-62 NET 'CN_CTP_28_POS' J10-29 NET 'CN_CTP_28_NEG' J10-63 NET 'CN_CTP_29_POS' J10-30 NET 'CN_CTP_29_NEG' J10-64 NET 'CN_CTP_30_POS' J10-31 NET 'CN_CTP_30_NEG' J10-65 NET 'CN_CTP_31_POS' J10-32 NET 'CN_CTP_31_NEG' J10-66 NET 'CN_CTP_64_POS' J10-33 NET 'CN_CTP_64_NEG' J10-67 NET 'GND_J10_34_68' J10-34 NET 'GND_J10_34_68' J10-68 # # CMX Front Panel Connector #11 Net-to-Pin File # ------------------------------------------------- # # # Original Rev. 16-Aug-2011 # Most Recent Rev. 20-July-2013 # # # This is the N2P file for Front Panel Connector #11 # on the CMX card. This is a 68 pin MDR connector # to the CTP. # # This is connector J11 in the CMX card design. # # Define the nets going to each pin. # NET 'CN_CTP_32_POS' J11-1 NET 'CN_CTP_32_NEG' J11-35 NET 'CN_CTP_33_POS' J11-2 NET 'CN_CTP_33_NEG' J11-36 NET 'CN_CTP_34_POS' J11-3 NET 'CN_CTP_34_NEG' J11-37 NET 'CN_CTP_35_POS' J11-4 NET 'CN_CTP_35_NEG' J11-38 NET 'CN_CTP_36_POS' J11-5 NET 'CN_CTP_36_NEG' J11-39 NET 'CN_CTP_37_POS' J11-6 NET 'CN_CTP_37_NEG' J11-40 NET 'CN_CTP_38_POS' J11-7 NET 'CN_CTP_38_NEG' J11-41 NET 'CN_CTP_39_POS' J11-8 NET 'CN_CTP_39_NEG' J11-42 NET 'CN_CTP_40_POS' J11-9 NET 'CN_CTP_40_NEG' J11-43 NET 'CN_CTP_41_POS' J11-10 NET 'CN_CTP_41_NEG' J11-44 NET 'CN_CTP_42_POS' J11-11 NET 'CN_CTP_42_NEG' J11-45 NET 'CN_CTP_43_POS' J11-12 NET 'CN_CTP_43_NEG' J11-46 NET 'CN_CTP_44_POS' J11-13 NET 'CN_CTP_44_NEG' J11-47 NET 'CN_CTP_45_POS' J11-14 NET 'CN_CTP_45_NEG' J11-48 NET 'CN_CTP_46_POS' J11-15 NET 'CN_CTP_46_NEG' J11-49 NET 'CN_CTP_47_POS' J11-16 NET 'CN_CTP_47_NEG' J11-50 NET 'CN_CTP_48_POS' J11-17 NET 'CN_CTP_48_NEG' J11-51 NET 'CN_CTP_49_POS' J11-18 NET 'CN_CTP_49_NEG' J11-52 NET 'CN_CTP_50_POS' J11-19 NET 'CN_CTP_50_NEG' J11-53 NET 'CN_CTP_51_POS' J11-20 NET 'CN_CTP_51_NEG' J11-54 NET 'CN_CTP_52_POS' J11-21 NET 'CN_CTP_52_NEG' J11-55 NET 'CN_CTP_53_POS' J11-22 NET 'CN_CTP_53_NEG' J11-56 NET 'CN_CTP_54_POS' J11-23 NET 'CN_CTP_54_NEG' J11-57 NET 'CN_CTP_55_POS' J11-24 NET 'CN_CTP_55_NEG' J11-58 NET 'CN_CTP_56_POS' J11-25 NET 'CN_CTP_56_NEG' J11-59 NET 'CN_CTP_57_POS' J11-26 NET 'CN_CTP_57_NEG' J11-60 NET 'CN_CTP_58_POS' J11-27 NET 'CN_CTP_58_NEG' J11-61 NET 'CN_CTP_59_POS' J11-28 NET 'CN_CTP_59_NEG' J11-62 NET 'CN_CTP_60_POS' J11-29 NET 'CN_CTP_60_NEG' J11-63 NET 'CN_CTP_61_POS' J11-30 NET 'CN_CTP_61_NEG' J11-64 NET 'CN_CTP_62_POS' J11-31 NET 'CN_CTP_62_NEG' J11-65 NET 'CN_CTP_63_POS' J11-32 NET 'CN_CTP_63_NEG' J11-66 NET 'CN_CTP_65_POS' J11-33 NET 'CN_CTP_65_NEG' J11-67 NET 'GND_J11_34_68' J11-34 NET 'GND_J11_34_68' J11-68 # # CMX Backplane LVDS Cable IO Net-to-Pin File # ------------------------------------------------- # # # Original Rev. 13-Oct-2011 # Rev. 14-Aug-2012 comment all out for change of IC # Rev. 22-Aug-2012 switch to using DS91M040 and 2.5-3.3V translators # Rev. 31-Aug-2012 Add layer assignment in comment # Rev: 07-Sep-2012 Add header comments # Rev: 2-Nov-2012 Edit what channels are used in the 74AVCAH164245 translators # to use the channels closest to the center of the pcb, i.e. # give as much space as possible to the 400 Processor Inputs # Most Recent Rev: 19-Nov-2012 Move layer assignment to match re-work of backplane inputs # Note: signals 81,82,83 were moved to layer 10 (bottom) to be determined. # # # ICs referenced in this file: # ---------------------------- # # U21 to U41 are National Semiconductor DS91M040 LVDS transceivers # # U42 to U47 are Texas Instrument 74AVCAH164245 level translators to interface between # the 2.5V CMOS logic level of the FPGA IO banks # and the 3.3V CMOS level side of the LVDS transceivers # # Signal Nets referenced in this file: # ------------------------------------ # # 'M_zz_POS' and 'M_zz_NEG' are the LVDS signal used for Cable IO # from a Crate CMX card to a System CMX card. 'M_zz_POS' is the # non-inverted signal and 'M_zz_NEG' is the inverted signal. # # There are up to 3 cables used for a given CMX card. # A Crate CMX card uses one cable as output only, # while a System CMX card receives 2 or 3 cables as input. # # A Rear Transition Module (RTM) card provides the interface to the three 34-signal # LVDS connectors where the IO cables can be connected. # Only 27 signals from each connector are routed on the current RTM cards. # zz=0 to 26 correspond to the first cable, # zz=27 to 53 correspond to the second cable, and # zz=54 to 80 correspond to the third cable. # # Additionally, 3 more differential pairs of signals are labelled on the backplane # but are not routed on the RTM: zz= 31 to 83 # The CMX card will route the currently unused M_81, M_82, and M_83 signals # to become usable as cable IO signals. The sets of cable signals thus are: # Cable #1 consists of signals M_00 to M_26 plus M_81 # Cable #2 consists of signals M_27 to M_53 plus M_82 # Cable #3 consists of signals M_54 to M_80 plus M_83 # The CMX card could thus be able to use 28 LVDS signals per cable while the CMM was only able # to use 27 signals. Using 28 signals would however require a new version of the RTM card. # This 28th signal can be left unused and set to a fixed state by the FPGA of the source Crate CMX # while the LVDS transceiver of the receiving System CMX will default to a defined value # for all non-connected inputs. # # The backplane connections for these M_zz signals are in files # backplane_connector_4_n2p.txt, backplane_connector_5_n2p.txt, and backplane_connector_6_n2p.txt # located in the the Net_Lists/Connectors_Backplane directory # # Each differential M_zz signal is connected to a DS91M040 transceiver channel. # Note that we connect *all* these signals backwards from the normal DS91M040 polarity. # This is to avoid needing to systematically crossing the traces from the two halves # of the signal at the transceiver end. # We thus connect the 'M_zz_POS' to a pin from the transceiver coresponding # to the inverted half of the differential signal and we connect the 'M_zz_NEG' # to a pin from the transceiver coresponding to the non-inverted half # of the differential signal. The signal on the single ended side # of the transceiver will thus be the inverse of the conventional # LVDS polarity on the cable. This can either be ignored since a CMX card # with this inversion is used at both the source and receiving end of the # connection which inverts the signal twice, OR the signal can also easily # be inverted at the FPGA IO block. # # The three LVDS cables will be able to operate as input or output independently # of each other (this feature is not necessary in normal operation, but useful for testing). # For each set of 28 cable signal we thus use two 16-wide 74AVCAH164245 level translator # chips and seven 4-channel DS91M040 LVDS transceivers. The direction for each set # of 38 cable signal is controlled independently. # # 'D_CBL_zz_B' are the cable IO signals available to the Base FPGA with zz=00 to 83. # The "_B" postfix is used to indicate that these signals are inverted with respect # to the LVDS signal polarity on the data cables. # These signals are connected here to the 2.5V side of the 74AVCAH164245 level translators. # The FPGA connections for the D_CBL_zz signals are in the file backplane_cable_io_n2r.txt # in the Net_Lists/Base_Fpga_Assign directory # # 'I_CBL_zz_B' are the intermediate cable IO signals with zz=00 to 83. # These signals connect the single ended side of the LVDS transceiver # to the 3.3V side of the 74AVCAH164245 level translators. # The "_B" postfix is used to indicate that these signals are inverted with respect # to the LVDS signal polarity on the data cables. # # # Note: Trace layer information is appended as comments below. # ----- # NET 'M_00_POS' U21-24 #> T02 # # ^ ^ # | | # Tailored comment flag to help with string searches -+ | # | # Target Trace Layer number to use for this net ----------+ # T01 is top layer, T02 the first inner layer, etc # ############################################################################################ # # Cable #1 consists of signals M_00 to M_26 plus M_81 # --------------------------------------------------- NET 'M_00_POS' U21-24 R21-1 #> T02 non-inverted Cable IO LVDS signal #00 # from backplane to non-inverted side of the # transceiver and termination resistor NET 'M_00_NEG' U21-23 R21-2 #> T02 inverted Cable IO LVDS signal #00 # from backplane to inverted side of the # transceiver and termination resistor NET 'I_CBL_00_B' U21-1 U21-2 U42-17 # intermediate connection between the two # 3.3V single ended ends of the LVDS # transceiver and the level translator NET 'D_CBL_00_B' U42-32 #> T02 2.5V side of the level translator NET 'M_01_POS' U21-22 R22-1 #> T05 (ditto for Cable IO signals 01 to 83 below...) NET 'M_01_NEG' U21-21 R22-2 #> T05 NET 'I_CBL_01_B' U21-3 U21-4 U42-16 NET 'D_CBL_01_B' U42-33 #> T02 NET 'M_02_POS' U21-20 R23-1 #> T03 NET 'M_02_NEG' U21-19 R23-2 #> T03 NET 'I_CBL_02_B' U21-5 U21-6 U42-14 NET 'D_CBL_02_B' U42-35 #> T02 NET 'M_03_POS' U21-18 R24-1 #> T09 NET 'M_03_NEG' U21-17 R24-2 #> T09 NET 'I_CBL_03_B' U21-7 U21-8 U42-13 NET 'D_CBL_03_B' U42-36 #> T02 NET 'M_04_POS' U22-24 R25-1 #> T04 NET 'M_04_NEG' U22-23 R25-2 #> T04 NET 'I_CBL_04_B' U22-1 U22-2 U42-12 NET 'D_CBL_04_B' U42-37 #> T02 NET 'M_05_POS' U22-22 R26-1 #> T02 NET 'M_05_NEG' U22-21 R26-2 #> T02 NET 'I_CBL_05_B' U22-3 U22-4 U42-11 NET 'D_CBL_05_B' U42-38 #> T02 NET 'M_06_POS' U22-20 R27-1 #> T05 NET 'M_06_NEG' U22-19 R27-2 #> T05 NET 'I_CBL_06_B' U22-5 U22-6 U42-9 NET 'D_CBL_06_B' U42-40 #> T02 NET 'M_07_POS' U22-18 R28-1 #> T03 NET 'M_07_NEG' U22-17 R28-2 #> T03 NET 'I_CBL_07_B' U22-7 U22-8 U42-8 NET 'D_CBL_07_B' U42-41 #> T02 NET 'M_08_POS' U23-24 R29-1 #> T04 NET 'M_08_NEG' U23-23 R29-2 #> T04 NET 'I_CBL_08_B' U23-1 U23-2 U42-6 NET 'D_CBL_08_B' U42-43 #> T02 NET 'M_09_POS' U23-22 R30-1 #> T02 NET 'M_09_NEG' U23-21 R30-2 #> T02 NET 'I_CBL_09_B' U23-3 U23-4 U42-5 NET 'D_CBL_09_B' U42-44 #> T02 NET 'M_10_POS' U23-20 R31-1 #> T05 NET 'M_10_NEG' U23-19 R31-2 #> T05 NET 'I_CBL_10_B' U23-5 U23-6 U42-3 NET 'D_CBL_10_B' U42-46 #> T02 NET 'M_11_POS' U23-18 R32-1 #> T03 NET 'M_11_NEG' U23-17 R32-2 #> T03 NET 'I_CBL_11_B' U23-7 U23-8 U42-2 NET 'D_CBL_11_B' U42-47 #> T02 NET 'M_12_POS' U24-24 R33-1 #> T09 NET 'M_12_NEG' U24-23 R33-2 #> T09 NET 'I_CBL_12_B' U24-1 U24-2 U43-23 NET 'D_CBL_12_B' U43-26 #> T02 NET 'M_13_POS' U24-22 R34-1 #> T04 NET 'M_13_NEG' U24-21 R34-2 #> T04 NET 'I_CBL_13_B' U24-3 U24-4 U43-22 NET 'D_CBL_13_B' U43-27 #> T02 NET 'M_14_POS' U24-20 R35-1 #> T02 NET 'M_14_NEG' U24-19 R35-2 #> T02 NET 'I_CBL_14_B' U24-5 U24-6 U43-20 NET 'D_CBL_14_B' U43-29 #> T02 NET 'M_15_POS' U24-18 R36-1 #> T03 NET 'M_15_NEG' U24-17 R36-2 #> T03 NET 'I_CBL_15_B' U24-7 U24-8 U43-19 NET 'D_CBL_15_B' U43-30 #> T02 NET 'M_16_POS' U25-24 R37-1 #> T09 NET 'M_16_NEG' U25-23 R37-2 #> T09 NET 'I_CBL_16_B' U25-1 U25-2 U43-17 NET 'D_CBL_16_B' U43-32 #> T02 NET 'M_17_POS' U25-22 R38-1 #> T04 NET 'M_17_NEG' U25-21 R38-2 #> T04 NET 'I_CBL_17_B' U25-3 U25-4 U43-16 NET 'D_CBL_17_B' U43-33 #> T02 NET 'M_18_POS' U25-20 R39-1 #> T02 NET 'M_18_NEG' U25-19 R39-2 #> T02 NET 'I_CBL_18_B' U25-5 U25-6 U43-14 NET 'D_CBL_18_B' U43-35 #> T05 NET 'M_19_POS' U25-18 R40-1 #> T05 NET 'M_19_NEG' U25-17 R40-2 #> T05 NET 'I_CBL_19_B' U25-7 U25-8 U43-13 NET 'D_CBL_19_B' U43-36 #> T05 NET 'M_20_POS' U26-24 R41-1 #> T03 NET 'M_20_NEG' U26-23 R41-2 #> T03 NET 'I_CBL_20_B' U26-1 U26-2 U43-12 NET 'D_CBL_20_B' U43-37 #> T05 NET 'M_21_POS' U26-22 R42-1 #> T09 NET 'M_21_NEG' U26-21 R42-2 #> T09 NET 'I_CBL_21_B' U26-3 U26-4 U43-11 NET 'D_CBL_21_B' U43-38 #> T05 NET 'M_22_POS' U26-20 R43-1 #> T04 NET 'M_22_NEG' U26-19 R43-2 #> T04 NET 'I_CBL_22_B' U26-5 U26-6 U43-9 NET 'D_CBL_22_B' U43-40 #> T05 NET 'M_23_POS' U26-18 R44-1 #> T02 NET 'M_23_NEG' U26-17 R44-2 #> T02 NET 'I_CBL_23_B' U26-7 U26-8 U43-8 NET 'D_CBL_23_B' U43-41 #> T05 NET 'M_24_POS' U27-24 R45-1 #> T05 NET 'M_24_NEG' U27-23 R45-2 #> T05 NET 'I_CBL_24_B' U27-1 U27-2 U43-6 NET 'D_CBL_24_B' U43-43 #> T04 NET 'M_25_POS' U27-22 R46-1 #> T03 NET 'M_25_NEG' U27-21 R46-2 #> T03 NET 'I_CBL_25_B' U27-3 U27-4 U43-5 NET 'D_CBL_25_B' U43-44 #> T04 NET 'M_26_POS' U27-20 R47-1 #> T04 NET 'M_26_NEG' U27-19 R47-2 #> T04 NET 'I_CBL_26_B' U27-5 U27-6 U43-3 NET 'D_CBL_26_B' U43-46 #> T04 NET 'M_81_POS' U27-18 R48-1 #> T10 NET 'M_81_NEG' U27-17 R48-2 #> T10 NET 'I_CBL_81_B' U27-7 U27-8 U43-2 NET 'D_CBL_81_B' U43-47 #> T04 # # Cable #2 consists of signals M_27 to M_53 plus M_82 # --------------------------------------------------- NET 'M_27_POS' U28-24 R49-1 #> T02 NET 'M_27_NEG' U28-23 R49-2 #> T02 NET 'I_CBL_27_B' U28-1 U28-2 U44-20 NET 'D_CBL_27_B' U44-29 #> T04 NET 'M_28_POS' U28-22 R50-1 #> T05 NET 'M_28_NEG' U28-21 R50-2 #> T05 NET 'I_CBL_28_B' U28-3 U28-4 U44-19 NET 'D_CBL_28_B' U44-30 #> T04 NET 'M_29_POS' U28-20 R51-1 #> T03 NET 'M_29_NEG' U28-19 R51-2 #> T03 NET 'I_CBL_29_B' U28-5 U28-6 U44-17 NET 'D_CBL_29_B' U44-32 #> T04 NET 'M_30_POS' U28-18 R52-1 #> T09 NET 'M_30_NEG' U28-17 R52-2 #> T09 NET 'I_CBL_30_B' U28-7 U28-8 U44-16 NET 'D_CBL_30_B' U44-33 #> T04 NET 'M_31_POS' U29-24 R53-1 #> T04 NET 'M_31_NEG' U29-23 R53-2 #> T04 NET 'I_CBL_31_B' U29-1 U29-2 U44-14 NET 'D_CBL_31_B' U44-35 #> T04 NET 'M_32_POS' U29-22 R54-1 #> T02 NET 'M_32_NEG' U29-21 R54-2 #> T02 NET 'I_CBL_32_B' U29-3 U29-4 U44-13 NET 'D_CBL_32_B' U44-36 #> T04 NET 'M_33_POS' U29-20 R55-1 #> T03 NET 'M_33_NEG' U29-19 R55-2 #> T03 NET 'I_CBL_33_B' U29-5 U29-6 U44-12 NET 'D_CBL_33_B' U44-37 #> T09 NET 'M_34_POS' U29-18 R56-1 #> T09 NET 'M_34_NEG' U29-17 R56-2 #> T09 NET 'I_CBL_34_B' U29-7 U29-8 U44-11 NET 'D_CBL_34_B' U44-38 #> T09 NET 'M_35_POS' U30-24 R57-1 #> T04 NET 'M_35_NEG' U30-23 R57-2 #> T04 NET 'I_CBL_35_B' U30-1 U30-2 U44-9 NET 'D_CBL_35_B' U44-40 #> T09 NET 'M_36_POS' U30-22 R58-1 #> T02 NET 'M_36_NEG' U30-21 R58-2 #> T02 NET 'I_CBL_36_B' U30-3 U30-4 U44-8 NET 'D_CBL_36_B' U44-41 #> T09 NET 'M_37_POS' U30-20 R59-1 #> T05 NET 'M_37_NEG' U30-19 R59-2 #> T05 NET 'I_CBL_37_B' U30-5 U30-6 U44-6 NET 'D_CBL_37_B' U44-43 #> T09 NET 'M_38_POS' U30-18 R60-1 #> T03 NET 'M_38_NEG' U30-17 R60-2 #> T03 NET 'I_CBL_38_B' U30-7 U30-8 U44-5 NET 'D_CBL_38_B' U44-44 #> T08 NET 'M_39_POS' U31-24 R61-1 #> T09 NET 'M_39_NEG' U31-23 R61-2 #> T09 NET 'I_CBL_39_B' U31-1 U31-2 U44-3 NET 'D_CBL_39_B' U44-46 #> T08 NET 'M_40_POS' U31-22 R62-1 #> T04 NET 'M_40_NEG' U31-21 R62-2 #> T04 NET 'I_CBL_40_B' U31-3 U31-4 U44-2 NET 'D_CBL_40_B' U44-47 #> T10 NET 'M_41_POS' U31-20 R63-1 #> T02 NET 'M_41_NEG' U31-19 R63-2 #> T02 NET 'I_CBL_41_B' U31-5 U31-6 U45-23 NET 'D_CBL_41_B' U45-26 #> T10 NET 'M_42_POS' U31-18 R64-1 #> T05 NET 'M_42_NEG' U31-17 R64-2 #> T05 NET 'I_CBL_42_B' U31-7 U31-8 U45-22 NET 'D_CBL_42_B' U45-27 #> T10 NET 'M_43_POS' U32-24 R65-1 #> T03 NET 'M_43_NEG' U32-23 R65-2 #> T03 NET 'I_CBL_43_B' U32-1 U32-2 U45-20 NET 'D_CBL_43_B' U45-29 #> T10 NET 'M_44_POS' U32-22 R66-1 #> T04 NET 'M_44_NEG' U32-21 R66-2 #> T04 NET 'I_CBL_44_B' U32-3 U32-4 U45-19 NET 'D_CBL_44_B' U45-30 #> T03 NET 'M_45_POS' U32-20 R67-1 #> T02 NET 'M_45_NEG' U32-19 R67-2 #> T02 NET 'I_CBL_45_B' U32-5 U32-6 U45-17 NET 'D_CBL_45_B' U45-32 #> T03 NET 'M_46_POS' U32-18 R68-1 #> T05 NET 'M_46_NEG' U32-17 R68-2 #> T05 NET 'I_CBL_46_B' U32-7 U32-8 U45-16 NET 'D_CBL_46_B' U45-33 #> T03 NET 'M_47_POS' U33-24 R69-1 #> T03 NET 'M_47_NEG' U33-23 R69-2 #> T03 NET 'I_CBL_47_B' U33-1 U33-2 U45-14 NET 'D_CBL_47_B' U45-35 #> T03 NET 'M_48_POS' U33-22 R70-1 #> T09 NET 'M_48_NEG' U33-21 R70-2 #> T09 NET 'I_CBL_48_B' U33-3 U33-4 U45-13 NET 'D_CBL_48_B' U45-36 #> T03 NET 'M_49_POS' U33-20 R71-1 #> T04 NET 'M_49_NEG' U33-19 R71-2 #> T04 NET 'I_CBL_49_B' U33-5 U33-6 U45-12 NET 'D_CBL_49_B' U45-37 #> T03 NET 'M_50_POS' U33-18 R72-1 #> T02 NET 'M_50_NEG' U33-17 R72-2 #> T02 NET 'I_CBL_50_B' U33-7 U33-8 U45-11 NET 'D_CBL_50_B' U45-38 #> T03 NET 'M_51_POS' U34-24 R73-1 #> T05 NET 'M_51_NEG' U34-23 R73-2 #> T05 NET 'I_CBL_51_B' U34-1 U34-2 U45-9 NET 'D_CBL_51_B' U45-40 #> T03 NET 'M_52_POS' U34-22 R74-1 #> T09 NET 'M_52_NEG' U34-21 R74-2 #> T09 NET 'I_CBL_52_B' U34-3 U34-4 U45-8 NET 'D_CBL_52_B' U45-41 #> T03 NET 'M_53_POS' U34-20 R75-1 #> T04 NET 'M_53_NEG' U34-19 R75-2 #> T04 NET 'I_CBL_53_B' U34-5 U34-6 U45-6 NET 'D_CBL_53_B' U45-43 #> T03 NET 'M_82_POS' U34-18 R76-1 #> T10 NET 'M_82_NEG' U34-17 R76-2 #> T10 NET 'I_CBL_82_B' U34-7 U34-8 U45-5 NET 'D_CBL_82_B' U45-44 #> T03 # # Cable #3 consists of signals M_54 to M_80 plus M_83 # --------------------------------------------------- NET 'M_54_POS' U35-24 R77-1 #> T05 NET 'M_54_NEG' U35-23 R77-2 #> T05 NET 'I_CBL_54_B' U35-1 U35-2 U46-23 NET 'D_CBL_54_B' U46-26 #> T03 NET 'M_55_POS' U35-22 R78-1 #> T03 NET 'M_55_NEG' U35-21 R78-2 #> T03 NET 'I_CBL_55_B' U35-3 U35-4 U46-22 NET 'D_CBL_55_B' U46-27 #> T02 NET 'M_56_POS' U35-20 R79-1 #> T09 NET 'M_56_NEG' U35-19 R79-2 #> T09 NET 'I_CBL_56_B' U35-5 U35-6 U46-20 NET 'D_CBL_56_B' U46-29 #> T02 NET 'M_57_POS' U35-18 R80-1 #> T04 NET 'M_57_NEG' U35-17 R80-2 #> T04 NET 'I_CBL_57_B' U35-7 U35-8 U46-19 NET 'D_CBL_57_B' U46-30 #> T02 NET 'M_58_POS' U36-24 R81-1 #> T05 NET 'M_58_NEG' U36-23 R81-2 #> T05 NET 'I_CBL_58_B' U36-1 U36-2 U46-17 NET 'D_CBL_58_B' U46-32 #> T02 NET 'M_59_POS' U36-22 R82-1 #> T09 NET 'M_59_NEG' U36-21 R82-2 #> T09 NET 'I_CBL_59_B' U36-3 U36-4 U46-16 NET 'D_CBL_59_B' U46-33 #> T02 NET 'M_60_POS' U36-20 R83-1 #> T04 NET 'M_60_NEG' U36-19 R83-2 #> T04 NET 'I_CBL_60_B' U36-5 U36-6 U46-14 NET 'D_CBL_60_B' U46-35 #> T05 NET 'M_61_POS' U36-18 R84-1 #> T03 NET 'M_61_NEG' U36-17 R84-2 #> T03 NET 'I_CBL_61_B' U36-7 U36-8 U46-13 NET 'D_CBL_61_B' U46-36 #> T05 NET 'M_62_POS' U37-24 R85-1 #> T09 NET 'M_62_NEG' U37-23 R85-2 #> T09 NET 'I_CBL_62_B' U37-1 U37-2 U46-12 NET 'D_CBL_62_B' U46-37 #> T05 NET 'M_63_POS' U37-22 R86-1 #> T04 NET 'M_63_NEG' U37-21 R86-2 #> T04 NET 'I_CBL_63_B' U37-3 U37-4 U46-11 NET 'D_CBL_63_B' U46-38 #> T05 NET 'M_64_POS' U37-20 R87-1 #> T05 NET 'M_64_NEG' U37-19 R87-2 #> T05 NET 'I_CBL_64_B' U37-5 U37-6 U46-9 NET 'D_CBL_64_B' U46-40 #> T05 NET 'M_65_POS' U37-18 R88-1 #> T03 NET 'M_65_NEG' U37-17 R88-2 #> T03 NET 'I_CBL_65_B' U37-7 U37-8 U46-8 NET 'D_CBL_65_B' U46-41 #> T05 NET 'M_66_POS' U38-24 R89-1 #> T04 NET 'M_66_NEG' U38-23 R89-2 #> T04 NET 'I_CBL_66_B' U38-1 U38-2 U46-6 NET 'D_CBL_66_B' U46-43 #> T09 NET 'M_67_POS' U38-22 R90-1 #> T03 NET 'M_67_NEG' U38-21 R90-2 #> T03 NET 'I_CBL_67_B' U38-3 U38-4 U46-5 NET 'D_CBL_67_B' U46-44 #> T09 NET 'M_68_POS' U38-20 R91-1 #> T09 NET 'M_68_NEG' U38-19 R91-2 #> T09 NET 'I_CBL_68_B' U38-5 U38-6 U46-3 NET 'D_CBL_68_B' U46-46 #> T09 NET 'M_69_POS' U38-18 R92-1 #> T04 NET 'M_69_NEG' U38-17 R92-2 #> T04 NET 'I_CBL_69_B' U38-7 U38-8 U46-2 NET 'D_CBL_69_B' U46-47 #> T09 NET 'M_70_POS' U39-24 R93-1 #> T03 NET 'M_70_NEG' U39-23 R93-2 #> T03 NET 'I_CBL_70_B' U39-1 U39-2 U47-23 NET 'D_CBL_70_B' U47-26 #> T04 NET 'M_71_POS' U39-22 R94-1 #> T09 NET 'M_71_NEG' U39-21 R94-2 #> T09 NET 'I_CBL_71_B' U39-3 U39-4 U47-22 NET 'D_CBL_71_B' U47-27 #> T10 NET 'M_72_POS' U39-20 R95-1 #> T04 NET 'M_72_NEG' U39-19 R95-2 #> T04 NET 'I_CBL_72_B' U39-5 U39-6 U47-20 NET 'D_CBL_72_B' U47-29 #> T10 NET 'M_73_POS' U39-18 R96-1 #> T09 NET 'M_73_NEG' U39-17 R96-2 #> T09 NET 'I_CBL_73_B' U39-7 U39-8 U47-19 NET 'D_CBL_73_B' U47-30 #> T10 NET 'M_74_POS' U40-24 R97-1 #> T04 NET 'M_74_NEG' U40-23 R97-2 #> T04 NET 'I_CBL_74_B' U40-1 U40-2 U47-17 NET 'D_CBL_74_B' U47-32 #> T10 NET 'M_75_POS' U40-22 R98-1 #> T09 NET 'M_75_NEG' U40-21 R98-2 #> T09 NET 'I_CBL_75_B' U40-3 U40-4 U47-16 NET 'D_CBL_75_B' U47-33 #> T10 NET 'M_76_POS' U40-20 R99-1 #> T09 NET 'M_76_NEG' U40-19 R99-2 #> T09 NET 'I_CBL_76_B' U40-5 U40-6 U47-14 NET 'D_CBL_76_B' U47-35 #> T10 NET 'M_77_POS' U40-18 R100-1 #> T04 NET 'M_77_NEG' U40-17 R100-2 #> T04 NET 'I_CBL_77_B' U40-7 U40-8 U47-13 NET 'D_CBL_77_B' U47-36 #> T08 NET 'M_78_POS' U41-24 R101-1 #> T04 NET 'M_78_NEG' U41-23 R101-2 #> T04 NET 'I_CBL_78_B' U41-1 U41-2 U47-12 NET 'D_CBL_78_B' U47-37 #> T08 NET 'M_79_POS' U41-22 R102-1 #> T04 NET 'M_79_NEG' U41-21 R102-2 #> T04 NET 'I_CBL_79_B' U41-3 U41-4 U47-11 NET 'D_CBL_79_B' U47-38 #> T08 NET 'M_80_POS' U41-20 R103-1 #> T04 NET 'M_80_NEG' U41-19 R103-2 #> T04 NET 'I_CBL_80_B' U41-5 U41-6 U47-9 NET 'D_CBL_80_B' U47-40 #> T08 NET 'M_83_POS' U41-18 R104-1 #> T10 NET 'M_83_NEG' U41-17 R104-2 #> T10 NET 'I_CBL_83_B' U41-7 U41-8 U47-8 NET 'D_CBL_83_B' U47-41 #> T08 # # CMX-0 Nets File # # Backplane LVDS Management Nets # --=========------------------------ # # # Original Rev. 1-Nov-2012 # Most Recent Rev. 4-Apr-2013 # # # # This file holds the nets involved in the management of the # Backplane LVDS Transceivers and Level Translators. # -------------- # # # The intent is to provide management of the backplane LVDS # connections so that the BF FPGA can independently choose # to Receive, Drive, or Ignore the 3 Backplane LVDS Cables. # # For each of the 3 Backplane LVDS Cables the intent is # that the BF_FPGA will have just 1 control signals, i.e. # a Direction signal signals. # # For each of the 3 Backplane LVDS Cables there will be # logic in the BSPT FPGA that take the direction request # signal from the BF FPGA and makes up the 3 control # signals that run to the Transceivers and Translators # for each Cable. The OE_B control signal to the # Translators goes through Hardwired Oversight Logic # that is between the BSPT and the Cable Translator # chips. # # The control to the OE_B pins to the Cable Translator # chips come from U363 in the Hardwired Oversight Logic. # # These OE_B signals to the Translator chips are named: # # CABLE_1_TRNSLT_OE_B # CABLE_2_TRNSLT_OE_B # CABLE_3_TRNSLT_OE_B # # These control signals originate in the BSPT FPGA but # pass through the Hardwired Oversight Logic on their # way to the OE_B pins on the Cable Translator chips. # As these signals come out of the BSPT FPGA that # are named: # # BSPT_CABLE_1_TRNSLT_OE_B # BSPT_CABLE_2_TRNSLT_OE_B # BSPT_CABLE_3_TRNSLT_OE_B # # # The UPPER set of Backplane LVDS management signals # ------- -------------- NET 'CABLE_1_TRNSLT_DIR' U42-1 U42-24 # Direction of 2V5<->3V3 Translators NET 'CABLE_1_TRNSLT_DIR' U43-1 U43-24 # Direction of 2V5<->3V3 Translators NET 'CABLE_1_TRNSLT_OE_B' U42-25 U42-48 # Output Enable Bar of Translators NET 'CABLE_1_TRNSLT_OE_B' U43-25 U43-48 # Output Enable Bar of Translators NET 'CABLE_1_TRNCVR_DIR' U21-13 U21-15 U21-26 U21-28 # Receiver Enb_B NET 'CABLE_1_TRNCVR_DIR' U22-13 U22-15 U22-26 U22-28 # Receiver Enb_B NET 'CABLE_1_TRNCVR_DIR' U23-13 U23-15 U23-26 U23-28 # Receiver Enb_B NET 'CABLE_1_TRNCVR_DIR' U24-13 U24-15 U24-26 U24-28 # Receiver Enb_B NET 'CABLE_1_TRNCVR_DIR' U25-13 U25-15 U25-26 U25-28 # Receiver Enb_B NET 'CABLE_1_TRNCVR_DIR' U26-13 U26-15 U26-26 U26-28 # Receiver Enb_B NET 'CABLE_1_TRNCVR_DIR' U27-13 U27-15 U27-26 U27-28 # Receiver Enb_B NET 'CABLE_1_TRNCVR_DIR' U21-14 U21-16 U21-25 U21-27 # Driver Enable NET 'CABLE_1_TRNCVR_DIR' U22-14 U22-16 U22-25 U22-27 # Driver Enable NET 'CABLE_1_TRNCVR_DIR' U23-14 U23-16 U23-25 U23-27 # Driver Enable NET 'CABLE_1_TRNCVR_DIR' U24-14 U24-16 U24-25 U24-27 # Driver Enable NET 'CABLE_1_TRNCVR_DIR' U25-14 U25-16 U25-25 U25-27 # Driver Enable NET 'CABLE_1_TRNCVR_DIR' U26-14 U26-16 U26-25 U26-27 # Driver Enable NET 'CABLE_1_TRNCVR_DIR' U27-14 U27-16 U27-25 U27-27 # Driver Enable NET 'BACK_UPPER_LVDS_FAILSAFE' U21-9 U21-32 U22-9 U22-32 # Receiver Failsafe NET 'BACK_UPPER_LVDS_FAILSAFE' U23-9 U23-32 U24-9 U24-32 # Receiver Failsafe NET 'BACK_UPPER_LVDS_FAILSAFE' U25-9 U25-32 U26-9 U26-32 # Receiver Failsafe NET 'BACK_UPPER_LVDS_FAILSAFE' U27-9 U27-32 # Receiver Failsafe NET 'BACK_UPPER_LVDS_MASTER_ENB' U21-10 U22-10 U23-10 U24-10 # Trncvr Master Enable NET 'BACK_UPPER_LVDS_MASTER_ENB' U25-10 U26-10 U27-10 # Trncvr Master Enable # The MIDDLE set of Backplane LVDS management signals # -------- -------------- NET 'CABLE_2_TRNSLT_DIR' U44-1 U44-24 # Direction of 2V5<->3V3 Translators NET 'CABLE_2_TRNSLT_DIR' U45-1 U45-24 # Direction of 2V5<->3V3 Translators NET 'CABLE_2_TRNSLT_OE_B' U44-25 U44-48 # Output Enable Bar of Translators NET 'CABLE_2_TRNSLT_OE_B' U45-25 U45-48 # Output Enable Bar of Translators NET 'CABLE_2_TRNCVR_DIR' U28-13 U28-15 U28-26 U28-28 # Receiver Enb_B NET 'CABLE_2_TRNCVR_DIR' U29-13 U29-15 U29-26 U29-28 # Receiver Enb_B NET 'CABLE_2_TRNCVR_DIR' U30-13 U30-15 U30-26 U30-28 # Receiver Enb_B NET 'CABLE_2_TRNCVR_DIR' U31-13 U31-15 U31-26 U31-28 # Receiver Enb_B NET 'CABLE_2_TRNCVR_DIR' U32-13 U32-15 U32-26 U32-28 # Receiver Enb_B NET 'CABLE_2_TRNCVR_DIR' U33-13 U33-15 U33-26 U33-28 # Receiver Enb_B NET 'CABLE_2_TRNCVR_DIR' U34-13 U34-15 U34-26 U34-28 # Receiver Enb_B NET 'CABLE_2_TRNCVR_DIR' U28-14 U28-16 U28-25 U28-27 # Driver Enable NET 'CABLE_2_TRNCVR_DIR' U29-14 U29-16 U29-25 U29-27 # Driver Enable NET 'CABLE_2_TRNCVR_DIR' U30-14 U30-16 U30-25 U30-27 # Driver Enable NET 'CABLE_2_TRNCVR_DIR' U31-14 U31-16 U31-25 U31-27 # Driver Enable NET 'CABLE_2_TRNCVR_DIR' U32-14 U32-16 U32-25 U32-27 # Driver Enable NET 'CABLE_2_TRNCVR_DIR' U33-14 U33-16 U33-25 U33-27 # Driver Enable NET 'CABLE_2_TRNCVR_DIR' U34-14 U34-16 U34-25 U34-27 # Driver Enable NET 'BACK_MIDDLE_LVDS_FAILSAFE' U28-9 U28-32 U29-9 U29-32 # Receiver Failsafe NET 'BACK_MIDDLE_LVDS_FAILSAFE' U30-9 U30-32 U31-9 U31-32 # Receiver Failsafe NET 'BACK_MIDDLE_LVDS_FAILSAFE' U32-9 U32-32 U33-9 U33-32 # Receiver Failsafe NET 'BACK_MIDDLE_LVDS_FAILSAFE' U34-9 U34-32 # Receiver Failsafe NET 'BACK_MIDDLE_LVDS_MASTER_ENB' U28-10 U29-10 U30-10 U31-10 # Trncvr Master Enable NET 'BACK_MIDDLE_LVDS_MASTER_ENB' U32-10 U33-10 U34-10 # Trncvr Master Enable # The LOWER set of Backplane LVDS management signals # ------- -------------- NET 'CABLE_3_TRNSLT_DIR' U46-1 U46-24 # Direction of 2V5<->3V3 Translators NET 'CABLE_3_TRNSLT_DIR' U47-1 U47-24 # Direction of 2V5<->3V3 Translators NET 'CABLE_3_TRNSLT_OE_B' U46-25 U46-48 # Output Enable Bar of Translators NET 'CABLE_3_TRNSLT_OE_B' U47-25 U47-48 # Output Enable Bar of Translators NET 'CABLE_3_TRNCVR_DIR' U35-13 U35-15 U35-26 U35-28 # Receiver Enb_B NET 'CABLE_3_TRNCVR_DIR' U36-13 U36-15 U36-26 U36-28 # Receiver Enb_B NET 'CABLE_3_TRNCVR_DIR' U37-13 U37-15 U37-26 U37-28 # Receiver Enb_B NET 'CABLE_3_TRNCVR_DIR' U38-13 U38-15 U38-26 U38-28 # Receiver Enb_B NET 'CABLE_3_TRNCVR_DIR' U39-13 U39-15 U39-26 U39-28 # Receiver Enb_B NET 'CABLE_3_TRNCVR_DIR' U40-13 U40-15 U40-26 U40-28 # Receiver Enb_B NET 'CABLE_3_TRNCVR_DIR' U41-13 U41-15 U41-26 U41-28 # Receiver Enb_B NET 'CABLE_3_TRNCVR_DIR' U35-14 U35-16 U35-25 U35-27 # Driver Enable NET 'CABLE_3_TRNCVR_DIR' U36-14 U36-16 U36-25 U36-27 # Driver Enable NET 'CABLE_3_TRNCVR_DIR' U37-14 U37-16 U37-25 U37-27 # Driver Enable NET 'CABLE_3_TRNCVR_DIR' U38-14 U38-16 U38-25 U38-27 # Driver Enable NET 'CABLE_3_TRNCVR_DIR' U39-14 U39-16 U39-25 U39-27 # Driver Enable NET 'CABLE_3_TRNCVR_DIR' U40-14 U40-16 U40-25 U40-27 # Driver Enable NET 'CABLE_3_TRNCVR_DIR' U41-14 U41-16 U41-25 U41-27 # Driver Enable NET 'BACK_LOWER_LVDS_FAILSAFE' U35-9 U35-32 U36-9 U36-32 # Receiver Failsafe NET 'BACK_LOWER_LVDS_FAILSAFE' U37-9 U37-32 U38-9 U38-32 # Receiver Failsafe NET 'BACK_LOWER_LVDS_FAILSAFE' U39-9 U39-32 U40-9 U40-32 # Receiver Failsafe NET 'BACK_LOWER_LVDS_FAILSAFE' U41-9 U41-32 # Receiver Failsafe NET 'BACK_LOWER_LVDS_MASTER_ENB' U35-10 U36-10 U37-10 U38-10 # Trncvr Master Enable NET 'BACK_LOWER_LVDS_MASTER_ENB' U39-10 U40-10 U41-10 # Trncvr Master Enable # # There are 2 functions of the DS91M040 LVDS Transceivers # that will be controlled only by the placement of # jumpers on the CMX card. These functions are: # Receiver Failsafe and Master_Enable # # Receiver Failsafe # # These are jumpers that pull the FSEN1 and FSEN2 pins # down to ground. There is a separate jumper for each # group of transceivers, i.e. the upper, middle, and # lower LVDS Cable transceivers. Normally we expect # all 3 of these jumpers to be installed so that all # 3 cables will have "Type 1" i.e. voltage symmetric # receivers. These 3 jumpers are reference designators # JMP 5, 6, and 7. JMP5 controlls the Upper Backplane # LVDS Cable receivers. JMP6 the Middle and JMP7 the # Lower LVDS Cable receivers. # NET 'BACK_UPPER_LVDS_FAILSAFE' JMP5-1 # Upper Cable Failsafe Jumper NET 'BACK_MIDDLE_LVDS_FAILSAFE' JMP6-1 # Middle Cable Failsafe Jumper NET 'BACK_LOWER_LVDS_FAILSAFE' JMP7-1 # Lower Cable Failsafe Jumper NET 'GROUND' JMP5-2 JMP6-2 JMP7-2 # Pull-Down to Ground # Master Enable # # When Master Enable is voltage HI then the DS91M040 # LVDS Transceiver will power up and operate. We expect # to always have these transceivers powered up. These # jumpers will actually be given resistor reference # designators on the CMX card because we never expect # to remove or change them. These will be nominal 1k # Ohm resistors from the Master Enable pin to BULK_3V3. # There will be a separate jumper (resistor) for each # group of tranceivers that services a cable, i.e. # upper, middle, or lower cables. R181 enables the # transceivers for the Upper Backplane LVDS Cable. # R182 the Middle and R183 the Lower Cable transceivers. NET 'BACK_UPPER_LVDS_MASTER_ENB' R181-1 # Lower Cable Trncvr Master Enable NET 'BACK_MIDDLE_LVDS_MASTER_ENB' R182-1 # Middle Cable Trncvr Master Enable NET 'BACK_LOWER_LVDS_MASTER_ENB' R183-1 # Upper Cable Trncvr Master Enable NET 'BULK_3V3' R181-2 R182-2 R183-2 # Pull-Up to 3.3 Volts # # CMX-0 Nets File # # Backplane LVDS Power Ground Bypass Cap Nets # --==============--------------------------------- # # # Original Rev. 2-Nov-2012 # Most Recent Rev. 27-Nov-2012 # # # # This file holds the nets that connect power, ground, # and the bypass capacitors to the Backplane LVDS # transceiver and level translators chips. # # # Power and ByPass for U42 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U42-7 U42-18 # U42 3.3V Vccb power NET 'BULK_2V5' U42-31 U42-42 # U42 2.5V Vcca power NET 'GROUND' U42-4 U42-10 # U42 Ground connections NET 'GROUND' U42-15 U42-21 # U42 Ground connections NET 'GROUND' U42-28 U42-34 # U42 Ground connections NET 'GROUND' U42-39 U42-45 # U42 Ground connections NET 'BULK_3V3' C502-1 C503-1 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C501-2 C504-2 # ByPass Cap 2.5V Vcca power NET 'GROUND' C502-2 C503-2 # ByPass Cap Ground connections NET 'GROUND' C501-1 C504-1 # ByPass Cap Ground connections # Power and ByPass for U43 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U43-7 U43-18 # U43 3.3V Vccb power NET 'BULK_2V5' U43-31 U43-42 # U43 2.5V Vcca power NET 'GROUND' U43-4 U43-10 # U43 Ground connections NET 'GROUND' U43-15 U43-21 # U43 Ground connections NET 'GROUND' U43-28 U43-34 # U43 Ground connections NET 'GROUND' U43-39 U43-45 # U43 Ground connections NET 'BULK_3V3' C506-1 C507-1 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C505-2 C508-2 # ByPass Cap 2.5V Vcca power NET 'GROUND' C506-2 C507-2 # ByPass Cap Ground connections NET 'GROUND' C505-1 C508-1 # ByPass Cap Ground connections # Power and ByPass for U44 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U44-7 U44-18 # U44 3.3V Vccb power NET 'BULK_2V5' U44-31 U44-42 # U44 2.5V Vcca power NET 'GROUND' U44-4 U44-10 # U44 Ground connections NET 'GROUND' U44-15 U44-21 # U44 Ground connections NET 'GROUND' U44-28 U44-34 # U44 Ground connections NET 'GROUND' U44-39 U44-45 # U44 Ground connections NET 'BULK_3V3' C510-1 C511-1 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C509-2 C512-2 # ByPass Cap 2.5V Vcca power NET 'GROUND' C510-2 C511-2 # ByPass Cap Ground connections NET 'GROUND' C509-1 C512-1 # ByPass Cap Ground connections # Power and ByPass for U45 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U45-7 U45-18 # U45 3.3V Vccb power NET 'BULK_2V5' U45-31 U45-42 # U45 2.5V Vcca power NET 'GROUND' U45-4 U45-10 # U45 Ground connections NET 'GROUND' U45-15 U45-21 # U45 Ground connections NET 'GROUND' U45-28 U45-34 # U45 Ground connections NET 'GROUND' U45-39 U45-45 # U45 Ground connections NET 'BULK_3V3' C514-1 C515-1 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C513-2 C516-2 # ByPass Cap 2.5V Vcca power NET 'GROUND' C514-2 C515-2 # ByPass Cap Ground connections NET 'GROUND' C513-1 C516-1 # ByPass Cap Ground connections # Power and ByPass for U46 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U46-7 U46-18 # U46 3.3V Vccb power NET 'BULK_2V5' U46-31 U46-42 # U46 2.5V Vcca power NET 'GROUND' U46-4 U46-10 # U46 Ground connections NET 'GROUND' U46-15 U46-21 # U46 Ground connections NET 'GROUND' U46-28 U46-34 # U46 Ground connections NET 'GROUND' U46-39 U46-45 # U46 Ground connections NET 'BULK_3V3' C518-1 C519-1 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C517-2 C520-2 # ByPass Cap 2.5V Vcca power NET 'GROUND' C518-2 C519-2 # ByPass Cap Ground connections NET 'GROUND' C517-1 C520-1 # ByPass Cap Ground connections # Power and ByPass for U47 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U47-7 U47-18 # U47 3.3V Vccb power NET 'BULK_2V5' U47-31 U47-42 # U47 2.5V Vcca power NET 'GROUND' U47-4 U47-10 # U47 Ground connections NET 'GROUND' U47-15 U47-21 # U47 Ground connections NET 'GROUND' U47-28 U47-34 # U47 Ground connections NET 'GROUND' U47-39 U47-45 # U47 Ground connections NET 'BULK_3V3' C522-1 C523-1 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C521-2 C524-2 # ByPass Cap 2.5V Vcca power NET 'GROUND' C522-2 C523-2 # ByPass Cap Ground connections NET 'GROUND' C521-1 C524-1 # ByPass Cap Ground connections # LVDS<-->3.3V_CMOS DS91M040 Transceivers # # DS91M040 +3.3V Power Connections NET 'BULK_3V3' U21-11 U21-12 U21-29 U21-30 NET 'BULK_3V3' U22-11 U22-12 U22-29 U22-30 NET 'BULK_3V3' U23-11 U23-12 U23-29 U23-30 NET 'BULK_3V3' U24-11 U24-12 U24-29 U24-30 NET 'BULK_3V3' U25-11 U25-12 U25-29 U25-30 NET 'BULK_3V3' U26-11 U26-12 U26-29 U26-30 NET 'BULK_3V3' U27-11 U27-12 U27-29 U27-30 NET 'BULK_3V3' U28-11 U28-12 U28-29 U28-30 NET 'BULK_3V3' U29-11 U29-12 U29-29 U29-30 NET 'BULK_3V3' U30-11 U30-12 U30-29 U30-30 NET 'BULK_3V3' U31-11 U31-12 U31-29 U31-30 NET 'BULK_3V3' U32-11 U32-12 U32-29 U32-30 NET 'BULK_3V3' U33-11 U33-12 U33-29 U33-30 NET 'BULK_3V3' U34-11 U34-12 U34-29 U34-30 NET 'BULK_3V3' U35-11 U35-12 U35-29 U35-30 NET 'BULK_3V3' U36-11 U36-12 U36-29 U36-30 NET 'BULK_3V3' U37-11 U37-12 U37-29 U37-30 NET 'BULK_3V3' U38-11 U38-12 U38-29 U38-30 NET 'BULK_3V3' U39-11 U39-12 U39-29 U39-30 NET 'BULK_3V3' U40-11 U40-12 U40-29 U40-30 NET 'BULK_3V3' U41-11 U41-12 U41-29 U41-30 # LVDS<-->3.3V_CMOS DS91M040 Transceivers # # DS91M040 GROUND Connections NET 'GROUND' U21-31 NET 'GROUND' U22-31 NET 'GROUND' U23-31 NET 'GROUND' U24-31 NET 'GROUND' U25-31 NET 'GROUND' U26-31 NET 'GROUND' U27-31 NET 'GROUND' U28-31 NET 'GROUND' U29-31 NET 'GROUND' U21-33 U21-34 U21-35 U21-36 NET 'GROUND' U22-33 U22-34 U22-35 U22-36 NET 'GROUND' U23-33 U23-34 U23-35 U23-36 NET 'GROUND' U24-33 U24-34 U24-35 U24-36 NET 'GROUND' U25-33 U25-34 U25-35 U25-36 NET 'GROUND' U26-33 U26-34 U26-35 U26-36 NET 'GROUND' U27-33 U27-34 U27-35 U27-36 NET 'GROUND' U28-33 U28-34 U28-35 U28-36 NET 'GROUND' U29-33 U29-34 U29-35 U29-36 NET 'GROUND' U30-31 NET 'GROUND' U31-31 NET 'GROUND' U32-31 NET 'GROUND' U33-31 NET 'GROUND' U34-31 NET 'GROUND' U35-31 NET 'GROUND' U36-31 NET 'GROUND' U37-31 NET 'GROUND' U38-31 NET 'GROUND' U39-31 NET 'GROUND' U30-33 U30-34 U30-35 U30-36 NET 'GROUND' U31-33 U31-34 U31-35 U31-36 NET 'GROUND' U32-33 U32-34 U32-35 U32-36 NET 'GROUND' U33-33 U33-34 U33-35 U33-36 NET 'GROUND' U34-33 U34-34 U34-35 U34-36 NET 'GROUND' U35-33 U35-34 U35-35 U35-36 NET 'GROUND' U36-33 U36-34 U36-35 U36-36 NET 'GROUND' U37-33 U37-34 U37-35 U37-36 NET 'GROUND' U38-33 U38-34 U38-35 U38-36 NET 'GROUND' U39-33 U39-34 U39-35 U39-36 NET 'GROUND' U40-31 NET 'GROUND' U41-31 NET 'GROUND' U40-33 U40-34 U40-35 U40-36 NET 'GROUND' U41-33 U41-34 U41-35 U41-36 # # Bypass Capacitors C601:C621 on the # DS91M040 LVDS Transceivers U21:U41 # NET 'BULK_3V3' C601-1 C602-1 C603-1 # ByPass Cap on 3.3V power NET 'BULK_3V3' C604-1 C605-1 C606-1 # ByPass Cap on 3.3V power NET 'BULK_3V3' C607-1 C608-1 C609-1 # ByPass Cap on 3.3V power NET 'BULK_3V3' C610-1 C611-1 C612-1 # ByPass Cap on 3.3V power NET 'BULK_3V3' C613-1 C614-1 C615-1 # ByPass Cap on 3.3V power NET 'BULK_3V3' C616-1 C617-1 C618-1 # ByPass Cap on 3.3V power NET 'BULK_3V3' C619-1 C620-1 C621-1 # ByPass Cap on 3.3V power NET 'GROUND' C601-2 C602-2 C603-2 # and its Ground connection NET 'GROUND' C604-2 C605-2 C606-2 # and its Ground connection NET 'GROUND' C607-2 C608-2 C609-2 # and its Ground connection NET 'GROUND' C610-2 C611-2 C612-2 # and its Ground connection NET 'GROUND' C613-2 C614-2 C615-2 # and its Ground connection NET 'GROUND' C616-2 C617-2 C618-2 # and its Ground connection NET 'GROUND' C619-2 C620-2 C621-2 # and its Ground connection # # CMX Front Panel Line Drivers for the CTP output # ------------------------------------------------- # Net-to-Pin File # # # Original Rev. 18-Oct-2011 # Rev. 25-Oct-2011 # Rev. 07-Sep-2012 switch to DS91M040 and 2.5-3.3V translators # Rev. 10-Sep-2012 renumber ICs # Rev. 2-Nov-2012 Remove translator U68, use half of translator U69 # for BF and half for TP, split the use of transceiver # U59 into 2 independent halves for BF and TP. # Rev. 5-Nov-2012 Now with completely independent control of BF and TP # Drive or Recieve on J10 and J11 # Rev: 19-Nov-2012 Rename nets to make Base or TP a prefix (DOUT_CTP_xx_BF -> BF_DOUT_CTP_xx) # Rev: 15-Apr-2013 swap driver used for signals 64 and 65 and correct IC numbers in header comments # Rev: 22-Apr-2013 Re-order Translator IC numbers # Rev: 26-Apr-2013 swap again lvds transceiver used for signals 64 and 65 # Most Recent Rev: 11-Jul-2013 swapped pins of R137 to match its twin # # # # # # # This is the N2P file for the LVDS Drivers on the CMX card # serving the Front Panel Connectors used for # sending data to the Central Trigger Processor # # ICs referenced in this file: # ---------------------------- # # U51 to U68 are 18x National Semiconductor DS91M040 LVDS transceivers # # U71 to U74 are 10x Texas Instrument 74AVCAH164245 level translators to interface between # the 2.5V CMOS logic level of the FPGA IO banks and the 3.3V CMOS level side # of the LVDS transceivers. # These translators also act as source selector to choose if the Base Function # FPGA or the TP Function FPGA is to drive the CTP output cables. # # Note that the two halves of translator U71 are used independently, # i.e. one half for BF signals and the other half for TP signals. # Two channels of LVDS translator U59 are also used and managed # independently, one for BF and one for TP. # # There are 33x LVDS signals per CTP cable. We use 8x quad-transceiver DS91M040 # to handle the lower 32x signals from each cable (numbered 00:31 and 32:64), # We also need one extra DS91M040 each for the 33rd signal from each connector # to handle the 33rd signal (indexed #64 and #65) from each connector. # We use U60 - U67 to handle CTP signals 0:31 from connector J10 of CTP cable #1 # We use U68 to handle CTP signal 64 from connector J10 # We use U51 - U58 to handle CTP signals 32:63 from connector J11 of CTP cable #2 # We use U59 to handle CTP signal 65 from connector J11 # # We use 2x sets of 74AVCAH164245 level translators which can be controlled to act as a MUX # to select which FPGA (Base Functionor TP Function) is driving the CTP output cables. # # We use 2x 16-channel 74AVCAH164245 level translators to handle the lower 32 signals # from each cable (numbered 00:31 and 32:64) and from each main FPGA, i.e. 4x ICs for both cables # and for both FPGA sources. We also need one extra pair of 74AVCAH164245 (with only 1/8 used) # to handle the 33rd signal (indexed #64 and #65) from each connector. # We use U77 & U78 to handle Base Function FPGA CTP signals 0:31 from cable #1 # We use U75 & U76 to handle Base Function FPGA CTP signals 32:63 from cable #2 # We use U72 & U73 to handle TP Function FPGA CTP signals 0:31 from cable #1 # We use U69 & U70 to handle TP Function FPGA CTP signals 32:63 from cable #2 # We use U74 to handle Base FPGA & TP FPGA CTP signal 64 from Cable #1 # We use U71 to handle Base FPGA & TP FPGA CTP signal 65 from Cable #2 # # Signal Nets referenced in this file: # ------------------------------------ # # There are 0, 1 or 2 CTP cables connected to a given CMX card. # A Crate CMX with only Base CMX functionality does not send any data to the CTP # A System CMX in a CPM crate sends information to the CTP over one cable # A System CMX in a JEM crate sends information to the CTP over two cables # A Crate CMX with TP functionality would probably send information to the CTP over two cables # # 'CN_CTP_xx_POS' and 'CN_CTP_xx_NEG' are the LVDS signal used on the CTP output cable with xx=00 to 65. # 'CN_CTP_xx_POS' is the non-inverted signal and 'CN_CTP_xx_NEG' is the inverted signal. # Each CTP output cable carries 33 LVDS signals consisting of 31 data bits, one clock # and one parity bit. # xx=0 to 30 carry data bits on cable #1 # xx=31 carry the clock on cable #1 # xx=64 carry the parity on cable #1 # xx=32 to 62 carry data bits on cable #2 # xx=63 carry the clock on cable #2 # xx=65 carry the parity on cable #2 # # 'BF_DOUT_CTP_xx' are the CTP output signals from the Base FPGA with xx=00 to 65. # These signals are connected here to the 2.5V side of the 74AVCAH164245 level translators. # The FPGA connections for the BF_DOUT_CTP_xx signals are in the file base_function_ctp_output_n2r.txt # in the Net_Lists/Base_Fpga_Assign directory # # 'TP_DOUT_CTP_xx' are the CTP output signals from the Topological Processing FPGA with xx=00 to 65. # These signals are connected here to the 2.5V side of the 74AVCAH164245 level translators. # The FPGA connections for the TP_DOUT_CTP_xx signals are in the file tp_function_ctp_output_n2r.txt # in the Net_Lists/TP_Fpga_Assign directory # # 'I_DOUT_CTP_xx' are the intermediate CTP output signals with xx=00 to 65. # These signals connect the single ended side of the LVDS transceiver # to the 3.3V side of the 74AVCAH164245 level translators. # # Note that signals 64 and 65 are handled just a little bit differently, # not in a logical sense, but in the way that they are layed out in the # Translator and Transceiver chips. # # CTP Cable #1 # NET 'BF_DOUT_CTP_00' U77-26 # Base Function FPGA 2.5V CTP signal #00 # to first bank of level translator/MUX NET 'TP_DOUT_CTP_00' U72-26 # TP Function FPGA 2.5V CTP signal #00 # to second bank of level translator/MUX NET 'I_DOUT_CTP_00' U77-23 U72-23 # Intermediate 3.3V CTP signal #00 # coming from both banks of level # translators/MUX NET 'I_DOUT_CTP_00' U60-1 U60-2 # Intermediate 3.3V CTP signal signal # to pair of pins on single ended side # of LVDS transceiver NET 'CN_CTP_00_POS' U60-23 R139-2 # Non-inverted CTP signal #00 from LVDS # transceiver and termination resistor NET 'CN_CTP_00_NEG' U60-24 R139-1 # inverted CTP signal #00 from LVDS # transceiver and termination resistor NET 'BF_DOUT_CTP_01' U77-27 # (ditto for CTP signals 01 to 65 below) NET 'TP_DOUT_CTP_01' U72-27 NET 'I_DOUT_CTP_01' U77-22 U72-22 NET 'I_DOUT_CTP_01' U60-3 U60-4 NET 'CN_CTP_01_POS' U60-21 R140-2 NET 'CN_CTP_01_NEG' U60-22 R140-1 NET 'BF_DOUT_CTP_02' U77-29 NET 'TP_DOUT_CTP_02' U72-29 NET 'I_DOUT_CTP_02' U77-20 U72-20 NET 'I_DOUT_CTP_02' U60-5 U60-6 NET 'CN_CTP_02_POS' U60-19 R141-1 NET 'CN_CTP_02_NEG' U60-20 R141-2 NET 'BF_DOUT_CTP_03' U77-30 NET 'TP_DOUT_CTP_03' U72-30 NET 'I_DOUT_CTP_03' U77-19 U72-19 NET 'I_DOUT_CTP_03' U60-7 U60-8 NET 'CN_CTP_03_POS' U60-17 R142-1 NET 'CN_CTP_03_NEG' U60-18 R142-2 NET 'BF_DOUT_CTP_04' U77-32 NET 'TP_DOUT_CTP_04' U72-32 NET 'I_DOUT_CTP_04' U77-17 U72-17 NET 'I_DOUT_CTP_04' U61-1 U61-2 NET 'CN_CTP_04_POS' U61-23 R143-2 NET 'CN_CTP_04_NEG' U61-24 R143-1 NET 'BF_DOUT_CTP_05' U77-33 NET 'TP_DOUT_CTP_05' U72-33 NET 'I_DOUT_CTP_05' U77-16 U72-16 NET 'I_DOUT_CTP_05' U61-3 U61-4 NET 'CN_CTP_05_POS' U61-21 R144-2 NET 'CN_CTP_05_NEG' U61-22 R144-1 NET 'BF_DOUT_CTP_06' U77-35 NET 'TP_DOUT_CTP_06' U72-35 NET 'I_DOUT_CTP_06' U77-14 U72-14 NET 'I_DOUT_CTP_06' U61-5 U61-6 NET 'CN_CTP_06_POS' U61-19 R145-1 NET 'CN_CTP_06_NEG' U61-20 R145-2 NET 'BF_DOUT_CTP_07' U77-36 NET 'TP_DOUT_CTP_07' U72-36 NET 'I_DOUT_CTP_07' U77-13 U72-13 NET 'I_DOUT_CTP_07' U61-7 U61-8 NET 'CN_CTP_07_POS' U61-17 R146-1 NET 'CN_CTP_07_NEG' U61-18 R146-2 NET 'BF_DOUT_CTP_08' U77-37 NET 'TP_DOUT_CTP_08' U72-37 NET 'I_DOUT_CTP_08' U77-12 U72-12 NET 'I_DOUT_CTP_08' U62-1 U62-2 NET 'CN_CTP_08_POS' U62-23 R147-2 NET 'CN_CTP_08_NEG' U62-24 R147-1 NET 'BF_DOUT_CTP_09' U77-38 NET 'TP_DOUT_CTP_09' U72-38 NET 'I_DOUT_CTP_09' U77-11 U72-11 NET 'I_DOUT_CTP_09' U62-3 U62-4 NET 'CN_CTP_09_POS' U62-21 R148-2 NET 'CN_CTP_09_NEG' U62-22 R148-1 NET 'BF_DOUT_CTP_10' U77-40 NET 'TP_DOUT_CTP_10' U72-40 NET 'I_DOUT_CTP_10' U77-9 U72-9 NET 'I_DOUT_CTP_10' U62-5 U62-6 NET 'CN_CTP_10_POS' U62-19 R149-1 NET 'CN_CTP_10_NEG' U62-20 R149-2 NET 'BF_DOUT_CTP_11' U77-41 NET 'TP_DOUT_CTP_11' U72-41 NET 'I_DOUT_CTP_11' U77-8 U72-8 NET 'I_DOUT_CTP_11' U62-7 U62-8 NET 'CN_CTP_11_POS' U62-17 R150-1 NET 'CN_CTP_11_NEG' U62-18 R150-2 NET 'BF_DOUT_CTP_12' U77-43 NET 'TP_DOUT_CTP_12' U72-43 NET 'I_DOUT_CTP_12' U77-6 U72-6 NET 'I_DOUT_CTP_12' U63-1 U63-2 NET 'CN_CTP_12_POS' U63-23 R151-2 NET 'CN_CTP_12_NEG' U63-24 R151-1 NET 'BF_DOUT_CTP_13' U77-44 NET 'TP_DOUT_CTP_13' U72-44 NET 'I_DOUT_CTP_13' U77-5 U72-5 NET 'I_DOUT_CTP_13' U63-3 U63-4 NET 'CN_CTP_13_POS' U63-21 R152-2 NET 'CN_CTP_13_NEG' U63-22 R152-1 NET 'BF_DOUT_CTP_14' U77-46 NET 'TP_DOUT_CTP_14' U72-46 NET 'I_DOUT_CTP_14' U77-3 U72-3 NET 'I_DOUT_CTP_14' U63-5 U63-6 NET 'CN_CTP_14_POS' U63-19 R153-1 NET 'CN_CTP_14_NEG' U63-20 R153-2 NET 'BF_DOUT_CTP_15' U77-47 NET 'TP_DOUT_CTP_15' U72-47 NET 'I_DOUT_CTP_15' U77-2 U72-2 NET 'I_DOUT_CTP_15' U63-7 U63-8 NET 'CN_CTP_15_POS' U63-17 R154-1 NET 'CN_CTP_15_NEG' U63-18 R154-2 NET 'BF_DOUT_CTP_16' U78-26 NET 'TP_DOUT_CTP_16' U73-26 NET 'I_DOUT_CTP_16' U78-23 U73-23 NET 'I_DOUT_CTP_16' U64-1 U64-2 NET 'CN_CTP_16_POS' U64-23 R155-2 NET 'CN_CTP_16_NEG' U64-24 R155-1 NET 'BF_DOUT_CTP_17' U78-27 NET 'TP_DOUT_CTP_17' U73-27 NET 'I_DOUT_CTP_17' U78-22 U73-22 NET 'I_DOUT_CTP_17' U64-3 U64-4 NET 'CN_CTP_17_POS' U64-21 R156-2 NET 'CN_CTP_17_NEG' U64-22 R156-1 NET 'BF_DOUT_CTP_18' U78-29 NET 'TP_DOUT_CTP_18' U73-29 NET 'I_DOUT_CTP_18' U78-20 U73-20 NET 'I_DOUT_CTP_18' U64-5 U64-6 NET 'CN_CTP_18_POS' U64-19 R157-1 NET 'CN_CTP_18_NEG' U64-20 R157-2 NET 'BF_DOUT_CTP_19' U78-30 NET 'TP_DOUT_CTP_19' U73-30 NET 'I_DOUT_CTP_19' U78-19 U73-19 NET 'I_DOUT_CTP_19' U64-7 U64-8 NET 'CN_CTP_19_POS' U64-17 R158-1 NET 'CN_CTP_19_NEG' U64-18 R158-2 NET 'BF_DOUT_CTP_20' U78-32 NET 'TP_DOUT_CTP_20' U73-32 NET 'I_DOUT_CTP_20' U78-17 U73-17 NET 'I_DOUT_CTP_20' U65-1 U65-2 NET 'CN_CTP_20_POS' U65-23 R159-2 NET 'CN_CTP_20_NEG' U65-24 R159-1 NET 'BF_DOUT_CTP_21' U78-33 NET 'TP_DOUT_CTP_21' U73-33 NET 'I_DOUT_CTP_21' U78-16 U73-16 NET 'I_DOUT_CTP_21' U65-3 U65-4 NET 'CN_CTP_21_POS' U65-21 R160-2 NET 'CN_CTP_21_NEG' U65-22 R160-1 NET 'BF_DOUT_CTP_22' U78-35 NET 'TP_DOUT_CTP_22' U73-35 NET 'I_DOUT_CTP_22' U78-14 U73-14 NET 'I_DOUT_CTP_22' U65-5 U65-6 NET 'CN_CTP_22_POS' U65-19 R161-1 NET 'CN_CTP_22_NEG' U65-20 R161-2 NET 'BF_DOUT_CTP_23' U78-36 NET 'TP_DOUT_CTP_23' U73-36 NET 'I_DOUT_CTP_23' U78-13 U73-13 NET 'I_DOUT_CTP_23' U65-7 U65-8 NET 'CN_CTP_23_POS' U65-17 R162-1 NET 'CN_CTP_23_NEG' U65-18 R162-2 NET 'BF_DOUT_CTP_24' U78-37 NET 'TP_DOUT_CTP_24' U73-37 NET 'I_DOUT_CTP_24' U78-12 U73-12 NET 'I_DOUT_CTP_24' U66-1 U66-2 NET 'CN_CTP_24_POS' U66-23 R163-2 NET 'CN_CTP_24_NEG' U66-24 R163-1 NET 'BF_DOUT_CTP_25' U78-38 NET 'TP_DOUT_CTP_25' U73-38 NET 'I_DOUT_CTP_25' U78-11 U73-11 NET 'I_DOUT_CTP_25' U66-3 U66-4 NET 'CN_CTP_25_POS' U66-21 R164-2 NET 'CN_CTP_25_NEG' U66-22 R164-1 NET 'BF_DOUT_CTP_26' U78-40 NET 'TP_DOUT_CTP_26' U73-40 NET 'I_DOUT_CTP_26' U78-9 U73-9 NET 'I_DOUT_CTP_26' U66-5 U66-6 NET 'CN_CTP_26_POS' U66-19 R165-1 NET 'CN_CTP_26_NEG' U66-20 R165-2 NET 'BF_DOUT_CTP_27' U78-41 NET 'TP_DOUT_CTP_27' U73-41 NET 'I_DOUT_CTP_27' U78-8 U73-8 NET 'I_DOUT_CTP_27' U66-7 U66-8 NET 'CN_CTP_27_POS' U66-17 R166-1 NET 'CN_CTP_27_NEG' U66-18 R166-2 NET 'BF_DOUT_CTP_28' U78-43 NET 'TP_DOUT_CTP_28' U73-43 NET 'I_DOUT_CTP_28' U78-6 U73-6 NET 'I_DOUT_CTP_28' U67-1 U67-2 NET 'CN_CTP_28_POS' U67-23 R167-2 NET 'CN_CTP_28_NEG' U67-24 R167-1 NET 'BF_DOUT_CTP_29' U78-44 NET 'TP_DOUT_CTP_29' U73-44 NET 'I_DOUT_CTP_29' U78-5 U73-5 NET 'I_DOUT_CTP_29' U67-3 U67-4 NET 'CN_CTP_29_POS' U67-21 R168-2 NET 'CN_CTP_29_NEG' U67-22 R168-1 NET 'BF_DOUT_CTP_30' U78-46 NET 'TP_DOUT_CTP_30' U73-46 NET 'I_DOUT_CTP_30' U78-3 U73-3 NET 'I_DOUT_CTP_30' U67-5 U67-6 NET 'CN_CTP_30_POS' U67-19 R169-1 NET 'CN_CTP_30_NEG' U67-20 R169-2 NET 'BF_DOUT_CTP_31' U78-47 NET 'TP_DOUT_CTP_31' U73-47 NET 'I_DOUT_CTP_31' U78-2 U73-2 NET 'I_DOUT_CTP_31' U67-7 U67-8 NET 'CN_CTP_31_POS' U67-17 R170-1 NET 'CN_CTP_31_NEG' U67-18 R170-2 NET 'BF_DOUT_CTP_64' U74-47 NET 'TP_DOUT_CTP_64' U74-36 NET 'I_DOUT_CTP_64' U74-2 U74-13 NET 'I_DOUT_CTP_64' U68-3 U68-4 NET 'CN_CTP_64_POS' U68-21 R138-1 NET 'CN_CTP_64_NEG' U68-22 R138-2 # # CTP Cable #2 # NET 'BF_DOUT_CTP_32' U75-26 NET 'TP_DOUT_CTP_32' U69-26 NET 'I_DOUT_CTP_32' U75-23 U69-23 NET 'I_DOUT_CTP_32' U51-1 U51-2 NET 'CN_CTP_32_POS' U51-23 R105-2 NET 'CN_CTP_32_NEG' U51-24 R105-1 NET 'BF_DOUT_CTP_33' U75-27 NET 'TP_DOUT_CTP_33' U69-27 NET 'I_DOUT_CTP_33' U75-22 U69-22 NET 'I_DOUT_CTP_33' U51-3 U51-4 NET 'CN_CTP_33_POS' U51-21 R106-2 NET 'CN_CTP_33_NEG' U51-22 R106-1 NET 'BF_DOUT_CTP_34' U75-29 NET 'TP_DOUT_CTP_34' U69-29 NET 'I_DOUT_CTP_34' U75-20 U69-20 NET 'I_DOUT_CTP_34' U51-5 U51-6 NET 'CN_CTP_34_POS' U51-19 R107-1 NET 'CN_CTP_34_NEG' U51-20 R107-2 NET 'BF_DOUT_CTP_35' U75-30 NET 'TP_DOUT_CTP_35' U69-30 NET 'I_DOUT_CTP_35' U75-19 U69-19 NET 'I_DOUT_CTP_35' U51-7 U51-8 NET 'CN_CTP_35_POS' U51-17 R108-1 NET 'CN_CTP_35_NEG' U51-18 R108-2 NET 'BF_DOUT_CTP_36' U75-32 NET 'TP_DOUT_CTP_36' U69-32 NET 'I_DOUT_CTP_36' U75-17 U69-17 NET 'I_DOUT_CTP_36' U52-1 U52-2 NET 'CN_CTP_36_POS' U52-23 R109-2 NET 'CN_CTP_36_NEG' U52-24 R109-1 NET 'BF_DOUT_CTP_37' U75-33 NET 'TP_DOUT_CTP_37' U69-33 NET 'I_DOUT_CTP_37' U75-16 U69-16 NET 'I_DOUT_CTP_37' U52-3 U52-4 NET 'CN_CTP_37_POS' U52-21 R110-2 NET 'CN_CTP_37_NEG' U52-22 R110-1 NET 'BF_DOUT_CTP_38' U75-35 NET 'TP_DOUT_CTP_38' U69-35 NET 'I_DOUT_CTP_38' U75-14 U69-14 NET 'I_DOUT_CTP_38' U52-5 U52-6 NET 'CN_CTP_38_POS' U52-19 R111-1 NET 'CN_CTP_38_NEG' U52-20 R111-2 NET 'BF_DOUT_CTP_39' U75-36 NET 'TP_DOUT_CTP_39' U69-36 NET 'I_DOUT_CTP_39' U75-13 U69-13 NET 'I_DOUT_CTP_39' U52-7 U52-8 NET 'CN_CTP_39_POS' U52-17 R112-1 NET 'CN_CTP_39_NEG' U52-18 R112-2 NET 'BF_DOUT_CTP_40' U75-37 NET 'TP_DOUT_CTP_40' U69-37 NET 'I_DOUT_CTP_40' U75-12 U69-12 NET 'I_DOUT_CTP_40' U53-1 U53-2 NET 'CN_CTP_40_POS' U53-23 R113-2 NET 'CN_CTP_40_NEG' U53-24 R113-1 NET 'BF_DOUT_CTP_41' U75-38 NET 'TP_DOUT_CTP_41' U69-38 NET 'I_DOUT_CTP_41' U75-11 U69-11 NET 'I_DOUT_CTP_41' U53-3 U53-4 NET 'CN_CTP_41_POS' U53-21 R114-2 NET 'CN_CTP_41_NEG' U53-22 R114-1 NET 'BF_DOUT_CTP_42' U75-40 NET 'TP_DOUT_CTP_42' U69-40 NET 'I_DOUT_CTP_42' U75-9 U69-9 NET 'I_DOUT_CTP_42' U53-5 U53-6 NET 'CN_CTP_42_POS' U53-19 R115-1 NET 'CN_CTP_42_NEG' U53-20 R115-2 NET 'BF_DOUT_CTP_43' U75-41 NET 'TP_DOUT_CTP_43' U69-41 NET 'I_DOUT_CTP_43' U75-8 U69-8 NET 'I_DOUT_CTP_43' U53-7 U53-8 NET 'CN_CTP_43_POS' U53-17 R116-1 NET 'CN_CTP_43_NEG' U53-18 R116-2 NET 'BF_DOUT_CTP_44' U75-43 NET 'TP_DOUT_CTP_44' U69-43 NET 'I_DOUT_CTP_44' U75-6 U69-6 NET 'I_DOUT_CTP_44' U54-1 U54-2 NET 'CN_CTP_44_POS' U54-23 R117-2 NET 'CN_CTP_44_NEG' U54-24 R117-1 NET 'BF_DOUT_CTP_45' U75-44 NET 'TP_DOUT_CTP_45' U69-44 NET 'I_DOUT_CTP_45' U75-5 U69-5 NET 'I_DOUT_CTP_45' U54-3 U54-4 NET 'CN_CTP_45_POS' U54-21 R118-2 NET 'CN_CTP_45_NEG' U54-22 R118-1 NET 'BF_DOUT_CTP_46' U75-46 NET 'TP_DOUT_CTP_46' U69-46 NET 'I_DOUT_CTP_46' U75-3 U69-3 NET 'I_DOUT_CTP_46' U54-5 U54-6 NET 'CN_CTP_46_POS' U54-19 R119-1 NET 'CN_CTP_46_NEG' U54-20 R119-2 NET 'BF_DOUT_CTP_47' U75-47 NET 'TP_DOUT_CTP_47' U69-47 NET 'I_DOUT_CTP_47' U75-2 U69-2 NET 'I_DOUT_CTP_47' U54-7 U54-8 NET 'CN_CTP_47_POS' U54-17 R120-1 NET 'CN_CTP_47_NEG' U54-18 R120-2 NET 'BF_DOUT_CTP_48' U76-26 NET 'TP_DOUT_CTP_48' U70-26 NET 'I_DOUT_CTP_48' U76-23 U70-23 NET 'I_DOUT_CTP_48' U55-1 U55-2 NET 'CN_CTP_48_POS' U55-23 R121-2 NET 'CN_CTP_48_NEG' U55-24 R121-1 NET 'BF_DOUT_CTP_49' U76-27 NET 'TP_DOUT_CTP_49' U70-27 NET 'I_DOUT_CTP_49' U76-22 U70-22 NET 'I_DOUT_CTP_49' U55-3 U55-4 NET 'CN_CTP_49_POS' U55-21 R122-2 NET 'CN_CTP_49_NEG' U55-22 R122-1 NET 'BF_DOUT_CTP_50' U76-29 NET 'TP_DOUT_CTP_50' U70-29 NET 'I_DOUT_CTP_50' U76-20 U70-20 NET 'I_DOUT_CTP_50' U55-5 U55-6 NET 'CN_CTP_50_POS' U55-19 R123-1 NET 'CN_CTP_50_NEG' U55-20 R123-2 NET 'BF_DOUT_CTP_51' U76-30 NET 'TP_DOUT_CTP_51' U70-30 NET 'I_DOUT_CTP_51' U76-19 U70-19 NET 'I_DOUT_CTP_51' U55-7 U55-8 NET 'CN_CTP_51_POS' U55-17 R124-1 NET 'CN_CTP_51_NEG' U55-18 R124-2 NET 'BF_DOUT_CTP_52' U76-32 NET 'TP_DOUT_CTP_52' U70-32 NET 'I_DOUT_CTP_52' U76-17 U70-17 NET 'I_DOUT_CTP_52' U56-1 U56-2 NET 'CN_CTP_52_POS' U56-23 R125-2 NET 'CN_CTP_52_NEG' U56-24 R125-1 NET 'BF_DOUT_CTP_53' U76-33 NET 'TP_DOUT_CTP_53' U70-33 NET 'I_DOUT_CTP_53' U76-16 U70-16 NET 'I_DOUT_CTP_53' U56-3 U56-4 NET 'CN_CTP_53_POS' U56-21 R126-2 NET 'CN_CTP_53_NEG' U56-22 R126-1 NET 'BF_DOUT_CTP_54' U76-35 NET 'TP_DOUT_CTP_54' U70-35 NET 'I_DOUT_CTP_54' U76-14 U70-14 NET 'I_DOUT_CTP_54' U56-5 U56-6 NET 'CN_CTP_54_POS' U56-19 R127-1 NET 'CN_CTP_54_NEG' U56-20 R127-2 NET 'BF_DOUT_CTP_55' U76-36 NET 'TP_DOUT_CTP_55' U70-36 NET 'I_DOUT_CTP_55' U76-13 U70-13 NET 'I_DOUT_CTP_55' U56-7 U56-8 NET 'CN_CTP_55_POS' U56-17 R128-1 NET 'CN_CTP_55_NEG' U56-18 R128-2 NET 'BF_DOUT_CTP_56' U76-37 NET 'TP_DOUT_CTP_56' U70-37 NET 'I_DOUT_CTP_56' U76-12 U70-12 NET 'I_DOUT_CTP_56' U57-1 U57-2 NET 'CN_CTP_56_POS' U57-23 R129-2 NET 'CN_CTP_56_NEG' U57-24 R129-1 NET 'BF_DOUT_CTP_57' U76-38 NET 'TP_DOUT_CTP_57' U70-38 NET 'I_DOUT_CTP_57' U76-11 U70-11 NET 'I_DOUT_CTP_57' U57-3 U57-4 NET 'CN_CTP_57_POS' U57-21 R130-2 NET 'CN_CTP_57_NEG' U57-22 R130-1 NET 'BF_DOUT_CTP_58' U76-40 NET 'TP_DOUT_CTP_58' U70-40 NET 'I_DOUT_CTP_58' U76-9 U70-9 NET 'I_DOUT_CTP_58' U57-5 U57-6 NET 'CN_CTP_58_POS' U57-19 R131-1 NET 'CN_CTP_58_NEG' U57-20 R131-2 NET 'BF_DOUT_CTP_59' U76-41 NET 'TP_DOUT_CTP_59' U70-41 NET 'I_DOUT_CTP_59' U76-8 U70-8 NET 'I_DOUT_CTP_59' U57-7 U57-8 NET 'CN_CTP_59_POS' U57-17 R132-1 NET 'CN_CTP_59_NEG' U57-18 R132-2 NET 'BF_DOUT_CTP_60' U76-43 NET 'TP_DOUT_CTP_60' U70-43 NET 'I_DOUT_CTP_60' U76-6 U70-6 NET 'I_DOUT_CTP_60' U58-1 U58-2 NET 'CN_CTP_60_POS' U58-23 R133-2 NET 'CN_CTP_60_NEG' U58-24 R133-1 NET 'BF_DOUT_CTP_61' U76-44 NET 'TP_DOUT_CTP_61' U70-44 NET 'I_DOUT_CTP_61' U76-5 U70-5 NET 'I_DOUT_CTP_61' U58-3 U58-4 NET 'CN_CTP_61_POS' U58-21 R134-2 NET 'CN_CTP_61_NEG' U58-22 R134-1 NET 'BF_DOUT_CTP_62' U76-46 NET 'TP_DOUT_CTP_62' U70-46 NET 'I_DOUT_CTP_62' U76-3 U70-3 NET 'I_DOUT_CTP_62' U58-5 U58-6 NET 'CN_CTP_62_POS' U58-19 R135-1 NET 'CN_CTP_62_NEG' U58-20 R135-2 NET 'BF_DOUT_CTP_63' U76-47 NET 'TP_DOUT_CTP_63' U70-47 NET 'I_DOUT_CTP_63' U76-2 U70-2 NET 'I_DOUT_CTP_63' U58-7 U58-8 NET 'CN_CTP_63_POS' U58-17 R136-1 NET 'CN_CTP_63_NEG' U58-18 R136-2 NET 'BF_DOUT_CTP_65' U71-47 NET 'TP_DOUT_CTP_65' U71-36 NET 'I_DOUT_CTP_65' U71-2 U71-13 NET 'I_DOUT_CTP_65' U59-3 U59-4 NET 'CN_CTP_65_POS' U59-21 R137-1 NET 'CN_CTP_65_NEG' U59-22 R137-2 # # CMX-0 Nets File # # Front-Panel LVDS CTP Management Nets # --===========---------------------------- # # # Original Rev. 1-Nov-2012 # Most Recent Rev. 25-Apr-2013 # # # # This file holds the nets involved in the management of the # Front-Panel LVDS CTP Transceivers and Level Translators. # ---------------------- # # # As of 2-Nov-2012 the intent is to provide management of the # front panel CTP LVDS connections so that: # # BF can independently Drive, Receive, or Ignore the # upper J10 and lower J11 print panel LVDS connectors # # and # # TP can independently Drive, Receive, or Ignore the # upper J10 and lower J11 front panel LVDS connectors. # # Specifically for example, BF could drive all lines on the # upper J10 connector while TP is driving all lines on the # lower J11 connector. # # The implementation of this independed control is straight # forward except that the physical layout of signsls 64 and 65 # in the Translator chips U69 and U74 is a little different # and there are separate Transceivers, i.e. U68 for thes # selected signal 64 in the upper CTP connector J10 and # U59 for the selected signal 65 in the lower CTP connector # J11. # # # Recall the Layout of the Translator and Transceiver Chips: # # Base Function Topology # Signals Translation/MUX Translation/MUX Transceiver Connector # ------- --------------- --------------- ----------- --------- # # 0:31 U77 and U78 U72 and U73 U60:U67 J10 # # 32:63 U75 and U76 U69 and U70 U51:U58 J11 # # 64 U74 sec. 1 U74 sec. 2 U68 J10 # # 65 U71 sec. 1 U71 sec. 2 U59 J11 # # # # # The control to the OE_B pins to the CTP Translator chips # come from U361 in the Hardwired Oversight Logic section. # # These OE_B signals to the Translator chips are named: # # CTP_1_BF_TRNSLT_OE_B CTP_2_BF_TRNSLT_OE_B # # CTP_1_TP_TRNSLT_OE_B CTP_2_TP_TRNSLT_OE_B # # These control signals originate in the BSPT FPGA but # pass through the Hardwired Oversight Logic on their # way to the OE_B pins on the Translator chips. As these # signals come out of the BSPT FPGA that are named: # # BSPT_CTP_1_BF_TRNSLT_OE_B BSPT_CTP_2_BF_TRNSLT_OE_B # # BSPT_CTP_1_TP_TRNSLT_OE_B BSPT_CTP_2_TP_TRNSLT_OE_B # # The UPPER i.e. J10 set of Front-Panel LVDS CTP Management Signals # ----- --- -------------------- # Upper Connector J10 Base Function Translation and MUX Control Signals NET 'CTP_1_BF_TRNSLT_DIR' U77-1 U77-24 # Direction of BF Translators 15:0 NET 'CTP_1_BF_TRNSLT_DIR' U78-1 U78-24 # Direction of BF Translators 31:16 NET 'CTP_1_BF_TRNSLT_DIR' U74-1 # Direction of BF Translators 64 NET 'CTP_1_BF_TRNSLT_OE_B' U77-25 U77-48 # Output Enable Bar of BF Translators 15:0 NET 'CTP_1_BF_TRNSLT_OE_B' U78-25 U78-48 # Output Enable Bar of BF Translators 31:16 NET 'CTP_1_BF_TRNSLT_OE_B' U74-48 # Output Enable Bar of BF Translators 64 # Upper Connector J10 Topological Translation and MUX Control Signals NET 'CTP_1_TP_TRNSLT_DIR' U72-1 U72-24 # Direction of TP Translators 15:0 NET 'CTP_1_TP_TRNSLT_DIR' U73-1 U73-24 # Direction of TP Translators 31:16 NET 'CTP_1_TP_TRNSLT_DIR' U74-24 # Direction of TP Translators 64 NET 'CTP_1_TP_TRNSLT_OE_B' U72-25 U72-48 # Output Enable Bar of TP Translators 15:0 NET 'CTP_1_TP_TRNSLT_OE_B' U73-25 U73-48 # Output Enable Bar of TP Translators 31:16 NET 'CTP_1_TP_TRNSLT_OE_B' U74-25 # Output Enable Bar of TP Translators 64 # Upper Connector J10 Tranceiver Control Signals NET 'CTP_1_TRNCVR_DIR' U60-13 U60-15 U60-26 U60-28 # Receiver Enb_B 3:0 NET 'CTP_1_TRNCVR_DIR' U61-13 U61-15 U61-26 U61-28 # Receiver Enb_B 7:4 NET 'CTP_1_TRNCVR_DIR' U62-13 U62-15 U62-26 U62-28 # Receiver Enb_B 11:8 NET 'CTP_1_TRNCVR_DIR' U63-13 U63-15 U63-26 U63-28 # Receiver Enb_B 15:12 NET 'CTP_1_TRNCVR_DIR' U64-13 U64-15 U64-26 U64-28 # Receiver Enb_B 19:16 NET 'CTP_1_TRNCVR_DIR' U65-13 U65-15 U65-26 U65-28 # Receiver Enb_B 23:20 NET 'CTP_1_TRNCVR_DIR' U66-13 U66-15 U66-26 U66-28 # Receiver Enb_B 27:24 NET 'CTP_1_TRNCVR_DIR' U67-13 U67-15 U67-26 U67-28 # Receiver Enb_B 31:28 NET 'CTP_1_TRNCVR_DIR' U68-13 U68-15 U68-26 U68-28 # Receiver Enb_B 64 NET 'CTP_1_TRNCVR_DIR' U60-14 U60-16 U60-25 U60-27 # Driver Enable 3:0 NET 'CTP_1_TRNCVR_DIR' U61-14 U61-16 U61-25 U61-27 # Driver Enable 7:4 NET 'CTP_1_TRNCVR_DIR' U62-14 U62-16 U62-25 U62-27 # Driver Enable 11:8 NET 'CTP_1_TRNCVR_DIR' U63-14 U63-16 U63-25 U63-27 # Driver Enable 15:12 NET 'CTP_1_TRNCVR_DIR' U64-14 U64-16 U64-25 U64-27 # Driver Enable 19:16 NET 'CTP_1_TRNCVR_DIR' U65-14 U65-16 U65-25 U65-27 # Driver Enable 23:20 NET 'CTP_1_TRNCVR_DIR' U66-14 U66-16 U66-25 U66-27 # Driver Enable 27:24 NET 'CTP_1_TRNCVR_DIR' U67-14 U67-16 U67-25 U67-27 # Driver Enable 31:28 NET 'CTP_1_TRNCVR_DIR' U68-14 U68-16 U68-25 U68-27 # Driver Enable 64 NET 'FRONT_UPPER_LVDS_FAILSAFE' U60-9 U60-32 U61-9 U61-32 # Receiver Failsafe NET 'FRONT_UPPER_LVDS_FAILSAFE' U62-9 U62-32 U63-9 U63-32 # Receiver Failsafe NET 'FRONT_UPPER_LVDS_FAILSAFE' U64-9 U64-32 U65-9 U65-32 # Receiver Failsafe NET 'FRONT_UPPER_LVDS_FAILSAFE' U66-9 U66-32 U67-9 U67-32 # Receiver Failsafe NET 'FRONT_UPPER_LVDS_FAILSAFE' U68-9 U68-32 # Receiver Failsafe NET 'FRONT_UPPER_LVDS_MASTER_ENB' U60-10 U61-10 U62-10 U63-10 # Trncvr Master Enable NET 'FRONT_UPPER_LVDS_MASTER_ENB' U64-10 U65-10 U66-10 U67-10 # Trncvr Master Enable NET 'FRONT_UPPER_LVDS_MASTER_ENB' U68-10 # Trncvr Master Enable # The LOWER i.e. J11 set of Front-Panel LVDS CTP Management Signals # ----- --- -------------------- # Upper Connector J11 Base Function Translation and MUX Control Signals NET 'CTP_2_BF_TRNSLT_DIR' U75-1 U75-24 # Direction of BF Translators 47:32 NET 'CTP_2_BF_TRNSLT_DIR' U76-1 U76-24 # Direction of BF Translators 63:48 NET 'CTP_2_BF_TRNSLT_DIR' U71-1 # Direction of BF Translators 65 NET 'CTP_2_BF_TRNSLT_OE_B' U75-25 U75-48 # Output Enable Bar of BF Translators 47:32 NET 'CTP_2_BF_TRNSLT_OE_B' U76-25 U76-48 # Output Enable Bar of BF Translators 63:48 NET 'CTP_2_BF_TRNSLT_OE_B' U71-48 # Output Enable Bar of BF Translators 65 # Upper Connector J11 Topological Translation and MUX Control Signals NET 'CTP_2_TP_TRNSLT_DIR' U69-1 U69-24 # Direction of TP Translators 47:32 NET 'CTP_2_TP_TRNSLT_DIR' U70-1 U70-24 # Direction of TP Translators 63:48 NET 'CTP_2_TP_TRNSLT_DIR' U71-24 # Direction of TP Translators 65 NET 'CTP_2_TP_TRNSLT_OE_B' U69-25 U69-48 # Output Enable Bar of TP Translators 47:32 NET 'CTP_2_TP_TRNSLT_OE_B' U70-25 U70-48 # Output Enable Bar of TP Translators 63:48 NET 'CTP_2_TP_TRNSLT_OE_B' U71-25 # Output Enable Bar of TP Translators 65 # Upper Connector J11 Tranceiver Control Signals NET 'CTP_2_TRNCVR_DIR' U51-13 U51-15 U51-26 U51-28 # Receiver Enb_B 35:32 NET 'CTP_2_TRNCVR_DIR' U52-13 U52-15 U52-26 U52-28 # Receiver Enb_B 39:36 NET 'CTP_2_TRNCVR_DIR' U53-13 U53-15 U53-26 U53-28 # Receiver Enb_B 43:40 NET 'CTP_2_TRNCVR_DIR' U54-13 U54-15 U54-26 U54-28 # Receiver Enb_B 47:44 NET 'CTP_2_TRNCVR_DIR' U55-13 U55-15 U55-26 U55-28 # Receiver Enb_B 51:48 NET 'CTP_2_TRNCVR_DIR' U56-13 U56-15 U56-26 U56-28 # Receiver Enb_B 55:52 NET 'CTP_2_TRNCVR_DIR' U57-13 U57-15 U57-26 U57-28 # Receiver Enb_B 59:56 NET 'CTP_2_TRNCVR_DIR' U58-13 U58-15 U58-26 U58-28 # Receiver Enb_B 63:60 NET 'CTP_2_TRNCVR_DIR' U59-13 U59-15 U59-26 U59-28 # Receiver Enb_B 65 NET 'CTP_2_TRNCVR_DIR' U51-14 U51-16 U51-25 U51-27 # Driver Enable 35:32 NET 'CTP_2_TRNCVR_DIR' U52-14 U52-16 U52-25 U52-27 # Driver Enable 39:36 NET 'CTP_2_TRNCVR_DIR' U53-14 U53-16 U53-25 U53-27 # Driver Enable 43:40 NET 'CTP_2_TRNCVR_DIR' U54-14 U54-16 U54-25 U54-27 # Driver Enable 47:44 NET 'CTP_2_TRNCVR_DIR' U55-14 U55-16 U55-25 U55-27 # Driver Enable 51:48 NET 'CTP_2_TRNCVR_DIR' U56-14 U56-16 U56-25 U56-27 # Driver Enable 55:52 NET 'CTP_2_TRNCVR_DIR' U57-14 U57-16 U57-25 U57-27 # Driver Enable 59:56 NET 'CTP_2_TRNCVR_DIR' U58-14 U58-16 U58-25 U58-27 # Driver Enable 63:60 NET 'CTP_2_TRNCVR_DIR' U59-14 U59-16 U59-25 U59-27 # Driver Enable 65 NET 'FRONT_LOWER_LVDS_FAILSAFE' U51-9 U51-32 U52-9 U52-32 # Receiver Failsafe NET 'FRONT_LOWER_LVDS_FAILSAFE' U53-9 U53-32 U54-9 U54-32 # Receiver Failsafe NET 'FRONT_LOWER_LVDS_FAILSAFE' U55-9 U55-32 U56-9 U56-32 # Receiver Failsafe NET 'FRONT_LOWER_LVDS_FAILSAFE' U57-9 U57-32 U58-9 U58-32 # Receiver Failsafe NET 'FRONT_LOWER_LVDS_FAILSAFE' U59-9 U59-32 # Receiver Failsafe NET 'FRONT_LOWER_LVDS_MASTER_ENB' U51-10 U52-10 U53-10 U54-10 # Trncvr Master Enable NET 'FRONT_LOWER_LVDS_MASTER_ENB' U55-10 U56-10 U57-10 U58-10 # Trncvr Master Enable NET 'FRONT_LOWER_LVDS_MASTER_ENB' U59-10 # Trncvr Master Enable # # There are 2 functions of the DS91M040 LVDS Transceivers # that will be controlled only by the placement of # jumpers on the CMX card. These functions are: # Receiver Failsafe and Master_Enable # # Receiver Failsafe # # These are jumpers that pull the FSEN1 and FSEN2 pins # down to ground. There is a separate jumper for each # group of transceivers, i.e. the front upper J10 and # the front lower j11 CTP Cable LVDS transceivers. # Normally we expect both of these jumpers to be installed # so that all both cables will have "Type 1" i.e. voltage # symmetric receivers. These 2 jumpers are reference # designators JMP8 and JMP9. JMP8 controlls the Upper # CTP connector J10. JMP9 controlls the Lower CTP # connector J11. # NET 'FRONT_UPPER_LVDS_FAILSAFE' JMP8-1 # Upper Cable Failsafe Jumper NET 'FRONT_LOWER_LVDS_FAILSAFE' JMP9-1 # Lower Cable Failsafe Jumper NET 'GROUND' JMP8-2 JMP9-2 # Pull-Down to Ground # Master Enable # # When Master Enable is voltage HI then the DS91M040 # LVDS Transceiver will power up and operate. We expect # to always have these transceivers powered up. These # jumpers will actually be given resistor reference # designators on the CMX card because we never expect # to remove or change them. These will be nominal 1k # Ohm resistors from the Master Enable pin to BULK_3V3. # There will be a separate jumper (resistor) for each # group of tranceivers that services a front panel # CTP cable connector, i.e. R184 enables the # transceivers for the upper CTP connector J10 and # R185 enables the transceivers for the lower CTP # connector J11. # NET 'FRONT_UPPER_LVDS_MASTER_ENB' R184-1 # Lower Cable Trncvr Master Enable NET 'FRONT_LOWER_LVDS_MASTER_ENB' R185-1 # Upper Cable Trncvr Master Enable NET 'BULK_3V3' R184-2 R185-2 # Pull-Up to 3.3 Volts # # CMX-0 Nets File # # Front-Panel CTP LVDS Power Ground Bypass Cap Nets # --====================--------------------------------- # # # Original Rev. 2-Nov-2012 # Most Recent Rev. 27-Nov-2012 # # # # This file holds the nets that connect power, ground, # and the bypass capacitors to the Front Panel CTP LVDS # transceiver and level translators chips. # # # Power and ByPass for U69 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U69-7 U69-18 # U69 3.3V Vccb power NET 'BULK_2V5' U69-31 U69-42 # U69 2.5V Vcca power NET 'GROUND' U69-4 U69-10 # U69 Ground connections NET 'GROUND' U69-15 U69-21 # U69 Ground connections NET 'GROUND' U69-28 U69-34 # U69 Ground connections NET 'GROUND' U69-39 U69-45 # U69 Ground connections NET 'BULK_3V3' C532-2 C533-2 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C531-1 C534-1 # ByPass Cap 2.5V Vcca power NET 'GROUND' C532-1 C533-1 # ByPass Cap Ground connections NET 'GROUND' C531-2 C534-2 # ByPass Cap Ground connections # Power and ByPass for U70 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U70-7 U70-18 # U70 3.3V Vccb power NET 'BULK_2V5' U70-31 U70-42 # U70 2.5V Vcca power NET 'GROUND' U70-4 U70-10 # U70 Ground connections NET 'GROUND' U70-15 U70-21 # U70 Ground connections NET 'GROUND' U70-28 U70-34 # U70 Ground connections NET 'GROUND' U70-39 U70-45 # U70 Ground connections NET 'BULK_3V3' C536-2 C537-2 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C535-1 C538-1 # ByPass Cap 2.5V Vcca power NET 'GROUND' C536-1 C537-1 # ByPass Cap Ground connections NET 'GROUND' C535-2 C538-2 # ByPass Cap Ground connections # Power and ByPass for U71 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U71-7 U71-18 # U71 3.3V Vccb power NET 'BULK_2V5' U71-31 U71-42 # U71 2.5V Vcca power NET 'GROUND' U71-4 U71-10 # U71 Ground connections NET 'GROUND' U71-15 U71-21 # U71 Ground connections NET 'GROUND' U71-28 U71-34 # U71 Ground connections NET 'GROUND' U71-39 U71-45 # U71 Ground connections NET 'BULK_3V3' C540-2 C541-2 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C539-1 C542-1 # ByPass Cap 2.5V Vcca power NET 'GROUND' C540-1 C541-1 # ByPass Cap Ground connections NET 'GROUND' C539-2 C542-2 # ByPass Cap Ground connections # Power and ByPass for U72 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U72-7 U72-18 # U72 3.3V Vccb power NET 'BULK_2V5' U72-31 U72-42 # U72 2.5V Vcca power NET 'GROUND' U72-4 U72-10 # U72 Ground connections NET 'GROUND' U72-15 U72-21 # U72 Ground connections NET 'GROUND' U72-28 U72-34 # U72 Ground connections NET 'GROUND' U72-39 U72-45 # U72 Ground connections NET 'BULK_3V3' C544-2 C545-2 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C543-1 C546-1 # ByPass Cap 2.5V Vcca power NET 'GROUND' C544-1 C545-1 # ByPass Cap Ground connections NET 'GROUND' C543-2 C546-2 # ByPass Cap Ground connections # Power and ByPass for U73 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U73-7 U73-18 # U73 3.3V Vccb power NET 'BULK_2V5' U73-31 U73-42 # U73 2.5V Vcca power NET 'GROUND' U73-4 U73-10 # U73 Ground connections NET 'GROUND' U73-15 U73-21 # U73 Ground connections NET 'GROUND' U73-28 U73-34 # U73 Ground connections NET 'GROUND' U73-39 U73-45 # U73 Ground connections NET 'BULK_3V3' C548-2 C549-2 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C547-1 C550-1 # ByPass Cap 2.5V Vcca power NET 'GROUND' C548-1 C549-1 # ByPass Cap Ground connections NET 'GROUND' C547-2 C550-2 # ByPass Cap Ground connections # Power and ByPass for U74 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U74-7 U74-18 # U74 3.3V Vccb power NET 'BULK_2V5' U74-31 U74-42 # U74 2.5V Vcca power NET 'GROUND' U74-4 U74-10 # U74 Ground connections NET 'GROUND' U74-15 U74-21 # U74 Ground connections NET 'GROUND' U74-28 U74-34 # U74 Ground connections NET 'GROUND' U74-39 U74-45 # U74 Ground connections NET 'BULK_3V3' C552-2 C553-2 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C551-1 C554-1 # ByPass Cap 2.5V Vcca power NET 'GROUND' C552-1 C553-1 # ByPass Cap Ground connections NET 'GROUND' C551-2 C554-2 # ByPass Cap Ground connections # Power and ByPass for U75 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U75-7 U75-18 # U75 3.3V Vccb power NET 'BULK_2V5' U75-31 U75-42 # U75 2.5V Vcca power NET 'GROUND' U75-4 U75-10 # U75 Ground connections NET 'GROUND' U75-15 U75-21 # U75 Ground connections NET 'GROUND' U75-28 U75-34 # U75 Ground connections NET 'GROUND' U75-39 U75-45 # U75 Ground connections NET 'BULK_3V3' C556-2 C557-2 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C555-1 C558-1 # ByPass Cap 2.5V Vcca power NET 'GROUND' C556-1 C557-1 # ByPass Cap Ground connections NET 'GROUND' C555-2 C558-2 # ByPass Cap Ground connections # Power and ByPass for U76 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U76-7 U76-18 # U76 3.3V Vccb power NET 'BULK_2V5' U76-31 U76-42 # U76 2.5V Vcca power NET 'GROUND' U76-4 U76-10 # U76 Ground connections NET 'GROUND' U76-15 U76-21 # U76 Ground connections NET 'GROUND' U76-28 U76-34 # U76 Ground connections NET 'GROUND' U76-39 U76-45 # U76 Ground connections NET 'BULK_3V3' C560-2 C561-2 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C559-1 C562-1 # ByPass Cap 2.5V Vcca power NET 'GROUND' C560-1 C561-1 # ByPass Cap Ground connections NET 'GROUND' C559-2 C562-2 # ByPass Cap Ground connections # Power and ByPass for U77 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U77-7 U77-18 # U77 3.3V Vccb power NET 'BULK_2V5' U77-31 U77-42 # U77 2.5V Vcca power NET 'GROUND' U77-4 U77-10 # U77 Ground connections NET 'GROUND' U77-15 U77-21 # U77 Ground connections NET 'GROUND' U77-28 U77-34 # U77 Ground connections NET 'GROUND' U77-39 U77-45 # U77 Ground connections NET 'BULK_3V3' C564-2 C565-2 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C563-1 C566-1 # ByPass Cap 2.5V Vcca power NET 'GROUND' C564-1 C565-1 # ByPass Cap Ground connections NET 'GROUND' C563-2 C566-2 # ByPass Cap Ground connections # Power and ByPass for U78 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U78-7 U78-18 # U77 3.3V Vccb power NET 'BULK_2V5' U78-31 U78-42 # U77 2.5V Vcca power NET 'GROUND' U78-4 U78-10 # U77 Ground connections NET 'GROUND' U78-15 U78-21 # U77 Ground connections NET 'GROUND' U78-28 U78-34 # U77 Ground connections NET 'GROUND' U78-39 U78-45 # U77 Ground connections NET 'BULK_3V3' C568-2 C569-2 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C567-1 C570-1 # ByPass Cap 2.5V Vcca power NET 'GROUND' C568-1 C569-1 # ByPass Cap Ground connections NET 'GROUND' C567-2 C570-2 # ByPass Cap Ground connections # # U51:U67 CTP LVDS DS91M040 Transceivers # # DS91M040 +3.3V Power Connections NET 'BULK_3V3' U51-11 U51-12 U51-29 U51-30 NET 'BULK_3V3' U52-11 U52-12 U52-29 U52-30 NET 'BULK_3V3' U53-11 U53-12 U53-29 U53-30 NET 'BULK_3V3' U54-11 U54-12 U54-29 U54-30 NET 'BULK_3V3' U55-11 U55-12 U55-29 U55-30 NET 'BULK_3V3' U56-11 U56-12 U56-29 U56-30 NET 'BULK_3V3' U57-11 U57-12 U57-29 U57-30 NET 'BULK_3V3' U58-11 U58-12 U58-29 U58-30 NET 'BULK_3V3' U59-11 U59-12 U59-29 U59-30 NET 'BULK_3V3' U60-11 U60-12 U60-29 U60-30 NET 'BULK_3V3' U61-11 U61-12 U61-29 U61-30 NET 'BULK_3V3' U62-11 U62-12 U62-29 U62-30 NET 'BULK_3V3' U63-11 U63-12 U63-29 U63-30 NET 'BULK_3V3' U64-11 U64-12 U64-29 U64-30 NET 'BULK_3V3' U65-11 U65-12 U65-29 U65-30 NET 'BULK_3V3' U66-11 U66-12 U66-29 U66-30 NET 'BULK_3V3' U67-11 U67-12 U67-29 U67-30 NET 'BULK_3V3' U68-11 U68-12 U68-29 U68-30 # U51:U67 CTP LVDS DS91M040 Transceivers # # DS91M040 GROUND Connections NET 'GROUND' U51-31 NET 'GROUND' U52-31 NET 'GROUND' U53-31 NET 'GROUND' U54-31 NET 'GROUND' U55-31 NET 'GROUND' U56-31 NET 'GROUND' U57-31 NET 'GROUND' U58-31 NET 'GROUND' U59-31 NET 'GROUND' U51-33 U51-34 U51-35 U51-36 NET 'GROUND' U52-33 U52-34 U52-35 U52-36 NET 'GROUND' U53-33 U53-34 U53-35 U53-36 NET 'GROUND' U54-33 U54-34 U54-35 U54-36 NET 'GROUND' U55-33 U55-34 U55-35 U55-36 NET 'GROUND' U56-33 U56-34 U56-35 U56-36 NET 'GROUND' U57-33 U57-34 U57-35 U57-36 NET 'GROUND' U58-33 U58-34 U58-35 U58-36 NET 'GROUND' U59-33 U59-34 U59-35 U59-36 NET 'GROUND' U60-31 NET 'GROUND' U61-31 NET 'GROUND' U62-31 NET 'GROUND' U63-31 NET 'GROUND' U64-31 NET 'GROUND' U65-31 NET 'GROUND' U66-31 NET 'GROUND' U67-31 NET 'GROUND' U68-31 NET 'GROUND' U60-33 U60-34 U60-35 U60-36 NET 'GROUND' U61-33 U61-34 U61-35 U61-36 NET 'GROUND' U62-33 U62-34 U62-35 U62-36 NET 'GROUND' U63-33 U63-34 U63-35 U63-36 NET 'GROUND' U64-33 U64-34 U64-35 U64-36 NET 'GROUND' U65-33 U65-34 U65-35 U65-36 NET 'GROUND' U66-33 U66-34 U66-35 U66-36 NET 'GROUND' U67-33 U67-34 U67-35 U67-36 NET 'GROUND' U68-33 U68-34 U68-35 U68-36 # # Bypass Capacitors C571:C578 on the # DS91M040 LVDS Transceivers U51:U67 # NET 'BULK_3V3' C571-1 C572-1 C573-1 # ByPass Cap on 3.3V power NET 'BULK_3V3' C574-1 C575-1 C576-1 # ByPass Cap on 3.3V power NET 'BULK_3V3' C577-1 C578-1 C579-1 # ByPass Cap on 3.3V power NET 'BULK_3V3' C580-1 C581-1 C582-1 # ByPass Cap on 3.3V power NET 'BULK_3V3' C583-1 C584-1 C585-1 # ByPass Cap on 3.3V power NET 'BULK_3V3' C586-1 C587-1 C588-1 # ByPass Cap on 3.3V power NET 'GROUND' C571-2 C572-2 C573-2 # and its Ground connection NET 'GROUND' C574-2 C575-2 C576-2 # and its Ground connection NET 'GROUND' C577-2 C578-2 C579-2 # and its Ground connection NET 'GROUND' C580-2 C581-2 C582-2 # and its Ground connection NET 'GROUND' C583-2 C584-2 C585-2 # and its Ground connection NET 'GROUND' C586-2 C587-2 C588-2 # and its Ground connection # # File created by Match_Resource_to_Pin V3.1 at Thu Oct 10 12:05:45 2013 # derived from input Netlist file <../Minipod_Assign/highspeed_receiver_1_minipod_n2r.txt> # and Resource to Pin dictionary <../Minipod_Resources/minipod_receiver_r2p.txt> # # # CMX Net-to-Resource File for highspeed Receiver 1 # --------------------------------------------------- # # # Original Rev. 1-Dec-2011 # Most Recent Rev. 3-Dec-2012 # NET 'HSOUT_R1_D9_N' MP3-H8 # DOUT_9_N NET 'HSOUT_R1_D9_P' MP3-J8 # DOUT_9_P NET 'HSOUT_R1_D10_N' MP3-D8 # DOUT_10_N NET 'HSOUT_R1_D10_P' MP3-D9 # DOUT_10_P NET 'HSOUT_R1_D8_N' MP3-B8 # DOUT_8_N NET 'HSOUT_R1_D8_P' MP3-A8 # DOUT_8_P NET 'HSOUT_R1_D11_N' MP3-F8 # DOUT_11_N NET 'HSOUT_R1_D11_P' MP3-F9 # DOUT_11_P NET 'HSOUT_R1_D7_N' MP3-H6 # DOUT_7_N NET 'HSOUT_R1_D7_P' MP3-J6 # DOUT_7_P NET 'HSOUT_R1_D6_N' MP3-B6 # DOUT_6_N NET 'HSOUT_R1_D6_P' MP3-A6 # DOUT_6_P NET 'HSOUT_R1_D3_N' MP3-H2 # DOUT_3_N NET 'HSOUT_R1_D3_P' MP3-J2 # DOUT_3_P NET 'HSOUT_R1_D5_N' MP3-H4 # DOUT_5_N NET 'HSOUT_R1_D5_P' MP3-J4 # DOUT_5_P NET 'HSOUT_R1_D2_N' MP3-B2 # DOUT_2_N NET 'HSOUT_R1_D2_P' MP3-A2 # DOUT_2_P NET 'HSOUT_R1_D4_N' MP3-B4 # DOUT_4_N NET 'HSOUT_R1_D4_P' MP3-A4 # DOUT_4_P NET 'HSOUT_R1_D1_N' MP3-F2 # DOUT_1_N NET 'HSOUT_R1_D1_P' MP3-F1 # DOUT_1_P NET 'HSOUT_R1_D0_N' MP3-D2 # DOUT_0_N NET 'HSOUT_R1_D0_P' MP3-D1 # DOUT_0_P # # File created by Match_Resource_to_Pin V3.1 at Thu Oct 10 12:05:45 2013 # derived from input Netlist file <../Minipod_Assign/highspeed_receiver_2_minipod_n2r.txt> # and Resource to Pin dictionary <../Minipod_Resources/minipod_receiver_r2p.txt> # # # CMX Net-to-Resource File for highspeed Receiver 2 # --------------------------------------------------- # # # Original Rev. 1-Dec-2011 # Most Recent Rev. 3-Dec-2012 # NET 'HSOUT_R2_D9_N' MP4-H8 # DOUT_9_N NET 'HSOUT_R2_D9_P' MP4-J8 # DOUT_9_P NET 'HSOUT_R2_D10_N' MP4-D8 # DOUT_10_N NET 'HSOUT_R2_D10_P' MP4-D9 # DOUT_10_P NET 'HSOUT_R2_D8_N' MP4-B8 # DOUT_8_N NET 'HSOUT_R2_D8_P' MP4-A8 # DOUT_8_P NET 'HSOUT_R2_D11_N' MP4-F8 # DOUT_11_N NET 'HSOUT_R2_D11_P' MP4-F9 # DOUT_11_P NET 'HSOUT_R2_D7_N' MP4-H6 # DOUT_7_N NET 'HSOUT_R2_D7_P' MP4-J6 # DOUT_7_P NET 'HSOUT_R2_D6_N' MP4-B6 # DOUT_6_N NET 'HSOUT_R2_D6_P' MP4-A6 # DOUT_6_P NET 'HSOUT_R2_D3_N' MP4-H2 # DOUT_3_N NET 'HSOUT_R2_D3_P' MP4-J2 # DOUT_3_P NET 'HSOUT_R2_D5_N' MP4-H4 # DOUT_5_N NET 'HSOUT_R2_D5_P' MP4-J4 # DOUT_5_P NET 'HSOUT_R2_D2_N' MP4-B2 # DOUT_2_N NET 'HSOUT_R2_D2_P' MP4-A2 # DOUT_2_P NET 'HSOUT_R2_D4_N' MP4-B4 # DOUT_4_N NET 'HSOUT_R2_D4_P' MP4-A4 # DOUT_4_P NET 'HSOUT_R2_D1_N' MP4-F2 # DOUT_1_N NET 'HSOUT_R2_D1_P' MP4-F1 # DOUT_1_P NET 'HSOUT_R2_D0_N' MP4-D2 # DOUT_0_N NET 'HSOUT_R2_D0_P' MP4-D1 # DOUT_0_P # # File created by Match_Resource_to_Pin V3.1 at Thu Oct 10 12:05:46 2013 # derived from input Netlist file <../Minipod_Assign/highspeed_receiver_3_minipod_n2r.txt> # and Resource to Pin dictionary <../Minipod_Resources/minipod_receiver_r2p.txt> # # # CMX Net-to-Resource File for highspeed Receiver 3 # --------------------------------------------------- # # # Original Rev. 1-Dec-2011 # Most Recent Rev. 3-Dec-2012 # NET 'HSOUT_R3_D9_N' MP5-H8 # DOUT_9_N NET 'HSOUT_R3_D9_P' MP5-J8 # DOUT_9_P NET 'HSOUT_R3_D10_N' MP5-D8 # DOUT_10_N NET 'HSOUT_R3_D10_P' MP5-D9 # DOUT_10_P NET 'HSOUT_R3_D8_N' MP5-B8 # DOUT_8_N NET 'HSOUT_R3_D8_P' MP5-A8 # DOUT_8_P NET 'HSOUT_R3_D11_N' MP5-F8 # DOUT_11_N NET 'HSOUT_R3_D11_P' MP5-F9 # DOUT_11_P NET 'HSOUT_R3_D7_N' MP5-H6 # DOUT_7_N NET 'HSOUT_R3_D7_P' MP5-J6 # DOUT_7_P NET 'HSOUT_R3_D6_N' MP5-B6 # DOUT_6_N NET 'HSOUT_R3_D6_P' MP5-A6 # DOUT_6_P NET 'HSOUT_R3_D3_N' MP5-H2 # DOUT_3_N NET 'HSOUT_R3_D3_P' MP5-J2 # DOUT_3_P NET 'HSOUT_R3_D5_N' MP5-H4 # DOUT_5_N NET 'HSOUT_R3_D5_P' MP5-J4 # DOUT_5_P NET 'HSOUT_R3_D2_N' MP5-B2 # DOUT_2_N NET 'HSOUT_R3_D2_P' MP5-A2 # DOUT_2_P NET 'HSOUT_R3_D4_N' MP5-B4 # DOUT_4_N NET 'HSOUT_R3_D4_P' MP5-A4 # DOUT_4_P NET 'HSOUT_R3_D1_N' MP5-F2 # DOUT_1_N NET 'HSOUT_R3_D1_P' MP5-F1 # DOUT_1_P NET 'HSOUT_R3_D0_N' MP5-D2 # DOUT_0_N NET 'HSOUT_R3_D0_P' MP5-D1 # DOUT_0_P # # File created by Match_Resource_to_Pin V3.1 at Thu Oct 10 12:05:44 2013 # derived from input Netlist file <../Minipod_Assign/highspeed_transmitter_1_minipod_n2r.txt> # and Resource to Pin dictionary <../Minipod_Resources/minipod_transmitter_r2p.txt> # # # CMX Net-to-Resource File for highspeed Transmitter 1 # ------------------------------------------------------ # # # Original Rev. 1-Dec-2011 # Most Recent Rev. 2-Oct-2013 # # # Transmitter 1 is MiniPOD device MP1 # # Note: To facilitate routing there is a criss-cross in the # Direct and Complement signals to the following # channels in Transmitter MiniPOD #1, i.e. MP1: # # F00, F01, F02, F03, F04, F05, F06, F07, F08, F09, F10, F11 # NET 'MP1_F00_QUAD_112_TRN_3_DIR' MP1-D2 # DIN_0_N NET 'MP1_F00_QUAD_112_TRN_3_CMP' MP1-D1 # DIN_0_P NET 'MP1_F01_QUAD_110_TRN_0_DIR' MP1-F2 # DIN_1_N NET 'MP1_F01_QUAD_110_TRN_0_CMP' MP1-F1 # DIN_1_P NET 'MP1_F02_QUAD_112_TRN_2_DIR' MP1-B2 # DIN_2_N NET 'MP1_F02_QUAD_112_TRN_2_CMP' MP1-A2 # DIN_2_P NET 'MP1_F03_QUAD_110_TRN_1_DIR' MP1-H2 # DIN_3_N NET 'MP1_F03_QUAD_110_TRN_1_CMP' MP1-J2 # DIN_3_P NET 'MP1_F04_QUAD_112_TRN_0_DIR' MP1-B4 # DIN_4_N NET 'MP1_F04_QUAD_112_TRN_0_CMP' MP1-A4 # DIN_4_P NET 'MP1_F05_QUAD_110_TRN_3_DIR' MP1-H4 # DIN_5_N NET 'MP1_F05_QUAD_110_TRN_3_CMP' MP1-J4 # DIN_5_P NET 'MP1_F06_QUAD_112_TRN_1_DIR' MP1-B6 # DIN_6_N NET 'MP1_F06_QUAD_112_TRN_1_CMP' MP1-A6 # DIN_6_P NET 'MP1_F07_QUAD_110_TRN_2_DIR' MP1-H6 # DIN_7_N NET 'MP1_F07_QUAD_110_TRN_2_CMP' MP1-J6 # DIN_7_P NET 'MP1_F08_QUAD_111_TRN_3_DIR' MP1-B8 # DIN_8_N NET 'MP1_F08_QUAD_111_TRN_3_CMP' MP1-A8 # DIN_8_P NET 'MP1_F09_QUAD_111_TRN_0_DIR' MP1-H8 # DIN_9_N NET 'MP1_F09_QUAD_111_TRN_0_CMP' MP1-J8 # DIN_9_P NET 'MP1_F10_QUAD_111_TRN_2_DIR' MP1-D8 # DIN_10_N NET 'MP1_F10_QUAD_111_TRN_2_CMP' MP1-D9 # DIN_10_P NET 'MP1_F11_QUAD_111_TRN_1_DIR' MP1-F8 # DIN_11_N NET 'MP1_F11_QUAD_111_TRN_1_CMP' MP1-F9 # DIN_11_P # # File created by Match_Resource_to_Pin V3.1 at Thu Oct 10 12:05:45 2013 # derived from input Netlist file <../Minipod_Assign/highspeed_transmitter_2_minipod_n2r.txt> # and Resource to Pin dictionary <../Minipod_Resources/minipod_transmitter_r2p.txt> # # # CMX Net-to-Resource File for highspeed Transmitter 2 # ------------------------------------------------------ # # # Original Rev. 1-Dec-2011 # Most Recent Rev. 1-Oct-2013 # # # Transmitter 2 is MiniPOD device MP2 # # Note: To facilitate routing there is a criss-cross in the # Direct and Complement signals to the following # channels in Transmitter MiniPOD #2, i.e. MP2: # # F00, F01, F02, F03, F04, F05, F06, F07, F10, F11 # NET 'MP2_F00_QUAD_115_TRN_3_DIR' MP2-D2 # DIN_0_N NET 'MP2_F00_QUAD_115_TRN_3_CMP' MP2-D1 # DIN_0_P NET 'MP2_F01_QUAD_113_TRN_0_DIR' MP2-F2 # DIN_1_N NET 'MP2_F01_QUAD_113_TRN_0_CMP' MP2-F1 # DIN_1_P NET 'MP2_F02_QUAD_115_TRN_2_DIR' MP2-B2 # DIN_2_N NET 'MP2_F02_QUAD_115_TRN_2_CMP' MP2-A2 # DIN_2_P NET 'MP2_F03_QUAD_113_TRN_1_DIR' MP2-H2 # DIN_3_N NET 'MP2_F03_QUAD_113_TRN_1_CMP' MP2-J2 # DIN_3_P NET 'MP2_F04_QUAD_115_TRN_0_DIR' MP2-B4 # DIN_4_N NET 'MP2_F04_QUAD_115_TRN_0_CMP' MP2-A4 # DIN_4_P NET 'MP2_F05_QUAD_113_TRN_3_DIR' MP2-H4 # DIN_5_N NET 'MP2_F05_QUAD_113_TRN_3_CMP' MP2-J4 # DIN_5_P NET 'MP2_F06_QUAD_115_TRN_1_DIR' MP2-B6 # DIN_6_N NET 'MP2_F06_QUAD_115_TRN_1_CMP' MP2-A6 # DIN_6_P NET 'MP2_F07_QUAD_113_TRN_2_DIR' MP2-H6 # DIN_7_N NET 'MP2_F07_QUAD_113_TRN_2_CMP' MP2-J6 # DIN_7_P NET 'MP2_F08_QUAD_114_TRN_3_DIR' MP2-A8 # DIN_8_P NET 'MP2_F08_QUAD_114_TRN_3_CMP' MP2-B8 # DIN_8_N NET 'MP2_F09_QUAD_114_TRN_0_DIR' MP2-J8 # DIN_9_P NET 'MP2_F09_QUAD_114_TRN_0_CMP' MP2-H8 # DIN_9_N NET 'MP2_F10_QUAD_114_TRN_2_DIR' MP2-D8 # DIN_10_N NET 'MP2_F10_QUAD_114_TRN_2_CMP' MP2-D9 # DIN_10_P NET 'MP2_F11_QUAD_114_TRN_1_DIR' MP2-F8 # DIN_11_N NET 'MP2_F11_QUAD_114_TRN_1_CMP' MP2-F9 # DIN_11_P # # File created by Match_Resource_to_Pin V3.1 at Thu Oct 10 12:05:43 2013 # derived from input Netlist file # and Resource to Pin dictionary # ############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for the 400 Backplane Processor Inputs # -=============------------------------------------------------------------- # # # Original Rev. 26-Sep-2011 as separate PN files # Rev. 3-Nov-2011 merged and ordered into one file # Rev. 21-May-2012 rework assignment using paper and pencil # Rev. 22-Jun-2012 move P08-P11 and P12-P15 to inner column # and reroute all while preserving all VREF and # one set of VRP/VRN per group of 3 IO banks. # Rev. 25-Jun-2012 move P00-P03 from IO banks 36-37-38 to 35-36-37, # move P4, P5, P6 clocks to remain at 2 clocks per H-row # (and fix IO bank used for P5_21, P5_22, P7_00, P7_01) # Rev. 27-Jun-2012 fix typo from P12_17 BA29 # to P12_17 BA20 # Rev. 29-Jun-2012 allow a few traces on top layer for P08-P11 group (banks 21-23) # in order to only use 10 layers (top+9) # Rev. 10-Jul-2012 fix problem: a VREF signal had been assigned to P12_13 # Rev. 12-Jul-2012 expunge information about "rank" # Rev. 20-Aug-2012 Assignment redone with corrected backplane pin order # Rev. 29-Aug-2012 switch P08-P11 to 11 layers, fixed P04-P07 template error # Rev. 07-Sep-2012 cosmetic changes to header comments # Rev. 12-Nov-2012 Complete re-think with a ring of vias and only 8 internal trace layers # Rev. 19-Nov-2012 Free up 4x SysMonit pairs on Bank 35 and 1x Global Clock pair on Bank 34 # Rev. 28-Nov-2012 cross-check assignments and add via row and number # Rev: 11-Dec-2012 Cosmetic changes for uniformity and consistency between Base and TP files # Rev: 24-Jan-2013 Bug fix: Move P12_17 to bank 33 (was in 34) by swapping with P15_20 # Rev: 28-Mar-2013 Move seven P14 and P15 signals to free the second Global Clock from Bank 34 # Rev: 08-May-2013 Swap location of P8_0:2 to match the newly displaced vias # Rev: 17-May-2013 Rearrange P14_1,2,6:9 to solve layer 4 boundary conflict (P08:11 vs P12:14), # swap P9_17 & _19 to better spread traces among via channels on layer 4 # and rearrange P12_18:21 to solve layer 9 boundary conflict (P08:11 vs P12:14) # which also involved putting pin AV23 into use and dropping AY24 # Most Recent Rev: 22-May-2013 Rearrange P6_8,9,10 to ease layer 3 trace density # # Here we assign Base FPGA resources for the 400x Px_y backplane signals, # with x=0:15 corresponding to the relative source processor module (JEM or CPM) in the crate, # and y=0:24 corresponding to the signal index number from that processor source. # Each Px_24 signal carries the clock/parity signal from a given source processor board. # All Px_24 signals must be connected to a single ended regional clock resource pin # (i.e. a signal named IO_L9P_MRCC_nn or IO_L10P_MRCC_nn, nn being the IO block number) # # Note: Trace layer information is appended as comments below. # ----- # # The Match Resource To Pin program will preserve this comment field, and append additional info. # # NET 'P0_7' U1- #> F07 R1V3 #> T04 J1-A18 P00_07 D13 # # ^ ^ ^ ^ ^ ^ ^ ^ # | | | | | | | | # Virtex 6 Resource name --------+ | | | | | | | # for Match_res2pin translation | | | | | | | # | | | | | | | # Tailored comment flag to help with string searches + | | | | | | # | | | | | | # Target Trace Layer number to use for this net --------+ | | | | | # as it exits the FPGA (to a near via or the backplane) | | | | | # F01 is top layer, F02 the first inner layer, etc | | | | | # | | | | | # When applicable: Via row (R1 is top row on sheet) --------+ | | | | # and via number (V1 is leftmost) as determined in paper study | | | | # | | | | # Target Trace Layer number to use for this net --------------------+ | | | # as it attaches to the backplane connector. | | | # T01 is top layer, T02 the first inner layer, etc | | | # | | | # Backplane Connector and Pin Number -----------------------------------+ | | # | | # Net Name repeated to help manual entry of Pin Number ---------------------------+ | # | # Target Pin Number read from paper drawing ---------------------------------------------+ # and cross-checked after Match_Res2Pin # ############################################################################################ ######################################################################################### # # The Processor Inputs in P0-P1-P2-P3 use IO resources from banks 35-36-37 # P0_24 uses a regional clock in IO bank 35 on trace layer 9 # P1_24 uses a regional clock in IO bank 35 on trace layer 9 # P2_24 uses a regional clock in IO bank 37 on trace layer 4 # P3_24 uses a regional clock in IO bank 36 on trace layer 9 # The DCI master for this group is IO bank 36 # NET 'P0_0' U1-L11 #> F02 #> T02 J1-A11 P00_00 L11 IO_L16N_VRP_35 NET 'P0_1' U1-M12 #> F02 #> T02 J1-A12 P00_01 M12 IO_L18N_GC_35 NET 'P0_2' U1-N13 #> F02 #> T02 J1-A13 P00_02 N13 IO_L10N_MRCC_35 NET 'P0_3' U1-N14 #> F02 #> T02 J1-A14 P00_03 N14 IO_L9N_MRCC_35 NET 'P0_4' U1-C14 #> F02 #> T02 J1-A15 P00_04 C14 IO_L13N_SM6N_35 NET 'P0_5' U1-L12 #> F04 #> T04 J1-A16 P00_05 L12 IO_L18P_GC_35 NET 'P0_6' U1-J13 #> F04 #> T04 J1-A17 P00_06 J13 IO_L12P_SM5P_35 NET 'P0_7' U1-D13 #> F07 R1V3 #> T04 J1-A18 P00_07 D13 IO_L17P_35 NET 'P0_8' U1-E12 #> F07 R1V1 #> T04 J1-A19 P00_08 E12 IO_L0N_35 NET 'P0_9' U1-H14 #> F04 #> T04 J2-A1 P00_09 H14 IO_L4P_35 NET 'P0_10' U1-F14 #> F04 #> T04 J2-A2 P00_10 F14 IO_L19N_GC_35 NET 'P0_11' U1-D17 #> F06 R2V3 #> T04 J2-A3 P00_11 D17 IO_L19P_36 NET 'P0_12' U1-B16 #> F01 R2V4 #> T04 J2-A4 P00_12 B16 IO_L1N_35 NET 'P0_13' U1-F15 #> F07 R2V1 #> T04 J2-A5 P00_13 F15 IO_L11N_SRCC_35 NET 'P0_14' U1-J16 #> F04 #> T04 J2-A6 P00_14 J16 IO_L4P_36 NET 'P0_15' U1-J17 #> F04 #> T04 J2-A7 P00_15 J17 IO_L6N_36 NET 'P0_16' U1-K18 #> F04 #> T04 J2-A8 P00_16 K18 IO_L0P_36 NET 'P0_17' U1-B18 #> F01 R3V6 #> T04 J2-A9 P00_17 B18 IO_L15P_36 NET 'P0_18' U1-E18 #> F07 R3V3 #> T04 J2-A10 P00_18 E18 IO_L5N_36 NET 'P0_19' U1-G18 #> F07 R3V1 #> T04 J2-A11 P00_19 G18 IO_L1N_36 NET 'P0_20' U1-J18 #> F04 #> T04 J2-A12 P00_20 J18 IO_L0N_36 NET 'P0_21' U1-F19 #> F04 #> T04 J2-A13 P00_21 F19 IO_L3N_36 NET 'P0_22' U1-E17 #> F09 R4V4 #> T04 J2-A14 P00_22 E17 IO_L19N_36 NET 'P0_23' U1-P18 #> F09 R4V2 #> T04 J2-A15 P00_23 P18 IO_L9P_MRCC_36 NET 'P0_24' U1-M13 #> F09 #> T09 J2-A16 P00_24 M13 IO_L10P_MRCC_35 NET 'P1_0' U1-K14 #> F03 #> T03 J1-B15 P01_00 K14 IO_L14P_35 NET 'P1_1' U1-J11 #> F09 #> T09 J1-C16 P01_01 J11 IO_L8N_SRCC_35 NET 'P1_2' U1-J12 #> F09 #> T09 J1-B17 P01_02 J12 IO_L8P_SRCC_35 NET 'P1_3' U1-F12 #> F09 #> T09 J1-C18 P01_03 F12 IO_L0P_35 NET 'P1_4' U1-B14 #> F01 R1V2 #> T05 J1-B19 P01_04 B14 IO_L13P_SM6P_35 NET 'P1_5' U1-A14 #> F01 R1V4 #> T05 J2-C1 P01_05 A14 IO_L5N_SM2N_35 NET 'P1_6' U1-K13 #> F03 R1V8 #> T05 J2-B2 P01_06 K13 IO_L12N_SM5N_35 NET 'P1_7' U1-K12 #> F05 #> T05 J2-C3 P01_07 K12 IO_L16P_VRN_35 NET 'P1_8' U1-E13 #> F05 #> T05 J2-B4 P01_08 E13 IO_L17N_35 NET 'P1_9' U1-G14 #> F05 #> T05 J2-C5 P01_09 G14 IO_L2N_SM0N_35 NET 'P1_10' U1-J15 #> F05 #> T05 J2-B6 P01_10 J15 IO_L14P_36 NET 'P1_11' U1-A16 #> F01 R2V5 #> T05 J2-C7 P01_11 A16 IO_L1P_35 NET 'P1_12' U1-A15 #> F01 R2V7 #> T05 J2-B8 P01_12 A15 IO_L5P_SM2P_35 NET 'P1_13' U1-E14 #> F07 R2V2 #> T05 J2-C9 P01_13 E14 IO_L19P_GC_35 NET 'P1_14' U1-G16 #> F05 #> T05 J2-B10 P01_14 G16 IO_L2P_36 NET 'P1_15' U1-G17 #> F05 #> T05 J2-C11 P01_15 G17 IO_L11N_SRCC_36 NET 'P1_16' U1-D18 #> F06 R3V5 #> T05 J2-B12 P01_16 D18 IO_L13P_36 NET 'P1_17' U1-H15 #> F09 R3V7 #> T05 J2-C13 P01_17 H15 IO_L2P_SM0P_35 NET 'P1_18' U1-E15 #> F07 R3V4 #> T05 J2-B14 P01_18 E15 IO_L11P_SRCC_35 NET 'P1_19' U1-F16 #> F07 R3V2 #> T05 J2-C15 P01_19 F16 IO_L2N_36 NET 'P1_20' U1-F17 #> F05 #> T05 J2-B16 P01_20 F17 IO_L11P_SRCC_36 NET 'P1_21' U1-H18 #> F05 #> T05 J2-B17 P01_21 H18 IO_L1P_36 NET 'P1_22' U1-A19 #> F01 R4V6 #> T05 J2-B18 P01_22 A19 IO_L15N_36 NET 'P1_23' U1-E19 #> F05 #> T05 J2-C19 P01_23 E19 IO_L5P_36 NET 'P1_24' U1-M14 #> F09 #> T09 J3-B1 P01_24 M14 IO_L9P_MRCC_35 NET 'P2_0' U1-L15 #> F03 #> T03 J1-D15 P02_00 L15 IO_L16N_36 NET 'P2_1' U1-L16 #> F03 #> T03 J1-D16 P02_01 L16 IO_L16P_36 NET 'P2_2' U1-B17 #> F01 R2V6 #> T03 J1-C17 P02_02 B17 IO_L17N_36 NET 'P2_3' U1-K17 #> F03 #> T03 J1-D18 P02_03 K17 IO_L6P_36 NET 'P2_4' U1-M18 #> F03 #> T03 J1-C19 P02_04 M18 IO_L8P_SRCC_36 NET 'P2_5' U1-K19 #> F03 #> T03 J2-D1 P02_05 K19 IO_L18P_37 NET 'P2_6' U1-G19 #> F03 #> T03 J2-C2 P02_06 G19 IO_L3P_36 NET 'P2_7' U1-F20 #> F03 #> T03 J2-D3 P02_07 F20 IO_L12N_VRP_37 NET 'P2_8' U1-G21 #> F03 #> T03 J2-C4 P02_08 G21 IO_L8N_SRCC_37 NET 'P2_9' U1-C20 #> F09 R4V1 #> T03 J2-D5 P02_09 C20 IO_L19P_37 NET 'P2_10' U1-A20 #> F01 R4V3 #> T03 J2-C6 P02_10 A20 IO_L15N_37 NET 'P2_11' U1-C21 #> F01 R4V5 #> T03 J2-D7 P02_11 C21 IO_L17P_37 NET 'P2_12' U1-H21 #> F03 #> T03 J2-C8 P02_12 H21 IO_L6P_37 NET 'P2_13' U1-G22 #> F03 #> T03 J2-D9 P02_13 G22 IO_L2P_37 NET 'P2_14' U1-E23 #> F03 #> T03 J2-C10 P02_14 E23 IO_L7N_37 NET 'P2_15' U1-B22 #> F01 R5V2 #> T03 J2-D11 P02_15 B22 IO_L5N_37 NET 'P2_16' U1-B24 #> F01 R5V5 #> T03 J2-C12 P02_16 B24 IO_L1P_37 NET 'P2_17' U1-A24 #> F01 R5V3 #> T03 J2-D13 P02_17 A24 IO_L1N_37 NET 'P2_18' U1-B23 #> F01 R5V1 #> T03 J2-C14 P02_18 B23 IO_L5P_37 NET 'P2_19' U1-D23 #> F03 #> T03 J2-D15 P02_19 D23 IO_L11P_SRCC_37 NET 'P2_20' U1-E20 #> F04 #> T04 J2-C16 P02_20 E20 IO_L12P_VRN_37 NET 'P2_21' U1-F21 #> F04 #> T04 J2-D17 P02_21 F21 IO_L4P_37 NET 'P2_22' U1-F22 #> F04 #> T04 J2-C18 P02_22 F22 IO_L2N_37 NET 'P2_23' U1-D22 #> F04 #> T04 J2-D19 P02_23 D22 IO_L11N_SRCC_37 NET 'P2_24' U1-J22 #> F04 #> T04 J3-C1 P02_24 J22 IO_L10P_MRCC_37 NET 'P3_0' U1-N15 #> F02 #> T02 J1-E15 P03_00 N15 IO_L18N_36 NET 'P3_1' U1-A17 #> F01 R2V8 #> T02 J1-E16 P03_01 A17 IO_L17P_36 NET 'P3_2' U1-M16 #> F02 #> T02 J1-E17 P03_02 M16 IO_L18P_36 NET 'P3_3' U1-P17 #> F02 #> T02 J1-E18 P03_03 P17 IO_L9N_MRCC_36 NET 'P3_4' U1-N18 #> F02 #> T02 J1-E19 P03_04 N18 IO_L8N_SRCC_36 NET 'P3_5' U1-C18 #> F02 #> T02 J2-E1 P03_05 C18 IO_L13N_36 NET 'P3_6' U1-L19 #> F02 #> T02 J2-E2 P03_06 L19 IO_L18N_37 NET 'P3_7' U1-B19 #> F01 R3V8 #> T02 J2-E3 P03_07 B19 IO_L7N_36 NET 'P3_8' U1-C19 #> F02 #> T02 J2-E4 P03_08 C19 IO_L7P_36 NET 'P3_9' U1-H20 #> F02 #> T02 J2-E5 P03_09 H20 IO_L8P_SRCC_37 NET 'P3_10' U1-J20 #> F02 #> T02 J2-E6 P03_10 J20 IO_L14P_37 NET 'P3_11' U1-D21 #> F02 #> T02 J2-E7 P03_11 D21 IO_L17N_37 NET 'P3_12' U1-J21 #> F02 #> T02 J2-E8 P03_12 J21 IO_L6N_37 NET 'P3_13' U1-A21 #> F01 R4V8 #> T02 J2-E9 P03_13 A21 IO_L13N_37 NET 'P3_14' U1-L22 #> F02 #> T02 J2-E10 P03_14 L22 IO_L9P_MRCC_37 NET 'P3_15' U1-K22 #> F02 #> T02 J2-E11 P03_15 K22 IO_L10N_MRCC_37 NET 'P3_16' U1-G23 #> F02 #> T02 J2-E12 P03_16 G23 IO_L0P_37 NET 'P3_17' U1-C23 #> F02 #> T02 J2-E13 P03_17 C23 IO_L3N_37 NET 'P3_18' U1-A22 #> F01 R5V4 #> T02 J2-E14 P03_18 A22 IO_L13P_37 NET 'P3_19' U1-B21 #> F01 R5V8 #> T02 J2-E15 P03_19 B21 IO_L15P_37 NET 'P3_20' U1-H23 #> F02 #> T02 J2-E16 P03_20 H23 IO_L0N_37 NET 'P3_21' U1-C24 #> F02 #> T02 J2-E17 P03_21 C24 IO_L3P_37 NET 'P3_22' U1-E24 #> F02 #> T02 J2-E18 P03_22 E24 IO_L7P_37 NET 'P3_23' U1-D20 #> F05 #> T05 J2-E19 P03_23 D20 IO_L19N_37 NET 'P3_24' U1-N16 #> F09 #> T09 J3-E1 P03_24 N16 IO_L10P_MRCC_36 NET 'P0TO3_DCI_P' U1-M17 #> T08 M17 IO_L12N_VRP_36 NET 'P0TO3_DCI_N' U1-L17 #> T08 L17 IO_L12P_VRN_36 NET 'VREF_P' U1-G13 #> T08 G13 IO_L4N_VREF_35 NET 'VREF_P' U1-L14 #> T08 L14 IO_L14N_VREF_35 NET 'VREF_P' U1-H16 #> T08 H16 IO_L4N_VREF_36 NET 'VREF_P' U1-K15 #> T08 K15 IO_L14N_VREF_36 NET 'VREF_P' U1-E22 #> T08 E22 IO_L4N_VREF_37 NET 'VREF_P' U1-H19 #> T08 H19 IO_L14N_VREF_37 ######################################################################################### # # The Processor Inputs in P4-P5-P6-P7 use IO resources from banks 26-27-28 # P4_24 uses a regional clock in IO bank 28 on trace layer 9 # P5_24 uses a regional clock in IO bank 28 on trace layer 9 # P6_24 uses a regional clock in IO bank 26 on trace layer 5 # P7_24 uses a regional clock in IO bank 27 on trace layer 9 # The DCI master for this group is IO bank 28 # NET 'P4_0' U1-N25 #> F02 #> T02 J3-A1 P04_00 N25 IO_L10N_MRCC_28 NET 'P4_1' U1-M26 #> F02 #> T02 J3-A2 P04_01 M26 IO_L19P_28 NET 'P4_2' U1-L27 #> F02 #> T02 J3-A3 P04_02 L27 IO_L18P_28 NET 'P4_3' U1-H28 #> F02 #> T02 J3-A4 P04_03 H28 IO_L14P_28 NET 'P4_4' U1-C29 #> F02 #> T02 J3-A5 P04_04 C29 IO_L15N_28 NET 'P4_5' U1-M29 #> F02 #> T02 J3-A6 P04_05 M29 IO_L10N_MRCC_27 NET 'P4_6' U1-E30 #> F02 #> T02 J3-A7 P04_06 E30 IO_L3P_28 NET 'P4_7' U1-C31 #> F02 #> T02 J3-A8 P04_07 C31 IO_L5P_28 NET 'P4_8' U1-H31 #> F02 #> T02 J3-A9 P04_08 H31 IO_L6P_27 NET 'P4_9' U1-G32 #> F02 #> T02 J3-A10 P04_09 G32 IO_L8N_SRCC_27 NET 'P4_10' U1-C33 #> F02 #> T02 J3-A11 P04_10 C33 IO_L3N_27 NET 'P4_11' U1-H33 #> F02 #> T02 J3-A12 P04_11 H33 IO_L12P_VRN_27 NET 'P4_12' U1-L25 #> F03 R1V2 #> T05 J3-A13 P04_12 L25 IO_L9N_MRCC_28 NET 'P4_13' U1-J26 #> F03 R1V4 #> T05 J3-A14 P04_13 J26 IO_L0N_28 NET 'P4_14' U1-A30 #> F01 R1V5 #> T05 J3-A15 P04_14 A30 IO_L17N_28 NET 'P4_15' U1-B29 #> F01 R1V3 #> T05 J3-A16 P04_15 B29 IO_L15P_28 NET 'P4_16' U1-A29 #> F01 R1V1 #> T05 J3-A17 P04_16 A29 IO_L17P_28 NET 'P4_17' U1-F27 #> F05 #> T05 J3-A18 P04_17 F27 IO_L11P_SRCC_28 NET 'P4_18' U1-D28 #> F05 #> T05 J3-A19 P04_18 D28 IO_L1P_28 NET 'P4_19' U1-E29 #> F05 #> T05 J4-A1 P04_19 E29 IO_L1N_28 NET 'P4_20' U1-C30 #> F05 #> T05 J4-A2 P04_20 C30 IO_L7P_28 NET 'P4_21' U1-D31 #> F05 #> T05 J4-A3 P04_21 D31 IO_L5N_28 NET 'P4_22' U1-D32 #> F05 #> T05 J4-A4 P04_22 D32 IO_L0N_27 NET 'P4_23' U1-D33 #> F05 #> T05 J4-A5 P04_23 D33 IO_L11P_SRCC_27 NET 'P4_24' U1-N24 #> F09 #> T09 J4-A6 P04_24 N24 IO_L10P_MRCC_28 NET 'P5_0' U1-G28 #> F03 #> T03 J3-C2 P05_00 G28 IO_L2P_28 NET 'P5_1' U1-P23 #> F04 #> T04 J3-B3 P05_01 P23 IO_L6N_28 NET 'P5_2' U1-R23 #> F04 #> T04 J3-C4 P05_02 R23 IO_L6P_28 NET 'P5_3' U1-P25 #> F04 #> T04 J3-B5 P05_03 P25 IO_L8N_SRCC_28 NET 'P5_4' U1-A31 #> F01 R1V8 #> T04 J3-C6 P05_04 A31 IO_L13P_28 NET 'P5_5' U1-K27 #> F03 R1V6 #> T04 J3-B7 P05_05 K27 IO_L18N_28 NET 'P5_6' U1-J27 #> F04 #> T04 J3-C8 P05_06 J27 IO_L0P_28 NET 'P5_7' U1-G27 #> F04 #> T04 J3-B9 P05_07 G27 IO_L2N_28 NET 'P5_8' U1-E28 #> F04 #> T04 J3-C10 P05_08 E28 IO_L11N_SRCC_28 NET 'P5_9' U1-B31 #> F01 R2V7 #> T04 J3-B11 P05_09 B31 IO_L13N_28 NET 'P5_10' U1-F32 #> F03 R2V8 #> T04 J3-C12 P05_10 F32 IO_L2P_27 NET 'P5_11' U1-G31 #> F03 R2V6 #> T04 J3-B13 P05_11 G31 IO_L6N_27 NET 'P5_12' U1-G29 #> F04 #> T04 J3-C14 P05_12 G29 IO_L4P_28 NET 'P5_13' U1-D30 #> F04 #> T04 J3-B15 P05_13 D30 IO_L7N_28 NET 'P5_14' U1-F31 #> F04 #> T04 J3-C16 P05_14 F31 IO_L2N_27 NET 'P5_15' U1-A36 #> F01 R3V7 #> T04 J3-B17 P05_15 A36 IO_L13P_27 NET 'P5_16' U1-B36 #> F01 R3V8 #> T04 J3-C18 P05_16 B36 IO_L13N_27 NET 'P5_17' U1-A35 #> F01 R3V6 #> T04 J3-B19 P05_17 A35 IO_L5N_27 NET 'P5_18' U1-E32 #> F04 #> T04 J4-C1 P05_18 E32 IO_L0P_27 NET 'P5_19' U1-E33 #> F04 #> T04 J4-B2 P05_19 E33 IO_L11N_SRCC_27 NET 'P5_20' U1-E34 #> F04 #> T04 J4-C3 P05_20 E34 IO_L17P_27 NET 'P5_21' U1-E35 #> F04 #> T04 J4-B4 P05_21 E35 IO_L4P_27 NET 'P5_22' U1-D36 #> F04 #> T04 J4-C5 P05_22 D36 IO_L19P_27 NET 'P5_23' U1-D37 #> F04 #> T04 J4-B6 P05_23 D37 IO_L19N_27 NET 'P5_24' U1-L26 #> F09 #> T09 J4-C7 P05_24 L26 IO_L9P_MRCC_28 NET 'P6_0' U1-A37 #> F01 R4V1 #> T03 J3-D2 P06_00 A37 IO_L1N_26 NET 'P6_1' U1-C35 #> F05 R4V3 #> T03 J3-C3 P06_01 C35 IO_L15P_27 NET 'P6_2' U1-F36 #> F05 R4V5 #> T03 J3-D4 P06_02 F36 IO_L10N_MRCC_26 NET 'P6_3' U1-A39 #> F01 R4V6 #> T03 J3-C5 P06_03 A39 IO_L3N_26 NET 'P6_4' U1-B38 #> F01 R4V4 #> T03 J3-D6 P06_04 B38 IO_L3P_26 NET 'P6_5' U1-B37 #> F01 R4V2 #> T03 J3-C7 P06_05 B37 IO_L1P_26 NET 'P6_6' U1-G36 #> F03 #> T03 J3-D8 P06_06 G36 IO_L0N_26 NET 'P6_7' U1-F37 #> F03 #> T03 J3-C9 P06_07 F37 IO_L4P_26 NET 'P6_8' U1-G42 #> F01 R5V3 #> T03 J3-D10 P06_08 G42 IO_L18N_26 NET 'P6_9' U1-F42 #> F01 R5V5 #> T03 J3-C11 P06_09 F42 IO_L19N_26 NET 'P6_10' U1-E42 #> F01 R5V4 #> T03 J3-D12 P06_10 E42 IO_L19P_26 NET 'P6_11' U1-A41 #> F01 R5V2 #> T03 J3-C13 P06_11 A41 IO_L7N_26 NET 'P6_12' U1-A40 #> F01 R5V1 #> T03 J3-D14 P06_12 A40 IO_L7P_26 NET 'P6_13' U1-D38 #> F03 #> T03 J3-C15 P06_13 D38 IO_L6P_26 NET 'P6_14' U1-B39 #> F03 #> T03 J3-D16 P06_14 B39 IO_L5P_26 NET 'P6_15' U1-C39 #> F03 #> T03 J3-C17 P06_15 C39 IO_L5N_26 NET 'P6_16' U1-C40 #> F03 #> T03 J3-D18 P06_16 C40 IO_L13P_26 NET 'P6_17' U1-B41 #> F03 #> T03 J3-C19 P06_17 B41 IO_L11P_SRCC_26 NET 'P6_18' U1-C41 #> F03 #> T03 J4-D1 P06_18 C41 IO_L13N_26 NET 'P6_19' U1-D41 #> F03 #> T03 J4-C2 P06_19 D41 IO_L15N_26 NET 'P6_20' U1-E40 #> F03 #> T03 J4-D3 P06_20 E40 IO_L17N_26 NET 'P6_21' U1-F40 #> F03 #> T03 J4-C4 P06_21 F40 IO_L16P_26 NET 'P6_22' U1-F41 #> F03 #> T03 J4-D5 P06_22 F41 IO_L16N_26 NET 'P6_23' U1-G41 #> F03 #> T03 J4-C6 P06_23 G41 IO_L18P_26 NET 'P6_24' U1-G34 #> F05 #> T05 J4-D7 P06_24 G34 IO_L9P_MRCC_26 NET 'P7_0' U1-K29 #> F03 R2V2 #> T09 J3-E2 P07_00 K29 IO_L18P_27 NET 'P7_1' U1-H30 #> F03 R2V4 #> T09 J3-E3 P07_01 H30 IO_L16P_27 NET 'P7_2' U1-B33 #> F01 R2V5 #> T09 J3-E4 P07_02 B33 IO_L3P_27 NET 'P7_3' U1-B32 #> F01 R2V3 #> T09 J3-E5 P07_03 B32 IO_L1N_27 NET 'P7_4' U1-A32 #> F01 R2V1 #> T09 J3-E6 P07_04 A32 IO_L1P_27 NET 'P7_5' U1-A34 #> F01 R3V2 #> T09 J3-E7 P07_05 A34 IO_L5P_27 NET 'P7_6' U1-B34 #> F01 R3V4 #> T09 J3-E8 P07_06 B34 IO_L7P_27 NET 'P7_7' U1-F35 #> F03 R3V5 #> T09 J3-E9 P07_07 F35 IO_L10P_MRCC_26 NET 'P7_8' U1-F34 #> F03 R3V3 #> T09 J3-E10 P07_08 F34 IO_L17N_27 NET 'P7_9' U1-G33 #> F03 R3V1 #> T09 J3-E11 P07_09 G33 IO_L8P_SRCC_27 NET 'P7_10' U1-C34 #> F02 #> T02 J3-E12 P07_10 C34 IO_L7N_27 NET 'P7_11' U1-H34 #> F02 #> T02 J3-E13 P07_11 H34 IO_L9N_MRCC_26 NET 'P7_12' U1-H35 #> F02 #> T02 J3-E14 P07_12 H35 IO_L2N_26 NET 'P7_13' U1-C36 #> F02 #> T02 J3-E15 P07_13 C36 IO_L15N_27 NET 'P7_14' U1-H36 #> F02 #> T02 J3-E16 P07_14 H36 IO_L0P_26 NET 'P7_15' U1-G37 #> F02 #> T02 J3-E17 P07_15 G37 IO_L14P_26 NET 'P7_16' U1-C38 #> F02 #> T02 J3-E18 P07_16 C38 IO_L6N_26 NET 'P7_17' U1-E38 #> F02 #> T02 J3-E19 P07_17 E38 IO_L8N_SRCC_26 NET 'P7_18' U1-D40 #> F02 #> T02 J4-E1 P07_18 D40 IO_L17P_26 NET 'P7_19' U1-B42 #> F02 #> T02 J4-E2 P07_19 B42 IO_L11N_SRCC_26 NET 'P7_20' U1-D42 #> F02 #> T02 J4-E3 P07_20 D42 IO_L15P_26 NET 'P7_21' U1-E39 #> F02 #> T02 J4-E4 P07_21 E39 IO_L8P_SRCC_26 NET 'P7_22' U1-F39 #> F02 #> T02 J4-E5 P07_22 F39 IO_L12P_VRN_26 NET 'P7_23' U1-G39 #> F02 #> T02 J4-E6 P07_23 G39 IO_L12N_VRP_26 NET 'P7_24' U1-L29 #> F09 #> T09 J4-E7 P07_24 L29 IO_L9P_MRCC_27 NET 'P4TO7_DCI_P' U1-N26 #> T08 N26 IO_L12N_VRP_28 NET 'P4TO7_DCI_N' U1-P26 #> T08 P26 IO_L12P_VRN_28 NET 'VREF_P' U1-E37 #> T08 E37 IO_L4N_VREF_26 NET 'VREF_P' U1-G38 #> T08 G38 IO_L14N_VREF_26 NET 'VREF_P' U1-D35 #> T08 D35 IO_L4N_VREF_27 NET 'VREF_P' U1-J31 #> T08 J31 IO_L14N_VREF_27 NET 'VREF_P' U1-F29 #> T08 F29 IO_L4N_VREF_28 NET 'VREF_P' U1-H29 #> T08 H29 IO_L14N_VREF_28 ######################################################################################### # # The Processor Inputs in P8-P9-P10-P11 use IO resources from banks 21-22-23 # P8_24 uses a regional clock in IO bank 22 on trace layer 9 # P9_24 uses a regional clock in IO bank 23 on trace layer 9 # P10_24 uses a regional clock in IO bank 21 on trace layer 9 # P11_24 uses a regional clock in IO bank 21 on trace layer 9 # The DCI master for this group is IO bank 23 # NET 'P8_0' U1-BA32 #> F01 R1V5 #> T02 J5-A14 P08_00 BA32 IO_L6P_22 NET 'P8_1' U1-BB33 #> F01 R1V8 #> T02 J5-A15 P08_01 BB33 IO_L14P_22 NET 'P8_2' U1-BA31 #> F01 R1V6 #> T02 J5-A16 P08_02 BA31 IO_L16P_22 NET 'P8_3' U1-AV33 #> F06 R1V3 #> T02 J5-A17 P08_03 AV33 IO_L19P_23 NET 'P8_4' U1-AW33 #> F06 R1V1 #> T02 J5-A18 P08_04 AW33 IO_L19N_23 NET 'P8_5' U1-AM33 #> F02 #> T02 J5-A19 P08_05 AM33 IO_L3P_23 NET 'P8_6' U1-AM32 #> F02 #> T02 J5-A20 P08_06 AM32 IO_L3N_23 NET 'P8_7' U1-BA29 #> F01 R2V8 #> T02 J5-A21 P08_07 BA29 IO_L12N_VRP_22 NET 'P8_8' U1-AY32 #> F02 #> T02 J5-A22 P08_08 AY32 IO_L4P_22 NET 'P8_9' U1-AM31 #> F02 #> T02 J5-A23 P08_09 AM31 IO_L1P_23 NET 'P8_10' U1-AL30 #> F02 #> T02 J5-A24 P08_10 AL30 IO_L2N_23 NET 'P8_11' U1-AY30 #> F02 #> T02 J5-A25 P08_11 AY30 IO_L8N_SRCC_22 NET 'P8_12' U1-AK29 #> F02 #> T02 J6-A1 P08_12 AK29 IO_L8N_SRCC_23 NET 'P8_13' U1-AY29 #> F02 #> T02 J6-A2 P08_13 AY29 IO_L12P_VRN_22 NET 'P8_14' U1-AM28 #> F02 #> T02 J6-A3 P08_14 AM28 IO_L6N_23 NET 'P8_15' U1-AK27 #> F02 #> T02 J6-A4 P08_15 AK27 IO_L16P_23 NET 'P8_16' U1-AN34 #> F09 #> T09 J6-A5 P08_16 AN34 IO_L5N_23 NET 'P8_17' U1-AU33 #> F09 #> T09 J6-A6 P08_17 AU33 IO_L17P_23 NET 'P8_18' U1-AU32 #> F09 #> T09 J6-A7 P08_18 AU32 IO_L17N_23 NET 'P8_19' U1-AU31 #> F09 #> T09 J6-A8 P08_19 AU31 IO_L13N_22 NET 'P8_20' U1-AT30 #> F09 #> T09 J6-A9 P08_20 AT30 IO_L7P_22 NET 'P8_21' U1-AT29 #> F09 #> T09 J6-A10 P08_21 AT29 IO_L5P_22 NET 'P8_22' U1-AN28 #> F09 #> T09 J6-A11 P08_22 AN28 IO_L10P_MRCC_22 NET 'P8_23' U1-AR27 #> F09 #> T09 J6-A12 P08_23 AR27 IO_L11P_SRCC_22 NET 'P8_24' U1-AM26 #> F09 #> T09 J6-A13 P08_24 AM26 IO_L9P_MRCC_22 NET 'P9_0' U1-AR33 #> F05 #> T05 J5-B23 P09_00 AR33 IO_L15P_23 NET 'P9_1' U1-AT32 #> F05 #> T05 J5-B24 P09_01 AT32 IO_L15N_23 NET 'P9_2' U1-AR34 #> F03 #> T03 J5-B25 P09_02 AR34 IO_L11P_SRCC_23 NET 'P9_3' U1-AN33 #> F03 #> T03 J6-C1 P09_03 AN33 IO_L5P_23 NET 'P9_4' U1-AP32 #> F03 #> T03 J6-B2 P09_04 AP32 IO_L13P_23 NET 'P9_5' U1-AW31 #> F07 R2V5 #> T03 J6-C3 P09_05 AW31 IO_L2P_22 NET 'P9_6' U1-BB31 #> F01 R2V7 #> T03 J6-B4 P09_06 BB31 IO_L16N_22 NET 'P9_7' U1-BA30 #> F01 R2V6 #> T03 J6-C5 P09_07 BA30 IO_L8P_SRCC_22 NET 'P9_8' U1-AN31 #> F03 #> T03 J6-B6 P09_08 AN31 IO_L7N_23 NET 'P9_9' U1-AN30 #> F03 #> T03 J6-C7 P09_09 AN30 IO_L0N_23 NET 'P9_10' U1-AL29 #> F03 #> T03 J6-B8 P09_10 AL29 IO_L2P_23 NET 'P9_11' U1-AV29 #> F07 R3V4 #> T03 J6-C9 P09_11 AV29 IO_L15N_22 NET 'P9_12' U1-BB28 #> F01 R3V6 #> T03 J6-B10 P09_12 BB28 IO_L18N_22 NET 'P9_13' U1-AV28 #> F06 R3V2 #> T03 J6-C11 P09_13 AV28 IO_L17N_22 NET 'P9_14' U1-AP28 #> F03 #> T03 J6-B12 P09_14 AP28 IO_L3N_22 NET 'P9_15' U1-AL27 #> F03 #> T03 J6-C13 P09_15 AL27 IO_L6P_23 NET 'P9_16' U1-AP33 #> F04 #> T04 J6-B14 P09_16 AP33 IO_L11N_SRCC_23 NET 'P9_17' U1-AR32 #> F07 R2V4 #> T04 J6-C15 P09_17 AR32 IO_L13N_23 NET 'P9_18' U1-AV30 #> F06 R2V2 #> T04 J6-B16 P09_18 AV30 IO_L0N_22 NET 'P9_19' U1-AW30 #> F04 #> T04 J6-C17 P09_19 AW30 IO_L0P_22 NET 'P9_20' U1-AP31 #> F04 #> T04 J6-B18 P09_20 AP31 IO_L7P_23 NET 'P9_21' U1-AP30 #> F04 #> T04 J6-C19 P09_21 AP30 IO_L0P_23 NET 'P9_22' U1-AN29 #> F04 #> T04 J7-B1 P09_22 AN29 IO_L4P_23 NET 'P9_23' U1-AR28 #> F04 #> T04 J7-B2 P09_23 AR28 IO_L3P_22 NET 'P9_24' U1-AJ25 #> F09 #> T09 J7-B3 P09_24 AJ25 IO_L9P_MRCC_23 NET 'P10_0' U1-AY33 #> F07 R1V4 #> T05 J6-D6 P10_00 AY33 IO_L6N_22 NET 'P10_1' U1-AV31 #> F06 R1V2 #> T05 J6-D7 P10_01 AV31 IO_L2N_22 NET 'P10_2' U1-AT31 #> F05 #> T05 J6-D8 P10_02 AT31 IO_L13P_22 NET 'P10_3' U1-AR30 #> F05 #> T05 J6-D9 P10_03 AR30 IO_L7N_22 NET 'P10_4' U1-AR29 #> F05 #> T05 J6-C10 P10_04 AR29 IO_L5N_22 NET 'P10_5' U1-AU29 #> F06 R2V3 #> T05 J6-D11 P10_05 AU29 IO_L15P_22 NET 'P10_6' U1-AU28 #> F05 #> T05 J6-C12 P10_06 AU28 IO_L17P_22 NET 'P10_7' U1-AP27 #> F05 #> T05 J6-D13 P10_07 AP27 IO_L1N_22 NET 'P10_8' U1-AT27 #> F06 R3V1 #> T05 J6-C14 P10_08 AT27 IO_L11N_SRCC_22 NET 'P10_9' U1-AU27 #> F06 R3V3 #> T05 J6-D15 P10_09 AU27 IO_L0N_21 NET 'P10_10' U1-AW28 #> F07 R3V5 #> T05 J6-C16 P10_10 AW28 IO_L19P_22 NET 'P10_11' U1-BB29 #> F01 R3V8 #> T05 J6-D17 P10_11 BB29 IO_L18P_22 NET 'P10_12' U1-AV26 #> F05 #> T05 J6-C18 P10_12 AV26 IO_L16P_21 NET 'P10_13' U1-AU26 #> F05 #> T05 J6-D19 P10_13 AU26 IO_L16N_21 NET 'P10_14' U1-AL25 #> F02 R4V1 #> T05 J7-D1 P10_14 AL25 IO_L10N_MRCC_21 NET 'P10_15' U1-AW25 #> F06 R4V3 #> T05 J7-C2 P10_15 AW25 IO_L18P_21 NET 'P10_16' U1-AW27 #> F07 R4V5 #> T05 J7-D3 P10_16 AW27 IO_L2N_21 NET 'P10_17' U1-BB26 #> F01 R4V8 #> T05 J7-C4 P10_17 BB26 IO_L6P_21 NET 'P10_18' U1-AV25 #> F05 #> T05 J7-D5 P10_18 AV25 IO_L12N_VRP_21 NET 'P10_19' U1-AU24 #> F05 #> T05 J7-C6 P10_19 AU24 IO_L8N_SRCC_21 NET 'P10_20' U1-AR23 #> F05 #> T05 J7-D7 P10_20 AR23 IO_L11N_SRCC_21 NET 'P10_21' U1-AV24 #> F07 R5V1 #> T05 J7-C8 P10_21 AV24 IO_L12P_VRN_21 NET 'P10_22' U1-AU23 #> F06 R5V2 #> T05 J7-D9 P10_22 AU23 IO_L8P_SRCC_21 NET 'P10_23' U1-BA25 #> F01 R5V8 #> T05 J7-C10 P10_23 BA25 IO_L14P_21 NET 'P10_24' U1-AP25 #> F09 #> T09 J7-D11 P10_24 AP25 IO_L9P_MRCC_21 NET 'P11_0' U1-AY27 #> F02 #> T02 J6-E14 P11_00 AY27 IO_L2P_21 NET 'P11_1' U1-AN26 #> F02 #> T02 J6-E15 P11_01 AN26 IO_L1P_22 NET 'P11_2' U1-AM24 #> F02 #> T02 J6-E16 P11_02 AM24 IO_L13P_21 NET 'P11_3' U1-AK23 #> F02 #> T02 J6-E17 P11_03 AK23 IO_L5N_21 NET 'P11_4' U1-AM23 #> F02 #> T02 J6-E18 P11_04 AM23 IO_L7P_21 NET 'P11_5' U1-AK22 #> F02 #> T02 J6-E19 P11_05 AK22 IO_L1P_21 NET 'P11_6' U1-AJ22 #> F02 #> T02 J7-E1 P11_06 AJ22 IO_L1N_21 NET 'P11_7' U1-AM27 #> F04 #> T04 J7-E2 P11_07 AM27 IO_L10N_MRCC_22 NET 'P11_8' U1-AT26 #> F04 #> T04 J7-E3 P11_08 AT26 IO_L0P_21 NET 'P11_9' U1-AW26 #> F06 R4V2 #> T04 J7-E4 P11_09 AW26 IO_L18N_21 NET 'P11_10' U1-BA26 #> F01 R4V6 #> T04 J7-E5 P11_10 BA26 IO_L4P_21 NET 'P11_11' U1-AY28 #> F07 R4V4 #> T04 J7-E6 P11_11 AY28 IO_L19N_22 NET 'P11_12' U1-AR25 #> F04 #> T04 J7-E7 P11_12 AR25 IO_L19N_21 NET 'P11_13' U1-AT25 #> F04 #> T04 J7-E8 P11_13 AT25 IO_L19P_21 NET 'P11_14' U1-AT24 #> F04 #> T04 J7-E9 P11_14 AT24 IO_L17N_21 NET 'P11_15' U1-AP23 #> F04 #> T04 J7-E10 P11_15 AP23 IO_L11P_SRCC_21 NET 'P11_16' U1-BB27 #> F01 R4V7 #> T03 J7-E11 P11_16 BB27 IO_L6N_21 NET 'P11_17' U1-AP26 #> F03 #> T03 J7-E12 P11_17 AP26 IO_L9N_MRCC_21 NET 'P11_18' U1-AN25 #> F03 #> T03 J7-E13 P11_18 AN25 IO_L15N_21 NET 'P11_19' U1-AR24 #> F03 #> T03 J7-E14 P11_19 AR24 IO_L17P_21 NET 'P11_20' U1-AN24 #> F03 #> T03 J7-E15 P11_20 AN24 IO_L15P_21 NET 'P11_21' U1-AN23 #> F03 #> T03 J7-E16 P11_21 AN23 IO_L7N_21 NET 'P11_22' U1-AM22 #> F03 #> T03 J7-E17 P11_22 AM22 IO_L3P_21 NET 'P11_23' U1-AL22 #> F03 #> T03 J7-E18 P11_23 AL22 IO_L3N_21 NET 'P11_24' U1-AK24 #> F09 #> T09 J7-E19 P11_24 AK24 IO_L10P_MRCC_21 NET 'P8TO11_DCI_P' U1-AJ28 #> T08 AJ28 IO_L12N_VRP_23 NET 'P8TO11_DCI_N' U1-AH28 #> T08 AH28 IO_L12P_VRN_23 NET 'VREF_P' U1-BA27 #> T08 BA27 IO_L4N_VREF_21 NET 'VREF_P' U1-AY25 #> T08 AY25 IO_L14N_VREF_21 NET 'VREF_P' U1-AW32 #> T08 AW32 IO_L4N_VREF_22 NET 'VREF_P' U1-BB32 #> T08 BB32 IO_L14N_VREF_22 NET 'VREF_P' U1-AM29 #> T08 AM29 IO_L4N_VREF_23 NET 'VREF_P' U1-AG27 #> T08 AG27 IO_L14N_VREF_23 ######################################################################################### # # The Processor Inputs in P12-P13-P14-P15 use IO resources from banks 32-33-34 # P12_24 uses a regional clock in IO bank 32 on trace layer 9 # P13_24 uses a regional clock in IO bank 33 on trace layer 9 # P14_24 uses a regional clock in IO bank 34 on trace layer 9 # P15_24 uses a regional clock in IO bank 34 on trace layer 9 # The DCI master for this group is IO bank 34 # NET 'P12_0' U1-BB22 #> F01 R1V7 #> T02 J7-A10 P12_00 BB22 IO_L18P_32 NET 'P12_1' U1-BA24 #> F01 R1V6 #> T02 J7-A11 P12_01 BA24 IO_L0N_32 NET 'P12_2' U1-BA22 #> F01 R1V5 #> T02 J7-A12 P12_02 BA22 IO_L14P_32 NET 'P12_3' U1-BB23 #> F01 R1V3 #> T02 J7-A13 P12_03 BB23 IO_L6N_32 NET 'P12_4' U1-AL21 #> F02 #> T02 J7-A14 P12_04 AL21 IO_L5N_32 NET 'P12_5' U1-AM21 #> F02 #> T02 J7-A15 P12_05 AM21 IO_L11P_SRCC_32 NET 'P12_6' U1-AR20 #> F02 #> T02 J7-A16 P12_06 AR20 IO_L3N_32 NET 'P12_7' U1-AY20 #> F02 #> T02 J7-A17 P12_07 AY20 IO_L8P_SRCC_32 NET 'P12_8' U1-AP20 #> F02 #> T02 J7-A18 P12_08 AP20 IO_L7N_32 NET 'P12_9' U1-AY19 #> F02 #> T02 J7-A19 P12_09 AY19 IO_L17N_33 NET 'P12_10' U1-AV18 #> F09 R3V8 #> T02 J8-A1 P12_10 AV18 IO_L13P_33 NET 'P12_11' U1-AK19 #> F02 #> T02 J8-A2 P12_11 AK19 IO_L10N_MRCC_32 NET 'P12_12' U1-AK18 #> F02 #> T02 J8-A3 P12_12 AK18 IO_L18P_33 NET 'P12_13' U1-AK17 #> F02 #> T02 J8-A4 P12_13 AK17 IO_L6N_33 NET 'P12_14' U1-AM17 #> F04 #> T04 J8-A5 P12_14 AM17 IO_L14P_33 NET 'P12_15' U1-AN16 #> F04 #> T04 J8-A6 P12_15 AN16 IO_L8P_SRCC_33 NET 'P12_16' U1-AN15 #> F04 #> T04 J8-A7 P12_16 AN15 IO_L2P_33 NET 'P12_17' U1-AM14 #> F04 #> T04 J8-A8 P12_17 AM14 IO_L2N_33 NET 'P12_18' U1-AW23 #> F09 #> T09 J8-A9 P12_18 AW23 IO_L4P_32 NET 'P12_19' U1-AY22 #> F09 #> T09 J8-A10 P12_19 AY22 IO_L16N_32 NET 'P12_20' U1-AW22 #> F09 #> T09 J8-A11 P12_20 AW22 IO_L16P_32 NET 'P12_21' U1-AV23 #> F09 #> T09 J8-A12 P12_21 AV23 IO_L2P_32 NET 'P12_22' U1-AW21 #> F09 #> T09 J8-A13 P12_22 AW21 IO_L12N_VRP_32 NET 'P12_23' U1-AW20 #> F09 #> T09 J8-A14 P12_23 AW20 IO_L13N_32 NET 'P12_24' U1-AK20 #> F09 #> T09 J8-A15 P12_24 AK20 IO_L10P_MRCC_32 NET 'P13_0' U1-AR22 #> F04 #> T04 J7-B10 P13_00 AR22 IO_L17N_32 NET 'P13_1' U1-AP22 #> F04 #> T04 J7-C11 P13_01 AP22 IO_L19N_32 NET 'P13_2' U1-AT21 #> F04 #> T04 J7-B12 P13_02 AT21 IO_L15N_32 NET 'P13_3' U1-BB24 #> F01 R1V4 #> T05 J7-C13 P13_03 BB24 IO_L6P_32 NET 'P13_4' U1-AU22 #> F05 #> T05 J7-B14 P13_04 AU22 IO_L2N_32 NET 'P13_5' U1-AT22 #> F05 #> T05 J7-C15 P13_05 AT22 IO_L17P_32 NET 'P13_6' U1-AU21 #> F05 #> T05 J7-B16 P13_06 AU21 IO_L15P_32 NET 'P13_7' U1-AV21 #> F05 #> T05 J7-C17 P13_07 AV21 IO_L12P_VRN_32 NET 'P13_8' U1-AV20 #> F05 #> T05 J7-B18 P13_08 AV20 IO_L13P_32 NET 'P13_9' U1-AR19 #> F05 #> T05 J7-C19 P13_09 AR19 IO_L11N_SRCC_33 NET 'P13_10' U1-AN21 #> F03 #> T03 J8-B1 P13_10 AN21 IO_L11N_SRCC_32 NET 'P13_11' U1-AP21 #> F03 #> T03 J8-C2 P13_11 AP21 IO_L19P_32 NET 'P13_12' U1-BB21 #> F01 R2V7 #> T03 J8-B3 P13_12 BB21 IO_L18N_32 NET 'P13_13' U1-BB19 #> F01 R2V8 #> T03 J8-C4 P13_13 BB19 IO_L15N_33 NET 'P13_14' U1-BA20 #> F01 R2V6 #> T03 J8-B5 P13_14 BA20 IO_L8N_SRCC_32 NET 'P13_15' U1-AT20 #> F03 #> T03 J8-C6 P13_15 AT20 IO_L3P_32 NET 'P13_16' U1-AM19 #> F03 #> T03 J8-B7 P13_16 AM19 IO_L1N_32 NET 'P13_17' U1-AL19 #> F03 #> T03 J8-C8 P13_17 AL19 IO_L1P_32 NET 'P13_18' U1-AN18 #> F03 #> T03 J8-B9 P13_18 AN18 IO_L16P_33 NET 'P13_19' U1-BA19 #> F01 R3V7 #> T03 J8-C10 P13_19 BA19 IO_L17P_33 NET 'P13_20' U1-AT19 #> F09 R3V6 #> T03 J8-B11 P13_20 AT19 IO_L19N_33 NET 'P13_21' U1-AL17 #> F03 #> T03 J8-C12 P13_21 AL17 IO_L4P_33 NET 'P13_22' U1-AM16 #> F03 #> T03 J8-B13 P13_22 AM16 IO_L8N_SRCC_33 NET 'P13_23' U1-AP16 #> F09 R4V6 #> T03 J8-C14 P13_23 AP16 IO_L12P_VRN_33 NET 'P13_24' U1-AK15 #> F09 #> T09 J8-B15 P13_24 AK15 IO_L9P_MRCC_33 NET 'P14_0' U1-AU19 #> F06 R2V2 #> T04 J7-C12 P14_00 AU19 IO_L19P_33 NET 'P14_1' U1-AY17 #> F06 R2V4 #> T04 J7-D13 P14_01 AY17 IO_L18P_A17_34 NET 'P14_2' U1-AW18 #> F07 R2V5 #> T04 J7-C14 P14_02 AW18 IO_L7N_33 NET 'P14_3' U1-AY18 #> F07 R2V3 #> T04 J7-D15 P14_03 AY18 IO_L7P_33 NET 'P14_4' U1-AV19 #> F07 R2V1 #> T04 J7-C16 P14_04 AV19 IO_L13N_33 NET 'P14_5' U1-AN19 #> F04 #> T04 J7-D17 P14_05 AN19 IO_L16N_33 NET 'P14_6' U1-BB18 #> F04 #> T04 J7-C18 P14_06 BB18 IO_L15P_33 NET 'P14_7' U1-AW16 #> F01 R3V5 #> T04 J7-D19 P14_07 AW16 IO_L8N_SRCC_34 NET 'P14_8' U1-AU17 #> F06 R3V3 #> T04 J8-C1 P14_08 AU17 IO_L3N_33 NET 'P14_9' U1-AR18 #> F06 R3V1 #> T04 J8-D2 P14_09 AR18 IO_L1N_33 NET 'P14_10' U1-AP18 #> F04 #> T04 J8-C3 P14_10 AP18 IO_L11P_SRCC_33 NET 'P14_11' U1-AJ16 #> F02 #> T02 J8-D4 P14_11 AJ16 IO_L10P_MRCC_33 NET 'P14_12' U1-AV16 #> F06 R4V3 #> T02 J8-C5 P14_12 AV16 IO_L8P_SRCC_34 NET 'P14_13' U1-AT17 #> F09 R4V8 #> T02 J8-D6 P14_13 AT17 IO_L5P_33 NET 'P14_14' U1-AY15 #> F02 #> T02 J8-C7 P14_14 AY15 IO_L6P_A07_D23_34 NET 'P14_15' U1-AL15 #> F02 #> T02 J8-D8 P14_15 AL15 IO_L0P_33 NET 'P14_16' U1-AK14 #> F02 #> T02 J8-C9 P14_16 AK14 IO_L9N_MRCC_33 NET 'P14_17' U1-AN13 #> F02 #> T02 J8-D10 P14_17 AN13 IO_L10N_MRCC_34 NET 'P14_18' U1-AV13 #> F06 R5V2 #> T02 J8-C11 P14_18 AV13 IO_L11P_SRCC_34 NET 'P14_19' U1-BA16 #> F01 R5V8 #> T02 J8-D12 P14_19 BA16 IO_L14P_A25_34 NET 'P14_20' U1-BB14 #> F01 R5V6 #> T02 J8-C13 P14_20 BB14 IO_L12N_A02_D18_34 NET 'P14_21' U1-BB13 #> F01 R5V4 #> T02 J8-D14 P14_21 BB13 IO_L12P_A03_D19_34 NET 'P14_22' U1-AW13 #> F07 R5V1 #> T02 J8-C15 P14_22 AW13 IO_L13N_A00_D16_34 NET 'P14_23' U1-AM12 #> F02 #> T02 J8-D16 P14_23 AM12 IO_L9N_MRCC_34 NET 'P14_24' U1-AN14 #> F09 #> T09 J8-C17 P14_24 AN14 IO_L10P_MRCC_34 NET 'P15_0' U1-AU18 #> F05 #> T05 J8-E1 P15_00 AU18 IO_L5N_33 NET 'P15_1' U1-AW17 #> F07 R3V2 #> T05 J8-E2 P15_01 AW17 IO_L18N_A16_34 NET 'P15_2' U1-AW15 #> F07 R3V4 #> T05 J8-E3 P15_02 AW15 IO_L6N_A06_D22_34 NET 'P15_3' U1-AP17 #> F05 #> T05 J8-E4 P15_03 AP17 IO_L12N_VRP_33 NET 'P15_4' U1-AR17 #> F05 #> T05 J8-E5 P15_04 AR17 IO_L1P_33 NET 'P15_5' U1-AT16 #> F05 #> T05 J8-E6 P15_05 AT16 IO_L3P_33 NET 'P15_6' U1-AV15 #> F07 R4V1 #> T05 J8-E7 P15_06 AV15 IO_L4P_A11_D27_34 NET 'P15_7' U1-AT14 #> F07 R4V4 #> T05 J8-E8 P15_07 AT14 IO_L15N_A22_34 NET 'P15_8' U1-BB17 #> F01 R4V7 #> T05 J8-E9 P15_08 BB17 IO_L16N_A20_34 NET 'P15_9' U1-BB16 #> F01 R4V5 #> T05 J8-E10 P15_09 BB16 IO_L16P_A21_34 NET 'P15_10' U1-AV14 #> F06 R4V2 #> T05 J8-E11 P15_10 AV14 IO_L11N_SRCC_34 NET 'P15_11' U1-AR15 #> F05 #> T05 J8-E12 P15_11 AR15 IO_L17N_A18_34 NET 'P15_12' U1-AR14 #> F05 #> T05 J8-E13 P15_12 AR14 IO_L15P_A23_34 NET 'P15_13' U1-BA15 #> F01 R5V7 #> T05 J8-E14 P15_13 BA15 IO_L2P_A15_D31_34 NET 'P15_14' U1-BA14 #> F01 R5V5 #> T05 J8-E15 P15_14 BA14 IO_L2N_A14_D30_34 NET 'P15_15' U1-AU13 #> F05 #> T05 J8-E16 P15_15 AU13 IO_L7N_A04_D20_34 NET 'P15_16' U1-AU12 #> F05 #> T05 J8-E17 P15_16 AU12 IO_L7P_A05_D21_34 NET 'P15_17' U1-AR13 #> F04 #> T04 J8-E18 P15_17 AR13 IO_L5N_A08_D24_34 NET 'P15_18' U1-AT12 #> F04 #> T04 J8-E19 P15_18 AT12 IO_L3N_A12_D28_34 NET 'P15_19' U1-AP15 #> F03 #> T03 J8-E20 P15_19 AP15 IO_L17P_A19_34 NET 'P15_20' U1-AL14 #> F03 #> T03 J8-E21 P15_20 AL14 IO_L0N_33 NET 'P15_21' U1-AP13 #> F03 #> T03 J8-E22 P15_21 AP13 IO_L5P_A09_D25_34 NET 'P15_22' U1-AR12 #> F03 #> T03 J8-E23 P15_22 AR12 IO_L3P_A13_D29_34 NET 'P15_23' U1-AW12 #> F09 R5V3 #> T03 J8-E24 P15_23 AW12 IO_L13P_A01_D17_34 NET 'P15_24' U1-AM13 #> F09 #> T09 J8-E25 P15_24 AM13 IO_L9P_MRCC_34 NET 'P12TO15_DCI_P' U1-AU16 #> T08 AU16 IO_L19N_VRP_34 NET 'P12TO15_DCI_N' U1-AT15 #> T08 AT15 IO_L19P_VRN_34 NET 'VREF_P' U1-AY23 #> T08 AY23 IO_L4N_VREF_32 NET 'VREF_P' U1-BA21 #> T08 BA21 IO_L14N_VREF_32 NET 'VREF_P' U1-AL16 #> T08 AL16 IO_L4N_VREF_33 NET 'VREF_P' U1-AM18 #> T08 AM18 IO_L14N_VREF_33 NET 'VREF_P' U1-AU14 #> T08 AU14 IO_L4N_VREF_A10_D26_34 NET 'VREF_P' U1-BA17 #> T08 BA17 IO_L14N_VREF_A24_34 ############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for the LVDS cable IO # -=============---------------------------------------------- # # # Original Rev. 18-Nov-2011 # Rev. 22-Jun-2012 comment all out because processor inputs have moved to banks 22&23 # Rev. 31-Aug-2012 Now on IO banks 15,16,17 and layer assigned # Rev: 07-Sep-2012 Add header comments # Rev: 19-Nov-2012 Re-do breakout strategy which frees up layers 6 and 7 now unused # Skip the 8 System Monitor pin pairs from IO Bank 15 # Rev. 30-Nov-2012 Studying the set of unused pins generated 2 allocation improvements here # Most Recent Rev: 03-Jun-2013 swap pin used for cable IO signal 83 (AE35 is now used; AF41 now unused) # # Signal Nets referenced in this file: # ------------------------------------ # # 'D_CBL_zz_B' are the cable IO signals available to the Base FPGA with zz=00 to 83. # The "_B" postfix is used to indicate that these signals are inverted with respect # to the LVDS signal polarity on the data cables. # # There are up to 3 cables used for a given CMX card. # A Crate CMX card uses one cable as output only, # while a System CMX card receives 2 or 3 cables as input. # # A Rear Transition Module (RTM) card provides the interface to the three 34-signal # LVDS connectors where the IO cables can be connected. # Only 27 signals from each connector are routed on the current RTM cards. # zz=0 to 26 correspond to the first cable, # zz=27 to 53 correspond to the second cable, and # zz=54 to 80 correspond to the third cable. # # Additionally, 3 more differential pairs of signals are labelled on the backplane # but are not routed on the RTM: zz= 31 to 83 # The CMX card will route the currently unused M_81, M_82, and M_83 signals # to become usable as cable IO signals. The sets of cable signals thus are: # Cable #1 consists of signals M_00 to M_26 plus M_81 # Cable #2 consists of signals M_27 to M_53 plus M_82 # Cable #3 consists of signals M_54 to M_80 plus M_83 # The CMX card could thus be able to use 28 LVDS signals per cable while the CMM was only able # to use 27 signals. Using 28 signals would however require a new version of the RTM card. # This 28th signal can be left unused and set to a fixed state by the FPGA of the source Crate CMX # while the LVDS transceiver of the receiving System CMX will default to a defined value # for all non-connected inputs. # # The path to the LVDS transceivers D_CBL_zz signals are in the file backplane_cable_tx_n2p.txt # in the Net_Lists/Components_Backplane_Tx directory # # Note: Trace layer information is appended as comments below. # ----- # # NET 'D_CBL_00' U1- #> T02 00 L12 # # ^ ^ ^ ^ # | | | | # Tailored comment flag to help with string searches -------------------+ | | | # | | | # Target Trace Layer number to use for this net ----------------------------+ | | # T01 is top layer, T02 the first inner layer, etc | | # | | # Signal number is repeated to help manual entry of Pin Number ----------------+ | # | # Target Pin Number read from paper drawing ----------------------------------------+ # and cross-checked after Match_Res2Pin # ############################################################################################ # # IO Cable #1 # # This group uses signals from IO banks 16 and 17 and a regional clock from bank 17 NET 'D_CBL_00_B' U1-L39 #> T02 00 L39 IO_L1P_17 NET 'D_CBL_01_B' U1-L42 #> T02 01 L42 IO_L3N_17 NET 'D_CBL_02_B' U1-M36 #> T02 02 M36 IO_L0P_17 NET 'D_CBL_03_B' U1-M42 #> T02 03 M42 IO_L7N_17 NET 'D_CBL_04_B' U1-N36 #> T02 04 N36 IO_L6P_17 NET 'D_CBL_05_B' U1-P37 #> T02 05 P37 IO_L6N_17 NET 'D_CBL_06_B' U1-P42 #> T02 06 P42 IO_L15P_17 NET 'D_CBL_07_B' U1-R35 #> T02 07 R35 IO_L14P_17 NET 'D_CBL_08_B' U1-R42 #> T02 08 R42 IO_L15N_17 NET 'D_CBL_09_B' U1-T35 #> T02 09 T35 IO_L18N_17 NET 'D_CBL_10_B' U1-T42 #> T02 10 T42 IO_L19N_17 NET 'D_CBL_11_B' U1-U36 #> T02 11 U36 IO_L16P_17 NET 'D_CBL_12_B' U1-U42 #> T02 12 U42 IO_L3P_16 NET 'D_CBL_13_B' U1-V36 #> T02 13 V36 IO_L2N_16 NET 'D_CBL_14_B' U1-W35 #> T02 14 W35 IO_L6P_16 NET 'D_CBL_15_B' U1-W42 #> T02 15 W42 IO_L15P_16 NET 'D_CBL_16_B' U1-Y34 #> T02 16 Y34 IO_L14N_VREF_16 NET 'D_CBL_17_B' U1-Y42 #> T02 17 Y42 IO_L15N_16 NET 'D_CBL_18_B' U1-Y35 #> T02 18 Y35 IO_L8N_SRCC_16 NET 'D_CBL_19_B' U1-AA34 #> T02 19 AA34 IO_L14P_16 NET 'D_CBL_20_B' U1-AA32 #> T02 20 AA32 IO_L12P_VRN_16 NET 'D_CBL_21_B' U1-L40 #> T03 21 L40 IO_L1N_17 NET 'D_CBL_22_B' U1-M37 #> T03 22 M37 IO_L0N_17 NET 'D_CBL_23_B' U1-M41 #> T09 23 M41 IO_L7P_17 NET 'D_CBL_24_B' U1-N41 #> T09 24 N41 IO_L11N_SRCC_17 NET 'D_CBL_25_B' U1-P36 # Clock #> T09 25 P36 IO_L9P_MRCC_17 NET 'D_CBL_26_B' U1-R40 # Parity #> T09 26 R40 IO_L17P_17 NET 'D_CBL_81_B' U1-N38 #> T03 81 N38 IO_L5P_17 # # IO Cable #2 # # This group uses signals from IO banks 16 and 17 and a regional clock from bank 17 NET 'D_CBL_27_B' U1-P38 #> T03 27 P38 IO_L8N_SRCC_17 NET 'D_CBL_28_B' U1-R37 #> T03 28 R37 IO_L12P_VRN_17 NET 'D_CBL_29_B' U1-T36 #> T03 29 T36 IO_L16N_17 NET 'D_CBL_30_B' U1-U37 #> T03 30 U37 IO_L1P_16 NET 'D_CBL_31_B' U1-V38 #> T03 31 V38 IO_L7P_16 NET 'D_CBL_32_B' U1-W36 #> T03 32 W36 IO_L2P_16 NET 'D_CBL_33_B' U1-W37 #> T03 33 W37 IO_L0P_16 NET 'D_CBL_34_B' U1-Y37 #> T03 34 Y37 IO_L0N_16 NET 'D_CBL_35_B' U1-AA36 #> T03 35 AA36 IO_L4P_16 NET 'D_CBL_36_B' U1-AA35 #> T03 36 AA35 IO_L8P_SRCC_16 NET 'D_CBL_37_B' U1-L41 #> T04 37 L41 IO_L3P_17 NET 'D_CBL_38_B' U1-M38 #> T04 38 M38 IO_L2P_17 NET 'D_CBL_39_B' U1-N39 #> T04 39 N39 IO_L5N_17 NET 'D_CBL_40_B' U1-P40 #> T04 40 P40 IO_L13P_17 NET 'D_CBL_41_B' U1-R38 #> T04 41 R38 IO_L10N_MRCC_17 NET 'D_CBL_42_B' U1-T37 #> T04 42 T37 IO_L12N_VRP_17 NET 'D_CBL_43_B' U1-U38 #> T04 43 U38 IO_L1N_16 NET 'D_CBL_44_B' U1-V39 #> T04 44 V39 IO_L5N_16 NET 'D_CBL_45_B' U1-V40 #> T04 45 V40 IO_L11P_SRCC_16 NET 'D_CBL_46_B' U1-W38 #> T04 46 W38 IO_L7N_16 NET 'D_CBL_47_B' U1-Y38 #> T04 47 Y38 IO_L19P_16 NET 'D_CBL_48_B' U1-T39 # Clock #> T09 48 T39 IO_L10P_MRCC_17 NET 'D_CBL_49_B' U1-T41 # Parity #> T09 49 T41 IO_L19P_17 NET 'D_CBL_50_B' U1-M39 #> T05 50 M39 IO_L2N_17 NET 'D_CBL_51_B' U1-N40 #> T05 51 N40 IO_L11P_SRCC_17 NET 'D_CBL_52_B' U1-P41 #> T05 52 P41 IO_L13N_17 NET 'D_CBL_53_B' U1-R39 #> T05 53 R39 IO_L8P_SRCC_17 NET 'D_CBL_82_B' U1-T40 #> T05 82 T40 IO_L17N_17 # # IO Cable #3 # # This group uses signals from IO banks 15 and 16 and a regional clock from bank 16 NET 'D_CBL_54_B' U1-AC36 #> T02 54 AC36 IO_L8P_SRCC_15 NET 'D_CBL_55_B' U1-AC35 #> T02 55 AC35 IO_L16P_VRN_15 NET 'D_CBL_56_B' U1-AE37 #> T02 56 AE37 IO_L10P_MRCC_15 NET 'D_CBL_57_B' U1-AF42 #> T02 57 AF42 IO_L17P_15 NET 'D_CBL_58_B' U1-AB34 #> T03 58 AB34 IO_L16N_VRP_15 NET 'D_CBL_59_B' U1-AB36 #> T03 59 AB36 IO_L8N_SRCC_15 NET 'D_CBL_60_B' U1-AC38 #> T03 60 AC38 IO_L4P_15 NET 'D_CBL_61_B' U1-AD37 #> T03 61 AD37 IO_L10N_MRCC_15 NET 'D_CBL_62_B' U1-AD36 #> T03 62 AD36 IO_L14P_15 NET 'D_CBL_63_B' U1-AE39 #> T03 63 AE39 IO_L19N_15 NET 'D_CBL_64_B' U1-AA39 #> T04 64 AA39 IO_L19N_16 NET 'D_CBL_65_B' U1-AA37 #> T04 65 AA37 IO_L4N_VREF_16 NET 'D_CBL_66_B' U1-AB37 #> T04 66 AB37 IO_L1P_15 NET 'D_CBL_67_B' U1-AB38 #> T04 67 AB38 IO_L1N_15 NET 'D_CBL_68_B' U1-AC39 #> T04 68 AC39 IO_L4N_VREF_15 NET 'D_CBL_69_B' U1-U39 #> T05 69 U39 IO_L5P_16 NET 'D_CBL_70_B' U1-U41 #> T05 70 U41 IO_L3N_16 NET 'D_CBL_71_B' U1-V41 #> T05 71 V41 IO_L13P_16 NET 'D_CBL_72_B' U1-W40 #> T05 72 W40 IO_L11N_SRCC_16 NET 'D_CBL_73_B' U1-Y39 #> T05 73 Y39 IO_L17N_16 NET 'D_CBL_74_B' U1-AC41 #> T05 74 AC41 IO_L11P_SRCC_15 NET 'D_CBL_75_B' U1-AD41 #> T05 75 AD41 IO_L11N_SRCC_15 NET 'D_CBL_76_B' U1-AE40 #> T05 76 AE40 IO_L19P_15 NET 'D_CBL_77_B' U1-V35 #> T09 77 V35 IO_L6N_16 NET 'D_CBL_78_B' U1-W32 # Clock #> T09 78 W32 IO_L9P_MRCC_16 NET 'D_CBL_79_B' U1-W41 # Parity #> T09 79 W41 IO_L13N_16 NET 'D_CBL_80_B' U1-Y40 #> T09 80 Y40 IO_L17P_16 NET 'D_CBL_83_B' U1-AE35 #> T09 83 AE35 IO_L0N_15 ############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for Front Panel CTP Output # -=============--------------------------------------------- # # # Original Rev. 15-Nov-2011 assign to banks 33 & 34 # Rev. 22-Jun-2012 comment everything out as 33&34 taken by Processor inputs # Rev. 10-Sep-2012 Reassign to IO Banks 12 & part of 13 # Rev: 19-Nov-2012 Re-do breakout strategy # and plan for "a matrix of vias" near FPGA South East corner # The long haul is temporarily recoreded as layer 1 (T01), to be determined. # Rename nets to make Base Function a prefix (DOUT_CTP_xx_BF -> BF_DOUT_CTP_xx) # Rev: 11-Dec-2012 File name changed for uniformity and consistency between Base and TP files # Rev: 14-Jan-2013 Edit header comments # Rev: 05-Apr-2013 Tentatively flag these signals to belong to layer 7 # Rev: 20-May-2013 Swap BF_DOUT_CTP_51 and BF_DOUT_CTP_57 to solve problem with backplane IO # Most Recent Rev: 06-Jun-2013 Update position of signal #65 and rotate position of upper half signals # after final location of 5th translator # # # Signal Nets referenced in this file: # ------------------------------------ # # There are 0, 1 or 2 CTP cables connected to a given CMX card. # A Crate CMX with only Base CMX functionality does not send any data to the CTP # A System CMX in a CPM crate sends information to the CTP over one cable # A System CMX in a JEM crate sends information to the CTP over two cables # A Crate CMX with TP functionality would probably send information to the CTP over two cables # # 'BF_DOUT_CTP_xx' are the CTP output signals from the Base FPGA with xx=00 to 65. # Each CTP output cable carries 33 LVDS signals consisting of 31 data bits, one clock # and one parity bit. # xx=0 to 30 carry data bits on cable #1 # xx=31 carry the clock on cable #1 # xx=64 carry the parity on cable #1 # xx=32 to 62 carry data bits on cable #2 # xx=63 carry the clock on cable #2 # xx=65 carry the parity on cable #2 # Note that regional clock signals are assigned to CTP output signals # 31 and 63 # for flexibility, so that the CTP output cables could be used as inputs instead. # # These CTP output signals are assigned here to resources in IO banks 12 and 13. # Only part of IO bank 13 is used here, namely only the pins in rows AN to BB # while 11 io pins in rows AK, AL and AM are used for the on-card bus. # # The rest of the circuitry used to drive the LVDS cables is in the file front_panel_ctp_driver_n2p.txt # in the Net_Lists/Front_Panel_CTP_IO_Nets directory # # # Note: Trace layer information is appended as comments below. # ----- # # NET 'BF_DOUT_CTP_00' U1- #> F02 #> T01 00 AW37 # # ^ ^ ^ ^ ^ # | | | | | # Tailored comment flag to help with string searches -----------------+ | | | | # | | | | # Target Trace Layer number to use for this net --------------------------+ | | | # as it exits the FPGA (to reach a via in the via matrix) | | | # F01 is top layer, F02 the first inner layer, etc | | | # | | | # Target Trace Layer number to use for this net ---------------------------------+ | | # as it reaches the level translator near the front of the card | | # T01 is top layer, T02 the first inner layer, etc | | # | | # Signal number is repeated to help manual entry of Pin Number ---------------------+ | # | # Target Pin Number read from paper study -----------------------------------------------+ # and cross-checked after Match_Res2Pin # ############################################################################################ # # CTP Cable #1 # # This group uses signals from IO banks 12 and 13 and a regional clock from bank 13 NET 'BF_DOUT_CTP_00' U1-AW37 #> F02 #> T07 00 AW37 IO_L8P_SRCC_12 NET 'BF_DOUT_CTP_01' U1-AU42 #> F02 #> T07 01 AU42 IO_L5N_13 NET 'BF_DOUT_CTP_02' U1-AT36 #> F02 #> T07 02 AT36 IO_L6N_12 NET 'BF_DOUT_CTP_03' U1-AR37 #> F03 #> T07 03 AR37 IO_L2N_12 NET 'BF_DOUT_CTP_04' U1-AY35 #> F05 #> T07 04 AY35 IO_L17N_12 NET 'BF_DOUT_CTP_05' U1-AP36 #> F09 #> T07 05 AP36 IO_L10P_MRCC_12 NET 'BF_DOUT_CTP_06' U1-BB38 #> F02 #> T07 06 BB38 IO_L7N_12 NET 'BF_DOUT_CTP_07' U1-AV38 #> F02 #> T07 07 AV38 IO_L1N_12 NET 'BF_DOUT_CTP_08' U1-AU37 #> F02 #> T07 08 AU37 IO_L4P_12 NET 'BF_DOUT_CTP_09' U1-AT37 #> F03 #> T07 09 AT37 IO_L0P_12 NET 'BF_DOUT_CTP_10' U1-BA36 #> F05 #> T07 10 BA36 IO_L13N_12 NET 'BF_DOUT_CTP_11' U1-AR40 #> F09 #> T07 11 AR40 IO_L8P_SRCC_13 NET 'BF_DOUT_CTP_12' U1-AW38 #> F02 #> T07 12 AW38 IO_L8N_SRCC_12 NET 'BF_DOUT_CTP_13' U1-AW40 #> F02 #> T07 13 AW40 IO_L19N_13 NET 'BF_DOUT_CTP_14' U1-AW42 #> F02 #> T07 14 AW42 IO_L7P_13 NET 'BF_DOUT_CTP_15' U1-AU38 #> F03 #> T07 15 AU38 IO_L4N_VREF_12 NET 'BF_DOUT_CTP_16' U1-AT41 #> F05 #> T07 16 AT41 IO_L8N_SRCC_13 NET 'BF_DOUT_CTP_17' U1-AY37 #> F03 #> T07 17 AY37 IO_L5N_12 NET 'BF_DOUT_CTP_18' U1-BB39 #> F02 #> T07 18 BB39 IO_L7P_12 NET 'BF_DOUT_CTP_19' U1-AY40 #> F02 #> T07 19 AY40 IO_L17N_13 NET 'BF_DOUT_CTP_20' U1-AY42 #> F02 #> T07 20 AY42 IO_L13P_13 NET 'BF_DOUT_CTP_21' U1-AV39 #> F03 #> T07 21 AV39 IO_L1P_12 NET 'BF_DOUT_CTP_22' U1-AU41 #> F05 #> T07 22 AU41 IO_L11N_SRCC_13 NET 'BF_DOUT_CTP_23' U1-AY38 #> F03 #> T07 23 AY38 IO_L5P_12 NET 'BF_DOUT_CTP_24' U1-AY39 #> F02 #> T07 24 AY39 IO_L3P_12 NET 'BF_DOUT_CTP_25' U1-BA41 #> F02 #> T07 25 BA41 IO_L15P_13 NET 'BF_DOUT_CTP_26' U1-BA42 #> F02 #> T07 26 BA42 IO_L13N_13 NET 'BF_DOUT_CTP_27' U1-AW41 #> F03 #> T07 27 AW41 IO_L7N_13 NET 'BF_DOUT_CTP_28' U1-AV41 #> F05 #> T07 28 AV41 IO_L11P_SRCC_13 NET 'BF_DOUT_CTP_29' U1-BA39 #> F03 #> T07 29 BA39 IO_L3N_12 NET 'BF_DOUT_CTP_30' U1-BA40 #> F02 #> T07 30 BA40 IO_L17P_13 NET 'BF_DOUT_CTP_31' U1-AT40 #> F09 #> T07 31 AT40 IO_L10P_MRCC_13 NET 'BF_DOUT_CTP_64' U1-BB41 #> F02 #> T07 64 BB41 IO_L15N_13 # # CTP Cable #2 # # This group uses signals from IO banks 12 and 13 and a regional clock from bank 12 NET 'BF_DOUT_CTP_32' U1-AN38 #> F02 #> T07 32 AN38 IO_L12P_VRN_13 NET 'BF_DOUT_CTP_33' U1-BB34 #> F04 #> T07 33 BB34 IO_L15P_12 NET 'BF_DOUT_CTP_34' U1-AN40 #> F02 #> T07 34 AN40 IO_L0P_13 NET 'BF_DOUT_CTP_35' U1-AU34 #> F02 #> T07 35 AU34 IO_L16P_12 NET 'BF_DOUT_CTP_36' U1-AP42 #> F04 #> T07 36 AP42 IO_L3P_13 NET 'BF_DOUT_CTP_37' U1-AP40 #> F05 #> T07 37 AP40 IO_L0N_13 NET 'BF_DOUT_CTP_38' U1-AN41 #> F04 #> T07 38 AN41 IO_L1P_13 NET 'BF_DOUT_CTP_39' U1-AV34 #> F03 #> T07 39 AV34 IO_L18P_12 NET 'BF_DOUT_CTP_40' U1-AV35 #> F02 #> T07 40 AV35 IO_L18N_12 NET 'BF_DOUT_CTP_41' U1-AT35 #> F02 #> T07 41 AT35 IO_L12N_VRP_12 NET 'BF_DOUT_CTP_42' U1-AP37 #> F04 #> T07 42 AP37 IO_L2P_12 NET 'BF_DOUT_CTP_43' U1-AR38 #> F05 #> T07 43 AR38 IO_L0N_12 NET 'BF_DOUT_CTP_44' U1-AP41 #> F04 #> T07 44 AP41 IO_L1N_13 NET 'BF_DOUT_CTP_45' U1-AW35 #> F03 #> T07 45 AW35 IO_L19N_12 NET 'BF_DOUT_CTP_46' U1-AV36 #> F02 #> T07 46 AV36 IO_L14N_VREF_12 NET 'BF_DOUT_CTP_47' U1-BB36 #> F02 #> T07 47 BB36 IO_L13P_12 NET 'BF_DOUT_CTP_48' U1-AR42 #> F04 #> T07 48 AR42 IO_L3N_13 NET 'BF_DOUT_CTP_49' U1-AT39 #> F05 #> T07 49 AT39 IO_L14N_VREF_13 NET 'BF_DOUT_CTP_50' U1-AR39 #> F04 #> T07 50 AR39 IO_L14P_13 NET 'BF_DOUT_CTP_51' U1-AW36 #> F09 #> T07 51 AW36 IO_L14P_12 NET 'BF_DOUT_CTP_52' U1-BA35 #> F02 #> T07 52 BA35 IO_L17P_12 NET 'BF_DOUT_CTP_53' U1-AU36 #> F02 #> T07 53 AU36 IO_L6P_12 NET 'BF_DOUT_CTP_54' U1-AR35 #> F04 #> T07 54 AR35 IO_L12P_VRN_12 NET 'BF_DOUT_CTP_55' U1-AU39 #> F03 #> T07 55 AU39 IO_L10N_MRCC_13 NET 'BF_DOUT_CTP_56' U1-AN39 #> F04 #> T07 56 AN39 IO_L2P_13 NET 'BF_DOUT_CTP_57' U1-BA37 #> F09 #> T07 57 BA37 IO_L11P_SRCC_12 NET 'BF_DOUT_CTP_58' U1-BA34 #> F02 #> T07 58 BA34 IO_L15N_12 NET 'BF_DOUT_CTP_59' U1-BB37 #> F02 #> T07 59 BB37 IO_L11N_SRCC_12 NET 'BF_DOUT_CTP_60' U1-AT42 #> F04 #> T07 60 AT42 IO_L5P_13 NET 'BF_DOUT_CTP_61' U1-AV40 #> F03 #> T07 61 AV40 IO_L19P_13 NET 'BF_DOUT_CTP_62' U1-AP38 #> F05 #> T07 62 AP38 IO_L12N_VRP_13 NET 'BF_DOUT_CTP_63' U1-AN35 #> F09 #> T07 63 AN35 IO_L9P_MRCC_12 NET 'BF_DOUT_CTP_65' U1-AY34 #> F02 #> T07 65 AY34 IO_L19P_12 ############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for the highspeed GTX Transmitters # -=============--------------------------------------------------------- # # # Base Function FPGA # ---------------------- # # # Original Rev. 16-Mar-2012 # Rev. 19-Nov-2012 Add termination resistors # Rev: 11-Dec-2012 File name changed for uniformity and consistency between Base and TP files # Rev: 31-Dec-2012 Change the net-name on the MGTAVTTRCAL_115 Calibration Resistor pin. # Rev. 16-Jan-2013 Add unused MGT transceiver pins and rename file # base_function_gtx_transceivers_n2r.txt # Rev. 14-May-2013 Rearrange the GTX Quad to MiniPOD connections to facilitate trace routing. # Most Recent Rev. 2-Oct-2013 Swap 4 Transceiver vs MiniPOD Fiber to equalize differential trace lengths. # # # Signal Nets referenced in this file: # ------------------------------------ # # 'MPn_Fpp_QUAD_qqq_TRN_r_xxx' are the net names assigned to the MGT Transmitter IO signals with: # "n" is the miniPOD device number (n=1:2 for transmitter 1:2) # "pp" is the fiber number on the minipod device (pp = 0:11) # "qqq" is the FPGA Quad number (qqq = 110:118, but only 110:115 used here) # "r" is the transmitter number on that Quad (r = 0:3) # "xxx" is the signal polarity (xxx = "DIR" for Direct aka Positive or Non-Inverted # or "CMP" for Complement aka Negative or Inverted) # ############################################################################################ # Transmitter 1 is MiniPOD device MP1 NET 'MP1_F01_QUAD_110_TRN_0_DIR' U1-BB3 # MGTTXP0_110 NET 'MP1_F01_QUAD_110_TRN_0_CMP' U1-BB4 # MGTTXN0_110 NET 'MP1_F03_QUAD_110_TRN_1_DIR' U1-BA1 # MGTTXP1_110 NET 'MP1_F03_QUAD_110_TRN_1_CMP' U1-BA2 # MGTTXN1_110 NET 'MP1_F07_QUAD_110_TRN_2_DIR' U1-AY3 # MGTTXP2_110 NET 'MP1_F07_QUAD_110_TRN_2_CMP' U1-AY4 # MGTTXN2_110 NET 'MP1_F05_QUAD_110_TRN_3_DIR' U1-AW1 # MGTTXP3_110 NET 'MP1_F05_QUAD_110_TRN_3_CMP' U1-AW2 # MGTTXN3_110 NET 'MP1_F09_QUAD_111_TRN_0_DIR' U1-AV3 # MGTTXP0_111 NET 'MP1_F09_QUAD_111_TRN_0_CMP' U1-AV4 # MGTTXN0_111 NET 'MP1_F11_QUAD_111_TRN_1_DIR' U1-AU1 # MGTTXP1_111 NET 'MP1_F11_QUAD_111_TRN_1_CMP' U1-AU2 # MGTTXN1_111 NET 'MP1_F10_QUAD_111_TRN_2_DIR' U1-AT3 # MGTTXP2_111 NET 'MP1_F10_QUAD_111_TRN_2_CMP' U1-AT4 # MGTTXN2_111 NET 'MP1_F08_QUAD_111_TRN_3_DIR' U1-AR1 # MGTTXP3_111 NET 'MP1_F08_QUAD_111_TRN_3_CMP' U1-AR2 # MGTTXN3_111 NET 'MP1_F04_QUAD_112_TRN_0_DIR' U1-AP3 # MGTTXP0_112 NET 'MP1_F04_QUAD_112_TRN_0_CMP' U1-AP4 # MGTTXN0_112 NET 'MP1_F06_QUAD_112_TRN_1_DIR' U1-AN1 # MGTTXP1_112 NET 'MP1_F06_QUAD_112_TRN_1_CMP' U1-AN2 # MGTTXN1_112 NET 'MP1_F02_QUAD_112_TRN_2_DIR' U1-AM3 # MGTTXP2_112 NET 'MP1_F02_QUAD_112_TRN_2_CMP' U1-AM4 # MGTTXN2_112 NET 'MP1_F00_QUAD_112_TRN_3_DIR' U1-AL1 # MGTTXP3_112 NET 'MP1_F00_QUAD_112_TRN_3_CMP' U1-AL2 # MGTTXN3_112 # Transmitter 2 is MiniPOD device MP2 NET 'MP2_F01_QUAD_113_TRN_0_DIR' U1-AK3 # MGTTXP0_113 NET 'MP2_F01_QUAD_113_TRN_0_CMP' U1-AK4 # MGTTXN0_113 NET 'MP2_F03_QUAD_113_TRN_1_DIR' U1-AJ1 # MGTTXP1_113 NET 'MP2_F03_QUAD_113_TRN_1_CMP' U1-AJ2 # MGTTXN1_113 NET 'MP2_F07_QUAD_113_TRN_2_DIR' U1-AH3 # MGTTXP2_113 NET 'MP2_F07_QUAD_113_TRN_2_CMP' U1-AH4 # MGTTXN2_113 NET 'MP2_F05_QUAD_113_TRN_3_DIR' U1-AG1 # MGTTXP3_113 NET 'MP2_F05_QUAD_113_TRN_3_CMP' U1-AG2 # MGTTXN3_113 NET 'MP2_F09_QUAD_114_TRN_0_DIR' U1-AE1 # MGTTXP0_114 NET 'MP2_F09_QUAD_114_TRN_0_CMP' U1-AE2 # MGTTXN0_114 NET 'MP2_F11_QUAD_114_TRN_1_DIR' U1-AC1 # MGTTXP1_114 NET 'MP2_F11_QUAD_114_TRN_1_CMP' U1-AC2 # MGTTXN1_114 NET 'MP2_F10_QUAD_114_TRN_2_DIR' U1-AA1 # MGTTXP2_114 NET 'MP2_F10_QUAD_114_TRN_2_CMP' U1-AA2 # MGTTXN2_114 NET 'MP2_F08_QUAD_114_TRN_3_DIR' U1-W1 # MGTTXP3_114 NET 'MP2_F08_QUAD_114_TRN_3_CMP' U1-W2 # MGTTXN3_114 NET 'MP2_F04_QUAD_115_TRN_0_DIR' U1-U1 # MGTTXP0_115 NET 'MP2_F04_QUAD_115_TRN_0_CMP' U1-U2 # MGTTXN0_115 NET 'MP2_F06_QUAD_115_TRN_1_DIR' U1-T3 # MGTTXP1_115 NET 'MP2_F06_QUAD_115_TRN_1_CMP' U1-T4 # MGTTXN1_115 NET 'MP2_F02_QUAD_115_TRN_2_DIR' U1-R1 # MGTTXP2_115 NET 'MP2_F02_QUAD_115_TRN_2_CMP' U1-R2 # MGTTXN2_115 NET 'MP2_F00_QUAD_115_TRN_3_DIR' U1-P3 # MGTTXP3_115 NET 'MP2_F00_QUAD_115_TRN_3_CMP' U1-P4 # MGTTXN3_115 # Now connect the GTX Termination Calibration Resistor # This is a precision 100 Ohm resistor. # See Chapter 5 page 274 of the # Virtex-6 GTX User Guide. # # The other half of these connections is in: # # ..../Everything_Else/dci_gtx_res_nets_n2p.txt # NET 'BF_MGTRREF' U1-B11 # B11 Base Function MGTRREF pin MGTRREF_115 NET 'BF_GTX_AVTT' U1-A12 # A12 Base Function MGTAVTTRCAL MGTAVTTRCAL_115 # connected to the BF_GTX_AVTT bus # as indicated in the User Guide ############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for the SFP Low-Speed DAQ & ROI Data # -=============---------------------------------------------------------- # # # This file includes the nets for: # # - the Base Function DAQ output data to SFP1 Transmitter # - the Base Function ROI output data to SFP2 Transmitter # - the S-Link Control Signals received on SFP1 SFP2 SFP3 SFP4 # # # Original Rev. 5-Dec-2012 # Rev: 11-Dec-2012 File name changed for uniformity and # consistency between Base and TP files # Rev: 16-Jan-2013 Rename nets to start with "BF_" # Most Recent Rev: 26-Apr-2013 Add the S-Link control signls received # from SFP1 SFP2 SFP3 SFP4 # # # Base Function FPGA # # DAQ and ROI Data Outputs to SFP Optical Transmitters # # SFP1 Base Function DAQ SFP Optical Output # SFP2 Base Function RIO SFP Optical Output # NET 'BF_DAQ_DATA_OUT_DIR' U1-B3 # B3 DAQ Data Output Direct MGTTXP3_118 NET 'BF_DAQ_DATA_OUT_CMP' U1-B4 # B4 DAQ Data Output Complement MGTTXN3_118 NET 'BF_ROI_DATA_OUT_DIR' U1-C1 # C1 ROI Data Output Direct MGTTXP2_118 NET 'BF_ROI_DATA_OUT_CMP' U1-C2 # C2 ROI Data Output Complement MGTTXN2_118 # # S-Link Control Singal Inputs from SFP1:SFP4 # # # SFP1 Received Data goes to Quad 117 Receiver 3 # SFP2 Received Data goes to Quad 117 Receiver 2 # SFP3 Received Data goes to Quad 117 Receiver 1 # SFP4 Received Data goes to Quad 117 Receiver 0 # NET 'SFP1_RD_DIR' U1-E5 # E5 SFP1 Receiver Data Direct MGTRXP3_117 NET 'SFP1_RD_CMP' U1-E6 # E6 SFP1 Receiver Data Complement MGTRXN3_117 NET 'SFP2_RD_DIR' U1-F7 # F7 SFP2 Receiver Data Direct MGTRXP2_117 NET 'SFP2_RD_CMP' U1-F8 # F8 SFP2 Receiver Data Complement MGTRXN2_117 NET 'SFP3_RD_DIR' U1-G5 # G5 SFP3 Receiver Data Direct MGTRXP1_117 NET 'SFP3_RD_CMP' U1-G6 # G6 SFP3 Receiver Data Complement MGTRXN1_117 NET 'SFP4_RD_DIR' U1-H7 # H7 SFP4 Receiver Data Direct MGTRXP0_117 NET 'SFP4_RD_CMP' U1-H8 # H8 SFP4 Receiver Data Complement MGTRXN0_117 ############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for the System Monitor IO signals # -=============-------------------------------------------------------- # # # Original Rev. 21-Nov-2012 Collect System Monitor signals freed from backplane input resources # Most Recent Rev: 11-Dec-2012 File name changed for uniformity and consistency between Base and TP files # # # Signal Nets referenced in this file: # ------------------------------------ # # 'BF_SYSMON_xx_P' and 'BF_SYSMON_xx_N' form the pair of pins used as system monitor inputs # The "_P" postfix is used for the positive pin and "_N" for the negative pin of the differential input. # The CMX is only able to use 12 of the 16 user inputs on the FPGA. # To help with Firmware, we keep the Virtex 6 channel numbering and end up with a # non-contiguous set of 12 channel numbers, namely xx= 2, 3, 4, 7, 8, 9, 10, 11, 12, 13, 14, 15 # # Note: Trace layer information is appended as comments below. # ----- # # NET 'BF_SYSMON_03_P' U1- #> F06 #> T01 00 H137 # # ^ ^ ^ ^ ^ # | | | | | # Tailored comment flag to help with string searches -----------------+ | | | | # | | | | # Target Trace Layer number to use for this net --------------------------+ | | | # as it exits the FPGA (to reach a via near the perimeter) | | | # F01 is top layer, F02 the first inner layer, etc | | | # | | | # Target Trace Layer number to use for this net ---------------------------------+ | | # for the long haul to the resource being monitored | | # T01 is top layer, T02 the first inner layer, etc | | # | | # Signal number is repeated to help manual entry of Pin Number ---------------------+ | # | # Target Pin Number read from paper study -----------------------------------------------+ # and cross-checked after Match_Res2Pin # ############################################################################################ # 'BF_SYSMON_00_P' This system Monitor user input is unaccessible # 'BF_SYSMON_00_N' as these pins are used for backplane inputs NET 'BF_SYSMON_01_P' U1-D16 #> F10 #> T0 00 D16 IO_L3P_SM1P_35 NET 'BF_SYSMON_01_N' U1-C16 #> F10 #> T0 00 C16 IO_L3N_SM1N_35 # 'BF_SYSMON_02_P' This system Monitor user input is unaccessible # 'BF_SYSMON_02_N' as these pins are used for backplane inputs NET 'BF_SYSMON_03_P' U1-H13 #> F06 #> T0 00 H13 IO_L6P_SM3P_35 NET 'BF_SYSMON_03_N' U1-G12 #> F06 #> T0 00 G12 IO_L6N_SM3N_35 NET 'BF_SYSMON_04_P' U1-C15 #> F06 #> T0 00 C15 IO_L7P_SM4P_35 NET 'BF_SYSMON_04_N' U1-D15 #> F06 #> T0 00 D15 IO_L7N_SM4N_35 # 'BF_SYSMON_05_P' This system Monitor user input is unaccessible # 'BF_SYSMON_05_N' as these pins are used for backplane inputs # 'BF_SYSMON_06_P' This system Monitor user input is unaccessible # 'BF_SYSMON_06_N' as these pins are used for backplane inputs NET 'BF_SYSMON_07_P' U1-C13 #> F10 #> T0 00 C13 IO_L15P_SM7P_35 NET 'BF_SYSMON_07_N' U1-D12 #> F10 #> T0 00 D12 IO_L15N_SM7N_35 NET 'BF_SYSMON_08_P' U1-AE33 #> F07 #> T0 00 AE33 IO_L2P_SM8P_15 NET 'BF_SYSMON_08_N' U1-AD33 #> F07 #> T0 00 AD33 IO_L2N_SM8N_15 NET 'BF_SYSMON_09_P' U1-AB39 #> F05 #> T0 00 AB39 IO_L3P_SM9P_15 NET 'BF_SYSMON_09_N' U1-AA40 #> F05 #> T0 00 AA40 IO_L3N_SM9N_15 NET 'BF_SYSMON_10_P' U1-AA41 #> F07 #> T0 00 AA41 IO_L5P_SM10P_15 NET 'BF_SYSMON_10_N' U1-AB41 #> F07 #> T0 00 AB41 IO_L5N_SM10N_15 NET 'BF_SYSMON_11_P' U1-AD38 #> F04 #> T0 00 AD38 IO_L6N_SM11N_15 NET 'BF_SYSMON_11_N' U1-AE38 #> F04 #> T0 00 AE38 IO_L6P_SM11P_15 NET 'BF_SYSMON_12_P' U1-AA42 #> F09 #> T0 00 AA42 IO_L7P_SM12P_15 NET 'BF_SYSMON_12_N' U1-AB42 #> F09 #> T0 00 AB42 IO_L7N_SM12N_15 NET 'BF_SYSMON_13_P' U1-AB32 #> F02 #> T0 00 AB32 IO_L12P_SM13P_15 NET 'BF_SYSMON_13_N' U1-AB33 #> F02 #> T0 00 AB33 IO_L12N_SM13N_15 NET 'BF_SYSMON_14_P' U1-AC40 #> F09 #> T0 00 AC40 IO_L13P_SM14P_15 NET 'BF_SYSMON_14_N' U1-AD40 #> F09 #> T0 00 AD40 IO_L13N_SM14N_15 NET 'BF_SYSMON_15_P' U1-AD42 #> F02 #> T0 00 AD42 IO_L15P_SM15P_15 NET 'BF_SYSMON_15_N' U1-AE42 #> F02 #> T0 00 AE42 IO_L15N_SM15N_15 ############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for the On-Card VME bus signals # -=============------------------------------------------------------ # # # Original Rev. 13-Sep-2012 # Rev: 17-Sep-2012 Arbitrary temporary assignement # Rev: 19-Nov-2012 Re-do breakout strategy and Add Goeographic Address signals. # Pick the quietest lines to share IO bank 13 with CTP output # Rev. 30-Nov-2012 Studying the set of unused pins generated 1 allocation improvement here # Rev: 11-Dec-2012 File name changed for uniformity and consistency between Base and TP files # Rev: 14-Jan-2013 Edit header comments and tentatively set comments to specify layer 7 for vertical run # Rev: 30-May-2013 Fix order of geographic address lines # Most Recent Rev: 03-Jun-2013 swap pins for OCB_GEO_ADRS_1 and _3 to avoid additional via # # # # Signal Nets referenced in this file: # ------------------------------------ # # 'OCB_Axx' are the On-Card Bus Address lines to the Base FPGA with xx=01 to 23 # (note there is no "A00" signal) # # 'OCB_Dyy' are the On-Card Bus Data lines to the Base FPGA with yy=00 to 15 # # 'OCB_GEO_ADRS_z' are the On-Card Bus Geographic Section Address lines with z=0 to 6 # # # 'OCB_SYS_RESET_B' is the On-Card Bus VME SYS_RESET signal # The "_B" postfix is used to indicate that the reset request is active # when the electrical signal is low # # 'OCB_DS_B' is the On-Card Bus Data strobe. # The "_B" postfix is used to indicate that the data strobe signal is on the # falling edge of the electrical signal. # # 'OCB_WRITE_B' is the On-Card Bus Data Direction # The "_B" postfix is used to indicate that the Write direction is # requested when the electrical signal is low. # # # IO Banks used # ------------- # # Most signal nets are assigned to IO Bank 14 and a few to Io Bank 13 # - All address line nets are in IO Bank 14 # - All data line nets are in IO Bank 14 # - The Data Strobe net is assigned to a regional clock pin in IO Bank 14 # - The Board Select net is assigned to a regional clock pin in IO Bank 13 # - The Write Net is assigned to an IO input pin in Bank 13 # - The Sys_Reset net is assigned to an IO input pin in Bank 13 # # The bulk of IO Bank 13 is used for the CTP output signals # # Note: Trace layer information is appended as comments below. # ----- # # NET 'OCB_A01' U1- #> F06 #> T07 A01 AM41 # # ^ ^ ^ ^ ^ # | | | | | # Tailored comment flag to help with string searches ------------------+ | | | | # | | | | # Target Trace Layer number to use for this net --------------------------+ | | | # as it exits the FPGA (to reach a nearby via) | | | # F01 is top layer, F02 the first inner layer, etc | | | # | | | # Target Trace Layer number to use for this net ---------------------------------+ | | # as it connects the VME bus transceiver section to the two FPGAs | | # T01 is top layer, T02 the first inner layer, etc | | # | | # Signal number is repeated to help manual entry of Pin Number ---------------------+ | # | # Target Pin Number read from paper drawing ---------------------------------------------+ # and cross-checked after Match_Res2Pin # ############################################################################################ # The lower Address (1:20), all Data, the Data Strobe, Direction and SysReset signals are in IO Bank 14 # The data strobe is assigned to a regional clock input pin (but probably not used as a clock) NET 'OCB_A01' U1-AM41 #> F06 #> T07 A01 AM41 IO_L15N_14 NET 'OCB_A02' U1-AM42 #> F06 #> T07 A02 AM42 IO_L13N_14 NET 'OCB_A03' U1-AL41 #> F06 #> T07 A03 AL41 IO_L15P_14 NET 'OCB_A04' U1-AL42 #> F06 #> T07 A04 AL42 IO_L13P_14 NET 'OCB_A05' U1-AK40 #> F06 #> T07 A05 AK40 IO_L17P_14 NET 'OCB_A06' U1-AK42 #> F06 #> T07 A06 AK42 IO_L7N_14 NET 'OCB_A07' U1-AJ41 #> F06 #> T07 A07 AJ41 IO_L5N_14 NET 'OCB_A08' U1-AJ42 #> F06 #> T07 A08 AJ42 IO_L7P_14 NET 'OCB_A09' U1-AH40 #> F06 #> T07 A09 AH40 IO_L5P_14 NET 'OCB_A10' U1-AH41 #> F06 #> T07 A10 AH41 IO_L3N_14 NET 'OCB_A11' U1-AG42 #> F06 #> T07 A11 AG42 IO_L3P_14 NET 'OCB_A12' U1-AG38 #> F06 #> T07 A12 AG38 IO_L4P_14 NET 'OCB_A13' U1-AJ36 #> F03 #> T07 A13 AJ36 IO_L12P_VRN_14 NET 'OCB_A14' U1-AH36 #> F03 #> T07 A14 AH36 IO_L14N_VREF_14 NET 'OCB_A15' U1-AG34 #> F03 #> T07 A15 AG34 IO_L0P_14 NET 'OCB_A16' U1-AF35 #> F03 #> T07 A16 AF35 IO_L16P_14 NET 'OCB_A17' U1-AL40 #> F05 #> T07 A17 AL40 IO_L17N_14 NET 'OCB_A18' U1-AK38 #> F05 #> T07 A18 AK38 IO_L8P_SRCC_14 NET 'OCB_A19' U1-AJ40 #> F05 #> T07 A19 AJ40 IO_L11N_SRCC_14 NET 'OCB_A20' U1-AH39 #> F05 #> T07 A20 AH39 IO_L11P_SRCC_14 NET 'OCB_D00' U1-AF34 #> F02 #> T07 D00 AF34 IO_L0N_14 NET 'OCB_D01' U1-AG33 #> F02 #> T07 D01 AG33 IO_L18N_14 NET 'OCB_D02' U1-AH35 #> F02 #> T07 D02 AH35 IO_L12N_VRP_14 NET 'OCB_D03' U1-AJ35 #> F02 #> T07 D03 AJ35 IO_L9N_MRCC_14 NET 'OCB_D04' U1-AF36 #> F04 #> T07 D04 AF36 IO_L16N_14 NET 'OCB_D05' U1-AG36 #> F04 #> T07 D05 AG36 IO_L14P_14 NET 'OCB_D06' U1-AH38 #> F04 #> T07 D06 AH38 IO_L4N_VREF_14 NET 'OCB_D07' U1-AJ38 #> F04 #> T07 D07 AJ38 IO_L8N_SRCC_14 NET 'OCB_D08' U1-AK37 #> F04 #> T07 D08 AK37 IO_L10N_MRCC_14 NET 'OCB_D09' U1-AL39 #> F04 #> T07 D09 AL39 IO_L19N_14 NET 'OCB_D10' U1-AF39 #> F05 #> T07 D10 AF39 IO_L2P_14 NET 'OCB_D11' U1-AF37 #> F05 #> T07 D11 AF37 IO_L6P_14 NET 'OCB_D12' U1-AG37 #> F05 #> T07 D12 AG37 IO_L6N_14 NET 'OCB_D13' U1-AF40 #> F09 #> T07 D13 AF40 IO_L1P_14 NET 'OCB_D14' U1-AG41 #> F09 #> T07 D14 AG41 IO_L1N_14 NET 'OCB_D15' U1-AG39 #> F09 #> T07 D15 AG39 IO_L2N_14 NET 'OCB_SYS_RESET_B' U1-AK39 #> F09 #> T07 RES AK39 IO_L19P_14 NET 'OCB_WRITE_B' U1-AJ37 #> F09 #> T07 WRI AJ37 IO_L10P_MRCC_14 NET 'OCB_DS_B' U1-AH34 #> F09 #> T07 DS AH34 IO_L9P_MRCC_14 # The upper Address (21:23), and all Geographic Address signals are in IO Bank 13 # as these signals are static or thought to change less often and will probably # minimize interaction with the CTP output also using Bank 13. NET 'OCB_A21' U1-AM34 #> F02 #> T07 A21 AM34 IO_L6P_13 NET 'OCB_A22' U1-AL36 #> F02 #> T07 A22 AL36 IO_L18N_13 NET 'OCB_A23' U1-AK34 #> F02 #> T07 A23 AK34 IO_L9N_MRCC_13 NET 'OCB_GEO_ADRS_0' U1-AM37 #> F03 #> T07 GA0 AM37 IO_L16P_13 NET 'OCB_GEO_ADRS_1' U1-AM36 #> F03 #> T07 GA1 AM36 IO_L16N_13 NET 'OCB_GEO_ADRS_2' U1-AL37 #> F03 #> T07 GA2 AL37 IO_L4P_13 NET 'OCB_GEO_ADRS_3' U1-AK35 #> F04 #> T07 GA3 AK35 IO_L18P_13 NET 'OCB_GEO_ADRS_4' U1-AM38 #> F05 #> T07 GA4 AM38 IO_L4N_VREF_13 NET 'OCB_GEO_ADRS_5' U1-AL35 #> F09 #> T07 GA5 AL35 IO_L6N_13 NET 'OCB_GEO_ADRS_6' U1-AM39 #> F09 #> T07 GA6 AM39 IO_L2N_13 ############################################################################################ # # CMX Net-to-Resource File # -------------------------- # # # Clock Connections to the Base Function FPGA # ----------------------------=============------- # # # # Original Rev. 24-AUG-2012 # Rev. 26-Nov-2012 # Rev: 11-Dec-2012 File name changed for uniformity and consistency between Base and TP files # Rev: 26-Dec-2012 Change "Clk" in net_names to "CLK". # Rev: 29-Dec-2012 Remove the JTAG nets from this file. Remove "jtag" from the filename. # Rev: 16-Jan-2013 Change "Not_Used_" to "No_Conn_". # Rev: 28-Mar-2013 Add third logic global clock # Most Recent Rev: 2-May-2013 Change Logic and GTX clock net names to # reflect the 40.08 or 320.64 MHz LHC clocks # and the 40.000 or 100.000 MHz Crystal clocks # # # Base Function FPGA Clocks for Logic and Transceivers # ---------------------======---------------------------- # # # LHC Locked Logic Clocks # # Connect the 40.08 MHz and 320.64 MHz Logic Clocks to # the Base Function FPGA. These are LHC locked LVDS clock # signals to the Logic in the Base Function FPGA. # # A Global Clock input in I/O Bank 34 receives the DeSkew #1 40.08 MHz Logic clock. # # A Global Clock input in I/O Bank 25 receives the DeSkew #2 40.08 MHz Logic clock. # # A Global Clock input in I/O Bank 34 receives the 320.64 MHz Logic clock. # NET 'CLK_40MHz08_DSKW_1_BF_LOGIC_DIR' U1-AY14 # AY14 40.08 MHz DeSkew-1 LHC Logic IO_L0P_GC_34 NET 'CLK_40MHz08_DSKW_1_BF_LOGIC_CMP' U1-AY13 # AY13 Clk to the Base Function FPGA IO_L0N_GC_34 NET 'CLK_40MHz08_DSKW_2_BF_LOGIC_DIR' U1-J42 # J42 40.08 MHz DeSkew-2 LHC Logic IO_L18P_GC_25 NET 'CLK_40MHz08_DSKW_2_BF_LOGIC_CMP' U1-K42 # K42 Clk to the Base Function FPGA IO_L18N_GC_25 NET 'CLK_320MHz64_LHC_BF_LOGIC_DIR' U1-AP12 # AP12 320.64 MHz LHC Logic Clock IO_L1N_GC_34 NET 'CLK_320MHz64_LHC_BF_LOGIC_CMP' U1-AP11 # AP11 to the Base Function FPGA IO_L1P_GC_34 # # Crystal Oscillator #1 GTX Clock # # Now to the Base Function FPGA connect the 40.000 MHz # Crystal Oscillator #1 LVPECL clock to the clock "0" # input of the GTX Transceiver Quad 118. # # This is the "G-Link" transciever for DAQ and RIO readout. # NET 'CLK_40MHz000_XTAL_1_BF_TRNCV_DIR' U1-C10 # C10 40.000 MHz Crystal Osc #1 MGTREFCLK0P_118 NET 'CLK_40MHz000_XTAL_1_BF_TRNCV_CMP' U1-C9 # C9 GTX Clk to the BF FPGA MGTREFCLK0N_118 # # Crystal Oscillator #2 GTX Clock # # Now to the Base Function FPGA connect the 40.000 MHz # or 100.000 Mhz Crystal Oscillator #2 LVPECL clock to # the clock "0" input of the GTX Transceiver Quad 117. # # This is the clock to the GTX Transcievers that receive # data from the 4 SFP optical components and thus may be # used to receive S-Link control information. # NET 'CLK_100MHz000_XTAL_2_BF_TRNCV_DIR' U1-G10 # G10 100.000 MHz Crystal Osc #2 MGTREFCLK0P_117 NET 'CLK_100MHz000_XTAL_2_BF_TRNCV_CMP' U1-G9 # G9 GTX Clk to the BF FPGA MGTREFCLK0N_117 # This could also be 40.000 MHz # # LHC Locked GTX Clocks # # Now on the Base Function FPGA connect the 320.64 MHz # LHC locked LVPECL clocks to the clock inputs for # the GTX Transceivers. # # We will use the "0" clock inputs to the Quad Banks # 111 and 114 to receive these Transceiver clocks. # These are the Base Function GTX Transceivers that # send out 6.4 Gbps data to the L1Topo system. # NET 'CLK_320MHz64_LHC_BF_QUAD_111_DIR' U1-AU10 # AU10 320.64 MHz LHC GTX Clk #1 MGTREFCLK0P_111 NET 'CLK_320MHz64_LHC_BF_QUAD_111_CMP' U1-AU9 # AU9 to the Base Function FPGA MGTREFCLK0N_111 NET 'CLK_320MHz64_LHC_BF_QUAD_114_DIR' U1-AB8 # AB8 320.64 MHz LHC GTX Clk #2 MGTREFCLK0P_114 NET 'CLK_320MHz64_LHC_BF_QUAD_114_CMP' U1-AB7 # AB7 to the Base Function FPGA MGTREFCLK0N_114 # # Now on the Base Function FPGA connect ALL of the # UN-Used Tranceiver Clock Inputs to single point nets. # # Not Used Bank 110 Clock Inputs NET 'No_Conn_BF_GTX_CLK_0_110_DIR' U1-BA10 # pin BA10 MGTREFCLK0P_110 NET 'No_Conn_BF_GTX_CLK_0_110_CMP' U1-BA9 # pin BA9 MGTREFCLK0N_110 NET 'No_Conn_BF_GTX_CLK_1_110_DIR' U1-AW10 # pin AW10 MGTREFCLK1P_110 NET 'No_Conn_BF_GTX_CLK_1_110_CMP' U1-AW9 # pin AW9 MGTREFCLK1N_110 # Not Used Bank 111 Clock Input NET 'No_Conn_BF_GTX_CLK_1_111_DIR' U1-AT8 # pin AT8 MGTREFCLK1P_111 NET 'No_Conn_BF_GTX_CLK_1_111_CMP' U1-AT7 # pin AT7 MGTREFCLK1N_111 # Not Used Bank 112 Clock Inputs NET 'No_Conn_BF_GTX_CLK_0_112_DIR' U1-AK8 # pin AK8 MGTREFCLK0P_112 NET 'No_Conn_BF_GTX_CLK_0_112_CMP' U1-AK7 # pin AK7 MGTREFCLK0N_112 NET 'No_Conn_BF_GTX_CLK_1_112_DIR' U1-AH8 # pin AH8 MGTREFCLK1P_112 NET 'No_Conn_BF_GTX_CLK_1_112_CMP' U1-AH7 # pin AH7 MGTREFCLK1N_112 # Not Used Bank 113 Clock Inputs NET 'No_Conn_BF_GTX_CLK_0_113_DIR' U1-AF8 # pin AF8 MGTREFCLK0P_113 NET 'No_Conn_BF_GTX_CLK_0_113_CMP' U1-AF7 # pin AF7 MGTREFCLK0N_113 NET 'No_Conn_BF_GTX_CLK_1_113_DIR' U1-AD8 # pin AD8 MGTREFCLK1P_113 NET 'No_Conn_BF_GTX_CLK_1_113_CMP' U1-AD7 # pin AD7 MGTREFCLK1N_113 # Not Used Bank 114 Clock Input NET 'No_Conn_BF_GTX_CLK_1_114_DIR' U1-Y8 # pin Y8 MGTREFCLK1P_114 NET 'No_Conn_BF_GTX_CLK_1_114_CMP' U1-Y7 # pin Y7 MGTREFCLK1N_114 # Not Used Bank 115 Clock Inputs NET 'No_Conn_BF_GTX_CLK_0_115_DIR' U1-V8 # pin V8 MGTREFCLK0P_115 NET 'No_Conn_BF_GTX_CLK_0_115_CMP' U1-V7 # pin V7 MGTREFCLK0N_115 NET 'No_Conn_BF_GTX_CLK_1_115_DIR' U1-T8 # pin T8 MGTREFCLK1P_115 NET 'No_Conn_BF_GTX_CLK_1_115_CMP' U1-T7 # pin T7 MGTREFCLK1N_115 # Not Used Bank 116 Clock Inputs NET 'No_Conn_BF_GTX_CLK_0_116_DIR' U1-M8 # pin M8 MGTREFCLK0P_116 NET 'No_Conn_BF_GTX_CLK_0_116_CMP' U1-M7 # pin M7 MGTREFCLK0N_116 NET 'No_Conn_BF_GTX_CLK_1_116_DIR' U1-K8 # pin K8 MGTREFCLK1P_116 NET 'No_Conn_BF_GTX_CLK_1_116_CMP' U1-K7 # pin K7 MGTREFCLK1N_116 # Not Used Bank 117 Clock Input NET 'No_Conn_BF_GTX_CLK_1_117_DIR' U1-E10 # pin E10 MGTREFCLK1P_117 NET 'No_Conn_BF_GTX_CLK_1_117_CMP' U1-E9 # pin E9 MGTREFCLK1N_117 # Not Used Bank 118 Clock Input NET 'No_Conn_BF_GTX_CLK_1_118_DIR' U1-A10 # pin A10 MGTREFCLK1P_118 NET 'No_Conn_BF_GTX_CLK_1_118_CMP' U1-A9 # pin A9 MGTREFCLK1N_118 ############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for the connections to the TTC signals # -=============------------------------------------------================== # # # Original Rev. 28-Mar-2012 # Most Recent Rev. 28-Mar-2013 find location for these 2x signals without interfering with backplane inputs # # Signal Nets referenced in this file: # ------------------------------------ # # BUF_TTC_L1_ACCEPT Buffered and series terminated copy of TTCdec L1 Accept signal # # BUF_TTC_BNCH_CNT_RES Buffered and series terminated copy of TTCdec Bunch Count Reset signal # ############################################################################################ # 2x signals are connecting to the buffered version of the TTCdec signals NET 'BUF_TTC_L1_ACCEPT' U1-H39 #> F05 #> T06 H39 IO_L6P_25 NET 'BUF_TTC_BNCH_CNT_RES' U1-K40 #> F05 #> T06 K40 IO_L16N_VRP_25 # Note: One global clock from this IO Bank is also used cf. base_function_22_clocks_n2r.txt # Note: Two differential signals from this IO Bank are also used cf. base_function_24_to_tp_fpga_n2r.txt ############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for the connections to the TP FPGA # -=============------------------------------------------================ # # Original Rev. 02-Apr-2012 # Most Recent Rev. 02-Apr-2013 find location for these signals whithout interfering with other signals # # BF to TP connections for support of S-link return channels # ========----------------------------====================== # # If the TP function needs to support S-link protocol (rather than G-link) # the CMX will need to receive the return channel of the Duplex S-link. # # The SFP optical receiver from the 2x S-link connections (DAQ and ROI) # cannot be directly received in the TP FPGA because all 36x MGT receivers # of the TP FPGA are already used with the 3x12 Avago optical receivers. # # The SFP optical receivers are instead routed to MGT receivers located # on the BF FPGA and the serial signal received is sent from the BF FPGA # to the TP FPGA via two differential Select IO signals. # # Signal Nets referenced in this file: # ------------------------------------ # # BF_TO_TP_DAQ_SLINK_RETURN_DIR Direct signal # BF_TO_TP_DAQ_SLINK_RETURN_CMP Complement signal # for the return S-link channel for DAQ readout # # BF_TO_TP_ROI_SLINK_RETURN_DIR Direct signal # BF_TO_TP_ROI_SLINK_RETURN_CMP Complement signal # for the return S-link channel for ROI readout # ############################################################################################ # 4x Select IO pins forming 2x differential signals going to the TP FPGA # This is IO Bank 25 and the signals will be routed south on trace layer 6. NET 'BF_TO_TP_DAQ_SLINK_RETURN_DIR' U1-H40 #> F05 #> T06 H40 IO_L12P_25 NET 'BF_TO_TP_DAQ_SLINK_RETURN_CMP' U1-H41 #> F05 #> T06 H41 IO_L12N_25 NET 'BF_TO_TP_ROI_SLINK_RETURN_DIR' U1-J40 #> F07 #> T06 J40 IO_L14P_25 NET 'BF_TO_TP_ROI_SLINK_RETURN_CMP' U1-J41 #> F07 #> T06 J41 IO_L14N_VREF_25 # Note: One global clock from this IO Bank is also used cf. base_function_22_clocks_n2r.txt # Note: Two pins from this IO Bank are also used for TTC cf. base_function_23_ttc_connections_n2r.txt ############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for the connections to the Board Support FPGA # -=============------------------------------------------========================== # # # Original Rev. 28-Mar-2012 # Rev. 28-Mar-2013 find location for these 18x signals without interfering with backplane inputs # Most Recent Rev: 30-May-2013 BF to BSPT connections were re-arranged after the layout of the backplane inputs # # Signal Nets referenced in this file: # ------------------------------------ # # BF_REQ_CTP_n_INPUT (n=1:2) 2x direction request for CTP cable n sent to BSPT FPGA # # BF_REQ_CABLE_n_INPUT (n=1:3) 3x direction request for Merger Cable n sent to BSPT FPGA # # BF_LED_REQ_n (n=0:4) 5x LED state request sent to BSPT FPGA # # BF_TO_FROM_BSPT_n (n=0:7) 8x un-assigned Input or Ouput connections to BSPT FPGA # ############################################################################################ # 18x signals are going to the Board Support FPGA on layer 7 # These signals are listed in west to east order as they leave the FPGA area on layer 7 # The middle 8 signals first reach a row of vias on layer 1 or 6 and exit on layer 7 NET 'BF_REQ_CTP_1_INPUT' U1-N19 #> F07 #> T07 N19 IO_L9N_MRCC_38 NET 'BF_REQ_CTP_2_INPUT' U1-N20 #> F07 #> T07 N20 IO_L19N_38 NET 'BF_REQ_CABLE_1_INPUT' U1-P21 #> F07 #> T07 P21 IO_L18P_38 NET 'BF_REQ_CABLE_2_INPUT' U1-P22 #> F07 #> T07 P22 IO_L18N_38 NET 'BF_REQ_CABLE_3_INPUT' U1-K23 #> F07 #> T07 K23 IO_L8N_SRCC_38 NET 'BF_LED_REQ_0' U1-G24 #> F07 #> T07 G24 IO_L0N_38 NET 'BF_LED_REQ_1' U1-F25 #> F07 #> T07 F25 IO_L2P_38 NET 'BF_LED_REQ_2' U1-A25 #> F01 #> T07 A25 IO_L11N_SRCC_38 NET 'BF_LED_REQ_3' U1-C25 #> F01 #> T07 C25 IO_L15N_38 NET 'BF_LED_REQ_4' U1-F24 #> F01 #> T07 F24 IO_L2N_38 NET 'BF_TO_FROM_BSPT_0' U1-A26 #> F06 #> T07 A26 IO_L11P_SRCC_38 NET 'BF_TO_FROM_BSPT_1' U1-B26 #> F06 #> T07 B26 IO_L15P_38 NET 'BF_TO_FROM_BSPT_2' U1-D25 #> F01 #> T07 D25 IO_L17P_38 NET 'BF_TO_FROM_BSPT_3' U1-A27 #> F01 #> T07 A27 IO_L7N_38 NET 'BF_TO_FROM_BSPT_4' U1-F26 #> F01 #> T07 F26 IO_L5N_38 NET 'BF_TO_FROM_BSPT_5' U1-E25 #> F07 #> T07 E25 IO_L17N_38 NET 'BF_TO_FROM_BSPT_6' U1-D26 #> F07 #> T07 D26 IO_L13N_38 NET 'BF_TO_FROM_BSPT_7' U1-E27 #> F07 #> T07 E27 IO_L1P_38 # note: other Select IO pins on IO Bank 38 are used for connections to the debug connector # cf. base_function_26_debug_connections_n2r.txt ############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for the connections to the Debug Connector # -=============------------------------------------------====================== # # # Original Rev. 28-Mar-2012 # Rev. 28-Mar-2013 find location for these 10x signals without interfering with backplane inputs # Rev: 30-May-2013 BF debug connections were re-arranged after the layout of the backplane inputs # Most Recent Rev: 10-Jul-2013 Reorder pin assignment for straight route near debug connector # # Signal Nets referenced in this file: # ------------------------------------ # # BF_DEBUG_n (n=0:9) 10x spare connections from the BF FPGA to debug connector J14 # ############################################################################################ # 10x signals are going to the Debug Connector on layer 6 # These signals are listed in west to east order as they come out of the FPGA on layer 6 # The order of the BF_DEBUG_n nets may be adjusted to optimize access near J14 NET 'BF_DEBUG_0' U1-B27 #> F06 #> T06 B27 IO_L7P_38 NET 'BF_DEBUG_1' U1-M21 #> F06 #> T06 M21 IO_L10N_MRCC_38 NET 'BF_DEBUG_2' U1-C26 #> F06 #> T06 C26 IO_L13P_38 NET 'BF_DEBUG_3' U1-N21 #> F06 #> T06 N21 IO_L10P_MRCC_38 NET 'BF_DEBUG_4' U1-D27 #> F06 #> T06 D27 IO_L1N_38 NET 'BF_DEBUG_5' U1-M19 #> F06 #> T06 M19 IO_L9P_MRCC_38 NET 'BF_DEBUG_6' U1-C28 #> F06 #> T06 C28 IO_L3P_38 NET 'BF_DEBUG_7' U1-M22 #> F06 #> T06 M22 IO_L14P_38 NET 'BF_DEBUG_8' U1-B28 #> F06 #> T06 B28 IO_L3N_38 NET 'BF_DEBUG_9' U1-J23 #> F06 #> T06 J23 IO_L8P_SRCC_38 # note: other Select IO pins on IO Bank 38 are used for connections to the BSPT FPGA # cf. base_function_25_bspt_connections_n2r.txt ############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals used for all unused and Not Connected MGT IO pins # -=============-----------------------------------------====================---------- # # # Original Rev. 16-Jan-2013 All 1760 pins on the Base function FPGA will have a net assigned # # Rev. 26-Apr-2013 The Quad 117 Receiver inputs are now used # for the 4 used for SFP Receiver signals. # # # # On the Base Function FPGA connect ALL of the # UN-Used Tranceiver IO Pins to single point nets. # # Signal Nets referenced in this file: # ------------------------------------ # # 'No_Conn_BF_xxxx' are the unique net names assigned to these MGT IO signals # where "xxxx" is the fpga MGT IO signal name # ############################################################################################ ################ # Receivers ################ # All Receiver Channels from MGT Quad 110 are unused NET 'No_Conn_BF_MGTRXP0_110' U1-BB7 # 110 BB7 MGTRXP0_110 NET 'No_Conn_BF_MGTRXN0_110' U1-BB8 # 110 BB8 MGTRXN0_110 NET 'No_Conn_BF_MGTRXP1_110' U1-BA5 # 110 BA5 MGTRXP1_110 NET 'No_Conn_BF_MGTRXN1_110' U1-BA6 # 110 BA6 MGTRXN1_110 NET 'No_Conn_BF_MGTRXP2_110' U1-AY7 # 110 AY7 MGTRXP2_110 NET 'No_Conn_BF_MGTRXN2_110' U1-AY8 # 110 AY8 MGTRXN2_110 NET 'No_Conn_BF_MGTRXP3_110' U1-AW5 # 110 AW5 MGTRXP3_110 NET 'No_Conn_BF_MGTRXN3_110' U1-AW6 # 110 AW6 MGTRXN3_110 # All Receiver Channels from MGT Quad 111 are unused NET 'No_Conn_BF_MGTRXP0_111' U1-AV7 # 111 AV7 MGTRXP0_111 NET 'No_Conn_BF_MGTRXN0_111' U1-AV8 # 111 AV8 MGTRXN0_111 NET 'No_Conn_BF_MGTRXP1_111' U1-AU5 # 111 AU5 MGTRXP1_111 NET 'No_Conn_BF_MGTRXN1_111' U1-AU6 # 111 AU6 MGTRXN1_111 NET 'No_Conn_BF_MGTRXP2_111' U1-AR5 # 111 AR5 MGTRXP2_111 NET 'No_Conn_BF_MGTRXN2_111' U1-AR6 # 111 AR6 MGTRXN2_111 NET 'No_Conn_BF_MGTRXP3_111' U1-AP7 # 111 AP7 MGTRXP3_111 NET 'No_Conn_BF_MGTRXN3_111' U1-AP8 # 111 AP8 MGTRXN3_111 # All Receiver Channels from MGT Quad 112 are unused NET 'No_Conn_BF_MGTRXP0_112' U1-AN5 # 112 AN5 MGTRXP0_112 NET 'No_Conn_BF_MGTRXN0_112' U1-AN6 # 112 AN6 MGTRXN0_112 NET 'No_Conn_BF_MGTRXP1_112' U1-AM7 # 112 AM7 MGTRXP1_112 NET 'No_Conn_BF_MGTRXN1_112' U1-AM8 # 112 AM8 MGTRXN1_112 NET 'No_Conn_BF_MGTRXP2_112' U1-AL5 # 112 AL5 MGTRXP2_112 NET 'No_Conn_BF_MGTRXN2_112' U1-AL6 # 112 AL6 MGTRXN2_112 NET 'No_Conn_BF_MGTRXP3_112' U1-AJ5 # 112 AJ5 MGTRXP3_112 NET 'No_Conn_BF_MGTRXN3_112' U1-AJ6 # 112 AJ6 MGTRXN3_112 # All Receiver Channels from MGT Quad 113 are unused NET 'No_Conn_BF_MGTRXP0_113' U1-AG5 # 113 AG5 MGTRXP0_113 NET 'No_Conn_BF_MGTRXN0_113' U1-AG6 # 113 AG6 MGTRXN0_113 NET 'No_Conn_BF_MGTRXP1_113' U1-AF3 # 113 AF3 MGTRXP1_113 NET 'No_Conn_BF_MGTRXN1_113' U1-AF4 # 113 AF4 MGTRXN1_113 NET 'No_Conn_BF_MGTRXP2_113' U1-AE5 # 113 AE5 MGTRXP2_113 NET 'No_Conn_BF_MGTRXN2_113' U1-AE6 # 113 AE6 MGTRXN2_113 NET 'No_Conn_BF_MGTRXP3_113' U1-AD3 # 113 AD3 MGTRXP3_113 NET 'No_Conn_BF_MGTRXN3_113' U1-AD4 # 113 AD4 MGTRXN3_113 NET 'No_Conn_BF_MGTRXP0_114' U1-AC5 # 114 AC5 MGTRXP0_114 # All Receiver Channels from MGT Quad 114 are unused NET 'No_Conn_BF_MGTRXN0_114' U1-AC6 # 114 AC6 MGTRXN0_114 NET 'No_Conn_BF_MGTRXP1_114' U1-AB3 # 114 AB3 MGTRXP1_114 NET 'No_Conn_BF_MGTRXN1_114' U1-AB4 # 114 AB4 MGTRXN1_114 NET 'No_Conn_BF_MGTRXP2_114' U1-AA5 # 114 AA5 MGTRXP2_114 NET 'No_Conn_BF_MGTRXN2_114' U1-AA6 # 114 AA6 MGTRXN2_114 NET 'No_Conn_BF_MGTRXP3_114' U1-Y3 # 114 Y3 MGTRXP3_114 NET 'No_Conn_BF_MGTRXN3_114' U1-Y4 # 114 Y4 MGTRXN3_114 NET 'No_Conn_BF_MGTRXP0_115' U1-W5 # 115 W5 MGTRXP0_115 # All Receiver Channels from MGT Quad 115 are unused NET 'No_Conn_BF_MGTRXN0_115' U1-W6 # 115 W6 MGTRXN0_115 NET 'No_Conn_BF_MGTRXP1_115' U1-V3 # 115 V3 MGTRXP1_115 NET 'No_Conn_BF_MGTRXN1_115' U1-V4 # 115 V4 MGTRXN1_115 NET 'No_Conn_BF_MGTRXP2_115' U1-U5 # 115 U5 MGTRXP2_115 NET 'No_Conn_BF_MGTRXN2_115' U1-U6 # 115 U6 MGTRXN2_115 NET 'No_Conn_BF_MGTRXP3_115' U1-R5 # 115 R5 MGTRXP3_115 NET 'No_Conn_BF_MGTRXN3_115' U1-R6 # 115 R6 MGTRXN3_115 # All Receiver Channels from MGT Quad 116 are unused NET 'No_Conn_BF_MGTRXP0_116' U1-P7 # 116 P7 MGTRXP0_116 NET 'No_Conn_BF_MGTRXN0_116' U1-P8 # 116 P8 MGTRXN0_116 NET 'No_Conn_BF_MGTRXP1_116' U1-N5 # 116 N5 MGTRXP1_116 NET 'No_Conn_BF_MGTRXN1_116' U1-N6 # 116 N6 MGTRXN1_116 NET 'No_Conn_BF_MGTRXP2_116' U1-L5 # 116 L5 MGTRXP2_116 NET 'No_Conn_BF_MGTRXN2_116' U1-L6 # 116 L6 MGTRXN2_116 NET 'No_Conn_BF_MGTRXP3_116' U1-J5 # 116 J5 MGTRXP3_116 NET 'No_Conn_BF_MGTRXN3_116' U1-J6 # 116 J6 MGTRXN3_116 # All Receiver Channels in MGT Quad 117 are # now used for the SFP Receiver signals. ##NET 'No_Conn_BF_MGTRXP0_117' U1- # 117 H7 ##NET 'No_Conn_BF_MGTRXN0_117' U1- # 117 H8 ##NET 'No_Conn_BF_MGTRXP1_117' U1- # 117 G5 ##NET 'No_Conn_BF_MGTRXN1_117' U1- # 117 G6 ##NET 'No_Conn_BF_MGTRXP2_117' U1- # 117 F7 ##NET 'No_Conn_BF_MGTRXN2_117' U1- # 117 F8 ##NET 'No_Conn_BF_MGTRXP3_117' U1- # 117 E5 ##NET 'No_Conn_BF_MGTRXN3_117' U1- # 117 E6 # All Receiver Channels from MGT Quad 118 are unused NET 'No_Conn_BF_MGTRXP0_118' U1-D7 # 118 D7 MGTRXP0_118 NET 'No_Conn_BF_MGTRXN0_118' U1-D8 # 118 D8 MGTRXN0_118 NET 'No_Conn_BF_MGTRXP1_118' U1-C5 # 118 C5 MGTRXP1_118 NET 'No_Conn_BF_MGTRXN1_118' U1-C6 # 118 C6 MGTRXN1_118 NET 'No_Conn_BF_MGTRXP2_118' U1-B7 # 118 B7 MGTRXP2_118 NET 'No_Conn_BF_MGTRXN2_118' U1-B8 # 118 B8 MGTRXN2_118 NET 'No_Conn_BF_MGTRXP3_118' U1-A5 # 118 A5 MGTRXP3_118 NET 'No_Conn_BF_MGTRXN3_118' U1-A6 # 118 A6 MGTRXN3_118 ################ # Transmitters ################ # All Tramsmitter Channels from MGT Quad 110 to 115 are used to drive the miniPOD transmitters # Those nets are defined in base_function_gtx_transmitters_n2r.txt # # All Tramsmitter Channels from MGT Quad 116 are unused NET 'No_Conn_BF_MGTTXP0_116' U1-N1 # 116 N1 MGTTXP0_116 NET 'No_Conn_BF_MGTTXN0_116' U1-N2 # 116 N2 MGTTXN0_116 NET 'No_Conn_BF_MGTTXP1_116' U1-M3 # 116 M3 MGTTXP1_116 NET 'No_Conn_BF_MGTTXN1_116' U1-M4 # 116 M4 MGTTXN1_116 NET 'No_Conn_BF_MGTTXP2_116' U1-L1 # 116 L1 MGTTXP2_116 NET 'No_Conn_BF_MGTTXN2_116' U1-L2 # 116 L2 MGTTXN2_116 NET 'No_Conn_BF_MGTTXP3_116' U1-K3 # 116 K3 MGTTXP3_116 NET 'No_Conn_BF_MGTTXN3_116' U1-K4 # 116 K4 MGTTXN3_116 # All Tramsmitter Channels from MGT Quad 117 are unused NET 'No_Conn_BF_MGTTXP0_117' U1-J1 # 117 J1 MGTTXP0_117 NET 'No_Conn_BF_MGTTXN0_117' U1-J2 # 117 J2 MGTTXN0_117 NET 'No_Conn_BF_MGTTXP1_117' U1-H3 # 117 H3 MGTTXP1_117 NET 'No_Conn_BF_MGTTXN1_117' U1-H4 # 117 H4 MGTTXN1_117 NET 'No_Conn_BF_MGTTXP2_117' U1-G1 # 117 G1 MGTTXP2_117 NET 'No_Conn_BF_MGTTXN2_117' U1-G2 # 117 G2 MGTTXN2_117 NET 'No_Conn_BF_MGTTXP3_117' U1-F3 # 117 F3 MGTTXP3_117 NET 'No_Conn_BF_MGTTXN3_117' U1-F4 # 117 F4 MGTTXN3_117 # Two of the Tramsmitter channels from MGT Quad 118 are used for the g-link output # Those nets are defined in base_function_low_speed_daq_roi_data_out_n2r.txt # The other two channels are unused NET 'No_Conn_BF_MGTTXP0_118' U1-E1 # 118 E1 MGTTXP0_118 NET 'No_Conn_BF_MGTTXN0_118' U1-E2 # 118 E2 MGTTXN0_118 NET 'No_Conn_BF_MGTTXP1_118' U1-D3 # 118 D3 MGTTXP1_118 NET 'No_Conn_BF_MGTTXN1_118' U1-D4 # 118 D4 MGTTXN1_118 ############################################################################################ # # CMX Net-to-Resource File for the # Base Function FPGA IO signals for all unused and Not Connected Select IO pins # -=============------------------------------------=======================------- # # # Original Rev. 28-Nov-2012 Initial collection of all unused pins # Rev. 30-Nov-2012 Studying the set of unused pins generated 3 allocation improvements # Rev. 11-Dec-2012 Sort unused pins in alphabetical order # Rev. 16-Jan-2013 Adopt NET naming convention to pre-pend "No_Conn_" for unused pins, # replace pin number with IO signal name to make unique net names # and add "Select IO" to file name: base_function_unconnected_select_io_pins_n2r.txt # 03-Apr-2013 Remove pins now assigned to connections to Board Support FPGA, Debug Connector, # BF to TP S-Link, TTC signals, and adding one Global Clock. # Rev: 17-May-2013 Rearranged P12_18:21 to solve layer 9 boundary conflict (P08:11 vs P12:14) # which also involved putting pin AV23 into use and dropping AY24 # Rev: 30-May-2013 P20 now unused while N19 now used (after BF to BSPT and debug connections rework) # Most Recent Rev: 03-Jun-2013 AE35 is now used and AF41 now unused (swap pin used for cable IO signal 83) # # Signal Nets referenced in this file: # ------------------------------------ # # 'No_Conn_BF_xxxx' are the unique net names assigned to these Select IO signals # where "xxxx" is the fpga Select IO signal name # ############################################################################################ # Unused pins from IO bank 12 ############################# # note: This bank is otherwise used for the CTP output NET 'No_Conn_BF_IO_L9N_MRCC_12' U1-AN36 # 12 AN36 IO_L9N_MRCC_12 NET 'No_Conn_BF_IO_L10N_MRCC_12' U1-AP35 # 12 AP35 IO_L10N_MRCC_12 NET 'No_Conn_BF_IO_L16N_12' U1-AT34 # 12 AT34 IO_L16N_12 # Unused pins from IO bank 13 ############################# # note: This bank is otherwise used for the CTP output and On-Card Bus NET 'No_Conn_BF_IO_L9P_MRCC_13' U1-AL34 # 13 AL34 IO_L9P_MRCC_13 # Unused pins from IO bank 14 ############################# # note: This bank is otherwise used for the On-Card Bus NET 'No_Conn_BF_IO_L18P_14' U1-AF32 # 14 AF32 IO_L18P_14 # Unused pins from IO bank 15 ############################# # note: This bank is otherwise used for the Cable IO # and System Monitor differential User Inputs NET 'No_Conn_BF_IO_L18N_15' U1-AC33 # 15 AC33 IO_L18N_15 NET 'No_Conn_BF_IO_L18P_15' U1-AC34 # 15 AC34 IO_L18P_15 NET 'No_Conn_BF_IO_L9P_MRCC_15' U1-AD32 # 15 AD32 IO_L9P_MRCC_15 NET 'No_Conn_BF_IO_L14N_VREF_15' U1-AD35 # 15 AD35 IO_L14N_VREF_15 NET 'No_Conn_BF_IO_L9N_MRCC_15' U1-AE32 # 15 AE32 IO_L9N_MRCC_15 NET 'No_Conn_BF_IO_L0P_15' U1-AE34 # 15 AE34 IO_L0P_15 NET 'No_Conn_BF_IO_L17N_15' U1-AF41 # 15 AF41 IO_L17N_15 # Unused pins from IO bank 16 ############################# # note: This bank is otherwise used for the Cable IO NET 'No_Conn_BF_IO_L16P_16' U1-U32 # 16 U32 IO_L16P_16 NET 'No_Conn_BF_IO_L16N_16' U1-U33 # 16 U33 IO_L16N_16 NET 'No_Conn_BF_IO_L10N_MRCC_16' U1-U34 # 16 U34 IO_L10N_MRCC_16 NET 'No_Conn_BF_IO_L18P_16' U1-V33 # 16 V33 IO_L18P_16 NET 'No_Conn_BF_IO_L10P_MRCC_16' U1-V34 # 16 V34 IO_L10P_MRCC_16 NET 'No_Conn_BF_IO_L18N_16' U1-W33 # 16 W33 IO_L18N_16 NET 'No_Conn_BF_IO_L12N_VRP_16' U1-Y32 # 16 Y32 IO_L12N_VRP_16 NET 'No_Conn_BF_IO_L9N_MRCC_16' U1-Y33 # 16 Y33 IO_L9N_MRCC_16 # Unused pins from IO bank 17 ############################# # note: This bank is otherwise used for the Cable IO NET 'No_Conn_BF_IO_L4N_VREF_17' U1-N34 # 17 N34 IO_L4N_VREF_17 NET 'No_Conn_BF_IO_L4P_17' U1-N35 # 17 N35 IO_L4P_17 NET 'No_Conn_BF_IO_L9N_MRCC_17' U1-P35 # 17 P35 IO_L9N_MRCC_17 NET 'No_Conn_BF_IO_L14N_VREF_17' U1-R34 # 17 R34 IO_L14N_VREF_17 NET 'No_Conn_BF_IO_L18P_17' U1-T34 # 17 T34 IO_L18P_17 # Unused pins from IO bank 21 ############################# # note: This bank is otherwise used for Backplane Inputs P10 and P11 NET 'No_Conn_BF_IO_L5P_21' U1-AJ23 # 21 AJ23 IO_L5P_21 NET 'No_Conn_BF_IO_L13N_21' U1-AL24 # 21 AL24 IO_L13N_21 # Unused pins from IO bank 22 ############################# # note: This bank is otherwise used for Backplane Inputs P08, P09, P10 and P11 NET 'No_Conn_BF_IO_L9N_MRCC_22' U1-AL26 # 22 AL26 IO_L9N_MRCC_22 # Unused pins from IO bank 23 ############################# # note: This bank is otherwise used for Backplane Inputs P08 and P09 NET 'No_Conn_BF_IO_L14P_23' U1-AG28 # 23 AG28 IO_L14P_23 NET 'No_Conn_BF_IO_L10P_MRCC_23' U1-AH24 # 23 AH24 IO_L10P_MRCC_23 NET 'No_Conn_BF_IO_L10N_MRCC_23' U1-AH25 # 23 AH25 IO_L10N_MRCC_23 NET 'No_Conn_BF_IO_L18N_23' U1-AH26 # 23 AH26 IO_L18N_23 NET 'No_Conn_BF_IO_L18P_23' U1-AJ26 # 23 AJ26 IO_L18P_23 NET 'No_Conn_BF_IO_L16N_23' U1-AJ27 # 23 AJ27 IO_L16N_23 NET 'No_Conn_BF_IO_L9N_MRCC_23' U1-AK25 # 23 AK25 IO_L9N_MRCC_23 NET 'No_Conn_BF_IO_L8P_SRCC_23' U1-AK28 # 23 AK28 IO_L8P_SRCC_23 NET 'No_Conn_BF_IO_L1N_23' U1-AL31 # 23 AL31 IO_L1N_23 # Unused pins from IO bank 24 ############################# # This IO bank has not yet been assigned NET 'No_Conn_BF_IO_L5P_D9_24' U1-N33 # 24 N33 IO_L5P_D9_24 NET 'No_Conn_BF_IO_L7P_D5_24' U1-P32 # 24 P32 IO_L7P_D5_24 NET 'No_Conn_BF_IO_L5N_D8_24' U1-P33 # 24 P33 IO_L5N_D8_24 NET 'No_Conn_BF_IO_L3N_D12_24' U1-R30 # 24 R30 IO_L3N_D12_24 NET 'No_Conn_BF_IO_L11P_SRCC_24' U1-R32 # 24 R32 IO_L11P_SRCC_24 NET 'No_Conn_BF_IO_L7N_D4_24' U1-R33 # 24 R33 IO_L7N_D4_24 NET 'No_Conn_BF_IO_L3P_D13_24' U1-T30 # 24 T30 IO_L3P_D13_24 NET 'No_Conn_BF_IO_L13P_D1_FS1_24' U1-T31 # 24 T31 IO_L13P_D1_FS1_24 NET 'No_Conn_BF_IO_L11N_SRCC_24' U1-T32 # 24 T32 IO_L11N_SRCC_24 NET 'No_Conn_BF_IO_L13N_D0_FS0_24' U1-U31 # 24 U31 IO_L13N_D0_FS0_24 NET 'No_Conn_BF_IO_L1N_GC_24' U1-V30 # 24 V30 IO_L1N_GC_24 NET 'No_Conn_BF_IO_L15P_FWE_B_24' U1-V31 # 24 V31 IO_L15P_FWE_B_24 NET 'No_Conn_BF_IO_L1P_GC_24' U1-W30 # 24 W30 IO_L1P_GC_24 NET 'No_Conn_BF_IO_L15N_RS1_24' U1-W31 # 24 W31 IO_L15N_RS1_24 NET 'No_Conn_BF_IO_L9P_MRCC_24' U1-Y30 # 24 Y30 IO_L9P_MRCC_24 NET 'No_Conn_BF_IO_L9N_MRCC_24' U1-AA30 # 24 AA30 IO_L9N_MRCC_24 NET 'No_Conn_BF_IO_L10P_MRCC_24' U1-AA31 # 24 AA31 IO_L10P_MRCC_24 NET 'No_Conn_BF_IO_L10N_MRCC_24' U1-AB31 # 24 AB31 IO_L10N_MRCC_24 NET 'No_Conn_BF_IO_L17N_VRP_24' U1-AC30 # 24 AC30 IO_L17N_VRP_24 NET 'No_Conn_BF_IO_L17P_VRN_24' U1-AC31 # 24 AC31 IO_L17P_VRN_24 NET 'No_Conn_BF_IO_L19N_24' U1-AD30 # 24 AD30 IO_L19N_24 NET 'No_Conn_BF_IO_L19P_24' U1-AD31 # 24 AD31 IO_L19P_24 NET 'No_Conn_BF_IO_L0P_GC_24' U1-AE30 # 24 AE30 IO_L0P_GC_24 NET 'No_Conn_BF_IO_L0N_GC_24' U1-AF30 # 24 AF30 IO_L0N_GC_24 NET 'No_Conn_BF_IO_L2N_D14_24' U1-AF31 # 24 AF31 IO_L2N_D14_24 NET 'No_Conn_BF_IO_L18N_24' U1-AG29 # 24 AG29 IO_L18N_24 NET 'No_Conn_BF_IO_L4N_VREF_D10_24' U1-AG31 # 24 AG31 IO_L4N_VREF_D10_24 NET 'No_Conn_BF_IO_L2P_D15_24' U1-AG32 # 24 AG32 IO_L2P_D15_24 NET 'No_Conn_BF_IO_L18P_24' U1-AH29 # 24 AH29 IO_L18P_24 NET 'No_Conn_BF_IO_L14P_FCS_B_24' U1-AH30 # 24 AH30 IO_L14P_FCS_B_24 NET 'No_Conn_BF_IO_L4P_D11_24' U1-AH31 # 24 AH31 IO_L4P_D11_24 NET 'No_Conn_BF_IO_L6N_D6_24' U1-AH33 # 24 AH33 IO_L6N_D6_24 NET 'No_Conn_BF_IO_L14N_VREF_FOE_B_MOSI_24' U1-AJ30 # 24 AJ30 IO_L14N_VREF_FOE_B_MOSI_24 NET 'No_Conn_BF_IO_L16P_RS0_24' U1-AJ31 # 24 AJ31 IO_L16P_RS0_24 NET 'No_Conn_BF_IO_L8N_SRCC_24' U1-AJ32 # 24 AJ32 IO_L8N_SRCC_24 NET 'No_Conn_BF_IO_L6P_D7_24' U1-AJ33 # 24 AJ33 IO_L6P_D7_24 NET 'No_Conn_BF_IO_L16N_CSO_B_24' U1-AK30 # 24 AK30 IO_L16N_CSO_B_24 NET 'No_Conn_BF_IO_L12P_D3_24' U1-AK32 # 24 AK32 IO_L12P_D3_24 NET 'No_Conn_BF_IO_L8P_SRCC_24' U1-AK33 # 24 AK33 IO_L8P_SRCC_24 NET 'No_Conn_BF_IO_L12N_D2_FS2_24' U1-AL32 # 24 AL32 IO_L12N_D2_FS2_24 # Unused pins from IO bank 25 ############################# # note: This IO bank is otherwise used for one differential global clock input for a 40.08 MHz logic clock # and two differential signals carrying the S-link return channels to the TP FPGA # and two pins are receiving TTC information NET 'No_Conn_BF_IO_L6N_25' U1-H38 # 25 H38 IO_L6N_25 NET 'No_Conn_BF_IO_L4N_VREF_25' U1-J36 # 25 J36 IO_L4N_VREF_25 NET 'No_Conn_BF_IO_L4P_25' U1-J37 # 25 J37 IO_L4P_25 NET 'No_Conn_BF_IO_L8N_SRCC_25' U1-J38 # 25 J38 IO_L8N_SRCC_25 NET 'No_Conn_BF_IO_L0N_25' U1-K32 # 25 K32 IO_L0N_25 NET 'No_Conn_BF_IO_L0P_25' U1-K33 # 25 K33 IO_L0P_25 NET 'No_Conn_BF_IO_L2N_25' U1-K34 # 25 K34 IO_L2N_25 NET 'No_Conn_BF_IO_L2P_25' U1-K35 # 25 K35 IO_L2P_25 NET 'No_Conn_BF_IO_L11P_SRCC_25' U1-K37 # 25 K37 IO_L11P_SRCC_25 NET 'No_Conn_BF_IO_L8P_SRCC_25' U1-K38 # 25 K38 IO_L8P_SRCC_25 NET 'No_Conn_BF_IO_L16P_VRN_25' U1-K39 # 25 K39 IO_L16P_VRN_25 NET 'No_Conn_BF_IO_L3P_25' U1-L31 # 25 L31 IO_L3P_25 NET 'No_Conn_BF_IO_L3N_25' U1-L32 # 25 L32 IO_L3N_25 NET 'No_Conn_BF_IO_L13P_25' U1-L34 # 25 L34 IO_L13P_25 NET 'No_Conn_BF_IO_L7P_25' U1-L35 # 25 L35 IO_L7P_25 NET 'No_Conn_BF_IO_L7N_25' U1-L36 # 25 L36 IO_L7N_25 NET 'No_Conn_BF_IO_L11N_SRCC_25' U1-L37 # 25 L37 IO_L11N_SRCC_25 NET 'No_Conn_BF_IO_L17P_25' U1-M31 # 25 M31 IO_L17P_25 NET 'No_Conn_BF_IO_L15N_25' U1-M32 # 25 M32 IO_L15N_25 NET 'No_Conn_BF_IO_L15P_25' U1-M33 # 25 M33 IO_L15P_25 NET 'No_Conn_BF_IO_L13N_25' U1-M34 # 25 M34 IO_L13N_25 NET 'No_Conn_BF_IO_L1P_25' U1-N28 # 25 N28 IO_L1P_25 NET 'No_Conn_BF_IO_L5P_25' U1-N29 # 25 N29 IO_L5P_25 NET 'No_Conn_BF_IO_L5N_25' U1-N30 # 25 N30 IO_L5N_25 NET 'No_Conn_BF_IO_L17N_25' U1-N31 # 25 N31 IO_L17N_25 NET 'No_Conn_BF_IO_L9P_MRCC_25' U1-P27 # 25 P27 IO_L9P_MRCC_25 NET 'No_Conn_BF_IO_L1N_25' U1-P28 # 25 P28 IO_L1N_25 NET 'No_Conn_BF_IO_L19P_GC_25' U1-P30 # 25 P30 IO_L19P_GC_25 NET 'No_Conn_BF_IO_L19N_GC_25' U1-P31 # 25 P31 IO_L19N_GC_25 NET 'No_Conn_BF_IO_L9N_MRCC_25' U1-R27 # 25 R27 IO_L9N_MRCC_25 NET 'No_Conn_BF_IO_L10P_MRCC_25' U1-R28 # 25 R28 IO_L10P_MRCC_25 NET 'No_Conn_BF_IO_L10N_MRCC_25' U1-R29 # 25 R29 IO_L10N_MRCC_25 # Unused pins from IO bank 26 ############################# # note: This bank is otherwise used for Backplane Inputs P06 and P07 NET 'No_Conn_BF_IO_L2P_26' U1-J35 # 26 J35 IO_L2P_26 # Unused pins from IO bank 27 ############################# # note: This bank is otherwise used for Backplane Inputs P04, P05, P06 and P07 NET 'No_Conn_BF_IO_L16N_27' U1-J30 # 27 J30 IO_L16N_27 NET 'No_Conn_BF_IO_L14P_27' U1-J32 # 27 J32 IO_L14P_27 NET 'No_Conn_BF_IO_L12N_VRP_27' U1-J33 # 27 J33 IO_L12N_VRP_27 NET 'No_Conn_BF_IO_L18N_27' U1-K30 # 27 K30 IO_L18N_27 NET 'No_Conn_BF_IO_L9N_MRCC_27' U1-L30 # 27 L30 IO_L9N_MRCC_27 NET 'No_Conn_BF_IO_L10P_MRCC_27' U1-M28 # 27 M28 IO_L10P_MRCC_27 # Unused pins from IO bank 28 ############################# # note: This bank is otherwise used for Backplane Inputs P04 and P05 NET 'No_Conn_BF_IO_L3N_28' U1-F30 # 28 F30 IO_L3N_28 NET 'No_Conn_BF_IO_L16P_28' U1-J28 # 28 J28 IO_L16P_28 NET 'No_Conn_BF_IO_L16N_28' U1-K28 # 28 K28 IO_L16N_28 NET 'No_Conn_BF_IO_L19N_28' U1-M27 # 28 M27 IO_L19N_28 NET 'No_Conn_BF_IO_L8P_SRCC_28' U1-R25 # 28 R25 IO_L8P_SRCC_28 # Unused pins from IO bank 32 ############################# # note: This bank is otherwise used for Backplane Inputs P12 and P13 NET 'No_Conn_BF_IO_L9N_MRCC_32' U1-AJ20 # 32 AJ20 IO_L9N_MRCC_32 NET 'No_Conn_BF_IO_L9P_MRCC_32' U1-AJ21 # 32 AJ21 IO_L9P_MRCC_32 NET 'No_Conn_BF_IO_L5P_32' U1-AL20 # 32 AL20 IO_L5P_32 NET 'No_Conn_BF_IO_L7P_32' U1-AN20 # 32 AN20 IO_L7P_32 NET 'No_Conn_BF_IO_L0P_32' U1-AY24 # 32 AY24 IO_L0P_32 # Unused pins from IO bank 33 ############################# # note: This bank is otherwise used for Backplane Inputs P12, P13, P14 and P15 NET 'No_Conn_BF_IO_L10N_MRCC_33' U1-AJ15 # 33 AJ15 IO_L10N_MRCC_33 NET 'No_Conn_BF_IO_L6P_33' U1-AJ17 # 33 AJ17 IO_L6P_33 NET 'No_Conn_BF_IO_L18N_33' U1-AJ18 # 33 AJ18 IO_L18N_33 # Unused pins from IO bank 34 ############################# # note: This bank is otherwise used for Backplane Inputs P14 and P15 # and two differential global clock inputs for 40.08 and 320.64 MHz logic clocks # All pins in this bank are used # Unused pins from IO bank 35 ############################# # note: This bank is otherwise used for Backplane Inputs P00 and P01 # and System Monitor differential User Inputs # All pins in this bank are used # Unused pins from IO bank 36 ############################# # note: This bank is otherwise used for Backplane Inputs P00, P01, P02 and P03 NET 'No_Conn_BF_IO_L10N_MRCC_36' U1-P16 # 36 P16 IO_L10N_MRCC_36 # Unused pins from IO bank 37 ############################# # note: This bank is otherwise used for Backplane Inputs P02 and P03 NET 'No_Conn_BF_IO_L16P_37' U1-K20 # 37 K20 IO_L16P_37 NET 'No_Conn_BF_IO_L16N_37' U1-L20 # 37 L20 IO_L16N_37 NET 'No_Conn_BF_IO_L9N_MRCC_37' U1-L21 # 37 L21 IO_L9N_MRCC_37 # Unused pins from IO bank 38 ############################# # note: This IO bank is otherwise used for connections to the Board Support FPGA # and connections to the Debug Connector NET 'No_Conn_BF_IO_L5P_38' U1-G26 # 38 G26 IO_L5P_38 NET 'No_Conn_BF_IO_L0P_38' U1-H24 # 38 H24 IO_L0P_38 NET 'No_Conn_BF_IO_L4N_VREF_38' U1-H25 # 38 H25 IO_L4N_VREF_38 NET 'No_Conn_BF_IO_L4P_38' U1-H26 # 38 H26 IO_L4P_38 NET 'No_Conn_BF_IO_L6N_38' U1-J25 # 38 J25 IO_L6N_38 NET 'No_Conn_BF_IO_L12N_VRP_38' U1-K24 # 38 K24 IO_L12N_VRP_38 NET 'No_Conn_BF_IO_L6P_38' U1-K25 # 38 K25 IO_L6P_38 NET 'No_Conn_BF_IO_L12P_VRN_38' U1-L24 # 38 L24 IO_L12P_VRN_38 NET 'No_Conn_BF_IO_L14N_VREF_38' U1-M23 # 38 M23 IO_L14N_VREF_38 NET 'No_Conn_BF_IO_L16N_38' U1-M24 # 38 M24 IO_L16N_38 NET 'No_Conn_BF_IO_L16P_38' U1-N23 # 38 N23 IO_L16P_38 NET 'No_Conn_BF_IO_L19P_38' U1-P20 # 38 P20 IO_L19P_38 # # CMX FF1759 Package NET-to-Pin File # -------------------------------------- # # # Original Rev. 30-Jan-2012 # Most Recent Rev. 14-Nov-2012 # # # # This is the N2P file is for Virtex-6 VCCO_xy Nets # in the FF1759 Package. # # This file is for the Base Function FPGA on the CMX card. # # The following 112 pins are the Virtex-6 VCCO power pins. # On the CMX card the VCCO power will come from the BULK_2V5 # power distribution bus. All Base Function FPGA I/O Banks # will have 2.5V signal levels. # NET 'BULK_2V5' U1-M10 U1-R11 # VCCO_0 NET 'BULK_2V5' U1-AP34 U1-AT38 U1-AU35 U1-AW39 U1-AY36 # VCCO_12 NET 'BULK_2V5' U1-AK36 U1-AN37 U1-AR41 U1-AV42 U1-BB40 # VCCO_13 NET 'BULK_2V5' U1-AF38 U1-AG35 U1-AH42 U1-AJ39 U1-AM40 # VCCO_14 NET 'BULK_2V5' U1-AA33 U1-AB40 U1-AC37 U1-AD34 U1-AE41 # VCCO_15 NET 'BULK_2V5' U1-U35 U1-V32 U1-V42 U1-W39 U1-Y36 # VCCO_16 NET 'BULK_2V5' U1-M40 U1-N37 U1-P34 U1-R41 U1-T38 # VCCO_17 NET 'BULK_2V5' U1-AH22 U1-AL23 U1-AP24 U1-AU25 U1-AY26 # VCCO_21 NET 'BULK_2V5' U1-AN27 U1-AT28 U1-AW29 U1-BA33 U1-BB30 # VCCO_22 NET 'BULK_2V5' U1-AG25 U1-AK26 U1-AL33 U1-AM30 U1-AR31 U1-AV32 # VCCO_23 NET 'BULK_2V5' U1-AB30 U1-AE31 U1-AH32 U1-AJ29 U1-R31 U1-W29 # VCCO_24 NET 'BULK_2V5' U1-H42 U1-J39 U1-K36 U1-L33 U1-M30 U1-T28 # VCCO_25 NET 'BULK_2V5' U1-B40 U1-C37 U1-E41 U1-F38 U1-G35 # VCCO_26 NET 'BULK_2V5' U1-A33 U1-D34 U1-E31 U1-H32 U1-J29 # VCCO_27 NET 'BULK_2V5' U1-B30 U1-F28 U1-K26 U1-N27 U1-P24 # VCCO_28 NET 'BULK_2V5' U1-AJ19 U1-AM20 U1-AR21 U1-AV22 U1-BA23 # VCCO_32 NET 'BULK_2V5' U1-AK16 U1-AL13 U1-AN17 U1-AT18 U1-AW19 U1-BB20 # VCCO_33 NET 'BULK_2V5' U1-AP14 U1-AR11 U1-AU15 U1-AV12 U1-AY16 U1-BA13 # VCCO_34 NET 'BULK_2V5' U1-C17 U1-D14 U1-G15 U1-H12 U1-L13 # VCCO_35 NET 'BULK_2V5' U1-B20 U1-F18 U1-K16 U1-N17 U1-P14 # VCCO_36 NET 'BULK_2V5' U1-A23 U1-D24 U1-E21 U1-H22 U1-J19 # VCCO_37 NET 'BULK_2V5' U1-C27 U1-G25 U1-L23 U1-M20 U1-R21 # VCCO_38 # # CMX FF1759 Package NET-to-Pin File # -------------------------------------- # # # Original Rev. 30-Jan-2012 # Most Recent Rev. 14-Nov-2012 # # # This is the N2P file is for Virtex-6 Ground Nets in the FF1759 Package. # # This file is for the Base Function FPGA on the CMX card. # # This file has 431 Ground Pins. # NET 'GROUND' U1-A2 U1-A3 U1-A4 U1-A7 U1-A8 U1-A11 U1-A13 U1-A18 U1-A28 NET 'GROUND' U1-A38 U1-AA3 U1-AA7 U1-AA9 U1-AA11 U1-AA13 U1-AA15 U1-AA17 U1-AA19 U1-AA23 NET 'GROUND' U1-AA25 U1-AA27 U1-AA29 U1-AA38 U1-AB1 U1-AB2 U1-AB5 U1-AB6 U1-AB9 U1-AB10 NET 'GROUND' U1-AB12 U1-AB14 U1-AB16 U1-AB18 U1-AB20 U1-AB24 U1-AB26 U1-AB28 U1-AB35 U1-AC3 NET 'GROUND' U1-AC7 U1-AC9 U1-AC11 U1-AC13 U1-AC15 U1-AC17 U1-AC19 U1-AC23 U1-AC25 U1-AC27 NET 'GROUND' U1-AC29 U1-AC32 U1-AC42 U1-AD1 U1-AD2 U1-AD5 U1-AD6 U1-AD9 U1-AD10 U1-AD12 NET 'GROUND' U1-AD14 U1-AD16 U1-AD18 U1-AD20 U1-AD22 U1-AD24 U1-AD26 U1-AD28 U1-AD39 U1-AE3 NET 'GROUND' U1-AE7 U1-AE9 U1-AE11 U1-AE13 U1-AE15 U1-AE17 U1-AE19 U1-AE21 U1-AE23 U1-AE25 NET 'GROUND' U1-AE27 U1-AE29 U1-AE36 U1-AF1 U1-AF2 U1-AF5 U1-AF6 U1-AF9 U1-AF10 U1-AF11 NET 'GROUND' U1-AF12 U1-AF14 U1-AF16 U1-AF18 U1-AF20 U1-AF22 U1-AF24 U1-AF26 U1-AF28 U1-AF33 NET 'GROUND' U1-AG3 U1-AG4 U1-AG7 U1-AG8 U1-AG9 U1-AG10 U1-AG11 U1-AG13 U1-AG15 U1-AG17 NET 'GROUND' U1-AG19 U1-AG21 U1-AG23 U1-AG30 U1-AG40 U1-AH1 U1-AH2 U1-AH5 U1-AH6 U1-AH9 NET 'GROUND' U1-AH11 U1-AH12 U1-AH14 U1-AH16 U1-AH17 U1-AH18 U1-AH20 U1-AH27 U1-AH37 U1-AJ3 NET 'GROUND' U1-AJ7 U1-AJ9 U1-AJ11 U1-AJ12 U1-AJ13 U1-AJ14 U1-AJ24 U1-AJ34 U1-AK1 U1-AK2 NET 'GROUND' U1-AK5 U1-AK6 U1-AK9 U1-AK11 U1-AK12 U1-AK13 U1-AK21 U1-AK31 U1-AK41 U1-AL3 NET 'GROUND' U1-AL7 U1-AL9 U1-AL12 U1-AL18 U1-AL28 U1-AL38 U1-AM1 U1-AM2 U1-AM5 U1-AM9 NET 'GROUND' U1-AM10 U1-AM15 U1-AM25 U1-AM35 U1-AN3 U1-AN7 U1-AN9 U1-AN12 U1-AN22 U1-AN32 NET 'GROUND' U1-AN42 U1-AP1 U1-AP2 U1-AP5 U1-AP9 U1-AP19 U1-AP29 U1-AP39 U1-AR3 U1-AR7 NET 'GROUND' U1-AR9 U1-AR16 U1-AR26 U1-AR36 U1-AT1 U1-AT2 U1-AT5 U1-AT6 U1-AT9 U1-AT10 NET 'GROUND' U1-AT11 U1-AT13 U1-AT23 U1-AT33 U1-AU3 U1-AU7 U1-AU11 U1-AU20 U1-AU30 U1-AU40 NET 'GROUND' U1-AV1 U1-AV2 U1-AV5 U1-AV9 U1-AV10 U1-AV11 U1-AV17 U1-AV27 U1-AV37 U1-AW3 NET 'GROUND' U1-AW7 U1-AW11 U1-AW14 U1-AW24 U1-AW34 U1-AY1 U1-AY2 U1-AY5 U1-AY9 U1-AY10 NET 'GROUND' U1-AY11 U1-AY12 U1-AY21 U1-AY31 U1-AY41 U1-B1 U1-B2 U1-B5 U1-B9 U1-B10 NET 'GROUND' U1-B12 U1-B13 U1-B15 U1-B25 U1-B35 U1-BA3 U1-BA7 U1-BA11 U1-BA12 U1-BA18 NET 'GROUND' U1-BA28 U1-BA38 U1-BB2 U1-BB5 U1-BB6 U1-BB9 U1-BB10 U1-BB11 U1-BB12 U1-BB15 NET 'GROUND' U1-BB25 U1-BB35 U1-C3 U1-C7 U1-C11 U1-C12 U1-C22 U1-C32 U1-C42 U1-D1 NET 'GROUND' U1-D2 U1-D5 U1-D9 U1-D10 U1-D11 U1-D19 U1-D29 U1-D39 U1-E3 U1-E7 NET 'GROUND' U1-E11 U1-E16 U1-E26 U1-E36 U1-F1 U1-F2 U1-F5 U1-F9 U1-F10 U1-F11 NET 'GROUND' U1-F13 U1-F23 U1-F33 U1-G3 U1-G7 U1-G11 U1-G20 U1-G30 U1-G40 U1-H1 NET 'GROUND' U1-H2 U1-H5 U1-H9 U1-H10 U1-H11 U1-H17 U1-H27 U1-H37 U1-J3 U1-J7 NET 'GROUND' U1-J9 U1-J14 U1-J24 U1-J34 U1-K1 U1-K2 U1-K5 U1-K6 U1-K9 U1-K11 NET 'GROUND' U1-K21 U1-K31 U1-K41 U1-L3 U1-L7 U1-L9 U1-L18 U1-L28 U1-L38 U1-M1 NET 'GROUND' U1-M2 U1-M5 U1-M6 U1-M9 U1-M15 U1-M25 U1-M35 U1-N3 U1-N7 U1-N9 NET 'GROUND' U1-N12 U1-N22 U1-N32 U1-N42 U1-P1 U1-P2 U1-P5 U1-P9 U1-P11 U1-P12 NET 'GROUND' U1-P19 U1-P29 U1-P39 U1-R3 U1-R7 U1-R9 U1-R13 U1-R15 U1-R16 U1-R17 NET 'GROUND' U1-R19 U1-R26 U1-R36 U1-T1 U1-T2 U1-T5 U1-T6 U1-T9 U1-T11 U1-T12 NET 'GROUND' U1-T14 U1-T16 U1-T18 U1-T20 U1-T22 U1-T24 U1-T26 U1-T33 U1-U3 U1-U4 NET 'GROUND' U1-U7 U1-U8 U1-U9 U1-U10 U1-U11 U1-U13 U1-U15 U1-U17 U1-U19 U1-U21 NET 'GROUND' U1-U23 U1-U25 U1-U27 U1-U29 U1-U30 U1-U40 U1-V1 U1-V2 U1-V5 U1-V6 NET 'GROUND' U1-V9 U1-V10 U1-V12 U1-V14 U1-V16 U1-V18 U1-V20 U1-V22 U1-V24 U1-V26 NET 'GROUND' U1-V28 U1-V37 U1-W3 U1-W7 U1-W9 U1-W11 U1-W13 U1-W15 U1-W17 U1-W19 NET 'GROUND' U1-W21 U1-W23 U1-W25 U1-W27 U1-W34 U1-Y1 U1-Y2 U1-Y5 U1-Y6 U1-Y9 NET 'GROUND' U1-Y10 U1-Y12 U1-Y14 U1-Y16 U1-Y18 U1-Y20 U1-Y24 U1-Y26 U1-Y28 U1-Y31 NET 'GROUND' U1-Y41 U1-AJ10 # # CMX FF1759 Package NET-to-Pin File # -------------------------------------- # # # Original Rev. 30-Jan-2012 # Most Recent Rev. 31-Dec-2012 # # # # This is the N2P file is for Virtex-6 MGTAVCC and MGTAVTT Nets # in the FF1759 Package. These are the analog power nets for # the high speed serial transceivers. # # This file is for the Base Function FPGA on the CMX card. # --------------- # # The following 18 pins are the Virtex-6 MGTAVCC power pins. # On the CMX card the MGTAVCC power will come from the GTX_AVTT # power distribution bus. NET 'BF_GTX_AVCC' U1-AA8 U1-C8 U1-E8 U1-G8 U1-J8 U1-L8 U1-N8 U1-R8 U1-W8 # MGTAVCC_N NET 'BF_GTX_AVCC' U1-AC8 U1-AE8 U1-AJ8 U1-AL8 U1-AN8 U1-AR8 U1-AU8 U1-AW8 U1-BA8 # MGTAVCC_S # The following 27 pins are the Virtex-6 MGTAVTT power pins. # On the CMX card the MGTAVTT power will come from the GTX_AVCC # power distribution bus. NET 'BF_GTX_AVTT' U1-B6 U1-C4 U1-D6 U1-E4 U1-F6 U1-G4 U1-H6 U1-J4 U1-L4 # MGTAVTT_N NET 'BF_GTX_AVTT' U1-N4 U1-P6 U1-R4 U1-W4 # MGTAVTT_N NET 'BF_GTX_AVTT' U1-AA4 U1-AC4 U1-AE4 U1-AJ4 U1-AL4 U1-AM6 U1-AN4 U1-AP6 # MGTAVTT_S NET 'BF_GTX_AVTT' U1-AR4 U1-AU4 U1-AV6 U1-AW4 U1-AY6 U1-BA4 # MGTAVTT_S # # CMX FF1759 Package NET-to-Pin File # -------------------------------------- # # # Bank 0 and Special Pins # ------===--------------------- # # # # Original Rev. 29-Dec-2012 # Most Recent Rev. 18-Mar-2012 # # # # This is the N2P file for Virtex-6 "Bank 0" and Special # Nets for the CMX Base Function FPGA. # # Pins with many and completely different functions are # included in what Xilinx calls "Bank 0". These are not # Select I/O pins. Rather these pins include those that # are involved with thinks like Configuration, System # Monitor, JTAG, Power Management, Si temperature # measurement, ... # # These are all special one of a kind fixed location pins. # # Other "special" pins, besides those in "Bank 0" should # be included in this Net to Pin file. Recall, we want # to assign a net to every one of the 1760 pins on this # component. # # # This file is for the Base Function FPGA on the CMX card. # ------------- # # # JTAG connections to the Base Function FPGA # # On the CMX's Virtex-6 FPGAs the JTAG connections # are pins in "Bank 0" NET 'CFG_TMS_from_ACE' U1-AN11 # TMS_0 CFG JTAG TMS from ACE pin 85 NET 'CFG_TCK_from_ACE' U1-AN10 # TCK_0 CFG JTAG TCK from ACE pin 80 NET 'CFG_ACE_TDO_to_BF_TDI' U1-AP10 # TDI_0 CFG JTAG Data from ACE to BF NET 'CFG_BF_TDO' U1-AR10 # TDO_0 CFG JTAG Data from BF to TP # # Configuration Nets NET 'BF_PROGRAM_B' U1-M11 # PROGRAM_B_0 NET 'BF_INIT_B' U1-N11 # INIT_B_0 NET 'BF_CONFIG_DONE' U1-N10 # DONE_0 NET 'BF_M0' U1-AL11 # M0_0 NET 'BF_M1' U1-AM11 # M1_0 NET 'BF_M2' U1-AL10 # M2_0 NET 'BF_CCLK' U1-K10 # CCLK_0 NET 'BF_DIN' U1-L10 # DIN_0 NET 'BF_DOUT_BUSY' U1-AK10 # DOUT_BUSY_0 NET 'BF_CSI_B' U1-T10 # CSI_B_0 NET 'BF_RDWR_B' U1-J10 # RDWR_B_0 # # System Monitor Nets NET 'BF_SM_AVDD' U1-Y22 # AVDD_0 NET 'BF_SM_AVSS' U1-Y21 # AVSS_0 NET 'BF_SM_VP' U1-AA22 # VP_0 NET 'BF_SM_VN' U1-AB21 # VN_0 NET 'BF_SM_VREFP' U1-AB22 # VREFP_0 NET 'BF_SM_AVSS' U1-AA21 # VREFN_0 # # Silicon Temperature Nets NET 'BF_SI_TEMP_DXP' U1-AC22 # DXP_0 NET 'BF_SI_TEMP_DXN' U1-AC21 # DXN_0 # # Other Special "Bank 0" Nets NET 'BF_HSWAPEN' U1-P10 # HSWAPEN_0 # VBATT is a power supply pin for the Decryptor Key memory. # The book says that when VBATT is not used to connect # this pin to either VccAUX or to GROUND. CMX will not # use the Decryptor Key VBATT supply. CMX will # permanently and irrevocably Ground this pin. # ## NET 'BF_VBATT' U1-R10 # VBATT_0 NET 'GROUND' U1-R10 # VBATT_0 # VFS is a power supply pin for programming the EFUSE. # The book says to Ground the VFS pin when it is not # being used. CMX will not use the EFUSE. Thus CMX # will permanently and irrevocably Ground this pin. # ## NET 'BF_VFS' U1-AH10 # VFS_0 NET 'GROUND' U1-AH10 # VFS_0 # # Special Non-Bank 0 Nets # # CMX FF1759 Package NET-to-Pin File # -------------------------------------- # # # Original Rev. 1-Feb-2012 # Most Recent Rev. 21-Dec-2012 # # # # This is the N2P file is for Virtex-6 VCCAUX and VCCINT Nets # in the FF1759 Package. # # This file is for the Base Function FPGA on the CMX card. # # The following 20 pins are the Virtex-6 VCCAUX power pins. # On the CMX card the VCCAUX power will come from the BULK_2V5 # power distribution bus. NET 'BULK_2V5' U1-AA10 U1-AA28 U1-AB11 U1-AB29 U1-AC10 U1-AC28 NET 'BULK_2V5' U1-AD11 U1-AD29 U1-AE10 U1-AE28 U1-AF27 U1-AF29 U1-T29 U1-U28 U1-V11 U1-V29 NET 'BULK_2V5' U1-W10 U1-W28 U1-Y11 U1-Y29 # The following 104 pins are the Virtex-6 VCCINT power pins. # On the CMX card the VCCINT power for the Base Function FPGA # will come from the BF_CORE power distribution bus. NET 'BF_CORE' U1-AA12 U1-AA14 U1-AA16 U1-AA18 U1-AA20 U1-AA24 NET 'BF_CORE' U1-AA26 U1-AB13 U1-AB15 U1-AB17 U1-AB19 U1-AB23 U1-AB25 U1-AB27 U1-AC12 U1-AC14 NET 'BF_CORE' U1-AC16 U1-AC18 U1-AC20 U1-AC24 U1-AC26 U1-AD13 U1-AD15 U1-AD17 U1-AD19 U1-AD21 NET 'BF_CORE' U1-AD23 U1-AD25 U1-AD27 U1-AE12 U1-AE14 U1-AE16 U1-AE18 U1-AE20 U1-AE22 U1-AE24 NET 'BF_CORE' U1-AE26 U1-AF13 U1-AF15 U1-AF17 U1-AF19 U1-AF21 U1-AF23 U1-AF25 U1-AG12 U1-AG14 NET 'BF_CORE' U1-AG16 U1-AG18 U1-AG20 U1-AG22 U1-AG24 U1-AG26 U1-AH13 U1-AH15 U1-AH19 U1-AH21 NET 'BF_CORE' U1-AH23 U1-P13 U1-P15 U1-R12 U1-R14 U1-R18 U1-R20 U1-R22 U1-R24 U1-T13 NET 'BF_CORE' U1-T15 U1-T17 U1-T19 U1-T21 U1-T23 U1-T25 U1-T27 U1-U12 U1-U14 U1-U16 NET 'BF_CORE' U1-U18 U1-U20 U1-U22 U1-U24 U1-U26 U1-V13 U1-V15 U1-V17 U1-V19 U1-V21 NET 'BF_CORE' U1-V23 U1-V25 U1-V27 U1-W12 U1-W14 U1-W16 U1-W18 U1-W20 U1-W22 U1-W24 NET 'BF_CORE' U1-W26 U1-Y13 U1-Y15 U1-Y17 U1-Y19 U1-Y23 U1-Y25 U1-Y27 # # File created by Match_Resource_to_Pin V3.1 at Thu Oct 10 12:05:44 2013 # derived from input Netlist file # and Resource to Pin dictionary # ############################################################################################ # # CMX Net-to-Resource File for the # TP Function FPGA IO signals used for Front Panel CTP Output # -=============------------------------------------------------ # # # Original Rev. 19-Nov-2012 Place holder # Rev: 11-Dec-2012 Copy Base FPGA pin assignment # Rev: 14-Jan-2013 Assign outer pins from IO banks 36, 37, 38 and route on layers 2,3,4,5 # Rev: 05-Apr-2013 Tentatively flag these signals to belong to layer 6 # Most Recent Rev: 04-Jun-2013 Update position of signal #65 after final location of 5th translator # # # Signal Nets referenced in this file: # ------------------------------------ # # There are 0, 1 or 2 CTP cables connected to a given CMX card. # A Crate CMX with only Base CMX functionality does not send any data to the CTP # A System CMX in a CPM crate sends information to the CTP over one cable # A System CMX in a JEM crate sends information to the CTP over two cables # A Crate CMX with TP functionality would probably send information to the CTP over two cables # # 'TP_DOUT_CTP_xx' are the CTP output signals from the TP FPGA with xx=00 to 65. # Each CTP output cable carries 33 LVDS signals consisting of 31 data bits, one clock # and one parity bit. # xx=0 to 30 carry data bits on cable #1 # xx=31 carry the clock on cable #1 # xx=64 carry the parity on cable #1 # xx=32 to 62 carry data bits on cable #2 # xx=63 carry the clock on cable #2 # xx=65 carry the parity on cable #2 # Note that regional clock signals are assigned to CTP output signals # 31 and 63 # for flexibility, so that the CTP output cables could be used as inputs instead. # # These CTP output signals are assigned here to resources in IO banks ??2 and ?? # # The rest of the circuitry used to drive the LVDS cables is in the file front_panel_ctp_driver_n2p.txt # in the Net_Lists/Front_Panel_CTP_IO_Nets directory # # # Note: Trace layer information is appended as comments below. # ----- # # NET 'TP_DOUT_CTP_00' U2- #> F02 #> T02 00 D22 # # ^ ^ ^ ^ ^ # | | | | | # Tailored comment flag to help with string searches -----------------+ | | | | # | | | | # Target Trace Layer number to use for this net --------------------------+ | | | # as it exits the FPGA (to reach a nearby via if needed) | | | # F01 is top layer, F02 the first inner layer, etc | | | # | | | # Target Trace Layer number to use for this net ---------------------------------+ | | # as it reaches the level translator near the front of the card | | # T01 is top layer, T02 the first inner layer, etc | | # | | # Signal number is repeated to help manual entry of Pin Number ---------------------+ | # | # Target Pin Number read from paper study -----------------------------------------------+ # and cross-checked after Match_Res2Pin # ############################################################################################ # # CTP Cable #1 # NET 'TP_DOUT_CTP_00' U2-D22 #> F02 #> T06 00 D22 IO_L11N_SRCC_37 NET 'TP_DOUT_CTP_01' U2-B22 #> F02 #> T06 01 B22 IO_L5N_37 NET 'TP_DOUT_CTP_02' U2-A22 #> F02 #> T06 02 A22 IO_L13P_37 NET 'TP_DOUT_CTP_03' U2-B23 #> F02 #> T06 03 B23 IO_L5P_37 NET 'TP_DOUT_CTP_04' U2-C23 #> F02 #> T06 04 C23 IO_L3N_37 NET 'TP_DOUT_CTP_05' U2-A24 #> F02 #> T06 05 A24 IO_L1N_37 NET 'TP_DOUT_CTP_06' U2-B24 #> F02 #> T06 06 B24 IO_L1P_37 NET 'TP_DOUT_CTP_07' U2-A25 #> F02 #> T06 07 A25 IO_L11N_SRCC_38 NET 'TP_DOUT_CTP_08' U2-C25 #> F02 #> T06 08 C25 IO_L15N_38 NET 'TP_DOUT_CTP_09' U2-A26 #> F02 #> T06 09 A26 IO_L11P_SRCC_38 NET 'TP_DOUT_CTP_10' U2-B26 #> F02 #> T06 10 B26 IO_L15P_38 NET 'TP_DOUT_CTP_11' U2-A27 #> F02 #> T06 11 A27 IO_L7N_38 NET 'TP_DOUT_CTP_12' U2-B27 #> F02 #> T06 12 B27 IO_L7P_38 NET 'TP_DOUT_CTP_13' U2-B28 #> F02 #> T06 13 B28 IO_L3N_38 NET 'TP_DOUT_CTP_14' U2-F22 #> F03 #> T06 14 F22 IO_L2N_37 NET 'TP_DOUT_CTP_15' U2-E22 #> F03 #> T06 15 E22 IO_L4N_VREF_37 NET 'TP_DOUT_CTP_16' U2-D23 #> F03 #> T06 16 D23 IO_L11P_SRCC_37 NET 'TP_DOUT_CTP_17' U2-E24 #> F03 #> T06 17 E24 IO_L7P_37 NET 'TP_DOUT_CTP_18' U2-C24 #> F03 #> T06 18 C24 IO_L3P_37 NET 'TP_DOUT_CTP_19' U2-D25 #> F03 #> T06 19 D25 IO_L17P_38 NET 'TP_DOUT_CTP_20' U2-C26 #> F03 #> T06 20 C26 IO_L13P_38 NET 'TP_DOUT_CTP_21' U2-D27 #> F03 #> T06 21 D27 IO_L1N_38 NET 'TP_DOUT_CTP_22' U2-C28 #> F03 #> T06 22 C28 IO_L3P_38 NET 'TP_DOUT_CTP_23' U2-K22 #> F04 #> T06 23 K22 IO_L10N_MRCC_37 NET 'TP_DOUT_CTP_24' U2-G22 #> F04 #> T06 24 G22 IO_L2P_37 NET 'TP_DOUT_CTP_25' U2-E23 #> F04 #> T06 25 E23 IO_L7N_37 NET 'TP_DOUT_CTP_26' U2-F24 #> F04 #> T06 26 F24 IO_L2N_38 NET 'TP_DOUT_CTP_27' U2-F25 #> F04 #> T06 27 F25 IO_L2P_38 NET 'TP_DOUT_CTP_28' U2-E25 #> F04 #> T06 28 E25 IO_L17N_38 NET 'TP_DOUT_CTP_29' U2-D26 #> F04 #> T06 29 D26 IO_L13N_38 NET 'TP_DOUT_CTP_30' U2-E27 #> F04 #> T06 30 E27 IO_L1P_38 NET 'TP_DOUT_CTP_31' U2-J22 #> F05 #> T06 31 J22 IO_L10P_MRCC_37 NET 'TP_DOUT_CTP_64' U2-F26 #> F05 #> T06 64 F26 IO_L5N_38 # # CTP Cable #2 # NET 'TP_DOUT_CTP_32' U2-B17 #> F02 #> T06 32 B17 IO_L17N_36 NET 'TP_DOUT_CTP_33' U2-A17 #> F02 #> T06 33 A17 IO_L17P_36 NET 'TP_DOUT_CTP_34' U2-B18 #> F02 #> T06 34 B18 IO_L15P_36 NET 'TP_DOUT_CTP_35' U2-B19 #> F02 #> T06 35 B19 IO_L7N_36 NET 'TP_DOUT_CTP_36' U2-A19 #> F02 #> T06 36 A19 IO_L15N_36 NET 'TP_DOUT_CTP_37' U2-C20 #> F02 #> T06 37 C20 IO_L19P_37 NET 'TP_DOUT_CTP_38' U2-A20 #> F02 #> T06 38 A20 IO_L15N_37 NET 'TP_DOUT_CTP_39' U2-D20 #> F02 #> T06 39 D20 IO_L19N_37 NET 'TP_DOUT_CTP_40' U2-A21 #> F02 #> T06 40 A21 IO_L13N_37 NET 'TP_DOUT_CTP_41' U2-B21 #> F02 #> T06 41 B21 IO_L15P_37 NET 'TP_DOUT_CTP_42' U2-C21 #> F02 #> T06 42 C21 IO_L17P_37 NET 'TP_DOUT_CTP_43' U2-D17 #> F03 #> T06 43 D17 IO_L19P_36 NET 'TP_DOUT_CTP_44' U2-C18 #> F03 #> T06 44 C18 IO_L13N_36 NET 'TP_DOUT_CTP_45' U2-C19 #> F03 #> T06 45 C19 IO_L7P_36 NET 'TP_DOUT_CTP_46' U2-E19 #> F03 #> T06 46 E19 IO_L5P_36 NET 'TP_DOUT_CTP_47' U2-E20 #> F03 #> T06 47 E20 IO_L12P_VRN_37 NET 'TP_DOUT_CTP_48' U2-D21 #> F03 #> T06 48 D21 IO_L17N_37 NET 'TP_DOUT_CTP_49' U2-F21 #> F03 #> T06 49 F21 IO_L4P_37 NET 'TP_DOUT_CTP_50' U2-E17 #> F04 #> T06 50 E17 IO_L19N_36 NET 'TP_DOUT_CTP_51' U2-D18 #> F04 #> T06 51 D18 IO_L13P_36 NET 'TP_DOUT_CTP_52' U2-E18 #> F04 #> T06 52 E18 IO_L5N_36 NET 'TP_DOUT_CTP_53' U2-F19 #> F04 #> T06 53 F19 IO_L3N_36 NET 'TP_DOUT_CTP_54' U2-F20 #> F04 #> T06 54 F20 IO_L12N_VRP_37 NET 'TP_DOUT_CTP_55' U2-G21 #> F04 #> T06 55 G21 IO_L8N_SRCC_37 NET 'TP_DOUT_CTP_56' U2-H21 #> F04 #> T06 56 H21 IO_L6P_37 NET 'TP_DOUT_CTP_57' U2-F16 #> F05 #> T06 57 F16 IO_L2N_36 NET 'TP_DOUT_CTP_58' U2-F17 #> F05 #> T06 58 F17 IO_L11P_SRCC_36 NET 'TP_DOUT_CTP_59' U2-G17 #> F05 #> T06 59 G17 IO_L11N_SRCC_36 NET 'TP_DOUT_CTP_60' U2-G18 #> F05 #> T06 60 G18 IO_L1N_36 NET 'TP_DOUT_CTP_61' U2-G19 #> F05 #> T06 61 G19 IO_L3P_36 NET 'TP_DOUT_CTP_62' U2-H20 #> F05 #> T06 62 H20 IO_L8P_SRCC_37 NET 'TP_DOUT_CTP_63' U2-L22 #> F05 #> T06 63 L22 IO_L9P_MRCC_37 NET 'TP_DOUT_CTP_65' U2-J21 #> F05 #> T06 65 J21 IO_L6N_37 ############################################################################################ # # CMX Net-to-Resource File for the # TP Function FPGA IO signals used the highspeed GTX Receivers # -=============------------------------------------------------- # # # Original Rev. 16-Mar-2012 # Rev. 5-Dec-2012 Rename nets and add termination resistors # Rev: 11-Dec-2012 File name changed for uniformity and consistency # between Base and TP files # Rev: 31-Dec-2012 Change the net-name on the MGTAVTTRCAL_115 # Calibration Resistor pin. # Rev: 23-May-2013 Assign full net names, including fiber number, to the # GTX Receivers in Quads 113, 114, 115, i.e. MiniPOD MP4. # Rev: 24-May-2013 Assign full net names, including fiber number, to the # GTX Receivers in Quads 110, 111, 112, i.e. MiniPOD MP3 # and to Quads 116, 117, 118, i.e. MiniPOD MP5. # Most Recent Rev: 8-Oct-2013 Change some GTX Transceiver - MiniPOD Fiber assignments # to allow better trace length match of DIR and CMP traces. # # # Receiver 1 MiniPOD MP3 # --------===----------===== NET 'MP3_F01_QUAD_110_REC_0_DIR' U2-BB7 # MGTRXP0_110 NET 'MP3_F01_QUAD_110_REC_0_CMP' U2-BB8 # MGTRXN0_110 NET 'MP3_F07_QUAD_110_REC_1_DIR' U2-BA5 # MGTRXP1_110 NET 'MP3_F07_QUAD_110_REC_1_CMP' U2-BA6 # MGTRXN1_110 NET 'MP3_F05_QUAD_110_REC_2_DIR' U2-AY7 # MGTRXP2_110 NET 'MP3_F05_QUAD_110_REC_2_CMP' U2-AY8 # MGTRXN2_110 NET 'MP3_F03_QUAD_110_REC_3_DIR' U2-AW5 # MGTRXP3_110 NET 'MP3_F03_QUAD_110_REC_3_CMP' U2-AW6 # MGTRXN3_110 NET 'MP3_F09_QUAD_111_REC_0_DIR' U2-AV7 # MGTRXP0_111 NET 'MP3_F09_QUAD_111_REC_0_CMP' U2-AV8 # MGTRXN0_111 NET 'MP3_F11_QUAD_111_REC_1_DIR' U2-AU5 # MGTRXP1_111 NET 'MP3_F11_QUAD_111_REC_1_CMP' U2-AU6 # MGTRXN1_111 NET 'MP3_F10_QUAD_111_REC_2_DIR' U2-AR5 # MGTRXP2_111 NET 'MP3_F10_QUAD_111_REC_2_CMP' U2-AR6 # MGTRXN2_111 NET 'MP3_F08_QUAD_111_REC_3_DIR' U2-AP7 # MGTRXP3_111 NET 'MP3_F08_QUAD_111_REC_3_CMP' U2-AP8 # MGTRXN3_111 NET 'MP3_F00_QUAD_112_REC_0_DIR' U2-AN5 # MGTRXP0_112 NET 'MP3_F00_QUAD_112_REC_0_CMP' U2-AN6 # MGTRXN0_112 NET 'MP3_F04_QUAD_112_REC_1_DIR' U2-AM7 # MGTRXP1_112 NET 'MP3_F04_QUAD_112_REC_1_CMP' U2-AM8 # MGTRXN1_112 NET 'MP3_F06_QUAD_112_REC_2_DIR' U2-AL5 # MGTRXP2_112 NET 'MP3_F06_QUAD_112_REC_2_CMP' U2-AL6 # MGTRXN2_112 NET 'MP3_F02_QUAD_112_REC_3_DIR' U2-AJ5 # MGTRXP3_112 NET 'MP3_F02_QUAD_112_REC_3_CMP' U2-AJ6 # MGTRXN3_112 # Receiver 2 MiniPOD MP4 # --------===----------===== NET 'MP4_F01_QUAD_113_REC_0_DIR' U2-AG5 # MGTRXP0_113 NET 'MP4_F01_QUAD_113_REC_0_CMP' U2-AG6 # MGTRXN0_113 NET 'MP4_F03_QUAD_113_REC_3_DIR' U2-AD3 # MGTRXP3_113 NET 'MP4_F03_QUAD_113_REC_3_CMP' U2-AD4 # MGTRXN3_113 NET 'MP4_F05_QUAD_113_REC_2_DIR' U2-AE5 # MGTRXP2_113 NET 'MP4_F05_QUAD_113_REC_2_CMP' U2-AE6 # MGTRXN2_113 NET 'MP4_F07_QUAD_113_REC_1_DIR' U2-AF3 # MGTRXP1_113 NET 'MP4_F07_QUAD_113_REC_1_CMP' U2-AF4 # MGTRXN1_113 NET 'MP4_F09_QUAD_114_REC_0_DIR' U2-AC5 # MGTRXP0_114 NET 'MP4_F09_QUAD_114_REC_0_CMP' U2-AC6 # MGTRXN0_114 NET 'MP4_F11_QUAD_114_REC_1_DIR' U2-AB3 # MGTRXP1_114 NET 'MP4_F11_QUAD_114_REC_1_CMP' U2-AB4 # MGTRXN1_114 NET 'MP4_F10_QUAD_114_REC_2_DIR' U2-AA5 # MGTRXP2_114 NET 'MP4_F10_QUAD_114_REC_2_CMP' U2-AA6 # MGTRXN2_114 NET 'MP4_F08_QUAD_114_REC_3_DIR' U2-Y3 # MGTRXP3_114 NET 'MP4_F08_QUAD_114_REC_3_CMP' U2-Y4 # MGTRXN3_114 NET 'MP4_F02_QUAD_115_REC_0_DIR' U2-W5 # MGTRXP0_115 NET 'MP4_F02_QUAD_115_REC_0_CMP' U2-W6 # MGTRXN0_115 NET 'MP4_F04_QUAD_115_REC_1_DIR' U2-V3 # MGTRXP1_115 NET 'MP4_F04_QUAD_115_REC_1_CMP' U2-V4 # MGTRXN1_115 NET 'MP4_F06_QUAD_115_REC_2_DIR' U2-U5 # MGTRXP2_115 NET 'MP4_F06_QUAD_115_REC_2_CMP' U2-U6 # MGTRXN2_115 NET 'MP4_F00_QUAD_115_REC_3_DIR' U2-R5 # MGTRXP3_115 NET 'MP4_F00_QUAD_115_REC_3_CMP' U2-R6 # MGTRXN3_115 # Receiver 3 MiniPOD MP5 # --------===----------===== NET 'MP5_F01_QUAD_116_REC_0_DIR' U2-P7 # MGTRXP0_116 NET 'MP5_F01_QUAD_116_REC_0_CMP' U2-P8 # MGTRXN0_116 NET 'MP5_F03_QUAD_116_REC_1_DIR' U2-N5 # MGTRXP1_116 NET 'MP5_F03_QUAD_116_REC_1_CMP' U2-N6 # MGTRXN1_116 NET 'MP5_F05_QUAD_116_REC_2_DIR' U2-L5 # MGTRXP2_116 NET 'MP5_F05_QUAD_116_REC_2_CMP' U2-L6 # MGTRXN2_116 NET 'MP5_F07_QUAD_116_REC_3_DIR' U2-J5 # MGTRXP3_116 NET 'MP5_F07_QUAD_116_REC_3_CMP' U2-J6 # MGTRXN3_116 NET 'MP5_F09_QUAD_117_REC_0_DIR' U2-H7 # MGTRXP0_117 NET 'MP5_F09_QUAD_117_REC_0_CMP' U2-H8 # MGTRXN0_117 NET 'MP5_F11_QUAD_117_REC_1_DIR' U2-G5 # MGTRXP1_117 NET 'MP5_F11_QUAD_117_REC_1_CMP' U2-G6 # MGTRXN1_117 NET 'MP5_F10_QUAD_117_REC_2_DIR' U2-F7 # MGTRXP2_117 NET 'MP5_F10_QUAD_117_REC_2_CMP' U2-F8 # MGTRXN2_117 NET 'MP5_F08_QUAD_117_REC_3_DIR' U2-E5 # MGTRXP3_117 NET 'MP5_F08_QUAD_117_REC_3_CMP' U2-E6 # MGTRXN3_117 NET 'MP5_F02_QUAD_118_REC_0_DIR' U2-D7 # MGTRXP0_118 NET 'MP5_F02_QUAD_118_REC_0_CMP' U2-D8 # MGTRXN0_118 NET 'MP5_F04_QUAD_118_REC_1_DIR' U2-C5 # MGTRXP1_118 NET 'MP5_F04_QUAD_118_REC_1_CMP' U2-C6 # MGTRXN1_118 NET 'MP5_F06_QUAD_118_REC_2_DIR' U2-B7 # MGTRXP2_118 NET 'MP5_F06_QUAD_118_REC_2_CMP' U2-B8 # MGTRXN2_118 NET 'MP5_F00_QUAD_118_REC_3_DIR' U2-A5 # MGTRXP3_118 NET 'MP5_F00_QUAD_118_REC_3_CMP' U2-A6 # MGTRXN3_118 # Now connect the GTX Termination Calibration Resistor # This is a precision 100 Ohm resistor. # See Chapter 5 page 274 of the # Virtex-6 GTX User Guide. # # The other half of these connections is in: # # ..../Everything_Else/dci_gtx_res_nets_n2p.txt # NET 'TP_MGTRREF' U2-B11 # B11 Topological MGTRREF pin MGTRREF_115 NET 'TP_GTX_AVTT' U2-A12 # A12 Topological MGTAVTTRCAL MGTAVTTRCAL_115 # connected to the TP_GTX_AVTT bus # as indicated in the User Guide ############################################################################################ # # CMX Net-to-Resource File for the # TP Function FPGA IO signals used for the Low-Speed DAQ & ROI Data Output # -=============-------------------------------------------------------------- # # # Original Rev. 17-Jan-2013 # Most Recent Rev. 17-Jan-2013 Assign lowest Two channels # # # TP Function FPGA # # DAQ and ROI Data Outputs to SFP Optical Transmitters # # SFP3 TP Function DAQ SFP Optical Output # SFP4 TP Function RIO SFP Optical Output # NET 'TP_DAQ_DATA_OUT_DIR' U2-BA1 # BA1 DAQ Data Output Direct MGTTXP1_110 NET 'TP_DAQ_DATA_OUT_CMP' U2-BA2 # BA2 DAQ Data Output Complement MGTTXN1_110 NET 'TP_ROI_DATA_OUT_DIR' U2-BB3 # BB3 ROI Data Output Direct MGTTXP0_110 NET 'TP_ROI_DATA_OUT_CMP' U2-BB4 # BB4 ROI Data Output Complement MGTTXN0_110 ############################################################################################ # # CMX Net-to-Resource File for the # TP Function FPGA IO signals used for the On-Card VME bus signals # -=============----------------------------------------------------- # # # Original Rev. 11-Dec-2012 Copy Base FPGA pin assignment # Most Recent Rev: 14-Jan-2013 Assign outer pins from IO banks 15, 16 &17 and route on layers 7 (most) & 6 (with via) # # # Signal Nets referenced in this file: # ------------------------------------ # # 'OCB_Axx' are the On-Card Bus Address lines to the Base FPGA with xx=01 to 23 # (note there is no "A00" signal) # # 'OCB_Dyy' are the On-Card Bus Data lines to the Base FPGA with yy=00 to 15 # # 'OCB_GEO_ADRS_z' are the On-Card Bus Geographic Section Address lines with z=0 to 6 # # # 'OCB_SYS_RESET_B' is the On-Card Bus VME SYS_RESET signal # The "_B" postfix is used to indicate that the reset request is active # when the electrical signal is low # # 'OCB_DS_B' is the On-Card Bus Data strobe. # The "_B" postfix is used to indicate that the data strobe signal is on the # falling edge of the electrical signal. # # 'OCB_WRITE_B' is the On-Card Bus Data Direction # The "_B" postfix is used to indicate that the Write direction is # requested when the electrical signal is low. # # # IO Banks used # ------------- # # Most signal nets are assigned to IO Bank 14 and a few to Io Bank 13 # - All address line nets are in IO Bank 14 # - All data line nets are in IO Bank 14 # - The Data Strobe net is assigned to a regional clock pin in IO Bank 14 # - The Board Select net is assigned to a regional clock pin in IO Bank 13 # - The Write Net is assigned to an IO input pin in Bank 13 # - The Sys_Reset net is assigned to an IO input pin in Bank 13 # # The bulk of IO Bank 13 is used for the CTP output signals # # Note: Trace layer information is appended as comments below. # ----- # # NET 'OCB_A01' U2- #> F07 #> T07 A01 AF41 # # ^ ^ ^ ^ ^ # | | | | | # Tailored comment flag to help with string searches ------------------+ | | | | # | | | | # Target Trace Layer number to use for this net --------------------------+ | | | # as it exits the FPGA (to reach a nearby via if needed) | | | # F01 is top layer, F02 the first inner layer, etc | | | # | | | # Target Trace Layer number to use for this net ---------------------------------+ | | # as it connects the VME bus transceiver section to the two FPGAs | | # T01 is top layer, T02 the first inner layer, etc | | # | | # Signal number is repeated to help manual entry of Pin Number ---------------------+ | # | # Target Pin Number read from paper drawing ---------------------------------------------+ # and cross-checked after Match_Res2Pin # ############################################################################################ # The lower Address (1:16), all Data lines, and the Data Strobe, will come in directly (no via) # The data strobe is assigned to a regional clock input pin (but probably not used as a clock) NET 'OCB_A01' U2-AF41 #> F07 #> T07 A01 AF41 IO_L17N_15 NET 'OCB_A02' U2-AF42 #> F07 #> T07 A02 AF42 IO_L17P_15 NET 'OCB_A03' U2-AE40 #> F07 #> T07 A03 AE40 IO_L19P_15 NET 'OCB_A04' U2-AE42 #> F07 #> T07 A04 AE42 IO_L15N_SM15N_15 NET 'OCB_A05' U2-AD41 #> F07 #> T07 A05 AD41 IO_L11N_SRCC_15 NET 'OCB_A06' U2-AD42 #> F07 #> T07 A06 AD42 IO_L15P_SM15P_15 NET 'OCB_A07' U2-AC41 #> F07 #> T07 A07 AC41 IO_L11P_SRCC_15 NET 'OCB_A08' U2-AC40 #> F07 #> T07 A08 AC40 IO_L13P_SM14P_15 NET 'OCB_A09' U2-AB42 #> F07 #> T07 A09 AB42 IO_L7N_SM12N_15 NET 'OCB_A10' U2-AB41 #> F07 #> T07 A10 AB41 IO_L5N_SM10N_15 NET 'OCB_A11' U2-AB39 #> F07 #> T07 A11 AB39 IO_L3P_SM9P_15 NET 'OCB_A12' U2-AA40 #> F07 #> T07 A12 AA40 IO_L3N_SM9N_15 NET 'OCB_A13' U2-AA41 #> F07 #> T07 A13 AA41 IO_L5P_SM10P_15 NET 'OCB_A14' U2-AA42 #> F07 #> T07 A14 AA42 IO_L7P_SM12P_15 NET 'OCB_A15' U2-Y40 #> F07 #> T07 A15 Y40 IO_L17P_16 NET 'OCB_A16' U2-Y42 #> F07 #> T07 A16 Y42 IO_L15N_16 NET 'OCB_D00' U2-L41 #> F07 #> T07 D00 L41 IO_L3P_17 NET 'OCB_D01' U2-L42 #> F07 #> T07 D01 L42 IO_L3N_17 NET 'OCB_D02' U2-M41 #> F07 #> T07 D02 M41 IO_L7P_17 NET 'OCB_D03' U2-M42 #> F07 #> T07 D03 M42 IO_L7N_17 NET 'OCB_D04' U2-N41 #> F07 #> T07 D04 N41 IO_L11N_SRCC_17 NET 'OCB_D05' U2-P41 #> F07 #> T07 D05 P41 IO_L13N_17 NET 'OCB_D06' U2-P42 #> F07 #> T07 D06 P42 IO_L15P_17 NET 'OCB_D07' U2-R40 #> F07 #> T07 D07 R40 IO_L17P_17 NET 'OCB_D08' U2-R42 #> F07 #> T07 D08 R42 IO_L15N_17 NET 'OCB_D09' U2-T41 #> F07 #> T07 D09 T41 IO_L19P_17 NET 'OCB_D10' U2-T42 #> F07 #> T07 D10 T42 IO_L19N_17 NET 'OCB_D11' U2-U41 #> F07 #> T07 D11 U41 IO_L3N_16 NET 'OCB_D12' U2-U42 #> F07 #> T07 D12 U42 IO_L3P_16 NET 'OCB_D13' U2-V41 #> F07 #> T07 D13 V41 IO_L13P_16 NET 'OCB_D14' U2-W41 #> F07 #> T07 D14 W41 IO_L13N_16 NET 'OCB_D15' U2-W42 #> F07 #> T07 D15 W42 IO_L15P_16 NET 'OCB_DS_B' U2-W32 #> F07 #> T07 DS W32 IO_L9P_MRCC_16 # The upper Address (17:23), the Direction, SysReset, and all Geographic Address signals # will need to transition to another trace layer (tentatively trace layer 2) NET 'OCB_A17' U2-W38 #> F02 #> T07 A17 W38 IO_L7N_16 NET 'OCB_A18' U2-W40 #> F02 #> T07 A18 W40 IO_L11N_SRCC_16 NET 'OCB_A19' U2-V40 #> F02 #> T07 A19 V40 IO_L11P_SRCC_16 NET 'OCB_A20' U2-U39 #> F02 #> T07 A20 U39 IO_L5P_16 NET 'OCB_A21' U2-T40 #> F02 #> T07 A21 T40 IO_L17N_17 NET 'OCB_A22' U2-R39 #> F02 #> T07 A22 R39 IO_L8P_SRCC_17 NET 'OCB_A23' U2-P40 #> F02 #> T07 A23 P40 IO_L13P_17 NET 'OCB_WRITE_B' U2-Y39 #> F02 #> T07 WRI Y39 IO_L17N_16 NET 'OCB_SYS_RESET_B' U2-AA39 #> F02 #> T07 RES AA39 IO_L19N_16 NET 'OCB_GEO_ADRS_0' U2-AB38 #> F02 #> T07 GA0 AB38 IO_L1N_15 NET 'OCB_GEO_ADRS_1' U2-L40 #> F02 #> T07 GA1 L40 IO_L1N_17 NET 'OCB_GEO_ADRS_2' U2-M39 #> F02 #> T07 GA2 M39 IO_L2N_17 NET 'OCB_GEO_ADRS_3' U2-N40 #> F02 #> T07 GA3 N40 IO_L11P_SRCC_17 NET 'OCB_GEO_ADRS_4' U2-AC39 #> F02 #> T07 GA4 AC39 IO_L4N_VREF_15 NET 'OCB_GEO_ADRS_5' U2-AD40 #> F02 #> T07 GA5 AD40 IO_L13N_SM14N_15 NET 'OCB_GEO_ADRS_6' U2-AE39 #> F02 #> T07 GA6 AE39 IO_L19N_15 ############################################################################################ # # CMX Net-to-Resource File for the # # # TP Function FPGA Clock Connections # -=============-----=======------------- # # # Original Rev. 24-AUG-2012 # Rev. 9-Dec-2012 # Rev: 11-Dec-2012 File name changed for uniformity and consistency between Base and TP files # Rev: 29-Dec-2012 Remove the JTAG nets from this file. Remove "jtag" from the filename. # Rev: 16-Jan-2013 Change "Not_Used_" to "No_Conn_". # Most Recent Rev: 2-May-2013 Change Logic and GTX clock net names to # reflect the 40.08 or 320.64 MHz LHC clocks # and the 40.000 or 100.000 MHz Crystal clocks # # # # Topological Processor FPGA Clocks Logic and Transceiver # -----------------------------======------------------------ # # # LHC Locked Logic Clocks # # Connect the 40.08 MHz and 320.64 MHz Logic Clocks to # the Topological Processor FPGA. These are LHC locked LVDS # clock signals to the Logic in the Topological Processor FPGA. # # A Global Clock input in I/O Bank 34 receives the DeSkew #1 40.08 MHz Logic clock. # # A Global Clock input in I/O Bank 25 receives the DeSkew #2 40.08 MHz Logic clock. # # A Global Clock input in I/O Bank 34 receives the 320.64 MHz Logic clock. # NET 'CLK_40MHz08_DSKW_1_TP_LOGIC_DIR' U2-AY14 # AY14 40.08 MHz DeSkew-1 LHC Logic IO_L0P_GC_34 NET 'CLK_40MHz08_DSKW_1_TP_LOGIC_CMP' U2-AY13 # AY13 Clk to the Topological FPGA IO_L0N_GC_34 NET 'CLK_40MHz08_DSKW_2_TP_LOGIC_DIR' U2-J42 # J42 40.08 MHz DeSkew-2 LHC Logic IO_L18P_GC_25 NET 'CLK_40MHz08_DSKW_2_TP_LOGIC_CMP' U2-K42 # K42 Clk to the Topological FPGA IO_L18N_GC_25 NET 'CLK_320MHz64_LHC_TP_LOGIC_DIR' U2-AP12 # AP12 320.64 MHz LHC Logic Clock IO_L1N_GC_34 NET 'CLK_320MHz64_LHC_TP_LOGIC_CMP' U2-AP11 # AP11 to the Topological FPGA IO_L1P_GC_34 # # Crystal Oscillator #2 GTX Clock # # Now to the Topological Processor FPGA connect the 40.000 MHz # or 100.000 Mhz Crystal Oscillator #2 LVPECL clock to the # clock "0" input of the GTX Transceiver Quad 110. # # This is the clock to the GTX Transcievers that # transmit the DAQ and ROI data either by G-Link # or by S-Link. # NET 'CLK_100MHz000_XTAL_2_TP_TRNCV_DIR' U2-BA10 # BA10 100.000 MHz Crystal Osc #2 MGTREFCLK0P_110 NET 'CLK_100MHz000_XTAL_2_TP_TRNCV_CMP' U2-BA9 # BA9 GTX Clk to the TP FPGA. MGTREFCLK0N_110 # This could also be 40.000 MHz # # LHC Locked GTX Clocks # # Now on the Topological Processor FPGA connect the # 320.64 MHz LHC locked LVPECL clocks to the clock # inputs of the GTX Transceivers. # # We will use the "0" clock inputs to the Quad Banks # 111, 114, and 117 to receive these Transceiver clocks. # These are the Topological Processor GTX Transceivers # that receive the 6.4 Gbps L1Topo data. # NET 'CLK_320MHz64_LHC_TP_QUAD_111_DIR' U2-AU10 # AU10 320.64 MHz LHC GTX Clk #1 MGTREFCLK0P_111 NET 'CLK_320MHz64_LHC_TP_QUAD_111_CMP' U2-AU9 # AU9 to the Topological FPGA MGTREFCLK0N_111 NET 'CLK_320MHz64_LHC_TP_QUAD_114_DIR' U2-AB8 # AB8 320.64 MHz LHC GTX Clk #2 MGTREFCLK0P_114 NET 'CLK_320MHz64_LHC_TP_QUAD_114_CMP' U2-AB7 # AB7 to the Topological FPGA MGTREFCLK0N_114 NET 'CLK_320MHz64_LHC_TP_QUAD_117_DIR' U2-G10 # G10 320.64 MHz LHC GTX Clk #3 MGTREFCLK0P_117 NET 'CLK_320MHz64_LHC_TP_QUAD_117_CMP' U2-G9 # G9 to the Topological FPGA MGTREFCLK0N_117 # # Now on the Topological Processor FPGA connect ALL of the # UN-Used Tranceiver Clock Inputs to single point nets. # # Not Used Bank 110 Clock Input NET 'No_Conn_TP_GTX_CLK_1_110_DIR' U2-AW10 # pin AW10 MGTREFCLK1P_110 NET 'No_Conn_TP_GTX_CLK_1_110_CMP' U2-AW9 # pin AW9 MGTREFCLK1N_110 # Not Used Bank 111 Clock Input NET 'No_Conn_TP_GTX_CLK_1_111_DIR' U2-AT8 # pin AT8 MGTREFCLK1P_111 NET 'No_Conn_TP_GTX_CLK_1_111_CMP' U2-AT7 # pin AT7 MGTREFCLK1N_111 # Not Used Bank 112 Clock Inputs NET 'No_Conn_TP_GTX_CLK_0_112_DIR' U2-AK8 # pin AK8 MGTREFCLK0P_112 NET 'No_Conn_TP_GTX_CLK_0_112_CMP' U2-AK7 # pin AK7 MGTREFCLK0N_112 NET 'No_Conn_TP_GTX_CLK_1_112_DIR' U2-AH8 # pin AH8 MGTREFCLK1P_112 NET 'No_Conn_TP_GTX_CLK_1_112_CMP' U2-AH7 # pin AH7 MGTREFCLK1N_112 # Not Used Bank 113 Clock Inputs NET 'No_Conn_TP_GTX_CLK_0_113_DIR' U2-AF8 # pin AF8 MGTREFCLK0P_113 NET 'No_Conn_TP_GTX_CLK_0_113_CMP' U2-AF7 # pin AF7 MGTREFCLK0N_113 NET 'No_Conn_TP_GTX_CLK_1_113_DIR' U2-AD8 # pin AD8 MGTREFCLK1P_113 NET 'No_Conn_TP_GTX_CLK_1_113_CMP' U2-AD7 # pin AD7 MGTREFCLK1N_113 # Not Used Bank 114 Clock Input NET 'No_Conn_TP_GTX_CLK_1_114_DIR' U2-Y8 # pin Y8 MGTREFCLK1P_114 NET 'No_Conn_TP_GTX_CLK_1_114_CMP' U2-Y7 # pin Y7 MGTREFCLK1N_114 # Not Used Bank 115 Clock Inputs NET 'No_Conn_TP_GTX_CLK_0_115_DIR' U2-V8 # pin V8 MGTREFCLK0P_115 NET 'No_Conn_TP_GTX_CLK_0_115_CMP' U2-V7 # pin V7 MGTREFCLK0N_115 NET 'No_Conn_TP_GTX_CLK_1_115_DIR' U2-T8 # pin T8 MGTREFCLK1P_115 NET 'No_Conn_TP_GTX_CLK_1_115_CMP' U2-T7 # pin T7 MGTREFCLK1N_115 # Not Used Bank 116 Clock Inputs NET 'No_Conn_TP_GTX_CLK_0_116_DIR' U2-M8 # pin M8 MGTREFCLK0P_116 NET 'No_Conn_TP_GTX_CLK_0_116_CMP' U2-M7 # pin M7 MGTREFCLK0N_116 NET 'No_Conn_TP_GTX_CLK_1_116_DIR' U2-K8 # pin K8 MGTREFCLK1P_116 NET 'No_Conn_TP_GTX_CLK_1_116_CMP' U2-K7 # pin K7 MGTREFCLK1N_116 # Not Used Bank 117 Clock Input NET 'No_Conn_TP_GTX_CLK_1_117_DIR' U2-E10 # pin E10 MGTREFCLK1P_117 NET 'No_Conn_TP_GTX_CLK_1_117_CMP' U2-E9 # pin E9 MGTREFCLK1N_117 # Not Used Bank 118 Clock Inputs NET 'No_Conn_TP_GTX_CLK_0_118_DIR' U2-C10 # pin C10 MGTREFCLK0P_118 NET 'No_Conn_TP_GTX_CLK_0_118_CMP' U2-C9 # pin C9 MGTREFCLK0N_118 NET 'No_Conn_TP_GTX_CLK_1_118_DIR' U2-A10 # pin A10 MGTREFCLK1P_118 NET 'No_Conn_TP_GTX_CLK_1_118_CMP' U2-A9 # pin A9 MGTREFCLK1N_118 ############################################################################################ # # CMX Net-to-Resource File for the # Topo Function FPGA IO signals used for the connections to the TTC signals # -=============------------------------------------------================== # # # Original Rev. 28-Mar-2012 # Most Recent Rev. 04-Apr-2013 find location for these 53x signals # # ############################################################################################ # 53x signals are connecting to the buffered version of the TTCdec signals NET 'BUF_TTC_BRCST_2' U2-BB34 #> F07 #> T07 BB34 IO_L15P_12 NET 'BUF_TTC_BRCST_3' U2-BA34 #> F07 #> T07 BA34 IO_L15N_12 NET 'BUF_TTC_BRCST_4' U2-BA35 #> F07 #> T07 BA35 IO_L17P_12 NET 'BUF_TTC_BRCST_5' U2-BB36 #> F07 #> T07 BB36 IO_L13P_12 NET 'BUF_TTC_BRCST_6' U2-BA36 #> F07 #> T07 BA36 IO_L13N_12 NET 'BUF_TTC_BRCST_7' U2-BB37 #> F07 #> T07 BB37 IO_L11N_SRCC_12 NET 'BUF_TTC_BRCST_STR_1' U2-BA37 #> F07 #> T07 BA37 IO_L11P_SRCC_12 NET 'BUF_TTC_BRCST_STR_2' U2-BB38 #> F07 #> T07 BB38 IO_L7N_12 NET 'BUF_TTC_SIN_ERR_STR' U2-AY38 #> F07 #> T07 AY38 IO_L5P_12 NET 'BUF_TTC_DB_ERR_STR' U2-BB39 #> F07 #> T07 BB39 IO_L7P_12 NET 'BUF_TTC_CLK_40_L1A' U2-BA39 #> F07 #> T07 BA39 IO_L3N_12 NET 'BUF_TTC_BNCH_CNT_RES' U2-BA40 #> F07 #> T07 BA40 IO_L17P_13 NET 'BUF_TTC_EV_CNT_RES' U2-BB41 #> F07 #> T07 BB41 IO_L15N_13 NET 'BUF_TTC_EV_CNT_H_STR' U2-BA41 #> F07 #> T07 BA41 IO_L15P_13 NET 'BUF_TTC_EV_CNT_L_STR' U2-BA42 #> F07 #> T07 BA42 IO_L13N_13 NET 'BUF_TTC_BNCH_CNT_STR' U2-AY39 #> F07 #> T07 AY39 IO_L3P_12 NET 'BUF_TTC_B_CNT_0' U2-AY40 #> F07 #> T07 AY40 IO_L17N_13 NET 'BUF_TTC_B_CNT_1' U2-AY42 #> F07 #> T07 AY42 IO_L13P_13 NET 'BUF_TTC_B_CNT_2' U2-AW40 #> F07 #> T07 AW40 IO_L19N_13 NET 'BUF_TTC_B_CNT_3' U2-AW41 #> F07 #> T07 AW41 IO_L7N_13 NET 'BUF_TTC_B_CNT_4' U2-AW42 #> F07 #> T07 AW42 IO_L7P_13 NET 'BUF_TTC_B_CNT_5' U2-AV40 #> F07 #> T07 AV40 IO_L19P_13 NET 'BUF_TTC_B_CNT_6' U2-AV41 #> F07 #> T07 AV41 IO_L11P_SRCC_13 NET 'BUF_TTC_B_CNT_7' U2-AU39 #> F07 #> T07 AU39 IO_L10N_MRCC_13 NET 'BUF_TTC_B_CNT_8' U2-AU41 #> F07 #> T07 AU41 IO_L11N_SRCC_13 NET 'BUF_TTC_B_CNT_9' U2-AU42 #> F07 #> T07 AU42 IO_L5N_13 NET 'BUF_TTC_B_CNT_10' U2-AT40 #> F07 #> T07 AT40 IO_L10P_MRCC_13 NET 'BUF_TTC_B_CNT_11' U2-AT41 #> F07 #> T07 AT41 IO_L8N_SRCC_13 NET 'BUF_TTC_DQ_0' U2-AT42 #> F07 #> T07 AT42 IO_L5P_13 NET 'BUF_TTC_DQ_1' U2-AR39 #> F07 #> T07 AR39 IO_L14P_13 NET 'BUF_TTC_DQ_2' U2-AR40 #> F07 #> T07 AR40 IO_L8P_SRCC_13 NET 'BUF_TTC_DQ_3' U2-AR42 #> F07 #> T07 AR42 IO_L3N_13 NET 'BUF_TTC_L1_ACCEPT' U2-AP40 #> F07 #> T07 AP40 IO_L0N_13 NET 'BUF_TTC_SER_B_CH' U2-AP41 #> F07 #> T07 AP41 IO_L1N_13 NET 'BUF_TTC_D_OUT_STR' U2-AP42 #> F07 #> T07 AP42 IO_L3P_13 NET 'BUF_TTC_READY' U2-AN40 #> F07 #> T07 AN40 IO_L0P_13 NET 'BUF_TTC_STATUS_2' U2-AN41 #> F07 #> T07 AN41 IO_L1P_13 NET 'BUF_TTC_D_OUT_0' U2-AM39 #> F07 #> T07 AM39 IO_L2N_13 NET 'BUF_TTC_D_OUT_1' U2-AM41 #> F07 #> T07 AM41 IO_L15N_14 NET 'BUF_TTC_D_OUT_2' U2-AM42 #> F07 #> T07 AM42 IO_L13N_14 NET 'BUF_TTC_D_OUT_3' U2-AL40 #> F07 #> T07 AL40 IO_L17N_14 NET 'BUF_TTC_D_OUT_4' U2-AL41 #> F07 #> T07 AL41 IO_L15P_14 NET 'BUF_TTC_D_OUT_5' U2-AL42 #> F07 #> T07 AL42 IO_L13P_14 NET 'BUF_TTC_D_OUT_6' U2-AK39 #> F07 #> T07 AK39 IO_L19P_14 NET 'BUF_TTC_D_OUT_7' U2-AK40 #> F07 #> T07 AK40 IO_L17P_14 NET 'BUF_TTC_SUB_ADRS_0' U2-AK42 #> F07 #> T07 AK42 IO_L7N_14 NET 'BUF_TTC_SUB_ADRS_1' U2-AJ40 #> F07 #> T07 AJ40 IO_L11N_SRCC_14 NET 'BUF_TTC_SUB_ADRS_2' U2-AJ41 #> F07 #> T07 AJ41 IO_L5N_14 NET 'BUF_TTC_SUB_ADRS_3' U2-AJ42 #> F07 #> T07 AJ42 IO_L7P_14 NET 'BUF_TTC_SUB_ADRS_4' U2-AH40 #> F07 #> T07 AH40 IO_L5P_14 NET 'BUF_TTC_SUB_ADRS_5' U2-AH41 #> F07 #> T07 AH41 IO_L3N_14 NET 'BUF_TTC_SUB_ADRS_6' U2-AG41 #> F07 #> T07 AG41 IO_L1N_14 NET 'BUF_TTC_SUB_ADRS_7' U2-AG42 #> F07 #> T07 AG42 IO_L3P_14 ############################################################################################ # # CMX Net-to-Resource File for the # Topo Function FPGA IO signals used for the connections to the TP FPGA # -=============------------------------------------------================ # # Original Rev. 02-Apr-2012 # Rev. 03-Apr-2013 find location for these signals # Most Recent Rev. 20-Jun-2013 swap the two channels to ease trace routing # # BF to TP connections for support of S-link return channels # ========----------------------------====================== # # If the TP function needs to support S-link protocol (rather than G-link) # the CMX will need to receive the return channel of the Duplex S-link. # # The SFP optical receiver from the 2x S-link connections (DAQ and ROI) # cannot be directly received in the TP FPGA because all 36x MGT receivers # of the TP FPGA are already used with the 3x12 Avago optical receivers. # # The SFP optical receivers are instead routed to MGT receivers located # on the BF FPGA and the serial signal received is sent from the BF FPGA # to the TP FPGA via two differential Select IO signals. # # Signal Nets referenced in this file: # ------------------------------------ # # BF_TO_TP_DAQ_SLINK_RETURN_DIR Direct signal # BF_TO_TP_DAQ_SLINK_RETURN_CMP Complement signal # for the return S-link channel for DAQ readout # # BF_TO_TP_ROI_SLINK_RETURN_DIR Direct signal # BF_TO_TP_ROI_SLINK_RETURN_CMP Complement signal # for the return S-link channel for ROI readout # ############################################################################################ # 4x Select IO pins forming 2x differential signals going to the TP FPGA # This is IO Bank 26 and the signals will be routed north on trace layer 6. NET 'BF_TO_TP_DAQ_SLINK_RETURN_DIR' U2-A40 #> F06 #> T06 A40 IO_L7P_26 NET 'BF_TO_TP_DAQ_SLINK_RETURN_CMP' U2-A41 #> F06 #> T06 A41 IO_L7N_26 NET 'BF_TO_TP_ROI_SLINK_RETURN_DIR' U2-B38 #> F06 #> T06 B38 IO_L3P_26 NET 'BF_TO_TP_ROI_SLINK_RETURN_CMP' U2-A39 #> F06 #> T06 A39 IO_L3N_26 ############################################################################################ # # CMX Net-to-Resource File for the # Topo Function FPGA IO signals used for the connections to the Board Support FPGA # -=============------------------------------------------========================== # # # Original Rev. 28-Mar-2012 # Rev. 03-Apr-2013 find location for these 15x signals # Most Recent Rev. 20-Jun-2013 Swap TP_TO_FROM_BSPT_6 and _7 to help trace layout # # Signal Nets referenced in this file: # ------------------------------------ # # TP_REQ_CTP_n_INPUT (n=1:2) 2x direction request for CTP cable n sent to BSPT FPGA # # TP_LED_REQ_n (n=0:4) 5x LED state request sent to BSPT FPGA # # TP_TO_FROM_BSPT_n (n=0:7) 8x un-assigned Input or Ouput connections to BSPT FPGA # ############################################################################################ # 15x signals are going to the Board Support FPGA on layer 7 # These signals are listed in west to east order as they leave the FPGA area on layer 7 NET 'TP_REQ_CTP_1_INPUT' U2-A32 #> F07 #> T07 A32 IO_L1P_27 NET 'TP_REQ_CTP_2_INPUT' U2-B32 #> F07 #> T07 B32 IO_L1N_27 NET 'TP_LED_REQ_0' U2-B33 #> F07 #> T07 B33 IO_L3P_27 NET 'TP_LED_REQ_1' U2-A34 #> F07 #> T07 A34 IO_L5P_27 NET 'TP_LED_REQ_2' U2-B34 #> F01 #> T07 B34 IO_L7P_27 NET 'TP_LED_REQ_3' U2-A35 #> F01 #> T07 A35 IO_L5N_27 NET 'TP_LED_REQ_4' U2-C35 #> F01 #> T07 C35 IO_L15P_27 NET 'TP_TO_FROM_BSPT_0' U2-A36 #> F06 #> T07 A36 IO_L13P_27 NET 'TP_TO_FROM_BSPT_1' U2-B36 #> F06 #> T07 B36 IO_L13N_27 NET 'TP_TO_FROM_BSPT_2' U2-A37 #> F01 #> T07 A37 IO_L1N_26 NET 'TP_TO_FROM_BSPT_3' U2-B37 #> F01 #> T07 B37 IO_L1P_26 NET 'TP_TO_FROM_BSPT_4' U2-C38 #> F01 #> T07 C38 IO_L6N_26 NET 'TP_TO_FROM_BSPT_5' U2-B39 #> F07 #> T07 B39 IO_L5P_26 NET 'TP_TO_FROM_BSPT_6' U2-B41 #> F07 #> T07 B41 IO_L11P_SRCC_26 NET 'TP_TO_FROM_BSPT_7' U2-C40 #> F07 #> T07 C40 IO_L13P_26 ############################################################################################ # # CMX Net-to-Resource File for the # Topo Function FPGA IO signals used for the connections to the Debug Connector # -=============------------------------------------------====================== # # # Original Rev. 28-Mar-2012 # Rev. 03-Apr-2013 find location for these 10x signals without interfering with backplane inputs # Most Recent Rev: 10-Jul-2013 Reorder pin assignment for straight route near debug connector # # Signal Nets referenced in this file: # ------------------------------------ # # TP_DEBUG_n (n=0:9) 10x spare connections from the BF FPGA to debug connector J14 # ############################################################################################ # 10x signals are going to the Debug Connector on layer 6 NET 'TP_DEBUG_0' U2-F42 #> F06 #> T06 F42 IO_L19N_26 NET 'TP_DEBUG_1' U2-D41 #> F06 #> T06 D41 IO_L15N_26 NET 'TP_DEBUG_2' U2-F41 #> F06 #> T06 F41 IO_L16N_26 NET 'TP_DEBUG_3' U2-D42 #> F06 #> T06 D42 IO_L15P_26 NET 'TP_DEBUG_4' U2-E42 #> F06 #> T06 E42 IO_L19P_26 NET 'TP_DEBUG_5' U2-E40 #> F06 #> T06 E40 IO_L17N_26 NET 'TP_DEBUG_6' U2-G41 #> F06 #> T06 G41 IO_L18P_26 NET 'TP_DEBUG_7' U2-C41 #> F06 #> T06 C41 IO_L13N_26 NET 'TP_DEBUG_8' U2-G42 #> F06 #> T06 G42 IO_L18N_26 NET 'TP_DEBUG_9' U2-B42 #> F06 #> T06 B42 IO_L11N_SRCC_26 ############################################################################################ # # CMX Net-to-Resource File for the # TP Function FPGA IO signals used for all unused and Not Connected MGT IO pins # -=============-----------------------------------------====================---------- # # # Original Rev. 17-Jan-2013 # Most Recent Rev. 17-Jan-2013 Initial roundup # # # On the TP Function FPGA connect ALL of the # UN-Used Tranceiver IO Pins to single point nets. # # Signal Nets referenced in this file: # ------------------------------------ # # 'No_Conn_TP_xxxx' are the unique net names assigned to these MGT IO signals # where "xxxx" is the fpga MGT IO signal name # ############################################################################################ ################ # Receivers ################ # All Receiver Channels from MGT Quad 110 to 118 are used to field the miniPOD recievers # Those nets are defined in tp_function_gtx_receivers_n2r.txt # ################ # Transmitters ################ # Two of the Tramsmitter channels from MGT Quad 110 are used for the g-link output # Those nets are defined in base_function_low_speed_daq_roi_data_out_n2r.txt # The other two channels are unused NET 'No_Conn_TP_MGTTXP2_110' U2-AY3 # 110 AY3 MGTTXP2_110 NET 'No_Conn_TP_MGTTXN2_110' U2-AY4 # 110 AY4 MGTTXN2_110 NET 'No_Conn_TP_MGTTXP3_110' U2-AW1 # 110 AW1 MGTTXP3_110 NET 'No_Conn_TP_MGTTXN3_110' U2-AW2 # 110 AW2 MGTTXN3_110 # All Tramsmitter Channels from MGT Quad 111 are unused NET 'No_Conn_TP_MGTTXP0_111' U2-AV3 # 111 AV3 MGTTXP0_111 NET 'No_Conn_TP_MGTTXN0_111' U2-AV4 # 111 AV4 MGTTXN0_111 NET 'No_Conn_TP_MGTTXP1_111' U2-AU1 # 111 AU1 MGTTXP1_111 NET 'No_Conn_TP_MGTTXN1_111' U2-AU2 # 111 AU2 MGTTXN1_111 NET 'No_Conn_TP_MGTTXP2_111' U2-AT3 # 111 AT3 MGTTXP2_111 NET 'No_Conn_TP_MGTTXN2_111' U2-AT4 # 111 AT4 MGTTXN2_111 NET 'No_Conn_TP_MGTTXP3_111' U2-AR1 # 111 AR1 MGTTXP3_111 NET 'No_Conn_TP_MGTTXN3_111' U2-AR2 # 111 AR2 MGTTXN3_111 # All Tramsmitter Channels from MGT Quad 112 are unused NET 'No_Conn_TP_MGTTXP0_112' U2-AP3 # 112 AP3 MGTTXP0_112 NET 'No_Conn_TP_MGTTXN0_112' U2-AP4 # 112 AP4 MGTTXN0_112 NET 'No_Conn_TP_MGTTXP1_112' U2-AN1 # 112 AN1 MGTTXP1_112 NET 'No_Conn_TP_MGTTXN1_112' U2-AN2 # 112 AN2 MGTTXN1_112 NET 'No_Conn_TP_MGTTXP2_112' U2-AM3 # 112 AM3 MGTTXP2_112 NET 'No_Conn_TP_MGTTXN2_112' U2-AM4 # 112 AM4 MGTTXN2_112 NET 'No_Conn_TP_MGTTXP3_112' U2-AL1 # 112 AL1 MGTTXP3_112 NET 'No_Conn_TP_MGTTXN3_112' U2-AL2 # 112 AL2 MGTTXN3_112 # All Tramsmitter Channels from MGT Quad 113 are unused NET 'No_Conn_TP_MGTTXP0_113' U2-AK3 # 113 AK3 MGTTXP0_113 NET 'No_Conn_TP_MGTTXN0_113' U2-AK4 # 113 AK4 MGTTXN0_113 NET 'No_Conn_TP_MGTTXP1_113' U2-AJ1 # 113 AJ1 MGTTXP1_113 NET 'No_Conn_TP_MGTTXN1_113' U2-AJ2 # 113 AJ2 MGTTXN1_113 NET 'No_Conn_TP_MGTTXP2_113' U2-AH3 # 113 AH3 MGTTXP2_113 NET 'No_Conn_TP_MGTTXN2_113' U2-AH4 # 113 AH4 MGTTXN2_113 NET 'No_Conn_TP_MGTTXP3_113' U2-AG1 # 113 AG1 MGTTXP3_113 NET 'No_Conn_TP_MGTTXN3_113' U2-AG2 # 113 AG2 MGTTXN3_113 # All Tramsmitter Channels from MGT Quad 114 are unused NET 'No_Conn_TP_MGTTXP0_114' U2-AE1 # 114 AE1 MGTTXP0_114 NET 'No_Conn_TP_MGTTXN0_114' U2-AE2 # 114 AE2 MGTTXN0_114 NET 'No_Conn_TP_MGTTXP1_114' U2-AC1 # 114 AC1 MGTTXP1_114 NET 'No_Conn_TP_MGTTXN1_114' U2-AC2 # 114 AC2 MGTTXN1_114 NET 'No_Conn_TP_MGTTXP2_114' U2-AA1 # 114 AA1 MGTTXP2_114 NET 'No_Conn_TP_MGTTXN2_114' U2-AA2 # 114 AA2 MGTTXN2_114 NET 'No_Conn_TP_MGTTXP3_114' U2-W1 # 114 W1 MGTTXP3_114 NET 'No_Conn_TP_MGTTXN3_114' U2-W2 # 114 W2 MGTTXN3_114 # All Tramsmitter Channels from MGT Quad 115 are unused NET 'No_Conn_TP_MGTTXP0_115' U2-U1 # 115 U1 MGTTXP0_115 NET 'No_Conn_TP_MGTTXN0_115' U2-U2 # 115 U2 MGTTXN0_115 NET 'No_Conn_TP_MGTTXP1_115' U2-T3 # 115 T3 MGTTXP1_115 NET 'No_Conn_TP_MGTTXN1_115' U2-T4 # 115 T4 MGTTXN1_115 NET 'No_Conn_TP_MGTTXP2_115' U2-R1 # 115 R1 MGTTXP2_115 NET 'No_Conn_TP_MGTTXN2_115' U2-R2 # 115 R2 MGTTXN2_115 NET 'No_Conn_TP_MGTTXP3_115' U2-P3 # 115 P3 MGTTXP3_115 NET 'No_Conn_TP_MGTTXN3_115' U2-P4 # 115 P4 MGTTXN3_115 # All Tramsmitter Channels from MGT Quad 116 are unused NET 'No_Conn_TP_MGTTXP0_116' U2-N1 # 116 N1 MGTTXP0_116 NET 'No_Conn_TP_MGTTXN0_116' U2-N2 # 116 N2 MGTTXN0_116 NET 'No_Conn_TP_MGTTXP1_116' U2-M3 # 116 M3 MGTTXP1_116 NET 'No_Conn_TP_MGTTXN1_116' U2-M4 # 116 M4 MGTTXN1_116 NET 'No_Conn_TP_MGTTXP2_116' U2-L1 # 116 L1 MGTTXP2_116 NET 'No_Conn_TP_MGTTXN2_116' U2-L2 # 116 L2 MGTTXN2_116 NET 'No_Conn_TP_MGTTXP3_116' U2-K3 # 116 K3 MGTTXP3_116 NET 'No_Conn_TP_MGTTXN3_116' U2-K4 # 116 K4 MGTTXN3_116 # All Tramsmitter Channels from MGT Quad 117 are unused NET 'No_Conn_TP_MGTTXP0_117' U2-J1 # 117 J1 MGTTXP0_117 NET 'No_Conn_TP_MGTTXN0_117' U2-J2 # 117 J2 MGTTXN0_117 NET 'No_Conn_TP_MGTTXP1_117' U2-H3 # 117 H3 MGTTXP1_117 NET 'No_Conn_TP_MGTTXN1_117' U2-H4 # 117 H4 MGTTXN1_117 NET 'No_Conn_TP_MGTTXP2_117' U2-G1 # 117 G1 MGTTXP2_117 NET 'No_Conn_TP_MGTTXN2_117' U2-G2 # 117 G2 MGTTXN2_117 NET 'No_Conn_TP_MGTTXP3_117' U2-F3 # 117 F3 MGTTXP3_117 NET 'No_Conn_TP_MGTTXN3_117' U2-F4 # 117 F4 MGTTXN3_117 # All Tramsmitter Channels from MGT Quad 118 are unused NET 'No_Conn_TP_MGTTXP0_118' U2-E1 # 118 E1 MGTTXP0_118 NET 'No_Conn_TP_MGTTXN0_118' U2-E2 # 118 E2 MGTTXN0_118 NET 'No_Conn_TP_MGTTXP1_118' U2-D3 # 118 D3 MGTTXP1_118 NET 'No_Conn_TP_MGTTXN1_118' U2-D4 # 118 D4 MGTTXN1_118 NET 'No_Conn_TP_MGTTXP2_118' U2-C1 # 118 C1 MGTTXP2_118 NET 'No_Conn_TP_MGTTXN2_118' U2-C2 # 118 C2 MGTTXN2_118 NET 'No_Conn_TP_MGTTXP3_118' U2-B3 # 118 B3 MGTTXP3_118 NET 'No_Conn_TP_MGTTXN3_118' U2-B4 # 118 B4 MGTTXN3_118 ############################################################################################ # # CMX Net-to-Resource File for the # TP Function FPGA IO signals used for all unused and Not Connected Select IO pins # -=============-----------------------------------------=======================------- # # # Original Rev. 17-Jan-2013 # Rev. 17-Jan-2013 Initial roundup # Most Recent Rev. 04-Apr-2013 Remove pins now assigned to connections to Board Support FPGA, # Debug Connector, BF to TP S-Link, and TTC signals. # # Signal Nets referenced in this file: # ------------------------------------ # # 'No_Conn_TP_xxxx' are the unique net names assigned to these Select IO signals # where "xxxx" is the fpga Select IO signal name # ############################################################################################ # Unused pins from IO bank 12 ############################# # note: This bank is otherwise used for TTC connections NET 'No_Conn_TP_IO_L9P_MRCC_12' U2-AN35 # 12 AN35 IO_L9P_MRCC_12 NET 'No_Conn_TP_IO_L9N_MRCC_12' U2-AN36 # 12 AN36 IO_L9N_MRCC_12 NET 'No_Conn_TP_IO_L10N_MRCC_12' U2-AP35 # 12 AP35 IO_L10N_MRCC_12 NET 'No_Conn_TP_IO_L10P_MRCC_12' U2-AP36 # 12 AP36 IO_L10P_MRCC_12 NET 'No_Conn_TP_IO_L2P_12' U2-AP37 # 12 AP37 IO_L2P_12 NET 'No_Conn_TP_IO_L12P_VRN_12' U2-AR35 # 12 AR35 IO_L12P_VRN_12 NET 'No_Conn_TP_IO_L2N_12' U2-AR37 # 12 AR37 IO_L2N_12 NET 'No_Conn_TP_IO_L0N_12' U2-AR38 # 12 AR38 IO_L0N_12 NET 'No_Conn_TP_IO_L16N_12' U2-AT34 # 12 AT34 IO_L16N_12 NET 'No_Conn_TP_IO_L12N_VRP_12' U2-AT35 # 12 AT35 IO_L12N_VRP_12 NET 'No_Conn_TP_IO_L6N_12' U2-AT36 # 12 AT36 IO_L6N_12 NET 'No_Conn_TP_IO_L0P_12' U2-AT37 # 12 AT37 IO_L0P_12 NET 'No_Conn_TP_IO_L16P_12' U2-AU34 # 12 AU34 IO_L16P_12 NET 'No_Conn_TP_IO_L6P_12' U2-AU36 # 12 AU36 IO_L6P_12 NET 'No_Conn_TP_IO_L4P_12' U2-AU37 # 12 AU37 IO_L4P_12 NET 'No_Conn_TP_IO_L4N_VREF_12' U2-AU38 # 12 AU38 IO_L4N_VREF_12 NET 'No_Conn_TP_IO_L18P_12' U2-AV34 # 12 AV34 IO_L18P_12 NET 'No_Conn_TP_IO_L18N_12' U2-AV35 # 12 AV35 IO_L18N_12 NET 'No_Conn_TP_IO_L14N_VREF_12' U2-AV36 # 12 AV36 IO_L14N_VREF_12 NET 'No_Conn_TP_IO_L1N_12' U2-AV38 # 12 AV38 IO_L1N_12 NET 'No_Conn_TP_IO_L1P_12' U2-AV39 # 12 AV39 IO_L1P_12 NET 'No_Conn_TP_IO_L19N_12' U2-AW35 # 12 AW35 IO_L19N_12 NET 'No_Conn_TP_IO_L14P_12' U2-AW36 # 12 AW36 IO_L14P_12 NET 'No_Conn_TP_IO_L8P_SRCC_12' U2-AW37 # 12 AW37 IO_L8P_SRCC_12 NET 'No_Conn_TP_IO_L8N_SRCC_12' U2-AW38 # 12 AW38 IO_L8N_SRCC_12 NET 'No_Conn_TP_IO_L19P_12' U2-AY34 # 12 AY34 IO_L19P_12 NET 'No_Conn_TP_IO_L17N_12' U2-AY35 # 12 AY35 IO_L17N_12 NET 'No_Conn_TP_IO_L5N_12' U2-AY37 # 12 AY37 IO_L5N_12 # Unused pins from IO bank 13 ############################# # note: This bank is otherwise used for TTC connections NET 'No_Conn_TP_IO_L9N_MRCC_13' U2-AK34 # 13 AK34 IO_L9N_MRCC_13 NET 'No_Conn_TP_IO_L18P_13' U2-AK35 # 13 AK35 IO_L18P_13 NET 'No_Conn_TP_IO_L9P_MRCC_13' U2-AL34 # 13 AL34 IO_L9P_MRCC_13 NET 'No_Conn_TP_IO_L6N_13' U2-AL35 # 13 AL35 IO_L6N_13 NET 'No_Conn_TP_IO_L18N_13' U2-AL36 # 13 AL36 IO_L18N_13 NET 'No_Conn_TP_IO_L4P_13' U2-AL37 # 13 AL37 IO_L4P_13 NET 'No_Conn_TP_IO_L6P_13' U2-AM34 # 13 AM34 IO_L6P_13 NET 'No_Conn_TP_IO_L16N_13' U2-AM36 # 13 AM36 IO_L16N_13 NET 'No_Conn_TP_IO_L16P_13' U2-AM37 # 13 AM37 IO_L16P_13 NET 'No_Conn_TP_IO_L4N_VREF_13' U2-AM38 # 13 AM38 IO_L4N_VREF_13 NET 'No_Conn_TP_IO_L12P_VRN_13' U2-AN38 # 13 AN38 IO_L12P_VRN_13 NET 'No_Conn_TP_IO_L2P_13' U2-AN39 # 13 AN39 IO_L2P_13 NET 'No_Conn_TP_IO_L12N_VRP_13' U2-AP38 # 13 AP38 IO_L12N_VRP_13 NET 'No_Conn_TP_IO_L14N_VREF_13' U2-AT39 # 13 AT39 IO_L14N_VREF_13 # Unused pins from IO bank 14 ############################# # note: This bank is otherwise used for TTC connections NET 'No_Conn_TP_IO_L18P_14' U2-AF32 # 14 AF32 IO_L18P_14 NET 'No_Conn_TP_IO_L0N_14' U2-AF34 # 14 AF34 IO_L0N_14 NET 'No_Conn_TP_IO_L16P_14' U2-AF35 # 14 AF35 IO_L16P_14 NET 'No_Conn_TP_IO_L16N_14' U2-AF36 # 14 AF36 IO_L16N_14 NET 'No_Conn_TP_IO_L6P_14' U2-AF37 # 14 AF37 IO_L6P_14 NET 'No_Conn_TP_IO_L2P_14' U2-AF39 # 14 AF39 IO_L2P_14 NET 'No_Conn_TP_IO_L1P_14' U2-AF40 # 14 AF40 IO_L1P_14 NET 'No_Conn_TP_IO_L18N_14' U2-AG33 # 14 AG33 IO_L18N_14 NET 'No_Conn_TP_IO_L0P_14' U2-AG34 # 14 AG34 IO_L0P_14 NET 'No_Conn_TP_IO_L14P_14' U2-AG36 # 14 AG36 IO_L14P_14 NET 'No_Conn_TP_IO_L6N_14' U2-AG37 # 14 AG37 IO_L6N_14 NET 'No_Conn_TP_IO_L4P_14' U2-AG38 # 14 AG38 IO_L4P_14 NET 'No_Conn_TP_IO_L2N_14' U2-AG39 # 14 AG39 IO_L2N_14 NET 'No_Conn_TP_IO_L9P_MRCC_14' U2-AH34 # 14 AH34 IO_L9P_MRCC_14 NET 'No_Conn_TP_IO_L12N_VRP_14' U2-AH35 # 14 AH35 IO_L12N_VRP_14 NET 'No_Conn_TP_IO_L14N_VREF_14' U2-AH36 # 14 AH36 IO_L14N_VREF_14 NET 'No_Conn_TP_IO_L4N_VREF_14' U2-AH38 # 14 AH38 IO_L4N_VREF_14 NET 'No_Conn_TP_IO_L11P_SRCC_14' U2-AH39 # 14 AH39 IO_L11P_SRCC_14 NET 'No_Conn_TP_IO_L9N_MRCC_14' U2-AJ35 # 14 AJ35 IO_L9N_MRCC_14 NET 'No_Conn_TP_IO_L12P_VRN_14' U2-AJ36 # 14 AJ36 IO_L12P_VRN_14 NET 'No_Conn_TP_IO_L10P_MRCC_14' U2-AJ37 # 14 AJ37 IO_L10P_MRCC_14 NET 'No_Conn_TP_IO_L8N_SRCC_14' U2-AJ38 # 14 AJ38 IO_L8N_SRCC_14 NET 'No_Conn_TP_IO_L10N_MRCC_14' U2-AK37 # 14 AK37 IO_L10N_MRCC_14 NET 'No_Conn_TP_IO_L8P_SRCC_14' U2-AK38 # 14 AK38 IO_L8P_SRCC_14 NET 'No_Conn_TP_IO_L19N_14' U2-AL39 # 14 AL39 IO_L19N_14 # Unused pins from IO bank 15 ############################# # note: some pins from this bank are used for the On-Card Bus NET 'No_Conn_TP_IO_L12P_SM13P_15' U2-AB32 # 15 AB32 IO_L12P_SM13P_15 NET 'No_Conn_TP_IO_L12N_SM13N_15' U2-AB33 # 15 AB33 IO_L12N_SM13N_15 NET 'No_Conn_TP_IO_L16N_VRP_15' U2-AB34 # 15 AB34 IO_L16N_VRP_15 NET 'No_Conn_TP_IO_L8N_SRCC_15' U2-AB36 # 15 AB36 IO_L8N_SRCC_15 NET 'No_Conn_TP_IO_L1P_15' U2-AB37 # 15 AB37 IO_L1P_15 NET 'No_Conn_TP_IO_L18N_15' U2-AC33 # 15 AC33 IO_L18N_15 NET 'No_Conn_TP_IO_L18P_15' U2-AC34 # 15 AC34 IO_L18P_15 NET 'No_Conn_TP_IO_L16P_VRN_15' U2-AC35 # 15 AC35 IO_L16P_VRN_15 NET 'No_Conn_TP_IO_L8P_SRCC_15' U2-AC36 # 15 AC36 IO_L8P_SRCC_15 NET 'No_Conn_TP_IO_L4P_15' U2-AC38 # 15 AC38 IO_L4P_15 NET 'No_Conn_TP_IO_L9P_MRCC_15' U2-AD32 # 15 AD32 IO_L9P_MRCC_15 NET 'No_Conn_TP_IO_L2N_SM8N_15' U2-AD33 # 15 AD33 IO_L2N_SM8N_15 NET 'No_Conn_TP_IO_L14N_VREF_15' U2-AD35 # 15 AD35 IO_L14N_VREF_15 NET 'No_Conn_TP_IO_L14P_15' U2-AD36 # 15 AD36 IO_L14P_15 NET 'No_Conn_TP_IO_L10N_MRCC_15' U2-AD37 # 15 AD37 IO_L10N_MRCC_15 NET 'No_Conn_TP_IO_L6N_SM11N_15' U2-AD38 # 15 AD38 IO_L6N_SM11N_15 NET 'No_Conn_TP_IO_L9N_MRCC_15' U2-AE32 # 15 AE32 IO_L9N_MRCC_15 NET 'No_Conn_TP_IO_L2P_SM8P_15' U2-AE33 # 15 AE33 IO_L2P_SM8P_15 NET 'No_Conn_TP_IO_L0P_15' U2-AE34 # 15 AE34 IO_L0P_15 NET 'No_Conn_TP_IO_L0N_15' U2-AE35 # 15 AE35 IO_L0N_15 NET 'No_Conn_TP_IO_L10P_MRCC_15' U2-AE37 # 15 AE37 IO_L10P_MRCC_15 NET 'No_Conn_TP_IO_L6P_SM11P_15' U2-AE38 # 15 AE38 IO_L6P_SM11P_15 # Unused pins from IO bank 16 ############################# # note: some pins from this bank are used for the On-Card Bus NET 'No_Conn_TP_IO_L16P_16' U2-U32 # 16 U32 IO_L16P_16 NET 'No_Conn_TP_IO_L16N_16' U2-U33 # 16 U33 IO_L16N_16 NET 'No_Conn_TP_IO_L10N_MRCC_16' U2-U34 # 16 U34 IO_L10N_MRCC_16 NET 'No_Conn_TP_IO_L1P_16' U2-U37 # 16 U37 IO_L1P_16 NET 'No_Conn_TP_IO_L1N_16' U2-U38 # 16 U38 IO_L1N_16 NET 'No_Conn_TP_IO_L18P_16' U2-V33 # 16 V33 IO_L18P_16 NET 'No_Conn_TP_IO_L10P_MRCC_16' U2-V34 # 16 V34 IO_L10P_MRCC_16 NET 'No_Conn_TP_IO_L6N_16' U2-V35 # 16 V35 IO_L6N_16 NET 'No_Conn_TP_IO_L2N_16' U2-V36 # 16 V36 IO_L2N_16 NET 'No_Conn_TP_IO_L7P_16' U2-V38 # 16 V38 IO_L7P_16 NET 'No_Conn_TP_IO_L5N_16' U2-V39 # 16 V39 IO_L5N_16 NET 'No_Conn_TP_IO_L18N_16' U2-W33 # 16 W33 IO_L18N_16 NET 'No_Conn_TP_IO_L6P_16' U2-W35 # 16 W35 IO_L6P_16 NET 'No_Conn_TP_IO_L2P_16' U2-W36 # 16 W36 IO_L2P_16 NET 'No_Conn_TP_IO_L0P_16' U2-W37 # 16 W37 IO_L0P_16 NET 'No_Conn_TP_IO_L12N_VRP_16' U2-Y32 # 16 Y32 IO_L12N_VRP_16 NET 'No_Conn_TP_IO_L9N_MRCC_16' U2-Y33 # 16 Y33 IO_L9N_MRCC_16 NET 'No_Conn_TP_IO_L14N_VREF_16' U2-Y34 # 16 Y34 IO_L14N_VREF_16 NET 'No_Conn_TP_IO_L8N_SRCC_16' U2-Y35 # 16 Y35 IO_L8N_SRCC_16 NET 'No_Conn_TP_IO_L0N_16' U2-Y37 # 16 Y37 IO_L0N_16 NET 'No_Conn_TP_IO_L19P_16' U2-Y38 # 16 Y38 IO_L19P_16 NET 'No_Conn_TP_IO_L12P_VRN_16' U2-AA32 # 16 AA32 IO_L12P_VRN_16 NET 'No_Conn_TP_IO_L14P_16' U2-AA34 # 16 AA34 IO_L14P_16 NET 'No_Conn_TP_IO_L8P_SRCC_16' U2-AA35 # 16 AA35 IO_L8P_SRCC_16 NET 'No_Conn_TP_IO_L4P_16' U2-AA36 # 16 AA36 IO_L4P_16 NET 'No_Conn_TP_IO_L4N_VREF_16' U2-AA37 # 16 AA37 IO_L4N_VREF_16 # Unused pins from IO bank 17 ############################# # note: some pins from this bank are used for the On-Card Bus NET 'No_Conn_TP_IO_L1P_17' U2-L39 # 17 L39 IO_L1P_17 NET 'No_Conn_TP_IO_L0P_17' U2-M36 # 17 M36 IO_L0P_17 NET 'No_Conn_TP_IO_L0N_17' U2-M37 # 17 M37 IO_L0N_17 NET 'No_Conn_TP_IO_L2P_17' U2-M38 # 17 M38 IO_L2P_17 NET 'No_Conn_TP_IO_L4N_VREF_17' U2-N34 # 17 N34 IO_L4N_VREF_17 NET 'No_Conn_TP_IO_L4P_17' U2-N35 # 17 N35 IO_L4P_17 NET 'No_Conn_TP_IO_L6P_17' U2-N36 # 17 N36 IO_L6P_17 NET 'No_Conn_TP_IO_L5P_17' U2-N38 # 17 N38 IO_L5P_17 NET 'No_Conn_TP_IO_L5N_17' U2-N39 # 17 N39 IO_L5N_17 NET 'No_Conn_TP_IO_L9N_MRCC_17' U2-P35 # 17 P35 IO_L9N_MRCC_17 NET 'No_Conn_TP_IO_L9P_MRCC_17' U2-P36 # 17 P36 IO_L9P_MRCC_17 NET 'No_Conn_TP_IO_L6N_17' U2-P37 # 17 P37 IO_L6N_17 NET 'No_Conn_TP_IO_L8N_SRCC_17' U2-P38 # 17 P38 IO_L8N_SRCC_17 NET 'No_Conn_TP_IO_L14N_VREF_17' U2-R34 # 17 R34 IO_L14N_VREF_17 NET 'No_Conn_TP_IO_L14P_17' U2-R35 # 17 R35 IO_L14P_17 NET 'No_Conn_TP_IO_L12P_VRN_17' U2-R37 # 17 R37 IO_L12P_VRN_17 NET 'No_Conn_TP_IO_L10N_MRCC_17' U2-R38 # 17 R38 IO_L10N_MRCC_17 NET 'No_Conn_TP_IO_L18P_17' U2-T34 # 17 T34 IO_L18P_17 NET 'No_Conn_TP_IO_L18N_17' U2-T35 # 17 T35 IO_L18N_17 NET 'No_Conn_TP_IO_L16N_17' U2-T36 # 17 T36 IO_L16N_17 NET 'No_Conn_TP_IO_L12N_VRP_17' U2-T37 # 17 T37 IO_L12N_VRP_17 NET 'No_Conn_TP_IO_L10P_MRCC_17' U2-T39 # 17 T39 IO_L10P_MRCC_17 NET 'No_Conn_TP_IO_L16P_17' U2-U36 # 17 U36 IO_L16P_17 # Unused pins from IO bank 21 ############################# NET 'No_Conn_TP_IO_L1N_21' U2-AJ22 # 21 AJ22 IO_L1N_21 NET 'No_Conn_TP_IO_L5P_21' U2-AJ23 # 21 AJ23 IO_L5P_21 NET 'No_Conn_TP_IO_L1P_21' U2-AK22 # 21 AK22 IO_L1P_21 NET 'No_Conn_TP_IO_L5N_21' U2-AK23 # 21 AK23 IO_L5N_21 NET 'No_Conn_TP_IO_L10P_MRCC_21' U2-AK24 # 21 AK24 IO_L10P_MRCC_21 NET 'No_Conn_TP_IO_L3N_21' U2-AL22 # 21 AL22 IO_L3N_21 NET 'No_Conn_TP_IO_L13N_21' U2-AL24 # 21 AL24 IO_L13N_21 NET 'No_Conn_TP_IO_L10N_MRCC_21' U2-AL25 # 21 AL25 IO_L10N_MRCC_21 NET 'No_Conn_TP_IO_L3P_21' U2-AM22 # 21 AM22 IO_L3P_21 NET 'No_Conn_TP_IO_L7P_21' U2-AM23 # 21 AM23 IO_L7P_21 NET 'No_Conn_TP_IO_L13P_21' U2-AM24 # 21 AM24 IO_L13P_21 NET 'No_Conn_TP_IO_L7N_21' U2-AN23 # 21 AN23 IO_L7N_21 NET 'No_Conn_TP_IO_L15P_21' U2-AN24 # 21 AN24 IO_L15P_21 NET 'No_Conn_TP_IO_L15N_21' U2-AN25 # 21 AN25 IO_L15N_21 NET 'No_Conn_TP_IO_L11P_SRCC_21' U2-AP23 # 21 AP23 IO_L11P_SRCC_21 NET 'No_Conn_TP_IO_L9P_MRCC_21' U2-AP25 # 21 AP25 IO_L9P_MRCC_21 NET 'No_Conn_TP_IO_L9N_MRCC_21' U2-AP26 # 21 AP26 IO_L9N_MRCC_21 NET 'No_Conn_TP_IO_L11N_SRCC_21' U2-AR23 # 21 AR23 IO_L11N_SRCC_21 NET 'No_Conn_TP_IO_L17P_21' U2-AR24 # 21 AR24 IO_L17P_21 NET 'No_Conn_TP_IO_L19N_21' U2-AR25 # 21 AR25 IO_L19N_21 NET 'No_Conn_TP_IO_L17N_21' U2-AT24 # 21 AT24 IO_L17N_21 NET 'No_Conn_TP_IO_L19P_21' U2-AT25 # 21 AT25 IO_L19P_21 NET 'No_Conn_TP_IO_L0P_21' U2-AT26 # 21 AT26 IO_L0P_21 NET 'No_Conn_TP_IO_L8P_SRCC_21' U2-AU23 # 21 AU23 IO_L8P_SRCC_21 NET 'No_Conn_TP_IO_L8N_SRCC_21' U2-AU24 # 21 AU24 IO_L8N_SRCC_21 NET 'No_Conn_TP_IO_L16N_21' U2-AU26 # 21 AU26 IO_L16N_21 NET 'No_Conn_TP_IO_L0N_21' U2-AU27 # 21 AU27 IO_L0N_21 NET 'No_Conn_TP_IO_L12P_VRN_21' U2-AV24 # 21 AV24 IO_L12P_VRN_21 NET 'No_Conn_TP_IO_L12N_VRP_21' U2-AV25 # 21 AV25 IO_L12N_VRP_21 NET 'No_Conn_TP_IO_L16P_21' U2-AV26 # 21 AV26 IO_L16P_21 NET 'No_Conn_TP_IO_L18P_21' U2-AW25 # 21 AW25 IO_L18P_21 NET 'No_Conn_TP_IO_L18N_21' U2-AW26 # 21 AW26 IO_L18N_21 NET 'No_Conn_TP_IO_L2N_21' U2-AW27 # 21 AW27 IO_L2N_21 NET 'No_Conn_TP_IO_L14N_VREF_21' U2-AY25 # 21 AY25 IO_L14N_VREF_21 NET 'No_Conn_TP_IO_L2P_21' U2-AY27 # 21 AY27 IO_L2P_21 NET 'No_Conn_TP_IO_L14P_21' U2-BA25 # 21 BA25 IO_L14P_21 NET 'No_Conn_TP_IO_L4P_21' U2-BA26 # 21 BA26 IO_L4P_21 NET 'No_Conn_TP_IO_L4N_VREF_21' U2-BA27 # 21 BA27 IO_L4N_VREF_21 NET 'No_Conn_TP_IO_L6P_21' U2-BB26 # 21 BB26 IO_L6P_21 NET 'No_Conn_TP_IO_L6N_21' U2-BB27 # 21 BB27 IO_L6N_21 # Unused pins from IO bank 22 ############################# NET 'No_Conn_TP_IO_L9N_MRCC_22' U2-AL26 # 22 AL26 IO_L9N_MRCC_22 NET 'No_Conn_TP_IO_L9P_MRCC_22' U2-AM26 # 22 AM26 IO_L9P_MRCC_22 NET 'No_Conn_TP_IO_L10N_MRCC_22' U2-AM27 # 22 AM27 IO_L10N_MRCC_22 NET 'No_Conn_TP_IO_L1P_22' U2-AN26 # 22 AN26 IO_L1P_22 NET 'No_Conn_TP_IO_L10P_MRCC_22' U2-AN28 # 22 AN28 IO_L10P_MRCC_22 NET 'No_Conn_TP_IO_L1N_22' U2-AP27 # 22 AP27 IO_L1N_22 NET 'No_Conn_TP_IO_L3N_22' U2-AP28 # 22 AP28 IO_L3N_22 NET 'No_Conn_TP_IO_L11P_SRCC_22' U2-AR27 # 22 AR27 IO_L11P_SRCC_22 NET 'No_Conn_TP_IO_L3P_22' U2-AR28 # 22 AR28 IO_L3P_22 NET 'No_Conn_TP_IO_L5N_22' U2-AR29 # 22 AR29 IO_L5N_22 NET 'No_Conn_TP_IO_L7N_22' U2-AR30 # 22 AR30 IO_L7N_22 NET 'No_Conn_TP_IO_L11N_SRCC_22' U2-AT27 # 22 AT27 IO_L11N_SRCC_22 NET 'No_Conn_TP_IO_L5P_22' U2-AT29 # 22 AT29 IO_L5P_22 NET 'No_Conn_TP_IO_L7P_22' U2-AT30 # 22 AT30 IO_L7P_22 NET 'No_Conn_TP_IO_L13P_22' U2-AT31 # 22 AT31 IO_L13P_22 NET 'No_Conn_TP_IO_L17P_22' U2-AU28 # 22 AU28 IO_L17P_22 NET 'No_Conn_TP_IO_L15P_22' U2-AU29 # 22 AU29 IO_L15P_22 NET 'No_Conn_TP_IO_L13N_22' U2-AU31 # 22 AU31 IO_L13N_22 NET 'No_Conn_TP_IO_L17N_22' U2-AV28 # 22 AV28 IO_L17N_22 NET 'No_Conn_TP_IO_L15N_22' U2-AV29 # 22 AV29 IO_L15N_22 NET 'No_Conn_TP_IO_L0N_22' U2-AV30 # 22 AV30 IO_L0N_22 NET 'No_Conn_TP_IO_L2N_22' U2-AV31 # 22 AV31 IO_L2N_22 NET 'No_Conn_TP_IO_L19P_22' U2-AW28 # 22 AW28 IO_L19P_22 NET 'No_Conn_TP_IO_L0P_22' U2-AW30 # 22 AW30 IO_L0P_22 NET 'No_Conn_TP_IO_L2P_22' U2-AW31 # 22 AW31 IO_L2P_22 NET 'No_Conn_TP_IO_L4N_VREF_22' U2-AW32 # 22 AW32 IO_L4N_VREF_22 NET 'No_Conn_TP_IO_L19N_22' U2-AY28 # 22 AY28 IO_L19N_22 NET 'No_Conn_TP_IO_L12P_VRN_22' U2-AY29 # 22 AY29 IO_L12P_VRN_22 NET 'No_Conn_TP_IO_L8N_SRCC_22' U2-AY30 # 22 AY30 IO_L8N_SRCC_22 NET 'No_Conn_TP_IO_L4P_22' U2-AY32 # 22 AY32 IO_L4P_22 NET 'No_Conn_TP_IO_L6N_22' U2-AY33 # 22 AY33 IO_L6N_22 NET 'No_Conn_TP_IO_L12N_VRP_22' U2-BA29 # 22 BA29 IO_L12N_VRP_22 NET 'No_Conn_TP_IO_L8P_SRCC_22' U2-BA30 # 22 BA30 IO_L8P_SRCC_22 NET 'No_Conn_TP_IO_L16P_22' U2-BA31 # 22 BA31 IO_L16P_22 NET 'No_Conn_TP_IO_L6P_22' U2-BA32 # 22 BA32 IO_L6P_22 NET 'No_Conn_TP_IO_L18N_22' U2-BB28 # 22 BB28 IO_L18N_22 NET 'No_Conn_TP_IO_L18P_22' U2-BB29 # 22 BB29 IO_L18P_22 NET 'No_Conn_TP_IO_L16N_22' U2-BB31 # 22 BB31 IO_L16N_22 NET 'No_Conn_TP_IO_L14N_VREF_22' U2-BB32 # 22 BB32 IO_L14N_VREF_22 NET 'No_Conn_TP_IO_L14P_22' U2-BB33 # 22 BB33 IO_L14P_22 # Unused pins from IO bank 23 ############################# NET 'No_Conn_TP_IO_L14N_VREF_23' U2-AG27 # 23 AG27 IO_L14N_VREF_23 NET 'No_Conn_TP_IO_L14P_23' U2-AG28 # 23 AG28 IO_L14P_23 NET 'No_Conn_TP_IO_L10P_MRCC_23' U2-AH24 # 23 AH24 IO_L10P_MRCC_23 NET 'No_Conn_TP_IO_L10N_MRCC_23' U2-AH25 # 23 AH25 IO_L10N_MRCC_23 NET 'No_Conn_TP_IO_L18N_23' U2-AH26 # 23 AH26 IO_L18N_23 NET 'No_Conn_TP_IO_L12P_VRN_23' U2-AH28 # 23 AH28 IO_L12P_VRN_23 NET 'No_Conn_TP_IO_L9P_MRCC_23' U2-AJ25 # 23 AJ25 IO_L9P_MRCC_23 NET 'No_Conn_TP_IO_L18P_23' U2-AJ26 # 23 AJ26 IO_L18P_23 NET 'No_Conn_TP_IO_L16N_23' U2-AJ27 # 23 AJ27 IO_L16N_23 NET 'No_Conn_TP_IO_L12N_VRP_23' U2-AJ28 # 23 AJ28 IO_L12N_VRP_23 NET 'No_Conn_TP_IO_L9N_MRCC_23' U2-AK25 # 23 AK25 IO_L9N_MRCC_23 NET 'No_Conn_TP_IO_L16P_23' U2-AK27 # 23 AK27 IO_L16P_23 NET 'No_Conn_TP_IO_L8P_SRCC_23' U2-AK28 # 23 AK28 IO_L8P_SRCC_23 NET 'No_Conn_TP_IO_L8N_SRCC_23' U2-AK29 # 23 AK29 IO_L8N_SRCC_23 NET 'No_Conn_TP_IO_L6P_23' U2-AL27 # 23 AL27 IO_L6P_23 NET 'No_Conn_TP_IO_L2P_23' U2-AL29 # 23 AL29 IO_L2P_23 NET 'No_Conn_TP_IO_L2N_23' U2-AL30 # 23 AL30 IO_L2N_23 NET 'No_Conn_TP_IO_L1N_23' U2-AL31 # 23 AL31 IO_L1N_23 NET 'No_Conn_TP_IO_L6N_23' U2-AM28 # 23 AM28 IO_L6N_23 NET 'No_Conn_TP_IO_L4N_VREF_23' U2-AM29 # 23 AM29 IO_L4N_VREF_23 NET 'No_Conn_TP_IO_L1P_23' U2-AM31 # 23 AM31 IO_L1P_23 NET 'No_Conn_TP_IO_L3N_23' U2-AM32 # 23 AM32 IO_L3N_23 NET 'No_Conn_TP_IO_L3P_23' U2-AM33 # 23 AM33 IO_L3P_23 NET 'No_Conn_TP_IO_L4P_23' U2-AN29 # 23 AN29 IO_L4P_23 NET 'No_Conn_TP_IO_L0N_23' U2-AN30 # 23 AN30 IO_L0N_23 NET 'No_Conn_TP_IO_L7N_23' U2-AN31 # 23 AN31 IO_L7N_23 NET 'No_Conn_TP_IO_L5P_23' U2-AN33 # 23 AN33 IO_L5P_23 NET 'No_Conn_TP_IO_L5N_23' U2-AN34 # 23 AN34 IO_L5N_23 NET 'No_Conn_TP_IO_L0P_23' U2-AP30 # 23 AP30 IO_L0P_23 NET 'No_Conn_TP_IO_L7P_23' U2-AP31 # 23 AP31 IO_L7P_23 NET 'No_Conn_TP_IO_L13P_23' U2-AP32 # 23 AP32 IO_L13P_23 NET 'No_Conn_TP_IO_L11N_SRCC_23' U2-AP33 # 23 AP33 IO_L11N_SRCC_23 NET 'No_Conn_TP_IO_L13N_23' U2-AR32 # 23 AR32 IO_L13N_23 NET 'No_Conn_TP_IO_L15P_23' U2-AR33 # 23 AR33 IO_L15P_23 NET 'No_Conn_TP_IO_L11P_SRCC_23' U2-AR34 # 23 AR34 IO_L11P_SRCC_23 NET 'No_Conn_TP_IO_L15N_23' U2-AT32 # 23 AT32 IO_L15N_23 NET 'No_Conn_TP_IO_L17N_23' U2-AU32 # 23 AU32 IO_L17N_23 NET 'No_Conn_TP_IO_L17P_23' U2-AU33 # 23 AU33 IO_L17P_23 NET 'No_Conn_TP_IO_L19P_23' U2-AV33 # 23 AV33 IO_L19P_23 NET 'No_Conn_TP_IO_L19N_23' U2-AW33 # 23 AW33 IO_L19N_23 # Unused pins from IO bank 24 ############################# NET 'No_Conn_TP_IO_L5P_D9_24' U2-N33 # 24 N33 IO_L5P_D9_24 NET 'No_Conn_TP_IO_L7P_D5_24' U2-P32 # 24 P32 IO_L7P_D5_24 NET 'No_Conn_TP_IO_L5N_D8_24' U2-P33 # 24 P33 IO_L5N_D8_24 NET 'No_Conn_TP_IO_L3N_D12_24' U2-R30 # 24 R30 IO_L3N_D12_24 NET 'No_Conn_TP_IO_L11P_SRCC_24' U2-R32 # 24 R32 IO_L11P_SRCC_24 NET 'No_Conn_TP_IO_L7N_D4_24' U2-R33 # 24 R33 IO_L7N_D4_24 NET 'No_Conn_TP_IO_L3P_D13_24' U2-T30 # 24 T30 IO_L3P_D13_24 NET 'No_Conn_TP_IO_L13P_D1_FS1_24' U2-T31 # 24 T31 IO_L13P_D1_FS1_24 NET 'No_Conn_TP_IO_L11N_SRCC_24' U2-T32 # 24 T32 IO_L11N_SRCC_24 NET 'No_Conn_TP_IO_L13N_D0_FS0_24' U2-U31 # 24 U31 IO_L13N_D0_FS0_24 NET 'No_Conn_TP_IO_L1N_GC_24' U2-V30 # 24 V30 IO_L1N_GC_24 NET 'No_Conn_TP_IO_L15P_FWE_B_24' U2-V31 # 24 V31 IO_L15P_FWE_B_24 NET 'No_Conn_TP_IO_L1P_GC_24' U2-W30 # 24 W30 IO_L1P_GC_24 NET 'No_Conn_TP_IO_L15N_RS1_24' U2-W31 # 24 W31 IO_L15N_RS1_24 NET 'No_Conn_TP_IO_L9P_MRCC_24' U2-Y30 # 24 Y30 IO_L9P_MRCC_24 NET 'No_Conn_TP_IO_L9N_MRCC_24' U2-AA30 # 24 AA30 IO_L9N_MRCC_24 NET 'No_Conn_TP_IO_L10P_MRCC_24' U2-AA31 # 24 AA31 IO_L10P_MRCC_24 NET 'No_Conn_TP_IO_L10N_MRCC_24' U2-AB31 # 24 AB31 IO_L10N_MRCC_24 NET 'No_Conn_TP_IO_L17N_VRP_24' U2-AC30 # 24 AC30 IO_L17N_VRP_24 NET 'No_Conn_TP_IO_L17P_VRN_24' U2-AC31 # 24 AC31 IO_L17P_VRN_24 NET 'No_Conn_TP_IO_L19N_24' U2-AD30 # 24 AD30 IO_L19N_24 NET 'No_Conn_TP_IO_L19P_24' U2-AD31 # 24 AD31 IO_L19P_24 NET 'No_Conn_TP_IO_L0P_GC_24' U2-AE30 # 24 AE30 IO_L0P_GC_24 NET 'No_Conn_TP_IO_L0N_GC_24' U2-AF30 # 24 AF30 IO_L0N_GC_24 NET 'No_Conn_TP_IO_L2N_D14_24' U2-AF31 # 24 AF31 IO_L2N_D14_24 NET 'No_Conn_TP_IO_L18N_24' U2-AG29 # 24 AG29 IO_L18N_24 NET 'No_Conn_TP_IO_L4N_VREF_D10_24' U2-AG31 # 24 AG31 IO_L4N_VREF_D10_24 NET 'No_Conn_TP_IO_L2P_D15_24' U2-AG32 # 24 AG32 IO_L2P_D15_24 NET 'No_Conn_TP_IO_L18P_24' U2-AH29 # 24 AH29 IO_L18P_24 NET 'No_Conn_TP_IO_L14P_FCS_B_24' U2-AH30 # 24 AH30 IO_L14P_FCS_B_24 NET 'No_Conn_TP_IO_L4P_D11_24' U2-AH31 # 24 AH31 IO_L4P_D11_24 NET 'No_Conn_TP_IO_L6N_D6_24' U2-AH33 # 24 AH33 IO_L6N_D6_24 NET 'No_Conn_TP_IO_L14N_VREF_FOE_B_MOSI_24' U2-AJ30 # 24 AJ30 IO_L14N_VREF_FOE_B_MOSI_24 NET 'No_Conn_TP_IO_L16P_RS0_24' U2-AJ31 # 24 AJ31 IO_L16P_RS0_24 NET 'No_Conn_TP_IO_L8N_SRCC_24' U2-AJ32 # 24 AJ32 IO_L8N_SRCC_24 NET 'No_Conn_TP_IO_L6P_D7_24' U2-AJ33 # 24 AJ33 IO_L6P_D7_24 NET 'No_Conn_TP_IO_L16N_CSO_B_24' U2-AK30 # 24 AK30 IO_L16N_CSO_B_24 NET 'No_Conn_TP_IO_L12P_D3_24' U2-AK32 # 24 AK32 IO_L12P_D3_24 NET 'No_Conn_TP_IO_L8P_SRCC_24' U2-AK33 # 24 AK33 IO_L8P_SRCC_24 NET 'No_Conn_TP_IO_L12N_D2_FS2_24' U2-AL32 # 24 AL32 IO_L12N_D2_FS2_24 # Unused pins from IO bank 25 ############################# # note: 2 pins from this bank are used for the 40 MHz Logic Clock NET 'No_Conn_TP_IO_L6N_25' U2-H38 # 25 H38 IO_L6N_25 NET 'No_Conn_TP_IO_L6P_25' U2-H39 # 25 H39 IO_L6P_25 NET 'No_Conn_TP_IO_L12P_25' U2-H40 # 25 H40 IO_L12P_25 NET 'No_Conn_TP_IO_L12N_25' U2-H41 # 25 H41 IO_L12N_25 NET 'No_Conn_TP_IO_L4N_VREF_25' U2-J36 # 25 J36 IO_L4N_VREF_25 NET 'No_Conn_TP_IO_L4P_25' U2-J37 # 25 J37 IO_L4P_25 NET 'No_Conn_TP_IO_L8N_SRCC_25' U2-J38 # 25 J38 IO_L8N_SRCC_25 NET 'No_Conn_TP_IO_L14P_25' U2-J40 # 25 J40 IO_L14P_25 NET 'No_Conn_TP_IO_L14N_VREF_25' U2-J41 # 25 J41 IO_L14N_VREF_25 NET 'No_Conn_TP_IO_L0N_25' U2-K32 # 25 K32 IO_L0N_25 NET 'No_Conn_TP_IO_L0P_25' U2-K33 # 25 K33 IO_L0P_25 NET 'No_Conn_TP_IO_L2N_25' U2-K34 # 25 K34 IO_L2N_25 NET 'No_Conn_TP_IO_L2P_25' U2-K35 # 25 K35 IO_L2P_25 NET 'No_Conn_TP_IO_L11P_SRCC_25' U2-K37 # 25 K37 IO_L11P_SRCC_25 NET 'No_Conn_TP_IO_L8P_SRCC_25' U2-K38 # 25 K38 IO_L8P_SRCC_25 NET 'No_Conn_TP_IO_L16P_VRN_25' U2-K39 # 25 K39 IO_L16P_VRN_25 NET 'No_Conn_TP_IO_L16N_VRP_25' U2-K40 # 25 K40 IO_L16N_VRP_25 NET 'No_Conn_TP_IO_L3P_25' U2-L31 # 25 L31 IO_L3P_25 NET 'No_Conn_TP_IO_L3N_25' U2-L32 # 25 L32 IO_L3N_25 NET 'No_Conn_TP_IO_L13P_25' U2-L34 # 25 L34 IO_L13P_25 NET 'No_Conn_TP_IO_L7P_25' U2-L35 # 25 L35 IO_L7P_25 NET 'No_Conn_TP_IO_L7N_25' U2-L36 # 25 L36 IO_L7N_25 NET 'No_Conn_TP_IO_L11N_SRCC_25' U2-L37 # 25 L37 IO_L11N_SRCC_25 NET 'No_Conn_TP_IO_L17P_25' U2-M31 # 25 M31 IO_L17P_25 NET 'No_Conn_TP_IO_L15N_25' U2-M32 # 25 M32 IO_L15N_25 NET 'No_Conn_TP_IO_L15P_25' U2-M33 # 25 M33 IO_L15P_25 NET 'No_Conn_TP_IO_L13N_25' U2-M34 # 25 M34 IO_L13N_25 NET 'No_Conn_TP_IO_L1P_25' U2-N28 # 25 N28 IO_L1P_25 NET 'No_Conn_TP_IO_L5P_25' U2-N29 # 25 N29 IO_L5P_25 NET 'No_Conn_TP_IO_L5N_25' U2-N30 # 25 N30 IO_L5N_25 NET 'No_Conn_TP_IO_L17N_25' U2-N31 # 25 N31 IO_L17N_25 NET 'No_Conn_TP_IO_L9P_MRCC_25' U2-P27 # 25 P27 IO_L9P_MRCC_25 NET 'No_Conn_TP_IO_L1N_25' U2-P28 # 25 P28 IO_L1N_25 NET 'No_Conn_TP_IO_L19P_GC_25' U2-P30 # 25 P30 IO_L19P_GC_25 NET 'No_Conn_TP_IO_L19N_GC_25' U2-P31 # 25 P31 IO_L19N_GC_25 NET 'No_Conn_TP_IO_L9N_MRCC_25' U2-R27 # 25 R27 IO_L9N_MRCC_25 NET 'No_Conn_TP_IO_L10P_MRCC_25' U2-R28 # 25 R28 IO_L10P_MRCC_25 NET 'No_Conn_TP_IO_L10N_MRCC_25' U2-R29 # 25 R29 IO_L10N_MRCC_25 # Unused pins from IO bank 26 ############################# # note: this bank is otherwise used for BF to TP S-link connection, and Debug connector connections NET 'No_Conn_TP_IO_L5N_26' U2-C39 # 26 C39 IO_L5N_26 NET 'No_Conn_TP_IO_L6P_26' U2-D38 # 26 D38 IO_L6P_26 NET 'No_Conn_TP_IO_L17P_26' U2-D40 # 26 D40 IO_L17P_26 NET 'No_Conn_TP_IO_L4N_VREF_26' U2-E37 # 26 E37 IO_L4N_VREF_26 NET 'No_Conn_TP_IO_L8N_SRCC_26' U2-E38 # 26 E38 IO_L8N_SRCC_26 NET 'No_Conn_TP_IO_L8P_SRCC_26' U2-E39 # 26 E39 IO_L8P_SRCC_26 NET 'No_Conn_TP_IO_L10P_MRCC_26' U2-F35 # 26 F35 IO_L10P_MRCC_26 NET 'No_Conn_TP_IO_L10N_MRCC_26' U2-F36 # 26 F36 IO_L10N_MRCC_26 NET 'No_Conn_TP_IO_L4P_26' U2-F37 # 26 F37 IO_L4P_26 NET 'No_Conn_TP_IO_L12P_VRN_26' U2-F39 # 26 F39 IO_L12P_VRN_26 NET 'No_Conn_TP_IO_L16P_26' U2-F40 # 26 F40 IO_L16P_26 NET 'No_Conn_TP_IO_L9P_MRCC_26' U2-G34 # 26 G34 IO_L9P_MRCC_26 NET 'No_Conn_TP_IO_L0N_26' U2-G36 # 26 G36 IO_L0N_26 NET 'No_Conn_TP_IO_L14P_26' U2-G37 # 26 G37 IO_L14P_26 NET 'No_Conn_TP_IO_L14N_VREF_26' U2-G38 # 26 G38 IO_L14N_VREF_26 NET 'No_Conn_TP_IO_L12N_VRP_26' U2-G39 # 26 G39 IO_L12N_VRP_26 NET 'No_Conn_TP_IO_L9N_MRCC_26' U2-H34 # 26 H34 IO_L9N_MRCC_26 NET 'No_Conn_TP_IO_L2N_26' U2-H35 # 26 H35 IO_L2N_26 NET 'No_Conn_TP_IO_L0P_26' U2-H36 # 26 H36 IO_L0P_26 NET 'No_Conn_TP_IO_L2P_26' U2-J35 # 26 J35 IO_L2P_26 # Unused pins from IO bank 27 ############################# # note: this bank is otherwise used for TP to BSPT connections NET 'No_Conn_TP_IO_L3N_27' U2-C33 # 27 C33 IO_L3N_27 NET 'No_Conn_TP_IO_L7N_27' U2-C34 # 27 C34 IO_L7N_27 NET 'No_Conn_TP_IO_L15N_27' U2-C36 # 27 C36 IO_L15N_27 NET 'No_Conn_TP_IO_L0N_27' U2-D32 # 27 D32 IO_L0N_27 NET 'No_Conn_TP_IO_L11P_SRCC_27' U2-D33 # 27 D33 IO_L11P_SRCC_27 NET 'No_Conn_TP_IO_L4N_VREF_27' U2-D35 # 27 D35 IO_L4N_VREF_27 NET 'No_Conn_TP_IO_L19P_27' U2-D36 # 27 D36 IO_L19P_27 NET 'No_Conn_TP_IO_L19N_27' U2-D37 # 27 D37 IO_L19N_27 NET 'No_Conn_TP_IO_L0P_27' U2-E32 # 27 E32 IO_L0P_27 NET 'No_Conn_TP_IO_L11N_SRCC_27' U2-E33 # 27 E33 IO_L11N_SRCC_27 NET 'No_Conn_TP_IO_L17P_27' U2-E34 # 27 E34 IO_L17P_27 NET 'No_Conn_TP_IO_L4P_27' U2-E35 # 27 E35 IO_L4P_27 NET 'No_Conn_TP_IO_L2N_27' U2-F31 # 27 F31 IO_L2N_27 NET 'No_Conn_TP_IO_L2P_27' U2-F32 # 27 F32 IO_L2P_27 NET 'No_Conn_TP_IO_L17N_27' U2-F34 # 27 F34 IO_L17N_27 NET 'No_Conn_TP_IO_L6N_27' U2-G31 # 27 G31 IO_L6N_27 NET 'No_Conn_TP_IO_L8N_SRCC_27' U2-G32 # 27 G32 IO_L8N_SRCC_27 NET 'No_Conn_TP_IO_L8P_SRCC_27' U2-G33 # 27 G33 IO_L8P_SRCC_27 NET 'No_Conn_TP_IO_L16P_27' U2-H30 # 27 H30 IO_L16P_27 NET 'No_Conn_TP_IO_L6P_27' U2-H31 # 27 H31 IO_L6P_27 NET 'No_Conn_TP_IO_L12P_VRN_27' U2-H33 # 27 H33 IO_L12P_VRN_27 NET 'No_Conn_TP_IO_L16N_27' U2-J30 # 27 J30 IO_L16N_27 NET 'No_Conn_TP_IO_L14N_VREF_27' U2-J31 # 27 J31 IO_L14N_VREF_27 NET 'No_Conn_TP_IO_L14P_27' U2-J32 # 27 J32 IO_L14P_27 NET 'No_Conn_TP_IO_L12N_VRP_27' U2-J33 # 27 J33 IO_L12N_VRP_27 NET 'No_Conn_TP_IO_L18P_27' U2-K29 # 27 K29 IO_L18P_27 NET 'No_Conn_TP_IO_L18N_27' U2-K30 # 27 K30 IO_L18N_27 NET 'No_Conn_TP_IO_L9P_MRCC_27' U2-L29 # 27 L29 IO_L9P_MRCC_27 NET 'No_Conn_TP_IO_L9N_MRCC_27' U2-L30 # 27 L30 IO_L9N_MRCC_27 NET 'No_Conn_TP_IO_L10P_MRCC_27' U2-M28 # 27 M28 IO_L10P_MRCC_27 NET 'No_Conn_TP_IO_L10N_MRCC_27' U2-M29 # 27 M29 IO_L10N_MRCC_27 # Unused pins from IO bank 28 ############################# NET 'No_Conn_TP_IO_L17P_28' U2-A29 # 28 A29 IO_L17P_28 NET 'No_Conn_TP_IO_L17N_28' U2-A30 # 28 A30 IO_L17N_28 NET 'No_Conn_TP_IO_L13P_28' U2-A31 # 28 A31 IO_L13P_28 NET 'No_Conn_TP_IO_L15P_28' U2-B29 # 28 B29 IO_L15P_28 NET 'No_Conn_TP_IO_L13N_28' U2-B31 # 28 B31 IO_L13N_28 NET 'No_Conn_TP_IO_L15N_28' U2-C29 # 28 C29 IO_L15N_28 NET 'No_Conn_TP_IO_L7P_28' U2-C30 # 28 C30 IO_L7P_28 NET 'No_Conn_TP_IO_L5P_28' U2-C31 # 28 C31 IO_L5P_28 NET 'No_Conn_TP_IO_L1P_28' U2-D28 # 28 D28 IO_L1P_28 NET 'No_Conn_TP_IO_L7N_28' U2-D30 # 28 D30 IO_L7N_28 NET 'No_Conn_TP_IO_L5N_28' U2-D31 # 28 D31 IO_L5N_28 NET 'No_Conn_TP_IO_L11N_SRCC_28' U2-E28 # 28 E28 IO_L11N_SRCC_28 NET 'No_Conn_TP_IO_L1N_28' U2-E29 # 28 E29 IO_L1N_28 NET 'No_Conn_TP_IO_L3P_28' U2-E30 # 28 E30 IO_L3P_28 NET 'No_Conn_TP_IO_L11P_SRCC_28' U2-F27 # 28 F27 IO_L11P_SRCC_28 NET 'No_Conn_TP_IO_L4N_VREF_28' U2-F29 # 28 F29 IO_L4N_VREF_28 NET 'No_Conn_TP_IO_L3N_28' U2-F30 # 28 F30 IO_L3N_28 NET 'No_Conn_TP_IO_L2N_28' U2-G27 # 28 G27 IO_L2N_28 NET 'No_Conn_TP_IO_L2P_28' U2-G28 # 28 G28 IO_L2P_28 NET 'No_Conn_TP_IO_L4P_28' U2-G29 # 28 G29 IO_L4P_28 NET 'No_Conn_TP_IO_L14P_28' U2-H28 # 28 H28 IO_L14P_28 NET 'No_Conn_TP_IO_L14N_VREF_28' U2-H29 # 28 H29 IO_L14N_VREF_28 NET 'No_Conn_TP_IO_L0N_28' U2-J26 # 28 J26 IO_L0N_28 NET 'No_Conn_TP_IO_L0P_28' U2-J27 # 28 J27 IO_L0P_28 NET 'No_Conn_TP_IO_L16P_28' U2-J28 # 28 J28 IO_L16P_28 NET 'No_Conn_TP_IO_L18N_28' U2-K27 # 28 K27 IO_L18N_28 NET 'No_Conn_TP_IO_L16N_28' U2-K28 # 28 K28 IO_L16N_28 NET 'No_Conn_TP_IO_L9N_MRCC_28' U2-L25 # 28 L25 IO_L9N_MRCC_28 NET 'No_Conn_TP_IO_L9P_MRCC_28' U2-L26 # 28 L26 IO_L9P_MRCC_28 NET 'No_Conn_TP_IO_L18P_28' U2-L27 # 28 L27 IO_L18P_28 NET 'No_Conn_TP_IO_L19P_28' U2-M26 # 28 M26 IO_L19P_28 NET 'No_Conn_TP_IO_L19N_28' U2-M27 # 28 M27 IO_L19N_28 NET 'No_Conn_TP_IO_L10P_MRCC_28' U2-N24 # 28 N24 IO_L10P_MRCC_28 NET 'No_Conn_TP_IO_L10N_MRCC_28' U2-N25 # 28 N25 IO_L10N_MRCC_28 NET 'No_Conn_TP_IO_L12N_VRP_28' U2-N26 # 28 N26 IO_L12N_VRP_28 NET 'No_Conn_TP_IO_L6N_28' U2-P23 # 28 P23 IO_L6N_28 NET 'No_Conn_TP_IO_L8N_SRCC_28' U2-P25 # 28 P25 IO_L8N_SRCC_28 NET 'No_Conn_TP_IO_L12P_VRN_28' U2-P26 # 28 P26 IO_L12P_VRN_28 NET 'No_Conn_TP_IO_L6P_28' U2-R23 # 28 R23 IO_L6P_28 NET 'No_Conn_TP_IO_L8P_SRCC_28' U2-R25 # 28 R25 IO_L8P_SRCC_28 # Unused pins from IO bank 32 ############################# NET 'No_Conn_TP_IO_L9N_MRCC_32' U2-AJ20 # 32 AJ20 IO_L9N_MRCC_32 NET 'No_Conn_TP_IO_L9P_MRCC_32' U2-AJ21 # 32 AJ21 IO_L9P_MRCC_32 NET 'No_Conn_TP_IO_L10N_MRCC_32' U2-AK19 # 32 AK19 IO_L10N_MRCC_32 NET 'No_Conn_TP_IO_L10P_MRCC_32' U2-AK20 # 32 AK20 IO_L10P_MRCC_32 NET 'No_Conn_TP_IO_L1P_32' U2-AL19 # 32 AL19 IO_L1P_32 NET 'No_Conn_TP_IO_L5P_32' U2-AL20 # 32 AL20 IO_L5P_32 NET 'No_Conn_TP_IO_L5N_32' U2-AL21 # 32 AL21 IO_L5N_32 NET 'No_Conn_TP_IO_L1N_32' U2-AM19 # 32 AM19 IO_L1N_32 NET 'No_Conn_TP_IO_L11P_SRCC_32' U2-AM21 # 32 AM21 IO_L11P_SRCC_32 NET 'No_Conn_TP_IO_L7P_32' U2-AN20 # 32 AN20 IO_L7P_32 NET 'No_Conn_TP_IO_L11N_SRCC_32' U2-AN21 # 32 AN21 IO_L11N_SRCC_32 NET 'No_Conn_TP_IO_L7N_32' U2-AP20 # 32 AP20 IO_L7N_32 NET 'No_Conn_TP_IO_L19P_32' U2-AP21 # 32 AP21 IO_L19P_32 NET 'No_Conn_TP_IO_L19N_32' U2-AP22 # 32 AP22 IO_L19N_32 NET 'No_Conn_TP_IO_L3N_32' U2-AR20 # 32 AR20 IO_L3N_32 NET 'No_Conn_TP_IO_L17N_32' U2-AR22 # 32 AR22 IO_L17N_32 NET 'No_Conn_TP_IO_L3P_32' U2-AT20 # 32 AT20 IO_L3P_32 NET 'No_Conn_TP_IO_L15N_32' U2-AT21 # 32 AT21 IO_L15N_32 NET 'No_Conn_TP_IO_L17P_32' U2-AT22 # 32 AT22 IO_L17P_32 NET 'No_Conn_TP_IO_L15P_32' U2-AU21 # 32 AU21 IO_L15P_32 NET 'No_Conn_TP_IO_L2N_32' U2-AU22 # 32 AU22 IO_L2N_32 NET 'No_Conn_TP_IO_L13P_32' U2-AV20 # 32 AV20 IO_L13P_32 NET 'No_Conn_TP_IO_L12P_VRN_32' U2-AV21 # 32 AV21 IO_L12P_VRN_32 NET 'No_Conn_TP_IO_L2P_32' U2-AV23 # 32 AV23 IO_L2P_32 NET 'No_Conn_TP_IO_L13N_32' U2-AW20 # 32 AW20 IO_L13N_32 NET 'No_Conn_TP_IO_L12N_VRP_32' U2-AW21 # 32 AW21 IO_L12N_VRP_32 NET 'No_Conn_TP_IO_L16P_32' U2-AW22 # 32 AW22 IO_L16P_32 NET 'No_Conn_TP_IO_L4P_32' U2-AW23 # 32 AW23 IO_L4P_32 NET 'No_Conn_TP_IO_L8P_SRCC_32' U2-AY20 # 32 AY20 IO_L8P_SRCC_32 NET 'No_Conn_TP_IO_L16N_32' U2-AY22 # 32 AY22 IO_L16N_32 NET 'No_Conn_TP_IO_L4N_VREF_32' U2-AY23 # 32 AY23 IO_L4N_VREF_32 NET 'No_Conn_TP_IO_L0P_32' U2-AY24 # 32 AY24 IO_L0P_32 NET 'No_Conn_TP_IO_L8N_SRCC_32' U2-BA20 # 32 BA20 IO_L8N_SRCC_32 NET 'No_Conn_TP_IO_L14N_VREF_32' U2-BA21 # 32 BA21 IO_L14N_VREF_32 NET 'No_Conn_TP_IO_L14P_32' U2-BA22 # 32 BA22 IO_L14P_32 NET 'No_Conn_TP_IO_L0N_32' U2-BA24 # 32 BA24 IO_L0N_32 NET 'No_Conn_TP_IO_L18N_32' U2-BB21 # 32 BB21 IO_L18N_32 NET 'No_Conn_TP_IO_L18P_32' U2-BB22 # 32 BB22 IO_L18P_32 NET 'No_Conn_TP_IO_L6N_32' U2-BB23 # 32 BB23 IO_L6N_32 NET 'No_Conn_TP_IO_L6P_32' U2-BB24 # 32 BB24 IO_L6P_32 # Unused pins from IO bank 33 ############################# NET 'No_Conn_TP_IO_L10N_MRCC_33' U2-AJ15 # 33 AJ15 IO_L10N_MRCC_33 NET 'No_Conn_TP_IO_L10P_MRCC_33' U2-AJ16 # 33 AJ16 IO_L10P_MRCC_33 NET 'No_Conn_TP_IO_L6P_33' U2-AJ17 # 33 AJ17 IO_L6P_33 NET 'No_Conn_TP_IO_L18N_33' U2-AJ18 # 33 AJ18 IO_L18N_33 NET 'No_Conn_TP_IO_L9N_MRCC_33' U2-AK14 # 33 AK14 IO_L9N_MRCC_33 NET 'No_Conn_TP_IO_L9P_MRCC_33' U2-AK15 # 33 AK15 IO_L9P_MRCC_33 NET 'No_Conn_TP_IO_L6N_33' U2-AK17 # 33 AK17 IO_L6N_33 NET 'No_Conn_TP_IO_L18P_33' U2-AK18 # 33 AK18 IO_L18P_33 NET 'No_Conn_TP_IO_L0N_33' U2-AL14 # 33 AL14 IO_L0N_33 NET 'No_Conn_TP_IO_L0P_33' U2-AL15 # 33 AL15 IO_L0P_33 NET 'No_Conn_TP_IO_L4N_VREF_33' U2-AL16 # 33 AL16 IO_L4N_VREF_33 NET 'No_Conn_TP_IO_L4P_33' U2-AL17 # 33 AL17 IO_L4P_33 NET 'No_Conn_TP_IO_L2N_33' U2-AM14 # 33 AM14 IO_L2N_33 NET 'No_Conn_TP_IO_L8N_SRCC_33' U2-AM16 # 33 AM16 IO_L8N_SRCC_33 NET 'No_Conn_TP_IO_L14P_33' U2-AM17 # 33 AM17 IO_L14P_33 NET 'No_Conn_TP_IO_L14N_VREF_33' U2-AM18 # 33 AM18 IO_L14N_VREF_33 NET 'No_Conn_TP_IO_L2P_33' U2-AN15 # 33 AN15 IO_L2P_33 NET 'No_Conn_TP_IO_L8P_SRCC_33' U2-AN16 # 33 AN16 IO_L8P_SRCC_33 NET 'No_Conn_TP_IO_L16P_33' U2-AN18 # 33 AN18 IO_L16P_33 NET 'No_Conn_TP_IO_L16N_33' U2-AN19 # 33 AN19 IO_L16N_33 NET 'No_Conn_TP_IO_L12P_VRN_33' U2-AP16 # 33 AP16 IO_L12P_VRN_33 NET 'No_Conn_TP_IO_L12N_VRP_33' U2-AP17 # 33 AP17 IO_L12N_VRP_33 NET 'No_Conn_TP_IO_L11P_SRCC_33' U2-AP18 # 33 AP18 IO_L11P_SRCC_33 NET 'No_Conn_TP_IO_L1P_33' U2-AR17 # 33 AR17 IO_L1P_33 NET 'No_Conn_TP_IO_L1N_33' U2-AR18 # 33 AR18 IO_L1N_33 NET 'No_Conn_TP_IO_L11N_SRCC_33' U2-AR19 # 33 AR19 IO_L11N_SRCC_33 NET 'No_Conn_TP_IO_L3P_33' U2-AT16 # 33 AT16 IO_L3P_33 NET 'No_Conn_TP_IO_L5P_33' U2-AT17 # 33 AT17 IO_L5P_33 NET 'No_Conn_TP_IO_L19N_33' U2-AT19 # 33 AT19 IO_L19N_33 NET 'No_Conn_TP_IO_L3N_33' U2-AU17 # 33 AU17 IO_L3N_33 NET 'No_Conn_TP_IO_L5N_33' U2-AU18 # 33 AU18 IO_L5N_33 NET 'No_Conn_TP_IO_L19P_33' U2-AU19 # 33 AU19 IO_L19P_33 NET 'No_Conn_TP_IO_L13P_33' U2-AV18 # 33 AV18 IO_L13P_33 NET 'No_Conn_TP_IO_L13N_33' U2-AV19 # 33 AV19 IO_L13N_33 NET 'No_Conn_TP_IO_L7N_33' U2-AW18 # 33 AW18 IO_L7N_33 NET 'No_Conn_TP_IO_L7P_33' U2-AY18 # 33 AY18 IO_L7P_33 NET 'No_Conn_TP_IO_L17N_33' U2-AY19 # 33 AY19 IO_L17N_33 NET 'No_Conn_TP_IO_L17P_33' U2-BA19 # 33 BA19 IO_L17P_33 NET 'No_Conn_TP_IO_L15P_33' U2-BB18 # 33 BB18 IO_L15P_33 NET 'No_Conn_TP_IO_L15N_33' U2-BB19 # 33 BB19 IO_L15N_33 # Unused pins from IO bank 34 ############################# # note: 4 pins from this bank are used for 40MHz and 320 MHz Logic Clocks NET 'No_Conn_TP_IO_L9N_MRCC_34' U2-AM12 # 34 AM12 IO_L9N_MRCC_34 NET 'No_Conn_TP_IO_L9P_MRCC_34' U2-AM13 # 34 AM13 IO_L9P_MRCC_34 NET 'No_Conn_TP_IO_L10N_MRCC_34' U2-AN13 # 34 AN13 IO_L10N_MRCC_34 NET 'No_Conn_TP_IO_L10P_MRCC_34' U2-AN14 # 34 AN14 IO_L10P_MRCC_34 NET 'No_Conn_TP_IO_L5P_A09_D25_34' U2-AP13 # 34 AP13 IO_L5P_A09_D25_34 NET 'No_Conn_TP_IO_L17P_A19_34' U2-AP15 # 34 AP15 IO_L17P_A19_34 NET 'No_Conn_TP_IO_L3P_A13_D29_34' U2-AR12 # 34 AR12 IO_L3P_A13_D29_34 NET 'No_Conn_TP_IO_L5N_A08_D24_34' U2-AR13 # 34 AR13 IO_L5N_A08_D24_34 NET 'No_Conn_TP_IO_L15P_A23_34' U2-AR14 # 34 AR14 IO_L15P_A23_34 NET 'No_Conn_TP_IO_L17N_A18_34' U2-AR15 # 34 AR15 IO_L17N_A18_34 NET 'No_Conn_TP_IO_L3N_A12_D28_34' U2-AT12 # 34 AT12 IO_L3N_A12_D28_34 NET 'No_Conn_TP_IO_L15N_A22_34' U2-AT14 # 34 AT14 IO_L15N_A22_34 NET 'No_Conn_TP_IO_L19P_VRN_34' U2-AT15 # 34 AT15 IO_L19P_VRN_34 NET 'No_Conn_TP_IO_L7P_A05_D21_34' U2-AU12 # 34 AU12 IO_L7P_A05_D21_34 NET 'No_Conn_TP_IO_L7N_A04_D20_34' U2-AU13 # 34 AU13 IO_L7N_A04_D20_34 NET 'No_Conn_TP_IO_L4N_VREF_A10_D26_34' U2-AU14 # 34 AU14 IO_L4N_VREF_A10_D26_34 NET 'No_Conn_TP_IO_L19N_VRP_34' U2-AU16 # 34 AU16 IO_L19N_VRP_34 NET 'No_Conn_TP_IO_L11P_SRCC_34' U2-AV13 # 34 AV13 IO_L11P_SRCC_34 NET 'No_Conn_TP_IO_L11N_SRCC_34' U2-AV14 # 34 AV14 IO_L11N_SRCC_34 NET 'No_Conn_TP_IO_L4P_A11_D27_34' U2-AV15 # 34 AV15 IO_L4P_A11_D27_34 NET 'No_Conn_TP_IO_L8P_SRCC_34' U2-AV16 # 34 AV16 IO_L8P_SRCC_34 NET 'No_Conn_TP_IO_L13P_A01_D17_34' U2-AW12 # 34 AW12 IO_L13P_A01_D17_34 NET 'No_Conn_TP_IO_L13N_A00_D16_34' U2-AW13 # 34 AW13 IO_L13N_A00_D16_34 NET 'No_Conn_TP_IO_L6N_A06_D22_34' U2-AW15 # 34 AW15 IO_L6N_A06_D22_34 NET 'No_Conn_TP_IO_L8N_SRCC_34' U2-AW16 # 34 AW16 IO_L8N_SRCC_34 NET 'No_Conn_TP_IO_L18N_A16_34' U2-AW17 # 34 AW17 IO_L18N_A16_34 NET 'No_Conn_TP_IO_L6P_A07_D23_34' U2-AY15 # 34 AY15 IO_L6P_A07_D23_34 NET 'No_Conn_TP_IO_L18P_A17_34' U2-AY17 # 34 AY17 IO_L18P_A17_34 NET 'No_Conn_TP_IO_L2N_A14_D30_34' U2-BA14 # 34 BA14 IO_L2N_A14_D30_34 NET 'No_Conn_TP_IO_L2P_A15_D31_34' U2-BA15 # 34 BA15 IO_L2P_A15_D31_34 NET 'No_Conn_TP_IO_L14P_A25_34' U2-BA16 # 34 BA16 IO_L14P_A25_34 NET 'No_Conn_TP_IO_L14N_VREF_A24_34' U2-BA17 # 34 BA17 IO_L14N_VREF_A24_34 NET 'No_Conn_TP_IO_L12P_A03_D19_34' U2-BB13 # 34 BB13 IO_L12P_A03_D19_34 NET 'No_Conn_TP_IO_L12N_A02_D18_34' U2-BB14 # 34 BB14 IO_L12N_A02_D18_34 NET 'No_Conn_TP_IO_L16P_A21_34' U2-BB16 # 34 BB16 IO_L16P_A21_34 NET 'No_Conn_TP_IO_L16N_A20_34' U2-BB17 # 34 BB17 IO_L16N_A20_34 # Unused pins from IO bank 35 ############################# NET 'No_Conn_TP_IO_L5N_SM2N_35' U2-A14 # 35 A14 IO_L5N_SM2N_35 NET 'No_Conn_TP_IO_L5P_SM2P_35' U2-A15 # 35 A15 IO_L5P_SM2P_35 NET 'No_Conn_TP_IO_L1P_35' U2-A16 # 35 A16 IO_L1P_35 NET 'No_Conn_TP_IO_L13P_SM6P_35' U2-B14 # 35 B14 IO_L13P_SM6P_35 NET 'No_Conn_TP_IO_L1N_35' U2-B16 # 35 B16 IO_L1N_35 NET 'No_Conn_TP_IO_L15P_SM7P_35' U2-C13 # 35 C13 IO_L15P_SM7P_35 NET 'No_Conn_TP_IO_L13N_SM6N_35' U2-C14 # 35 C14 IO_L13N_SM6N_35 NET 'No_Conn_TP_IO_L7P_SM4P_35' U2-C15 # 35 C15 IO_L7P_SM4P_35 NET 'No_Conn_TP_IO_L3N_SM1N_35' U2-C16 # 35 C16 IO_L3N_SM1N_35 NET 'No_Conn_TP_IO_L15N_SM7N_35' U2-D12 # 35 D12 IO_L15N_SM7N_35 NET 'No_Conn_TP_IO_L17P_35' U2-D13 # 35 D13 IO_L17P_35 NET 'No_Conn_TP_IO_L7N_SM4N_35' U2-D15 # 35 D15 IO_L7N_SM4N_35 NET 'No_Conn_TP_IO_L3P_SM1P_35' U2-D16 # 35 D16 IO_L3P_SM1P_35 NET 'No_Conn_TP_IO_L0N_35' U2-E12 # 35 E12 IO_L0N_35 NET 'No_Conn_TP_IO_L17N_35' U2-E13 # 35 E13 IO_L17N_35 NET 'No_Conn_TP_IO_L19P_GC_35' U2-E14 # 35 E14 IO_L19P_GC_35 NET 'No_Conn_TP_IO_L11P_SRCC_35' U2-E15 # 35 E15 IO_L11P_SRCC_35 NET 'No_Conn_TP_IO_L0P_35' U2-F12 # 35 F12 IO_L0P_35 NET 'No_Conn_TP_IO_L19N_GC_35' U2-F14 # 35 F14 IO_L19N_GC_35 NET 'No_Conn_TP_IO_L11N_SRCC_35' U2-F15 # 35 F15 IO_L11N_SRCC_35 NET 'No_Conn_TP_IO_L6N_SM3N_35' U2-G12 # 35 G12 IO_L6N_SM3N_35 NET 'No_Conn_TP_IO_L4N_VREF_35' U2-G13 # 35 G13 IO_L4N_VREF_35 NET 'No_Conn_TP_IO_L2N_SM0N_35' U2-G14 # 35 G14 IO_L2N_SM0N_35 NET 'No_Conn_TP_IO_L6P_SM3P_35' U2-H13 # 35 H13 IO_L6P_SM3P_35 NET 'No_Conn_TP_IO_L4P_35' U2-H14 # 35 H14 IO_L4P_35 NET 'No_Conn_TP_IO_L2P_SM0P_35' U2-H15 # 35 H15 IO_L2P_SM0P_35 NET 'No_Conn_TP_IO_L8N_SRCC_35' U2-J11 # 35 J11 IO_L8N_SRCC_35 NET 'No_Conn_TP_IO_L8P_SRCC_35' U2-J12 # 35 J12 IO_L8P_SRCC_35 NET 'No_Conn_TP_IO_L12P_SM5P_35' U2-J13 # 35 J13 IO_L12P_SM5P_35 NET 'No_Conn_TP_IO_L16P_VRN_35' U2-K12 # 35 K12 IO_L16P_VRN_35 NET 'No_Conn_TP_IO_L12N_SM5N_35' U2-K13 # 35 K13 IO_L12N_SM5N_35 NET 'No_Conn_TP_IO_L14P_35' U2-K14 # 35 K14 IO_L14P_35 NET 'No_Conn_TP_IO_L16N_VRP_35' U2-L11 # 35 L11 IO_L16N_VRP_35 NET 'No_Conn_TP_IO_L18P_GC_35' U2-L12 # 35 L12 IO_L18P_GC_35 NET 'No_Conn_TP_IO_L14N_VREF_35' U2-L14 # 35 L14 IO_L14N_VREF_35 NET 'No_Conn_TP_IO_L18N_GC_35' U2-M12 # 35 M12 IO_L18N_GC_35 NET 'No_Conn_TP_IO_L10P_MRCC_35' U2-M13 # 35 M13 IO_L10P_MRCC_35 NET 'No_Conn_TP_IO_L9P_MRCC_35' U2-M14 # 35 M14 IO_L9P_MRCC_35 NET 'No_Conn_TP_IO_L10N_MRCC_35' U2-N13 # 35 N13 IO_L10N_MRCC_35 NET 'No_Conn_TP_IO_L9N_MRCC_35' U2-N14 # 35 N14 IO_L9N_MRCC_35 # Unused pins from IO bank 36 ############################# # note: some pins from this bank are used for the CTP Output NET 'No_Conn_TP_IO_L2P_36' U2-G16 # 36 G16 IO_L2P_36 NET 'No_Conn_TP_IO_L4N_VREF_36' U2-H16 # 36 H16 IO_L4N_VREF_36 NET 'No_Conn_TP_IO_L1P_36' U2-H18 # 36 H18 IO_L1P_36 NET 'No_Conn_TP_IO_L14P_36' U2-J15 # 36 J15 IO_L14P_36 NET 'No_Conn_TP_IO_L4P_36' U2-J16 # 36 J16 IO_L4P_36 NET 'No_Conn_TP_IO_L6N_36' U2-J17 # 36 J17 IO_L6N_36 NET 'No_Conn_TP_IO_L0N_36' U2-J18 # 36 J18 IO_L0N_36 NET 'No_Conn_TP_IO_L14N_VREF_36' U2-K15 # 36 K15 IO_L14N_VREF_36 NET 'No_Conn_TP_IO_L6P_36' U2-K17 # 36 K17 IO_L6P_36 NET 'No_Conn_TP_IO_L0P_36' U2-K18 # 36 K18 IO_L0P_36 NET 'No_Conn_TP_IO_L16N_36' U2-L15 # 36 L15 IO_L16N_36 NET 'No_Conn_TP_IO_L16P_36' U2-L16 # 36 L16 IO_L16P_36 NET 'No_Conn_TP_IO_L12P_VRN_36' U2-L17 # 36 L17 IO_L12P_VRN_36 NET 'No_Conn_TP_IO_L18P_36' U2-M16 # 36 M16 IO_L18P_36 NET 'No_Conn_TP_IO_L12N_VRP_36' U2-M17 # 36 M17 IO_L12N_VRP_36 NET 'No_Conn_TP_IO_L8P_SRCC_36' U2-M18 # 36 M18 IO_L8P_SRCC_36 NET 'No_Conn_TP_IO_L18N_36' U2-N15 # 36 N15 IO_L18N_36 NET 'No_Conn_TP_IO_L10P_MRCC_36' U2-N16 # 36 N16 IO_L10P_MRCC_36 NET 'No_Conn_TP_IO_L8N_SRCC_36' U2-N18 # 36 N18 IO_L8N_SRCC_36 NET 'No_Conn_TP_IO_L10N_MRCC_36' U2-P16 # 36 P16 IO_L10N_MRCC_36 NET 'No_Conn_TP_IO_L9N_MRCC_36' U2-P17 # 36 P17 IO_L9N_MRCC_36 NET 'No_Conn_TP_IO_L9P_MRCC_36' U2-P18 # 36 P18 IO_L9P_MRCC_36 # Unused pins from IO bank 37 ############################# # note: some pins from this bank are used for the CTP Output NET 'No_Conn_TP_IO_L0P_37' U2-G23 # 37 G23 IO_L0P_37 NET 'No_Conn_TP_IO_L14N_VREF_37' U2-H19 # 37 H19 IO_L14N_VREF_37 NET 'No_Conn_TP_IO_L0N_37' U2-H23 # 37 H23 IO_L0N_37 NET 'No_Conn_TP_IO_L14P_37' U2-J20 # 37 J20 IO_L14P_37 NET 'No_Conn_TP_IO_L18P_37' U2-K19 # 37 K19 IO_L18P_37 NET 'No_Conn_TP_IO_L16P_37' U2-K20 # 37 K20 IO_L16P_37 NET 'No_Conn_TP_IO_L18N_37' U2-L19 # 37 L19 IO_L18N_37 NET 'No_Conn_TP_IO_L16N_37' U2-L20 # 37 L20 IO_L16N_37 NET 'No_Conn_TP_IO_L9N_MRCC_37' U2-L21 # 37 L21 IO_L9N_MRCC_37 # Unused pins from IO bank 38 ############################# # note: some pins from this bank are used for the CTP Output NET 'No_Conn_TP_IO_L0N_38' U2-G24 # 38 G24 IO_L0N_38 NET 'No_Conn_TP_IO_L5P_38' U2-G26 # 38 G26 IO_L5P_38 NET 'No_Conn_TP_IO_L0P_38' U2-H24 # 38 H24 IO_L0P_38 NET 'No_Conn_TP_IO_L4N_VREF_38' U2-H25 # 38 H25 IO_L4N_VREF_38 NET 'No_Conn_TP_IO_L4P_38' U2-H26 # 38 H26 IO_L4P_38 NET 'No_Conn_TP_IO_L8P_SRCC_38' U2-J23 # 38 J23 IO_L8P_SRCC_38 NET 'No_Conn_TP_IO_L6N_38' U2-J25 # 38 J25 IO_L6N_38 NET 'No_Conn_TP_IO_L8N_SRCC_38' U2-K23 # 38 K23 IO_L8N_SRCC_38 NET 'No_Conn_TP_IO_L12N_VRP_38' U2-K24 # 38 K24 IO_L12N_VRP_38 NET 'No_Conn_TP_IO_L6P_38' U2-K25 # 38 K25 IO_L6P_38 NET 'No_Conn_TP_IO_L12P_VRN_38' U2-L24 # 38 L24 IO_L12P_VRN_38 NET 'No_Conn_TP_IO_L9P_MRCC_38' U2-M19 # 38 M19 IO_L9P_MRCC_38 NET 'No_Conn_TP_IO_L10N_MRCC_38' U2-M21 # 38 M21 IO_L10N_MRCC_38 NET 'No_Conn_TP_IO_L14P_38' U2-M22 # 38 M22 IO_L14P_38 NET 'No_Conn_TP_IO_L14N_VREF_38' U2-M23 # 38 M23 IO_L14N_VREF_38 NET 'No_Conn_TP_IO_L16N_38' U2-M24 # 38 M24 IO_L16N_38 NET 'No_Conn_TP_IO_L9N_MRCC_38' U2-N19 # 38 N19 IO_L9N_MRCC_38 NET 'No_Conn_TP_IO_L19N_38' U2-N20 # 38 N20 IO_L19N_38 NET 'No_Conn_TP_IO_L10P_MRCC_38' U2-N21 # 38 N21 IO_L10P_MRCC_38 NET 'No_Conn_TP_IO_L16P_38' U2-N23 # 38 N23 IO_L16P_38 NET 'No_Conn_TP_IO_L19P_38' U2-P20 # 38 P20 IO_L19P_38 NET 'No_Conn_TP_IO_L18P_38' U2-P21 # 38 P21 IO_L18P_38 NET 'No_Conn_TP_IO_L18N_38' U2-P22 # 38 P22 IO_L18N_38 # # CMX FF1759 Package NET-to-Pin File # -------------------------------------- # # # Original Rev. 1-Feb-2012 # Most Recent Rev. 14-Nov-2012 # # # # This is the N2P file is for Virtex-6 VCCAUX and VCCINT Nets # in the FF1759 Package. # # This file is for the TP FPGA on the CMX card. # # The following 20 pins are the Virtex-6 VCCAUX power pins. # On the CMX card the VCCAUX power will come from the BULK_2V5 # power distribution bus. NET 'BULK_2V5' U2-AA10 U2-AA28 U2-AB11 U2-AB29 U2-AC10 U2-AC28 NET 'BULK_2V5' U2-AD11 U2-AD29 U2-AE10 U2-AE28 U2-AF27 U2-AF29 U2-T29 U2-U28 U2-V11 U2-V29 NET 'BULK_2V5' U2-W10 U2-W28 U2-Y11 U2-Y29 # The following 104 pins are the Virtex-6 VCCINT power pins. # On the CMX card the VCCINT power for the Base Function FPGA # will come from the BASE_CORE power distribution bus. NET 'TP_CORE' U2-AA12 U2-AA14 U2-AA16 U2-AA18 U2-AA20 U2-AA24 NET 'TP_CORE' U2-AA26 U2-AB13 U2-AB15 U2-AB17 U2-AB19 U2-AB23 U2-AB25 U2-AB27 U2-AC12 U2-AC14 NET 'TP_CORE' U2-AC16 U2-AC18 U2-AC20 U2-AC24 U2-AC26 U2-AD13 U2-AD15 U2-AD17 U2-AD19 U2-AD21 NET 'TP_CORE' U2-AD23 U2-AD25 U2-AD27 U2-AE12 U2-AE14 U2-AE16 U2-AE18 U2-AE20 U2-AE22 U2-AE24 NET 'TP_CORE' U2-AE26 U2-AF13 U2-AF15 U2-AF17 U2-AF19 U2-AF21 U2-AF23 U2-AF25 U2-AG12 U2-AG14 NET 'TP_CORE' U2-AG16 U2-AG18 U2-AG20 U2-AG22 U2-AG24 U2-AG26 U2-AH13 U2-AH15 U2-AH19 U2-AH21 NET 'TP_CORE' U2-AH23 U2-P13 U2-P15 U2-R12 U2-R14 U2-R18 U2-R20 U2-R22 U2-R24 U2-T13 NET 'TP_CORE' U2-T15 U2-T17 U2-T19 U2-T21 U2-T23 U2-T25 U2-T27 U2-U12 U2-U14 U2-U16 NET 'TP_CORE' U2-U18 U2-U20 U2-U22 U2-U24 U2-U26 U2-V13 U2-V15 U2-V17 U2-V19 U2-V21 NET 'TP_CORE' U2-V23 U2-V25 U2-V27 U2-W12 U2-W14 U2-W16 U2-W18 U2-W20 U2-W22 U2-W24 NET 'TP_CORE' U2-W26 U2-Y13 U2-Y15 U2-Y17 U2-Y19 U2-Y23 U2-Y25 U2-Y27 # # CMX FF1759 Package NET-to-Pin File # -------------------------------------- # # # Bank 0 and Special Pins # ------===--------------------- # # # # Original Rev. 29-Dec-2012 # Most Recent Rev. 18-Mar-2012 # # # # This is the N2P file for Virtex-6 "Bank 0" and Special # Nets for the CMX Topological Function FPGA. # # Pins with many and completely different functions are # included in what Xilinx calls "Bank 0". These are not # Select I/O pins. Rather these pins include those that # are involved with thinks like Configuration, System # Monitor, JTAG, Power Management, Si temperature # measurement, ... # # These are all special one of a kind fixed location pins. # # Other "special" pins, besides those in "Bank 0" should # be included in this Net to Pin file. Recall, we want # to assign a net to every one of the 1760 pins on this # component. # # # This file is for the Topological Function FPGA on the CMX card. # -------------------- # # # JTAG connections to the Topological Function FPGA # # On the CMX's Virtex-6 FPGAs the JTAG connections # are pins in "Bank 0" NET 'CFG_TMS_from_ACE' U2-AN11 # TMS_0 CFG JTAG TMS from ACE pin 85 NET 'CFG_TCK_from_ACE' U2-AN10 # TCK_0 CFG JTAG TCK from ACE pin 80 NET 'CFG_TP_TDI' U2-AP10 # TDI_0 CFG JTAG Data from BF to TP NET 'CFG_TP_TDO' U2-AR10 # TDO_0 CFG JTAG Data from TP to ACE # # Configuration Nets NET 'TP_PROGRAM_B' U2-M11 # PROGRAM_B_0 NET 'TP_INIT_B' U2-N11 # INIT_B_0 NET 'TP_CONFIG_DONE' U2-N10 # DONE_0 NET 'TP_M0' U2-AL11 # M0_0 NET 'TP_M1' U2-AM11 # M1_0 NET 'TP_M2' U2-AL10 # M2_0 NET 'TP_CCLK' U2-K10 # CCLK_0 NET 'TP_DIN' U2-L10 # DIN_0 NET 'TP_DOUT_BUSY' U2-AK10 # DOUT_BUSY_0 NET 'TP_CSI_B' U2-T10 # CSI_B_0 NET 'TP_RDWR_B' U2-J10 # RDWR_B_0 # # System Monitor Nets NET 'TP_SM_AVDD' U2-Y22 # AVDD_0 NET 'TP_SM_AVSS' U2-Y21 # AVSS_0 NET 'TP_SM_VP' U2-AA22 # VP_0 NET 'TP_SM_VN' U2-AB21 # VN_0 NET 'TP_SM_VREFP' U2-AB22 # VREFP_0 NET 'TP_SM_AVSS' U2-AA21 # VREFN_0 # # Silicon Temperature Nets NET 'TP_SI_TEMP_DXP' U2-AC22 # DXP_0 NET 'TP_SI_TEMP_DXN' U2-AC21 # DXN_0 # # Other Special "Bank 0" Nets NET 'TP_HSWAPEN' U2-P10 # HSWAPEN_0 # VBATT is a power supply pin for the Decryptor Key memory. # The book says that when VBATT is not used to connect # this pin to either VccAUX or to GROUND. CMX will not # use the Decryptor Key VBATT supply. CMX will # permanently and irrevocably Ground this pin. # ## NET 'TP_VBATT' U2-R10 # VBATT_0 NET 'GROUND' U2-R10 # VBATT_0 # VFS is a power supply pin for programming the EFUSE. # The book says to Ground the VFS pin when it is not # being used. CMX will not use the EFUSE. Thus CMX # will permanently and irrevocably Ground this pin. # ## NET 'TP_VFS' U2-AH10 # VFS_0 NET 'GROUND' U2-AH10 # VFS_0 # # Special Non-Bank 0 Nets # # CMX FF1759 Package NET-to-Pin File # -------------------------------------- # # # Original Rev. 30-Jan-2012 # Most Recent Rev. 14-Nov-2012 # # # This is the N2P file is for Virtex-6 Ground Nets in the FF1759 Package. # # This file is for the TP FPGA on the CMX card. # # This file has 431 Ground Pins. # NET 'GROUND' U2-A2 U2-A3 U2-A4 U2-A7 U2-A8 U2-A11 U2-A13 U2-A18 U2-A28 NET 'GROUND' U2-A38 U2-AA3 U2-AA7 U2-AA9 U2-AA11 U2-AA13 U2-AA15 U2-AA17 U2-AA19 U2-AA23 NET 'GROUND' U2-AA25 U2-AA27 U2-AA29 U2-AA38 U2-AB1 U2-AB2 U2-AB5 U2-AB6 U2-AB9 U2-AB10 NET 'GROUND' U2-AB12 U2-AB14 U2-AB16 U2-AB18 U2-AB20 U2-AB24 U2-AB26 U2-AB28 U2-AB35 U2-AC3 NET 'GROUND' U2-AC7 U2-AC9 U2-AC11 U2-AC13 U2-AC15 U2-AC17 U2-AC19 U2-AC23 U2-AC25 U2-AC27 NET 'GROUND' U2-AC29 U2-AC32 U2-AC42 U2-AD1 U2-AD2 U2-AD5 U2-AD6 U2-AD9 U2-AD10 U2-AD12 NET 'GROUND' U2-AD14 U2-AD16 U2-AD18 U2-AD20 U2-AD22 U2-AD24 U2-AD26 U2-AD28 U2-AD39 U2-AE3 NET 'GROUND' U2-AE7 U2-AE9 U2-AE11 U2-AE13 U2-AE15 U2-AE17 U2-AE19 U2-AE21 U2-AE23 U2-AE25 NET 'GROUND' U2-AE27 U2-AE29 U2-AE36 U2-AF1 U2-AF2 U2-AF5 U2-AF6 U2-AF9 U2-AF10 U2-AF11 NET 'GROUND' U2-AF12 U2-AF14 U2-AF16 U2-AF18 U2-AF20 U2-AF22 U2-AF24 U2-AF26 U2-AF28 U2-AF33 NET 'GROUND' U2-AG3 U2-AG4 U2-AG7 U2-AG8 U2-AG9 U2-AG10 U2-AG11 U2-AG13 U2-AG15 U2-AG17 NET 'GROUND' U2-AG19 U2-AG21 U2-AG23 U2-AG30 U2-AG40 U2-AH1 U2-AH2 U2-AH5 U2-AH6 U2-AH9 NET 'GROUND' U2-AH11 U2-AH12 U2-AH14 U2-AH16 U2-AH17 U2-AH18 U2-AH20 U2-AH27 U2-AH37 U2-AJ3 NET 'GROUND' U2-AJ7 U2-AJ9 U2-AJ11 U2-AJ12 U2-AJ13 U2-AJ14 U2-AJ24 U2-AJ34 U2-AK1 U2-AK2 NET 'GROUND' U2-AK5 U2-AK6 U2-AK9 U2-AK11 U2-AK12 U2-AK13 U2-AK21 U2-AK31 U2-AK41 U2-AL3 NET 'GROUND' U2-AL7 U2-AL9 U2-AL12 U2-AL18 U2-AL28 U2-AL38 U2-AM1 U2-AM2 U2-AM5 U2-AM9 NET 'GROUND' U2-AM10 U2-AM15 U2-AM25 U2-AM35 U2-AN3 U2-AN7 U2-AN9 U2-AN12 U2-AN22 U2-AN32 NET 'GROUND' U2-AN42 U2-AP1 U2-AP2 U2-AP5 U2-AP9 U2-AP19 U2-AP29 U2-AP39 U2-AR3 U2-AR7 NET 'GROUND' U2-AR9 U2-AR16 U2-AR26 U2-AR36 U2-AT1 U2-AT2 U2-AT5 U2-AT6 U2-AT9 U2-AT10 NET 'GROUND' U2-AT11 U2-AT13 U2-AT23 U2-AT33 U2-AU3 U2-AU7 U2-AU11 U2-AU20 U2-AU30 U2-AU40 NET 'GROUND' U2-AV1 U2-AV2 U2-AV5 U2-AV9 U2-AV10 U2-AV11 U2-AV17 U2-AV27 U2-AV37 U2-AW3 NET 'GROUND' U2-AW7 U2-AW11 U2-AW14 U2-AW24 U2-AW34 U2-AY1 U2-AY2 U2-AY5 U2-AY9 U2-AY10 NET 'GROUND' U2-AY11 U2-AY12 U2-AY21 U2-AY31 U2-AY41 U2-B1 U2-B2 U2-B5 U2-B9 U2-B10 NET 'GROUND' U2-B12 U2-B13 U2-B15 U2-B25 U2-B35 U2-BA3 U2-BA7 U2-BA11 U2-BA12 U2-BA18 NET 'GROUND' U2-BA28 U2-BA38 U2-BB2 U2-BB5 U2-BB6 U2-BB9 U2-BB10 U2-BB11 U2-BB12 U2-BB15 NET 'GROUND' U2-BB25 U2-BB35 U2-C3 U2-C7 U2-C11 U2-C12 U2-C22 U2-C32 U2-C42 U2-D1 NET 'GROUND' U2-D2 U2-D5 U2-D9 U2-D10 U2-D11 U2-D19 U2-D29 U2-D39 U2-E3 U2-E7 NET 'GROUND' U2-E11 U2-E16 U2-E26 U2-E36 U2-F1 U2-F2 U2-F5 U2-F9 U2-F10 U2-F11 NET 'GROUND' U2-F13 U2-F23 U2-F33 U2-G3 U2-G7 U2-G11 U2-G20 U2-G30 U2-G40 U2-H1 NET 'GROUND' U2-H2 U2-H5 U2-H9 U2-H10 U2-H11 U2-H17 U2-H27 U2-H37 U2-J3 U2-J7 NET 'GROUND' U2-J9 U2-J14 U2-J24 U2-J34 U2-K1 U2-K2 U2-K5 U2-K6 U2-K9 U2-K11 NET 'GROUND' U2-K21 U2-K31 U2-K41 U2-L3 U2-L7 U2-L9 U2-L18 U2-L28 U2-L38 U2-M1 NET 'GROUND' U2-M2 U2-M5 U2-M6 U2-M9 U2-M15 U2-M25 U2-M35 U2-N3 U2-N7 U2-N9 NET 'GROUND' U2-N12 U2-N22 U2-N32 U2-N42 U2-P1 U2-P2 U2-P5 U2-P9 U2-P11 U2-P12 NET 'GROUND' U2-P19 U2-P29 U2-P39 U2-R3 U2-R7 U2-R9 U2-R13 U2-R15 U2-R16 U2-R17 NET 'GROUND' U2-R19 U2-R26 U2-R36 U2-T1 U2-T2 U2-T5 U2-T6 U2-T9 U2-T11 U2-T12 NET 'GROUND' U2-T14 U2-T16 U2-T18 U2-T20 U2-T22 U2-T24 U2-T26 U2-T33 U2-U3 U2-U4 NET 'GROUND' U2-U7 U2-U8 U2-U9 U2-U10 U2-U11 U2-U13 U2-U15 U2-U17 U2-U19 U2-U21 NET 'GROUND' U2-U23 U2-U25 U2-U27 U2-U29 U2-U30 U2-U40 U2-V1 U2-V2 U2-V5 U2-V6 NET 'GROUND' U2-V9 U2-V10 U2-V12 U2-V14 U2-V16 U2-V18 U2-V20 U2-V22 U2-V24 U2-V26 NET 'GROUND' U2-V28 U2-V37 U2-W3 U2-W7 U2-W9 U2-W11 U2-W13 U2-W15 U2-W17 U2-W19 NET 'GROUND' U2-W21 U2-W23 U2-W25 U2-W27 U2-W34 U2-Y1 U2-Y2 U2-Y5 U2-Y6 U2-Y9 NET 'GROUND' U2-Y10 U2-Y12 U2-Y14 U2-Y16 U2-Y18 U2-Y20 U2-Y24 U2-Y26 U2-Y28 U2-Y31 NET 'GROUND' U2-Y41 U2-AJ10 # # CMX FF1759 Package NET-to-Pin File # -------------------------------------- # # # Original Rev. 30-Jan-2012 # Most Recent Rev. 31-Dec-2012 # # # # This is the N2P file is for Virtex-6 MGTAVCC and MGTAVTT Nets # in the FF1759 Package. These are the analog power nets for # the high speed serial transceivers. # # This file is for the Topological Processor FPGA on the CMX card. # ----------------------- # # The following 18 pins are the Virtex-6 MGTAVCC power pins. # On the CMX card the MGTAVCC power will come from the GTX_AVTT # power distribution bus. NET 'TP_GTX_AVCC' U2-AA8 U2-C8 U2-E8 U2-G8 U2-J8 U2-L8 U2-N8 U2-R8 U2-W8 # MGTAVCC_N NET 'TP_GTX_AVCC' U2-AC8 U2-AE8 U2-AJ8 U2-AL8 U2-AN8 U2-AR8 U2-AU8 U2-AW8 U2-BA8 # MGTAVCC_S # The following 27 pins are the Virtex-6 MGTAVTT power pins. # On the CMX card the MGTAVTT power will come from the GTX_AVCC # power distribution bus. NET 'TP_GTX_AVTT' U2-B6 U2-C4 U2-D6 U2-E4 U2-F6 U2-G4 U2-H6 U2-J4 U2-L4 # MGTAVTT_N NET 'TP_GTX_AVTT' U2-N4 U2-P6 U2-R4 U2-W4 # MGTAVTT_N NET 'TP_GTX_AVTT' U2-AA4 U2-AC4 U2-AE4 U2-AJ4 U2-AL4 U2-AM6 U2-AN4 U2-AP6 # MGTAVTT_S NET 'TP_GTX_AVTT' U2-AR4 U2-AU4 U2-AV6 U2-AW4 U2-AY6 U2-BA4 # MGTAVTT_S # # CMX FF1759 Package NET-to-Pin File # -------------------------------------- # # # Original Rev. 30-Jan-2012 # Most Recent Rev. 14-Nov-2012 # # # # This is the N2P file is for Virtex-6 VCCO_xy Nets # in the FF1759 Package. # # This file is for the TP FPGA on the CMX card. # # The following 112 pins are the Virtex-6 VCCO power pins. # On the CMX card the VCCO power will come from the BULK_2V5 # power distribution bus. All TP FPGA I/O Banks will have # 2.5V signal levels. # NET 'BULK_2V5' U2-M10 U2-R11 # VCCO_0 NET 'BULK_2V5' U2-AP34 U2-AT38 U2-AU35 U2-AW39 U2-AY36 # VCCO_12 NET 'BULK_2V5' U2-AK36 U2-AN37 U2-AR41 U2-AV42 U2-BB40 # VCCO_13 NET 'BULK_2V5' U2-AF38 U2-AG35 U2-AH42 U2-AJ39 U2-AM40 # VCCO_14 NET 'BULK_2V5' U2-AA33 U2-AB40 U2-AC37 U2-AD34 U2-AE41 # VCCO_15 NET 'BULK_2V5' U2-U35 U2-V32 U2-V42 U2-W39 U2-Y36 # VCCO_16 NET 'BULK_2V5' U2-M40 U2-N37 U2-P34 U2-R41 U2-T38 # VCCO_17 NET 'BULK_2V5' U2-AH22 U2-AL23 U2-AP24 U2-AU25 U2-AY26 # VCCO_21 NET 'BULK_2V5' U2-AN27 U2-AT28 U2-AW29 U2-BA33 U2-BB30 # VCCO_22 NET 'BULK_2V5' U2-AG25 U2-AK26 U2-AL33 U2-AM30 U2-AR31 U2-AV32 # VCCO_23 NET 'BULK_2V5' U2-AB30 U2-AE31 U2-AH32 U2-AJ29 U2-R31 U2-W29 # VCCO_24 NET 'BULK_2V5' U2-H42 U2-J39 U2-K36 U2-L33 U2-M30 U2-T28 # VCCO_25 NET 'BULK_2V5' U2-B40 U2-C37 U2-E41 U2-F38 U2-G35 # VCCO_26 NET 'BULK_2V5' U2-A33 U2-D34 U2-E31 U2-H32 U2-J29 # VCCO_27 NET 'BULK_2V5' U2-B30 U2-F28 U2-K26 U2-N27 U2-P24 # VCCO_28 NET 'BULK_2V5' U2-AJ19 U2-AM20 U2-AR21 U2-AV22 U2-BA23 # VCCO_32 NET 'BULK_2V5' U2-AK16 U2-AL13 U2-AN17 U2-AT18 U2-AW19 U2-BB20 # VCCO_33 NET 'BULK_2V5' U2-AP14 U2-AR11 U2-AU15 U2-AV12 U2-AY16 U2-BA13 # VCCO_34 NET 'BULK_2V5' U2-C17 U2-D14 U2-G15 U2-H12 U2-L13 # VCCO_35 NET 'BULK_2V5' U2-B20 U2-F18 U2-K16 U2-N17 U2-P14 # VCCO_36 NET 'BULK_2V5' U2-A23 U2-D24 U2-E21 U2-H22 U2-J19 # VCCO_37 NET 'BULK_2V5' U2-C27 U2-G25 U2-L23 U2-M20 U2-R21 # VCCO_38 # # CMX-0 Nets File # # JTAG Chains TEST and Configuration Nets # ------------------------------------------- # # # Original Rev. 22-Aug-2012 # Most Recent Rev. 3-Sept-2013 # # # # This file holds the nets for both of the JTAG chains on the # CMX card. There is a "TEST" and a "Configuration" JTAG # chain on the CMX card. TEST and Configuration are the names # given by Xilinx to the two JTAG ports on the System-Ace chip. # # The TEST JTAG chain starts at the front panel JTAG connector, # J12, runs to the TEST port on the System-Ace U321, and then # to the TTCDec mezzanine card TTC_Mez, and then to the # Configuration PROM for the Board Support FPGA, and then # to the Spartan 3A BSPT FPGA itself, and then finally back # to the J12 connector. This is a 3.3 Volt JTAG chain. # # The front panel TEST JTAG chain is buffered right were it # enters the CMX card on J12. 74LVC04A chips are used to # buffer these JTAG signals. There are pull-up resistors # on the TEST TMS TCK and TDI signals as they enter on J12. # # The Configuration JTAG chain starts at the Configuration port # of the System-Ace U321, runs to the Base Function FPGA U1, # and then runs to the Topological Processor FPGA U2, and then # finally runs back to the System-Ace Configuration port. # This is a 2.5V JTAG chain. # # # This design includes jumpers so that one can jump around # any of the devices in either the JTAG TEST Chain or in the # JTAG CONFIG Chain. # # # This design includes fuse F3 that supplies BULK_3V3 to # pin 2 on the front panel TEST JTAG connector J12. # # # Recal the Xilinx "standard" JTAG connector pinout. # # Xilinx uses the normal standard pin numbering vs physical # layout system for the 14 pin connector on their JTAG Pod. # # Unlike most cabling systems Xilinx puts the Ground on # the odd numbered pins and puts the signals on the even # numbered pins. # # CMX uses the normal standard pin numbering scheme for # its J12 connector near the bottom of the front panel. # # The first 5 signals on CMX connector J12 match the # pinout used by Xilinx so that a 1-to-1 cable can be # used for just this section of J12 to connect a # Xilinx JTAG pod to the CMX card's J12 connector. # # The only difference is that CMX will use a 2x8 16 pin # connector for its J12. The first 10 pins of J12 match # the Xilinx JTAG Pod connector. # # # Note that: # # - J12 pins 11 and 12 are used for CAN-Bus uProcessor # Reset and Mode control signals from the Programmer. # # - J12 pins 13 and 14 are used for RS-232 communications # with the CAN-Bus microprocessor. # # - J12 pins 15 and 16 are used for Front Panel Access # Signals #1 and #2. # # - The cable between the Xilinx JTAG Pod and the CMX J12 # connector must connect only pins 1 through 10, i.e. # the first 5 signal/ground pairs from the JTAG Pod. # # - The Xilinx Pod signals named Vtst and INIT are not # connected to the CMX card - these are not JTAG signals. # # # # # CMX J12 Connector Pin-Out TEST JTAG # # All odd pins, 1 through 9, are Ground # # pin #2 Fused 3.3 Volt proper voltage to power the "pod". # This is 3.3V for the CMX. It must be fused. # # pin #4 TMS This could have a series terminator/limiter # CMM pulls TMS up with 4.7k Ohm. # # pin #6 TCK This could have a series terminator/limiter # CMM pulls TCK up with 4.7k Ohm. # # pin #8 TDO This could have a series terminator/limiter # This is Test Data from CMX to the Pod # # pin #10 TDI This could have a series terminator/limiter # CMM pulls TDI up with 4.7k Ohm. # This is Test Data from the Pod to CMX # # pin #11 Mode Control signal to the CAN-Bus uProcessor. # # pin #12 Reset Signal to the CAN-Bus uProcessor. # # pins #13 and #14 are the RS-232 signals with the # CAN-Bus micro-controller # # pins #15 and #16 are two Front Panel Access Signals # # Note that the Ground pins associated with the JTAG # section of J12, i.e. 5 odd odd pins 1 through 9 # will also be used as grounds for the Access # Signal and RS-232 functions of J12. # # # Components referenced in this file include: # # J12 front panel JTAG connection to the TEST JTAG chain # U1 Base Function FPGA Virtex-6 # U2 Topological Processor FPGA Virtex-6 # U321 System-Ace # U322 TEST JTAG Buffer chip # U323 TEST JTAG Buffer chip # U351 Board Support FPGA Spartan 3a # U359 Config_PROM for the BSPT_FPGA # # JMP61:JMP68 Jumpers in the JTAG TEST Chain # JMP71:JMP76 Jumpers in the JTAG CONFIG Chain # # R331:R333 4.7k Pull-Up resistors on J12 TEST Chain # # R313:R315 47 Ohm series terminators in the Config JTAG chain # # F3 Fuse for the TEST JTAG Connector VCC Pin # # C333:C336 Bypass capacitors for U322 and U323 # # # # TEST JTAG Chain: # ------------------ # # Nets for the pins on the J12 # front panel TEST JTAG chain connector NET 'GROUND' J12-1 J12-3 J12-5 # front panel connector NET 'GROUND' J12-7 J12-9 # for the TEST JTAG chain NET 'TEST_TMS_from_J12' J12-4 # TMS received on J12 pin #4 NET 'TEST_TCK_fron_J12' J12-6 # TCK received on J12 pin #6 NET 'TEST_J12_to_ACE_TDI' J12-10 # TDI received on J12 pin #10 # going to the System-Ace Test port NET 'TEST_TDO_BUF_OUT' J12-8 # Buffered TDO from the BSPT FPGA # sent out on J12 pin #8 # J12 TEST JTAG Chain Pull-Up Resistors NET 'TEST_TMS_from_J12' R331-1 # Pull_Up TMS received on J12 NET 'TEST_TCK_fron_J12' R332-1 # Pull_Up TCK received on J12 NET 'TEST_J12_to_ACE_TDI' R333-1 # Pull-Up TDI received on J12 NET 'BULK_3V3' R331-2 R332-2 R333-2 # BULK_3V3 To Pull_ups # # Buffer the TEST JTAG Signals # ------------------------------ # Buffer the TEST TMS Signal NET 'TEST_TMS_from_J12' U322-1 # Input to the TEST JTAG TMS Buffer NET 'TEST_TMS_2_BUF_STAGE' U322-2 U323-1 # 2nd stage TEST TMS Buffer NET 'TEST_TMS_2_BUF_STAGE' U323-3 # 2nd stage TEST TMS Buffer NET 'TEST_TMS_BUF_OUT_1' U323-2 # Output of 2nd stage TEST TMS Buf 1 NET 'TEST_TMS_BUF_OUT_2' U323-4 # Output of 2nd stage TEST TMS Buf 2 # Buffer the TEST TCK Signal NET 'TEST_TCK_fron_J12' U322-3 # Input to the TEST JTAG TCK Buffer NET 'TEST_TCK_2_BUF_STAGE' U322-4 U323-5 # 2nd stage TEST TCK Buffer NET 'TEST_TCK_2_BUF_STAGE' U323-9 # 2nd stage TEST TCK Buffer NET 'TEST_TCK_BUF_OUT_1' U323-6 # Output of 2nd stage TEST TCK Buf 1 NET 'TEST_TCK_BUF_OUT_2' U323-8 # Output of 2nd stage TEST TCK Buf 2 # Buffer the TEST TDI Signal NET 'TEST_J12_to_ACE_TDI' U322-5 # Input to the TEST JTAG TDI Buffer NET 'TEST_TDI_2_BUF_STAGE' U322-6 U322-9 # 2nd stage TEST TDI Buffer NET 'TEST_TDI_BUF_OUT' U322-8 # Output of 2nd stage TEST TDI Buffer # Buffer the TEST TDO Signal NET 'TEST_TDO_TO_BUF' U322-13 # Buffer input for TEST TDO from BSPT FPGA NET 'TEST_TDO_2_BUF_STAGE' U322-12 U322-11 # 2nd stage TEST TDO Buffer NET 'TEST_TDO_BUF_OUT' U322-10 # TEST TDO 2nd Buffer Output to J12 # # Nets on the System-Ace TEST port # NET 'TEST_TMS_BUF_OUT_2' U321-98 # TMS into the System-Ace Test port NET 'TEST_TCK_BUF_OUT_2' U321-101 # TCK into the System-Ace Test port NET 'TEST_TDI_BUF_OUT' U321-102 # TDI from the Buffer to System # Ace Test port TDI pin and to NET 'TEST_TDI_BUF_OUT' JMP62-1 # Jumper around the System-ACE NET 'TEST_ACE_TDO_to_JUMPER' U321-97 # TDO from the System-Ace NET 'TEST_ACE_TDO_to_JUMPER' JMP61-1 # going to JMP61 NET 'TEST_JUMPER_to_TTCDec_TDI' JMP61-2 # Jumpers to select the signal NET 'TEST_JUMPER_to_TTCDec_TDI' JMP62-2 # going to the TTCDec TDI # # Nets on the TTCDec Mezzanine JTAG port # NET 'TEST_TMS_BUF_OUT_2' TTC_Mez-H1_51 # TMS into the TTCDec Mezzanine NET 'TEST_TCK_BUF_OUT_2' TTC_Mez-H1_55 # TCK into the TTCDec Mezzanine NET 'TEST_JUMPER_to_TTCDec_TDI' TTC_Mez-H1_49 # TDO from the System-Ace # Test port going to the # TTCDec TDI pin and the NET 'TEST_JUMPER_to_TTCDec_TDI' JMP64-1 # Jumper around the TTCDec NET 'TEST_TTCDec_TDO_to_JUMPER' TTC_Mez-H1_53 # TDO from the TTCDec NET 'TEST_TTCDec_TDO_to_JUMPER' JMP63-1 # going to JMP63 NET 'TEST_JUMPER_to_PROM_TDI' JMP63-2 # Jumpers to select the signal NET 'TEST_JUMPER_to_PROM_TDI' JMP64-2 # going to the Config PROM TDI # # Nets on the JTAG port of the Configuration PROM for the BSPT_FPGA # NET 'TEST_TMS_BUF_OUT_1' U359-5 # TMS into the Config_PROM NET 'TEST_TCK_BUF_OUT_1' U359-6 # TCK into the Config_PROM NET 'TEST_JUMPER_to_PROM_TDI' U359-4 # TDO from the TTCDec Mezzanine # going to the Config_PROM TDI and NET 'TEST_JUMPER_to_PROM_TDI' JMP66-1 # the Jumper around the Config PROM NET 'TEST_PROM_TDO_to_JUMPER' U359-17 # TDO from the Config_PROM NET 'TEST_PROM_TDO_to_JUMPER' JMP65-1 # going to JMP65 NET 'TEST_JUMPER_to_BSPT_TDI' JMP65-2 # Jumpers to select the signal NET 'TEST_JUMPER_to_BSPT_TDI' JMP66-2 # going to the BSPT FPGA TDI. # # Nets on the JTAG port of the Spartan 3A BSPT_FPGA # NET 'TEST_TMS_BUF_OUT_1' U351-E4 # TMS into the BSPT FPGA NET 'TEST_TCK_BUF_OUT_1' U351-A19 # TCK into the BSPT FPGA NET 'TEST_JUMPER_to_BSPT_TDI' U351-F5 # TDO from the Config_PROM # going to the BSPT FPGA TDI and NET 'TEST_JUMPER_to_BSPT_TDI' JMP68-1 # the Jumper around the BSPT_FPGA NET 'TEST_BSPT_TDO_to_JUMPER' U351-E17 # TDO from the BSPT FPGA NET 'TEST_BSPT_TDO_to_JUMPER' JMP67-1 # going to JMP67 NET 'TEST_TDO_TO_BUF' JMP67-2 # Jumpers to select the signal NET 'TEST_TDO_TO_BUF' JMP68-2 # going to the TEST TDO Buffer # and then to J12 TDO pin #8. # # Now the 3.3 Volt Fused Power to the TEST JTAG VCC Pin # NET 'BULK_3V3' F3-2 # BULK_3V3 power to the TEST JTAG Fuse. NET 'TEST_JTAG_VCC' F3-1 J12-2 # Fused 3.3V Power to TEST JTAG Connector # # Configuration JTAG Chain: # --------------------------- # # # Nets on the System-Ace Configuration port # NET 'CFG_TMS_from_ACE_to_Term' U321-85 R314-1 # CFG JTAG TMS from ACE to Term NET 'CFG_TCK_from_ACE_to_Term' U321-80 R315-1 # CFG JTAG TCK from ACE to Term NET 'CFG_ACE_TDO_to_Term' U321-82 R313-1 # JTAG Data from ACE to Term NET 'CFG_TP_TDO_to_ACE_TDI' U321-81 # JTAG Data from TP FPGA to ACE # # The CFG_TMS, CFG_TCK, and CFG_TDO loop through series terminators # NET 'CFG_TMS_from_ACE' R314-2 # CFG JTAG TMS from ACE Term NET 'CFG_TCK_from_ACE' R315-2 # CFG JTAG TCK from ACE Term NET 'CFG_ACE_TDO_to_BF_TDI' R313-2 # JTAG Data from ACE Term to BF FPGA # # Jumpers around the Base Function FPGA # NET 'CFG_ACE_TDO_to_BF_TDI' JMP72-1 # CFG JTAG Data from ACE to BF NET 'CFG_BF_TDO' JMP71-1 # CFG JTAG Data from BF NET 'CFG_TP_TDI' JMP72-2 # CFG JTAG Data To TP NET 'CFG_TP_TDI' JMP71-2 # CFG JTAG Data To TP # # Jumpers around the Topological Processor FPGA # NET 'CFG_TP_TDI' JMP74-1 # CFG JTAG Data from BF to TP NET 'CFG_TP_TDO' JMP73-1 # CFG JTAG Data from TP NET 'CFG_TP_TDO_to_ACE_TDI' JMP74-2 # CFG JTAG Data To ACE NET 'CFG_TP_TDO_to_ACE_TDI' JMP73-2 # CFG JTAG Data To ACE # # The JTAG nets on the Base Function and Topological Processor # FPGAs are connected in their Bank #0 n2p file. # # # Connect power and ground to buffers U322 and U323. # Include their bypass capacitors C333:C336. NET 'BULK_3V3' U322-14 U323-14 # Power to the buffers NET 'GROUND' U322-7 U323-7 # Ground to the buffers NET 'BULK_3V3' C333-2 C334-2 C335-2 C336-2 # Bypass Caps. NET 'GROUND' C333-1 C334-1 C335-1 C336-1 # Bypass Caps. # # CMX-0 Nets File # # Compact Flash Socket Nets # --------------------------- # # # Original Rev. 10-Aug-2012 # Most Recent Rev. 17-Aug-2013 # # # # This file holds the nets for ALL of the connections to the # Compact Flash Memory Socket. # # This net list file includes the nets to all of the components # that are directly associated with the Compact Flash Memory # Socket, e.g. its bypass capacitors and its resistors to set # default control signal states. # # This net list file includes both ends of the signal nets # that run between the Compact Flash Socket and the System-Ace # chip. # # This net list file includes nets to the following components: # # CF_SK_1 the Compact Flash Memory Socket # R301:R307 CF Mem default signal pull up down resistors # C301,C303 47 nFd Bypass capacitors for the CF Memory Socket # C302,C304 100 nFd Bypass capacitors for the CF Memory Socket # U321 the System-Ace chip # # CF Socket Connections to the System-Ace # Data Lines between System-Ace and Compact Flash bi-directional NET 'CF_DATA_0' CF_SK_1-21 U321-5 # Compact Flash Data 0 NET 'CF_DATA_1' CF_SK_1-22 U321-6 # Compact Flash Data 1 NET 'CF_DATA_2' CF_SK_1-23 U321-8 # Compact Flash Data 2 NET 'CF_DATA_3' CF_SK_1-2 U321-104 # Compact Flash Data 3 NET 'CF_DATA_4' CF_SK_1-3 U321-106 # Compact Flash Data 4 NET 'CF_DATA_5' CF_SK_1-4 U321-113 # Compact Flash Data 5 NET 'CF_DATA_6' CF_SK_1-5 U321-115 # Compact Flash Data 6 NET 'CF_DATA_7' CF_SK_1-6 U321-117 # Compact Flash Data 7 NET 'CF_DATA_8' CF_SK_1-47 U321-7 # Compact Flash Data 8 NET 'CF_DATA_9' CF_SK_1-48 U321-11 # Compact Flash Data 9 NET 'CF_DATA_10' CF_SK_1-49 U321-12 # Compact Flash Data 10 NET 'CF_DATA_11' CF_SK_1-27 U321-105 # Compact Flash Data 11 NET 'CF_DATA_12' CF_SK_1-28 U321-107 # Compact Flash Data 12 NET 'CF_DATA_13' CF_SK_1-29 U321-114 # Compact Flash Data 13 NET 'CF_DATA_14' CF_SK_1-30 U321-116 # Compact Flash Data 14 NET 'CF_DATA_15' CF_SK_1-31 U321-118 # Compact Flash Data 15 # Address lines from System-Ace to the Compact Flash NET 'CF_ADRS_0' CF_SK_1-20 U321-4 # Compact Flash Address 0 NET 'CF_ADRS_1' CF_SK_1-19 U321-142 # Compact Flash Address 1 NET 'CF_ADRS_2' CF_SK_1-18 U321-141 # Compact Flash Address 2 NET 'CF_ADRS_3' CF_SK_1-17 U321-139 # Compact Flash Address 3 NET 'CF_ADRS_4' CF_SK_1-16 U321-137 # Compact Flash Address 4 NET 'CF_ADRS_5' CF_SK_1-15 U321-135 # Compact Flash Address 5 NET 'CF_ADRS_6' CF_SK_1-14 U321-134 # Compact Flash Address 6 NET 'CF_ADRS_7' CF_SK_1-12 U321-132 # Compact Flash Address 7 NET 'CF_ADRS_8' CF_SK_1-11 U321-130 # Compact Flash Address 8 NET 'CF_ADRS_9' CF_SK_1-10 U321-125 # Compact Flash Address 9 NET 'CF_ADRS_10' CF_SK_1-8 U321-121 # Compact Flash Address 10 # Control lines from System-Ace to the Compact Flash NET 'CF_CE1_B' CF_SK_1-7 U321-119 # CF Chip Enable 1 NET 'CF_CE2_B' CF_SK_1-32 U321-138 # CF Chip Enable 2 NET 'CF_REG_B' CF_SK_1-44 U321-3 # CF Register Select NET 'CF_WE_B' CF_SK_1-36 U321-131 # CF Write Enable NET 'CF_OE_B' CF_SK_1-9 U321-123 # CF Output Enable NET 'CF_CD1_B' CF_SK_1-26 U321-103 # CF Card Detect 1 NET 'CF_CD2_B' CF_SK_1-25 U321-13 # CF Card Detect 2 # Control line from the Compact Flash to System-Ace NET 'CF_WAIT_B' CF_SK_1-42 U321-140 # CF Memory Cycle Wait # Using Pull-Up and Pull-Down resistors # set default states to some CF Socket signals # Pull-Up: IORD_B IOWR_B BVD1 BVD2 NET 'CF_IORD_B_PU' CF_SK_1-34 R306-1 # CF IORD_B Pull-Up NET 'CF_IOWR_B_PU' CF_SK_1-35 R305-1 # CF IOWR_B Pull-Up NET 'CF_BVD1_PU' CF_SK_1-46 R301-1 # CF BVD1 Pull-Up NET 'CF_BVD2_PU' CF_SK_1-45 R302-1 # CF BVD2 Pull-Up NET 'BULK_3V3' R301-2 R302-2 R305-2 R306-2 # PU Resistors to 3.3V # Pull-Down: RESET CSEL_B NET 'CF_RESET_PD' CF_SK_1-41 R303-1 # CF Reset Pull-Down NET 'CF_CSEL_B_PD' CF_SK_1-39 R304-1 # CF CSEL_B Pull-Down NET 'GROUND' R303-2 R304-2 # Ground PD Resistors # Tie LOW one signal VS1_B NET 'GROUND' CF_SK_1-33 # Tie LOW VS1_B # # Required Pull-Up Resistor on a Compact Flash # System-Ace pin NET 'ACE_CF_RSVD' U321-133 # Sys-ACE Compact Flash Reserved input Vcch NET 'ACE_CF_RSVD' R307-2 # Must be pulled up externally to Vcch NET 'BULK_3V3' R307-1 # Pull-Up to 3.3 Volt with 5k Ohm # Compact Flash Socket pins that are not connected - left floating: # # Assign single-point nets to them to help check for errors. # # WP pin 24 RDY/BSY pin 37 # VS2_B pin 40 INPACK_B pin 43 # NET 'No_Conn_CF_WP' CF_SK_1-24 # CF Socket No Connect signal WP NET 'No_Conn_CF_RDY_BSY' CF_SK_1-37 # CF Socket No Connect signal RDY/BSY NET 'No_Conn_CF_VS2_B' CF_SK_1-40 # CF Socket No Connect signal VS2_B NET 'No_Conn_CF_INPACK_B' CF_SK_1-43 # CF Socket No Connect signal INPACK_B # Connect the 3.3V power and Ground to the CF Socket NET 'BULK_3V3' CF_SK_1-13 CF_SK_1-38 # 3.3V supply to CF Socket NET 'GROUND' CF_SK_1-1 CF_SK_1-50 # CF Socket Grounds # CF Socket bypass capacitors # NET 'BULK_3V3' C301-1 C302-1 C303-1 C304-1 NET 'GROUND' C301-2 C302-2 C303-2 C304-2 # # Ground the 2 Mounting Screw "pins" on the # Compact Flash Memory Card Socket. NET 'GROUND' CF_SK_1-SCRW1 CF_SK_1-SCRW2 # CF Mounting Screws # # CMX-0 Nets File # # VME Bus Interface Chips Nets # ------------------------------- # # # Original Rev. 13-Aug-2012 # Most Recent Rev. 24-Sept-2013 # # # # This file holds the nets for all of the connections involved # with the chips that connect directly to the VME Bus and the # 2.5V <--> 3.3V translator chips for the On-Card-Bus signals. # # That is this file connects the backplane VME bus to the OCB. # # This file holds the nets for all 7 of the Geographic Address lines. # # This file does not include the pins on any of the three FPGAs # that are connected to the OCB. # # This file does not include the nets of the logic that manages # the On-Card-Bus. # # The following components are referenced in this file: # # # U352 74 LVT 16245B Date 15:0 to/from backplane # U355 74 AVCAH 164245 Data 15:0 2.5V to/from 3.3V translation # # U353 74 LVC 16373A Adrs 23:17, Control Signals, Geo-Adrs # Receive from the VME backplane # U356 74 AVCAH 164245 Adrs 23:17, Control Signals, Geo-Adrs # 3.3V to 2.5V translation # # U354 74 LVC 16373A Adrs 16:1 receive from the VME backplane # U357 74 AVCAH 164245 Adrs 16:1 3.3V to 2.5V translation # # U358 74 LVC 38A Drive DTACK_B onto the VME Bus # Two sections used to drive VME DTACK_B # # R351:R357 pull-up resistors for the Geographic Address lines 0:6 # # JMP1:JMP3 Jumpers to control Geographic Address lines 1,2,3 # # C401, .... 47 nFd Bypass capacitors # ...., C428 100 nFd Bypass capacitors # # Data Bus connections OCB to/from backplane VME # ------------------------------------------------- # # Notes about running this Data Bus connection: # # Transceivers: # The 74LVT16245B are connected Side "A" is the On-Card-Bus # Side "B" is towards the VME backplane. # # Translators: # On the 74AVCAH164245 recall that all 4 control pins are # referenced to its Vcca power pin. We want these control # lines to be 2.5V signals thus Vcca is 2.5V and Vccb is 3.3V # So the 74AVCAH164245 Side "A" is the On-Card-Bus and its # Side "B" is towards the VME backplane. # # # For VME READ (CMX card sends out data) # # 74LVT16245B receives data on "A" sends out data on "B" # DIR pin (pins #1 and #24) must be HI # OE_B pin (pins #25 and #48) must be LOW # # 74AVCAH164245 receives data on "A" sends out data on "B" # DIR pins (pins #1 and #24) must be HI # OE_B pins (pins #25 and #48) must be LOW # # For VME WRITE (CMX card receives data) # # 74LVT16245B receives data on "B" sends out data on "A" # DIR pin (pins #1 and #24) must be LOW # OE_B pin (pins #25 and #48) must be LOW # # 74AVCAH164245 receives data on "B" sends out data on "A" # DIR pins (pins #1 and #24) must be LOW # OE_B pins (pins #25 and #48) must be LOW # # When a given CMX card is not participating in a VME # cycles then the control pins will be: # # 74LVT16245B # DIR pin (pins #1 and #24) must be ?? # OE_B pin (pins #25 and #48) must be HI --> Disable the outputs # # 74AVCAH164245 # DIR pins (pin #1 and #24) must be ?? # OE_B pins (pin #25 and #48) must be HI ?? # # Recall that the DIR and OE_B pins on the 74LVT16245B # are 3.3V CMOS inputs. # # VME Data Bus Transceiver Control Pins (3.3V control inputs): NET 'VME_D_BUS_TRNCVR_DIR' U352-1 U352-24 # VME Data Transceiver # Direction NET 'VME_D_BUS_TRNCVR_OE_B' U352-48 U352-25 # VME Data Transceiver # Output-Enable_B # Note that VME_D_BUS_TRNCVR_OE_B comes from U366 in the # Harwired Oversight Logic. This signal starts as # BSPT_VME_D_BUS_TRNCVR_OE_B from the Board Support FPGA. # VME Data Bus Translator Control Pins (2.5V control inputs): NET 'OCB_D_BUS_TRNSLT_DIR' U355-1 U355-24 # VME Data Translator # Direction NET 'OCB_D_BUS_TRNSLT_OE_B' U355-48 U355-25 # VME Data Translator # Output-Enable_B # VME and OCB Data Bus Lines Transceivers and Translators: NET 'VME_D00' U352-23 # Data 00 backplane connection NET 'TRN32_D00' U352-26 U355-23 # Data 00 VME I/F <--> Translator NET 'OCB_D00' U355-26 # Data 00 On_Card_Bus NET 'VME_D01' U352-19 # Data 01 backplane connection NET 'TRN32_D01' U352-30 U355-22 # Data 01 VME I/F <--> Translator NET 'OCB_D01' U355-27 # Data 01 On_Card_Bus NET 'VME_D02' U352-17 # Data 02 backplane connection NET 'TRN32_D02' U352-32 U355-20 # Data 02 VME I/F <--> Translator NET 'OCB_D02' U355-29 # Data 02 On_Card_Bus NET 'VME_D03' U352-13 # Data 03 backplane connection NET 'TRN32_D03' U352-36 U355-19 # Data 03 VME I/F <--> Translator NET 'OCB_D03' U355-30 # Data 03 On_Card_Bus NET 'VME_D04' U352-9 # Data 04 backplane connection NET 'TRN32_D04' U352-40 U355-17 # Data 04 VME I/F <--> Translator NET 'OCB_D04' U355-32 # Data 04 On_Card_Bus NET 'VME_D05' U352-8 # Data 05 backplane connection NET 'TRN32_D05' U352-41 U355-16 # Data 05 VME I/F <--> Translator NET 'OCB_D05' U355-33 # Data 05 On_Card_Bus NET 'VME_D06' U352-3 # Data 06 backplane connection NET 'TRN32_D06' U352-46 U355-14 # Data 06 VME I/F <--> Translator NET 'OCB_D06' U355-35 # Data 06 On_Card_Bus NET 'VME_D07' U352-2 # Data 07 backplane connection NET 'TRN32_D07' U352-47 U355-13 # Data 07 VME I/F <--> Translator NET 'OCB_D07' U355-36 # Data 07 On_Card_Bus NET 'VME_D08' U352-22 # Data 08 backplane connection NET 'TRN32_D08' U352-27 U355-12 # Data 08 VME I/F <--> Translator NET 'OCB_D08' U355-37 # Data 08 On_Card_Bus NET 'VME_D09' U352-20 # Data 09 backplane connection NET 'TRN32_D09' U352-29 U355-11 # Data 09 VME I/F <--> Translator NET 'OCB_D09' U355-38 # Data 09 On_Card_Bus NET 'VME_D10' U352-16 # Data 10 backplane connection NET 'TRN32_D10' U352-33 U355-9 # Data 10 VME I/F <--> Translator NET 'OCB_D10' U355-40 # Data 10 On_Card_Bus NET 'VME_D11' U352-14 # Data 11 backplane connection NET 'TRN32_D11' U352-35 U355-8 # Data 11 VME I/F <--> Translator NET 'OCB_D11' U355-41 # Data 11 On_Card_Bus NET 'VME_D12' U352-12 # Data 12 backplane connection NET 'TRN32_D12' U352-37 U355-6 # Data 12 VME I/F <--> Translator NET 'OCB_D12' U355-43 # Data 12 On_Card_Bus NET 'VME_D13' U352-11 # Data 13 backplane connection NET 'TRN32_D13' U352-38 U355-5 # Data 13 VME I/F <--> Translator NET 'OCB_D13' U355-44 # Data 13 On_Card_Bus NET 'VME_D14' U352-6 # Data 14 backplane connection NET 'TRN32_D14' U352-43 U355-3 # Data 14 VME I/F <--> Translator NET 'OCB_D14' U355-46 # Data 14 On_Card_Bus NET 'VME_D15' U352-5 # Data 15 backplane connection NET 'TRN32_D15' U352-44 U355-2 # Data 15 VME I/F <--> Translator NET 'OCB_D15' U355-47 # Data 15 On_Card_Bus # Address Bus connections VME Address to the OCB # ------------------------------------------------ # # Notes about the Address Bus connection: # # The 23 Address lines are received by (and optionally latched by) # type 74 LVC 16373A chips. These run on 3.3V power and can work # with the 5V VME bus signals. # # The 23 Address lines are then translated to 2.5V CMOS signals # by type 74 AVCAH 164245 translators. # # # The 74LVC16373A are connected Side "A" is the On-Card-Bus # Side "B" is towards the VME backplane. # # The 74AVCAH164245 Side "A" is the On-Card-Bus # Side "B" is towards the VME backplane. # # # These Address lines are received by 74LVC16373A # # The output pins on the 74LVC16373A must always be enabled # so its OE_B pins, i.e. pins #1 and #24, are held Low. # # The latching function in the 74LVC16373A must either be # held transparent by keeping its LE pins, i.e. pins #25 # and #48, held HI or these LE pins must be controled by # logic on the CMX card, e.g. in the Board Support FPGA. # Recall that the LE pins are 3.3V CMOS inputs. # # These Address lines must always be driven towards the On-Card-Bus # so the 74AVCAH164245 must be setup # # The output pins of the 74AVCAH164245 must always be enabled, # so the OE_B pins, i.e. pins #25 and #48, are held Low. # # The direction of the 74AVCAH164245 must always be towards # the OCB, i.e. from B to A, so the DIR pins, pins #1 and #24, # are held Low. # # # Recall that the LE and OE_B pins on the 74LVC16373A # receiver latch are 3.3V CMOS inputs. # # VME Address Receiver-Latch Control Pins (3.3V control inputs): NET 'VME_ADRS_RECVR_LE' U353-25 U354-48 U354-25 # VME Address Receiver # Latch_Enable NET 'VME_ADRS_AND_CTRL_RECVR_OE_B' U353-24 U354-1 U354-24 # VME Address Receiver # Output-Enable_B # VME Address Bus Translator Control Pins (2.5V control inputs): NET 'OCB_ADRS_AND_CTRL_TRNSLT_DIR' U356-24 U357-1 U357-24 # VME Address Translator # Direction NET 'OCB_ADRS_AND_CTRL_TRNSLT_OE_B' U356-25 U357-48 U357-25 # VME Address Translator # Output-Enable_B # Note that OCB_ADRS_AND_CTRL_TRNSLT_OE_B comes from U366 # in the Harwired Oversight Logic. This signal starts as # BSPT_OCB_ADRS_AND_CTRL_TRNSLT_OE_B from the Board Support FPGA. # VME Address Bus Receiver-Latch and Translator NET 'VME_A23' U353-23 # Adrs 23 backplane connection NET 'TRN32_A23' U353-26 U356-23 # Adrs 23 VME I/F --> Translator NET 'OCB_A23' U356-26 # Adrs 23 On_Card_Bus NET 'VME_A22' U353-22 # Adrs 22 backplane connection NET 'TRN32_A22' U353-27 U356-22 # Adrs 22 VME I/F --> Translator NET 'OCB_A22' U356-27 # Adrs 22 On_Card_Bus NET 'VME_A21' U353-20 # Adrs 21 backplane connection NET 'TRN32_A21' U353-29 U356-20 # Adrs 21 VME I/F --> Translator NET 'OCB_A21' U356-29 # Adrs 21 On_Card_Bus NET 'VME_A20' U353-19 # Adrs 20 backplane connection NET 'TRN32_A20' U353-30 U356-19 # Adrs 20 VME I/F --> Translator NET 'OCB_A20' U356-30 # Adrs 20 On_Card_Bus NET 'VME_A19' U353-17 # Adrs 19 backplane connection NET 'TRN32_A19' U353-32 U356-17 # Adrs 19 VME I/F --> Translator NET 'OCB_A19' U356-32 # Adrs 19 On_Card_Bus NET 'VME_A18' U353-16 # Adrs 18 backplane connection NET 'TRN32_A18' U353-33 U356-16 # Adrs 18 VME I/F --> Translator NET 'OCB_A18' U356-33 # Adrs 18 On_Card_Bus NET 'VME_A17' U353-14 # Adrs 17 backplane connection NET 'TRN32_A17' U353-35 U356-14 # Adrs 17 VME I/F --> Translator NET 'OCB_A17' U356-35 # Adrs 17 On_Card_Bus NET 'VME_A16' U354-23 # Adrs 16 backplane connection NET 'TRN32_A16' U354-26 U357-23 # Adrs 16 VME I/F --> Translator NET 'OCB_A16' U357-26 # Adrs 16 On_Card_Bus NET 'VME_A15' U354-22 # Adrs 15 backplane connection NET 'TRN32_A15' U354-27 U357-22 # Adrs 15 VME I/F --> Translator NET 'OCB_A15' U357-27 # Adrs 15 On_Card_Bus NET 'VME_A14' U354-20 # Adrs 14 backplane connection NET 'TRN32_A14' U354-29 U357-20 # Adrs 14 VME I/F --> Translator NET 'OCB_A14' U357-29 # Adrs 14 On_Card_Bus NET 'VME_A13' U354-16 # Adrs 13 backplane connection NET 'TRN32_A13' U354-33 U357-19 # Adrs 13 VME I/F --> Translator NET 'OCB_A13' U357-30 # Adrs 13 On_Card_Bus NET 'VME_A12' U354-14 # Adrs 12 backplane connection NET 'TRN32_A12' U354-35 U357-17 # Adrs 12 VME I/F --> Translator NET 'OCB_A12' U357-32 # Adrs 12 On_Card_Bus NET 'VME_A11' U354-12 # Adrs 11 backplane connection NET 'TRN32_A11' U354-37 U357-16 # Adrs 11 VME I/F --> Translator NET 'OCB_A11' U357-33 # Adrs 11 On_Card_Bus NET 'VME_A10' U354-11 # Adrs 10 backplane connection NET 'TRN32_A10' U354-38 U357-14 # Adrs 10 VME I/F --> Translator NET 'OCB_A10' U357-35 # Adrs 10 On_Card_Bus NET 'VME_A09' U354-6 # Adrs 09 backplane connection NET 'TRN32_A09' U354-43 U357-13 # Adrs 09 VME I/F --> Translator NET 'OCB_A09' U357-36 # Adrs 09 On_Card_Bus NET 'VME_A08' U354-5 # Adrs 08 backplane connection NET 'TRN32_A08' U354-44 U357-12 # Adrs 08 VME I/F --> Translator NET 'OCB_A08' U357-37 # Adrs 08 On_Card_Bus NET 'VME_A07' U354-17 # Adrs 07 backplane connection NET 'TRN32_A07' U354-32 U357-11 # Adrs 07 VME I/F --> Translator NET 'OCB_A07' U357-38 # Adrs 07 On_Card_Bus NET 'VME_A06' U354-19 # Adrs 06 backplane connection NET 'TRN32_A06' U354-30 U357-9 # Adrs 06 VME I/F --> Translator NET 'OCB_A06' U357-40 # Adrs 06 On_Card_Bus NET 'VME_A05' U354-13 # Adrs 05 backplane connection NET 'TRN32_A05' U354-36 U357-8 # Adrs 05 VME I/F --> Translator NET 'OCB_A05' U357-41 # Adrs 05 On_Card_Bus NET 'VME_A04' U354-8 # Adrs 04 backplane connection NET 'TRN32_A04' U354-41 U357-6 # Adrs 04 VME I/F --> Translator NET 'OCB_A04' U357-43 # Adrs 04 On_Card_Bus NET 'VME_A03' U354-9 # Adrs 03 backplane connection NET 'TRN32_A03' U354-40 U357-5 # Adrs 03 VME I/F --> Translator NET 'OCB_A03' U357-44 # Adrs 03 On_Card_Bus NET 'VME_A02' U354-3 # Adrs 02 backplane connection NET 'TRN32_A02' U354-46 U357-3 # Adrs 02 VME I/F --> Translator NET 'OCB_A02' U357-46 # Adrs 02 On_Card_Bus NET 'VME_A01' U354-2 # Adrs 01 backplane connection NET 'TRN32_A01' U354-47 U357-2 # Adrs 01 VME I/F --> Translator NET 'OCB_A01' U357-47 # Adrs 01 On_Card_Bus # Control Signals and Geographic Address VME Bus to the OCB # ----------------------------------------------------------- # # Notes about the Control Signals and Geographic Address lines # from the Backplane VME-- Bus # # The following Control Signals and Geographic Address # lines are received by one half of a 74 LVC 16373A # # The output pins on this half of the 74LVC16373A # must always be enabled so its OE_B pin, i.e. pin #1, # is held Low. # # This half of the 74LVC16373A must always be # transparent so its LE pin, i.e. pin #48, is held HI. # Recall that the LE pins are 3.3V CMOS inputs. # # These Control Signals and Goegraphic Address lines # must always be driven towards the On-Card-Bus so # the 74 AVCAH 164245 must be setup # # The output pins on this half of the 74AVCAH164245 # must always be enabled, so the OE_B pin, i.e. pin #48, # is held Low. # # The direction of this half of the 74AVCAH164245 # must always be towards the OCB, i.e. from B to A, # so the DIR pin, pin #1, is held Low # # # Recall that the LE and OE_B pins on the 74LVC16373A # receiver latch are 3.3V CMOS inputs. # # Unused sections in U353 74LVC16373A: 12-->37 and 13-->36 # Unused sections in U356 74AVCAH164245: 12-->37 and 13-->36 # # Note that there are Pull-Up resistors on the Geographic Address lines. # # VME Control & Geo_Adrs Signal Receiver-Latch Control Pins (3.3V control inputs): NET 'VME_CTRL_RECVR_LE' U353-48 # VME Control Signal Receiver # Latch_Enable NET 'VME_ADRS_AND_CTRL_RECVR_OE_B' U353-1 # VME Control Signal Receiver # Output-Enable_B # VME Control & Geo_Adrs Signal Translator Control Pins (2.5V control inputs): NET 'OCB_ADRS_AND_CTRL_TRNSLT_DIR' U356-1 # VME Control Signal Translator # Direction NET 'OCB_ADRS_AND_CTRL_TRNSLT_OE_B' U356-48 # VME Control Signal Translator # Output-Enable_B # Note that OCB_ADRS_AND_CTRL_TRNSLT_OE_B comes from U366 # in the Harwired Oversight Logic. This signal starts as # BSPT_OCB_ADRS_AND_CTRL_TRNSLT_OE_B from the Board Support FPGA. # VME Control Signal Receiver-Latch and Translator NET 'VME_DS_B' U353-11 # DS_B backplane connection NET 'TRN32_DS_B' U353-38 U356-11 # DS_B VME I/F --> Translator NET 'OCB_DS_B' U356-38 # OCB_DS_B to the OCB NET 'VME_WRITE_B' U353-9 # WRITE_B backplane connection NET 'TRN32_WRITE_B' U353-40 U356-9 # WRITE_B VME I/F --> Translator NET 'OCB_WRITE_B' U356-40 # OCB_WRITE_B to the OCB NET 'VME_SYS_RESET_B' U353-8 # SYS_RESET_B backplane connection NET 'TRN32_SYS_RESET_B' U353-41 U356-8 # SYS_RESET_B VME I/F --> Translator NET 'OCB_SYS_RESET_B' U356-41 # OCB_SYS_RESET_B to the OCB # VME Geographic Address Receiver-Latch and Translator NET 'VME_GEO_ADRS_4' U353-6 # GEO_ADRS_4 backplane connection NET 'TRN32_GEO_ADRS_4' U353-43 U356-5 # GEO_ADRS_4 VME I/F --> Translator NET 'OCB_GEO_ADRS_4' U356-44 # OCB_GEO_ADRS_4 to the OCB NET 'VME_GEO_ADRS_5' U353-5 # GEO_ADRS_5 backplane connection NET 'TRN32_GEO_ADRS_5' U353-44 U356-3 # GEO_ADRS_5 VME I/F --> Translator NET 'OCB_GEO_ADRS_5' U356-46 # OCB_GEO_ADRS_5 to the OCB NET 'VME_GEO_ADRS_6' U353-3 # GEO_ADRS_6 backplane connection NET 'TRN32_GEO_ADRS_6' U353-46 U356-2 # GEO_ADRS_6 VME I/F --> Translator NET 'OCB_GEO_ADRS_6' U356-47 # OCB_GEO_ADRS_6 to the OCB NET 'VME_GEO_ADRS_0' U353-2 # GEO_ADRS_0 backplane connection NET 'TRN32_GEO_ADRS_0' U353-47 U356-6 # GEO_ADRS_0 VME I/F --> Translator NET 'OCB_GEO_ADRS_0' U356-43 # OCB_GEO_ADRS_0 to the OCB # Pull-Up Resistors on the 4 Geographic Address Lines. # Pull these lines up to 3.3V with 10k Ohm. NET 'VME_GEO_ADRS_0' R351-1 # GEO_ADRS_0 pull up NET 'VME_GEO_ADRS_4' R354-1 # GEO_ADRS_0 pull up NET 'VME_GEO_ADRS_5' R353-1 # GEO_ADRS_0 pull up NET 'VME_GEO_ADRS_6' R352-1 # GEO_ADRS_0 pull up NET 'BULK_3V3' R351-2 R353-2 # Pull-Up to 3.3 Volts NET 'BULK_3V3' R352-2 R354-2 # Pull-Up to 3.3 Volts # Control Signal from the OCB to the VME Bus # -------------------------------------------- # # Notes about DTACK_B the one Control Signal that flows # from the On_Card_Bus to the VME Bus. # # The VME_DTACK_B signal comes from a 3.3V output pin # on the Board Support FPGA that has the net name: # BSPT_SEND_VME_DTACK_B # # U358 a 74LVC38A open drain driver puts the # VME_DTACK_B signal onto the VME Bus. # # Note that the VME_DTACK_B signal is qualified by # Hardwired Oversight Logic signal ALLOW_BUSSED_IO # before DTACK_B goes to the VME Bus. # # This gating of DTACK_B is included in the Hardwired # Oversight Logic net list section. # # Note that U358 the 74LVC38A is powered by 3.3 Volts. # # Note that both the original 4,5,6 section of U358 # and now the 1,2,3 section are used to drive the # VME DTACK_B signal onto the backplane bus. NET 'VME_DTACK_B' U358-3 # VME_DTACK_B to the VME Bus. NET 'VME_DTACK_B' U358-6 # VME_DTACK_B to the VME Bus. # Geographic Address Lines 1,2,3: # -------------------------------- # # 4 of the 7 Geographic Address lines come from the backplane. # The backplane Geographic Address lines are 0,4,5,6. The reception # of these nets from the backplane was described above. # # The remaining 3 Geographic Address lines 1,2,3 are set by # jumpers JMP1 through JMP3 on the CMX card. The nets for # these 3 Geographic Address lines are defined here because # they are part of the On-Card-Bus. The jumpers JMP1:JMP3 # allow you to either ground or pull up to 2.5V any combination # of Geographic Address lines 1,2,3. # # Geographic Address 1 Install JMP1 to pull Low. NET 'OCB_GEO_ADRS_1' R355-2 JMP1-2 # OCB_GEO_ADRS_1 NET 'BULK_2V5' R355-1 # Geo Adrs 1 pull-up 2.5V NET 'GROUND' JMP1-1 # Geo Adrs 1 Ground connection # Geographic Address 2 Install JMP2 to pull Low. NET 'OCB_GEO_ADRS_2' R356-2 JMP2-2 # OCB_GEO_ADRS_2 NET 'BULK_2V5' R356-1 # Geo Adrs 2 pull-up 2.5V NET 'GROUND' JMP2-1 # Geo Adrs 2 Ground connection # Geographic Address 3 Install JMP3 to pull Low. NET 'OCB_GEO_ADRS_3' R357-2 JMP3-2 # OCB_GEO_ADRS_3 NET 'BULK_2V5' R357-1 # Geo Adrs 3 pull-up 2.5V NET 'GROUND' JMP3-1 # Geo Adrs 3 Ground connection # Power Connections and ByPass Capacitor Connections for the VME I/F # Power and ByPass for U352 74LVT16245B all power is BULK_3V3 NET 'BULK_3V3' U352-7 U352-18 # U352 3.3V power connections NET 'BULK_3V3' U352-31 U352-42 # U352 3.3V power connections NET 'GROUND' U352-4 U352-10 # U352 Ground connections NET 'GROUND' U352-15 U352-21 # U352 Ground connections NET 'GROUND' U352-28 U352-34 # U352 Ground connections NET 'GROUND' U352-39 U352-45 # U352 Ground connections NET 'BULK_3V3' C401-2 C402-1 # ByPass Cap 3.3V power connections NET 'BULK_3V3' C403-1 C404-2 # ByPass Cap 3.3V power connections NET 'GROUND' C401-1 C402-2 # ByPass Cap Ground connections NET 'GROUND' C403-2 C404-1 # ByPass Cap Ground connections # Power and ByPass for U353 74LVC16373A all power is BULK_3V3 NET 'BULK_3V3' U353-7 U353-18 # U353 3.3V power connections NET 'BULK_3V3' U353-31 U353-42 # U353 3.3V power connections NET 'GROUND' U353-4 U353-10 # U353 Ground connections NET 'GROUND' U353-15 U353-21 # U353 Ground connections NET 'GROUND' U353-28 U353-34 # U353 Ground connections NET 'GROUND' U353-39 U353-45 # U353 Ground connections NET 'BULK_3V3' C405-2 C406-1 # ByPass Cap 3.3V power connections NET 'BULK_3V3' C407-1 C408-2 # ByPass Cap 3.3V power connections NET 'GROUND' C405-1 C406-2 # ByPass Cap Ground connections NET 'GROUND' C407-2 C408-1 # ByPass Cap Ground connections # Power and ByPass for U354 74LVC16373A all power is BULK_3V3 NET 'BULK_3V3' U354-7 U354-18 # U354 3.3V power connections NET 'BULK_3V3' U354-31 U354-42 # U354 3.3V power connections NET 'GROUND' U354-4 U354-10 # U354 Ground connections NET 'GROUND' U354-15 U354-21 # U354 Ground connections NET 'GROUND' U354-28 U354-34 # U354 Ground connections NET 'GROUND' U354-39 U354-45 # U354 Ground connections NET 'BULK_3V3' C409-2 C410-1 # ByPass Cap 3.3V power connections NET 'BULK_3V3' C411-1 C412-2 # ByPass Cap 3.3V power connections NET 'GROUND' C409-1 C410-2 # ByPass Cap Ground connections NET 'GROUND' C411-2 C412-1 # ByPass Cap Ground connections # Power and ByPass for U355 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U355-7 U355-18 # U355 3.3V Vccb power NET 'BULK_2V5' U355-31 U355-42 # U355 2.5V Vcca power NET 'GROUND' U355-4 U355-10 # U355 Ground connections NET 'GROUND' U355-15 U355-21 # U355 Ground connections NET 'GROUND' U355-28 U355-34 # U355 Ground connections NET 'GROUND' U355-39 U355-45 # U355 Ground connections NET 'BULK_3V3' C414-1 C415-1 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C413-2 C416-2 # ByPass Cap 2.5V Vcca power NET 'GROUND' C414-2 C415-2 # ByPass Cap Ground connections NET 'GROUND' C413-1 C416-1 # ByPass Cap Ground connections # Power and ByPass for U356 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U356-7 U356-18 # U356 3.3V Vccb power NET 'BULK_2V5' U356-31 U356-42 # U356 2.5V Vcca power NET 'GROUND' U356-4 U356-10 # U356 Ground connections NET 'GROUND' U356-15 U356-21 # U356 Ground connections NET 'GROUND' U356-28 U356-34 # U356 Ground connections NET 'GROUND' U356-39 U356-45 # U356 Ground connections NET 'BULK_3V3' C418-1 C419-1 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C417-2 C420-2 # ByPass Cap 2.5V Vcca power NET 'GROUND' C418-2 C419-2 # ByPass Cap Ground connections NET 'GROUND' C417-1 C420-1 # ByPass Cap Ground connections # Power and ByPass for U357 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U357-7 U357-18 # U357 3.3V Vccb power NET 'BULK_2V5' U357-31 U357-42 # U357 2.5V Vcca power NET 'GROUND' U357-4 U357-10 # U357 Ground connections NET 'GROUND' U357-15 U357-21 # U357 Ground connections NET 'GROUND' U357-28 U357-34 # U357 Ground connections NET 'GROUND' U357-39 U357-45 # U357 Ground connections NET 'BULK_3V3' C422-1 C423-1 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C421-2 C424-2 # ByPass Cap 2.5V Vcca power NET 'GROUND' C422-2 C423-2 # ByPass Cap Ground connections NET 'GROUND' C421-1 C424-1 # ByPass Cap Ground connections # Power and ByPass for U358 74F38 # is included in the Hardwired Oversight Logic # nets file. U358 is both part of the VME IF # and is part of the Hardwired Oversight Logic. # # CMX-0 Nets File # # SFP "Slow" Optical Connectors Nets # ------------------------------------- # # # Original Rev. 14-Aug-2012 # Rev. 5-Dec-2012 # Rev: 16-Jan-2013 Adopt NET naming convention to pre-pend # "No_Conn_" for unused pins. Rename G-link # signal nets to start with "BF_" # 26-Apr-2013 Add nets for: the SFP Receiver power filters, # and the Received Signal Lost pull-up # 9-May-2013 Swap some power filter capacitor pins. # 16-May-2013 Swap some receiver and transmitters pins # DIR<->CMP to facilitate routing. # Most Recent Rev: 13-Sept-2013 Swap SFP Transmitters signals from TP Data & ROI # DIR<->CMP to facilitate routing. # # # # # This file holds the nets for all 4 of the SFP "slow" optical # connectors. # # # NOTE: We may now end up using both the Receiver and # Transmitter section of some or all of the SFP # optical components. This change (from using # only the transmitter) happened in the prototype # review in February 2013 when we were requested # to provide S-Link compatable output on the CMX. # # # Note that on the CMX card, the SFP transmitter is used for the G-Link # DAQ and RIO readout (possibly S-Link format readout if that is used) # and that the SFP Receiver (if used at all) will be used for S-Link # control signal input. # # This file includes the ground and power supply pins to the # SFP connectors and the associated bypass capacitors, power # filter chokes, and the pull-up and receiver termination resistors. # # # The net list file references the following components: # # SFP1 Base Function DAQ SFP Optical Output # SFP2 Base Function RIO SFP Optical Output # # SFP3 Topo-Processor DAQ SFP Optical Output # SFP4 Topo-Processor RIO SFP Optical Output # # R? R? Pull-Up and Termination Resistors # # # C746, ... 47 nFd Bypass capacitors for SFP power # C756, ... 100 nFd Bypass capacitors for SFP power # C766, .... 33 uFd Bypass capacitors for SFP power # # C776, ... 47 nFd Bypass capacitors for SFP Transmitter power # C786, ... 100 nFd Bypass capacitors for SFP Transmitter power # C796, .... 33 uFd Bypass capacitors for SFP Transmitter power # # C736, ... 47 nFd Bypass capacitors for SFP Receiver power # C746, ... 100 nFd Bypass capacitors for SFP Receiver power # C756, .... 33 uFd Bypass capacitors for SFP Receiver power # # L26, ... 4.7 uH Power Chokes for SFP Transmitter power # L36, ... 4.7 uH Power Chokes for SFP Receiver power # # # SFP1 Base Function DAQ Data Transmitter # ---- # NOTE: Flipped Receiver Data DIR<->CMP # NET 'GROUND' SFP1-1 # SFP1 Transmitter Ground NET 'SFP1_TX_FAULT' SFP1-2 # SFP1 Transmitter Fault NET 'SFP1_TX_DISABLE' SFP1-3 # SFP1 Transmitter Disable NET 'SFP1_MOD_SER_DATA' SFP1-4 # SFP1 2 Wire Serial Data MOD-DEF2 NET 'SFP1_MOD_SER_CLK' SFP1-5 # SFP1 2 Wire Serial Clock MOD-DEF1 NET 'SFP1_MOD_PRESENT' SFP1-6 # SFP1 Module Present ->GND MOD-DEF0 NET 'No_Conn_SFP1_PIN_7' SFP1-7 # SFP1 No Connection NET 'SFP1_RX_LOST' SFP1-8 # SFP1 Receiver Signal Lost NET 'GROUND' SFP1-9 # SFP1 Receiver Ground NET 'GROUND' SFP1-10 # SFP1 Receiver Ground NET 'GROUND' SFP1-11 # SFP1 Receiver Ground NET 'SFP1_RD_DIR' SFP1-12 # SFP1 Receiver Data Complement Out NET 'SFP1_RD_CMP' SFP1-13 # SFP1 Receiver Data Direct Out NET 'GROUND' SFP1-14 # SFP1 Receiver Ground NET 'SFP1_RECVR_3V3' SFP1-15 # SFP1 Receiver Power 3.3V NET 'SFP1_TRMTR_3V3' SFP1-16 # SFP1 Transmitter Power 3.3V NET 'GROUND' SFP1-17 # SFP1 Transmitter Ground NET 'BF_DAQ_DATA_OUT_DIR' SFP1-18 # SFP1 Transmitter Data Direct In NET 'BF_DAQ_DATA_OUT_CMP' SFP1-19 # SFP1 Transmitter Data Complement In NET 'GROUND' SFP1-20 # SFP1 Transmitter Ground # # SFP2 Base Function ROI Data Transmitter # ---- # NOTE: Flipped Receiver Data DIR<->CMP # NET 'GROUND' SFP2-1 # SFP2 Transmitter Ground NET 'SFP2_TX_FAULT' SFP2-2 # SFP2 Transmitter Fault NET 'SFP2_TX_DISABLE' SFP2-3 # SFP2 Transmitter Disable NET 'SFP2_MOD_SER_DATA' SFP2-4 # SFP2 2 Wire Serial Data MOD-DEF2 NET 'SFP2_MOD_SER_CLK' SFP2-5 # SFP2 2 Wire Serial Clock MOD-DEF1 NET 'SFP2_MOD_PRESENT' SFP2-6 # SFP2 Module Present ->GND MOD-DEF0 NET 'No_Conn_SFP2_PIN_7' SFP2-7 # SFP2 No Connection NET 'SFP2_RX_LOST' SFP2-8 # SFP2 Receiver Signal Lost NET 'GROUND' SFP2-9 # SFP2 Receiver Ground NET 'GROUND' SFP2-10 # SFP2 Receiver Ground NET 'GROUND' SFP2-11 # SFP2 Receiver Ground NET 'SFP2_RD_DIR' SFP2-12 # SFP2 Receiver Data Complement Out NET 'SFP2_RD_CMP' SFP2-13 # SFP2 Receiver Data Direct Out NET 'GROUND' SFP2-14 # SFP2 Receiver Ground NET 'SFP2_RECVR_3V3' SFP2-15 # SFP2 Receiver Power 3.3V NET 'SFP2_TRMTR_3V3' SFP2-16 # SFP2 Transmitter Power 3.3V NET 'GROUND' SFP2-17 # SFP2 Transmitter Ground NET 'BF_ROI_DATA_OUT_DIR' SFP2-18 # SFP2 Transmitter Data Direct In NET 'BF_ROI_DATA_OUT_CMP' SFP2-19 # SFP2 Transmitter Data Complement In NET 'GROUND' SFP2-20 # SFP2 Transmitter Ground # # SFP3 Topological Processor DAQ Data Transmitter # NET 'GROUND' SFP3-1 # SFP3 Transmitter Ground NET 'SFP3_TX_FAULT' SFP3-2 # SFP3 Transmitter Fault NET 'SFP3_TX_DISABLE' SFP3-3 # SFP3 Transmitter Disable NET 'SFP3_MOD_SER_DATA' SFP3-4 # SFP3 2 Wire Serial Data MOD-DEF2 NET 'SFP3_MOD_SER_CLK' SFP3-5 # SFP3 2 Wire Serial Clock MOD-DEF1 NET 'SFP3_MOD_PRESENT' SFP3-6 # SFP3 Module Present ->GND MOD-DEF0 NET 'No_Conn_SFP3_PIN_7' SFP3-7 # SFP3 No Connection NET 'SFP3_RX_LOST' SFP3-8 # SFP3 Receiver Signal Lost NET 'GROUND' SFP3-9 # SFP3 Receiver Ground NET 'GROUND' SFP3-10 # SFP3 Receiver Ground NET 'GROUND' SFP3-11 # SFP3 Receiver Ground NET 'SFP3_RD_CMP' SFP3-12 # SFP3 Receiver Data Complement Out NET 'SFP3_RD_DIR' SFP3-13 # SFP3 Receiver Data Direct Out NET 'GROUND' SFP3-14 # SFP3 Receiver Ground NET 'SFP3_RECVR_3V3' SFP3-15 # SFP3 Receiver Power 3.3V NET 'SFP3_TRMTR_3V3' SFP3-16 # SFP3 Transmitter Power 3.3V NET 'GROUND' SFP3-17 # SFP3 Transmitter Ground NET 'TP_DAQ_DATA_OUT_DIR' SFP3-19 # SFP3 Transmitter Data Complement In NET 'TP_DAQ_DATA_OUT_CMP' SFP3-18 # SFP3 Transmitter Data Direct In # NOTE: DIR <--> CMP Swap NET 'GROUND' SFP3-20 # SFP3 Transmitter Ground # # SFP4 Topological Processor ROI Data Transmitter # NET 'GROUND' SFP4-1 # SFP4 Transmitter Ground NET 'SFP4_TX_FAULT' SFP4-2 # SFP4 Transmitter Fault NET 'SFP4_TX_DISABLE' SFP4-3 # SFP4 Transmitter Disable NET 'SFP4_MOD_SER_DATA' SFP4-4 # SFP4 2 Wire Serial Data MOD-DEF2 NET 'SFP4_MOD_SER_CLK' SFP4-5 # SFP4 2 Wire Serial Clock MOD-DEF1 NET 'SFP4_MOD_PRESENT' SFP4-6 # SFP4 Module Present ->GND MOD-DEF0 NET 'No_Conn_SFP4_PIN_7' SFP4-7 # SFP4 No Connection NET 'SFP4_RX_LOST' SFP4-8 # SFP4 Receiver Signal Lost NET 'GROUND' SFP4-9 # SFP4 Receiver Ground NET 'GROUND' SFP4-10 # SFP4 Receiver Ground NET 'GROUND' SFP4-11 # SFP4 Receiver Ground NET 'SFP4_RD_CMP' SFP4-12 # SFP4 Receiver Data Complement Out NET 'SFP4_RD_DIR' SFP4-13 # SFP4 Receiver Data Direct Out NET 'GROUND' SFP4-14 # SFP4 Receiver Ground NET 'SFP4_RECVR_3V3' SFP4-15 # SFP4 Receiver Power 3.3V NET 'SFP4_TRMTR_3V3' SFP4-16 # SFP4 Transmitter Power 3.3V NET 'GROUND' SFP4-17 # SFP4 Transmitter Ground NET 'TP_ROI_DATA_OUT_DIR' SFP4-19 # SFP4 Transmitter Data Complement In NET 'TP_ROI_DATA_OUT_CMP' SFP4-18 # SFP4 Transmitter Data Direct In # NOTE: DIR <--> CMP Swap NET 'GROUND' SFP4-20 # SFP4 Transmitter Ground # # Pull-Up Resistors on SFP: TX_FAULT SER_DATA SER_CLK and # MOD_PRESENT control-monitor signals. These are normal 3.3V # signals to/from the BSPT FPGA I/O Bank #3. # NET 'SFP1_TX_FAULT' R766-2 # SFP1 Trans Fault Pull-Up Resistor NET 'SFP1_MOD_SER_DATA' R786-2 # SFP1 2 Wire Data Pull-Up Resistor NET 'SFP1_MOD_SER_CLK' R756-2 # SFP1 2 Wire Clock Pull-Up Resistor NET 'SFP1_MOD_PRESENT' R776-2 # SFP1 Module Present Pull-Up Resistor NET 'SFP2_TX_FAULT' R767-2 # SFP2 Trans Fault Pull-Up Resistor NET 'SFP2_MOD_SER_DATA' R787-2 # SFP2 2 Wire Data Pull-Up Resistor NET 'SFP2_MOD_SER_CLK' R757-2 # SFP2 2 Wire Clock Pull-Up Resistor NET 'SFP2_MOD_PRESENT' R777-2 # SFP2 Module Present Pull-Up Resistor NET 'SFP3_TX_FAULT' R768-2 # SFP3 Trans Fault Pull-Up Resistor NET 'SFP3_MOD_SER_DATA' R788-2 # SFP3 2 Wire Data Pull-Up Resistor NET 'SFP3_MOD_SER_CLK' R758-2 # SFP3 2 Wire Clock Pull-Up Resistor NET 'SFP3_MOD_PRESENT' R778-2 # SFP3 Module Present Pull-Up Resistor NET 'SFP4_TX_FAULT' R769-2 # SFP4 Trans Fault Pull-Up Resistor NET 'SFP4_MOD_SER_DATA' R789-2 # SFP4 2 Wire Data Pull-Up Resistor NET 'SFP4_MOD_SER_CLK' R759-2 # SFP4 2 Wire Clock Pull-Up Resistor NET 'SFP4_MOD_PRESENT' R779-2 # SFP4 Module Present Pull-Up Resistor NET 'BULK_3V3' R756-1 R766-1 R776-1 R786-1 # BULK_3V3 Pull-Up NET 'BULK_3V3' R757-1 R767-1 R777-1 R787-1 # BULK_3V3 Pull-Up NET 'BULK_3V3' R758-1 R768-1 R778-1 R788-1 # BULK_3V3 Pull-Up NET 'BULK_3V3' R759-1 R769-1 R779-1 R789-1 # BULK_3V3 Pull-Up # # Pull-Up Resistor on SFP RX_LOST control-monitor signal. # This is a special 2.5V signal to/from the BSPT FPGA I/O Bank #2. # NET 'SFP1_RX_LOST' R696-2 # 2.5V Pull-Up on Receiver Signal Lost NET 'SFP2_RX_LOST' R697-2 # 2.5V Pull-Up on Receiver Signal Lost NET 'SFP3_RX_LOST' R698-2 # 2.5V Pull-Up on Receiver Signal Lost NET 'SFP4_RX_LOST' R699-2 # 2.5V Pull-Up on Receiver Signal Lost NET 'BULK_2V5' R696-1 R697-1 R698-1 R699-1 # BULK_2V5 Pull-Up # # Power Filters in the 3.3 Volt Power for the SFP Components # # NOTE: We may now end up using both the Receiver and # Transmitter section of some or all of the SFP # optical components. # # The input to each SFP's dual power filter consists # of 3 capacitors, e.g. C746, C756, C766 for SFP1. # # The filter for the Transmitter section, Vcc pin 16, # consists of a series inductor and 3 capacitors to # ground. For the Transmitter section of SFP1 these # components are: L26, C776, C786, C796. # # The filter for the Receiver section, Vcc pin 15, # consists of a series inductor and 3 capacitors to # ground. For the Receiver section of SFP1 these # components are: L36, C636, C646, C656 # # I don't know which Vcc power supply pin on the # SFP powers its monitoring-control functions. # # # Power Connections to SFP1 # ------ # # List the 3.3 Volt power filter connections to SFP1 # SFP1 Power Filter Input Capacitors NET 'BULK_3V3' L26-2 L36-2 C746-1 C756-1 C766-1 NET 'GROUND' C746-2 C756-2 C766-2 # SFP1 Transmitter Power Filter NET 'SFP1_TRMTR_3V3' L26-1 C776-1 C786-2 C796-1 NET 'GROUND' C776-2 C786-1 C796-2 # SFP1 Receiver Power Filter NET 'SFP1_RECVR_3V3' L36-1 C636-1 C646-2 C656-1 NET 'GROUND' C636-2 C646-1 C656-2 # Power Connections to SFP2 # ------ # # List the 3.3 Volt power filter connections to SFP2 # SFP2 Power Filter Input Capacitors NET 'BULK_3V3' L27-2 L37-2 C747-1 C757-1 C767-1 NET 'GROUND' C747-2 C757-2 C767-2 # SFP2 Transmitter Power Filter NET 'SFP2_TRMTR_3V3' L27-1 C777-1 C787-2 C797-1 NET 'GROUND' C777-2 C787-1 C797-2 # SFP2 Receiver Power Filter NET 'SFP2_RECVR_3V3' L37-1 C637-1 C647-2 C657-1 NET 'GROUND' C637-2 C647-1 C657-2 # Power Connections to SFP3 # ------ # # List the 3.3 Volt power filter connections to SFP3 NET 'BULK_3V3' L28-2 L38-2 C748-1 C758-1 C768-1 NET 'GROUND' C748-2 C758-2 C768-2 # SFP3 Transmitter Power Filter NET 'SFP3_TRMTR_3V3' L28-1 C778-1 C788-2 C798-1 NET 'GROUND' C778-2 C788-1 C798-2 # SFP3 Receiver Power Filter NET 'SFP3_RECVR_3V3' L38-1 C638-1 C648-2 C658-1 NET 'GROUND' C638-2 C648-1 C658-2 # Power Connections to SFP4 # ------ # # List the 3.3 Volt power filter connections to SFP4 NET 'BULK_3V3' L29-2 L39-2 C749-1 C759-1 C769-1 NET 'GROUND' C749-2 C759-2 C769-2 # SFP4 Transmitter Power Filter NET 'SFP4_TRMTR_3V3' L29-1 C779-1 C789-2 C799-1 NET 'GROUND' C779-2 C789-1 C799-2 # SFP4 Receiver Power Filter NET 'SFP4_RECVR_3V3' L39-1 C639-1 C649-2 C659-1 NET 'GROUND' C639-2 C649-1 C659-2 # # CMX-0 Nets File # # Board Support FPGA - Configuration Nets # ----------------------------------------- # # # Original Rev. 1-Nov-2012 # Most Recent Rev. 4-Apr-2013 # # # # This file holds the nets for all of the connections involved # involved with the Configuration of the Board Support FPGA. # # # The parts referenced in this file include: # # U351 BSPT_FPGA # U359 Configuration PROM for the BSPT_FPGA # # R321 Pullup on the BSPT_FPGA INIT_B # R322 Pullup on the BSPT_FPGA DONE # R323 Pullup on the BSPT_FPGA PROG_B # # JMP4 Allows JTAG to the Config PROM to cause configuration of the BSPT_FPGA # # JMP51:JMP56 Set the BSPT FPGA M2, M1, M0 Configuration signals # # C441:C443 Bypass Capacitors for the BSPT_FPGA Configuration PROM # # # # XCF04SVOG20C Configuration PROM Nets # # This file shows all 20 pins of the Configuration PROM. # NET 'BSPT_CONFIG_DIN' U359-1 U351-W18 # Config PROM Data to the FPGA NET 'No_Conn_CONFIG_PROM_P2' U359-2 # DNC Do Not Connect Pin #2 NET 'BSPT_CONFIG_CCLK' U359-3 U351-Y19 # CCLK from the FPGA ## NET 'CONFIG_PROM_TDI' U359-4 # see the "JTAG_Chain" n2p file ## NET 'JTAG_TMS' U359-5 # see the "JTAG_Chain" n2p file ## NET 'JTAG_TCK' U359-6 # see the "JTAG_Chain" n2p file NET 'CONFIG_PROM_CF_BAR' U359-7 # Config PROM's CF_Bar output pin, # JTAG can cause this pin to pulse # and can tie it to BSPT_FPGA PROG_B. NET 'BSPT_CONFIG_INIT_B' U359-8 U351-Y14 # Config PROM OE/RESET_BAR pin is driven # by INIT_B from the FPGA which pulses # voltage low while the FPGA is clearing # its configuration memory, this # resets the Configuration PROM. NET 'No_Conn_CONFIG_PROM_P9' U359-9 # DNC Do Not Connect Pin #9 NET 'BSPT_CONFIG_DONE' U359-10 U351-W19 # Config PROM CE_bar pin is driven by # the BSPT_FPGA DONE signal. When the # FPGA finishes configuration it drives # the PROM's CE_bar to the voltage hi, i.e. # inactive state. Power down the PROM. NET 'GROUND' U359-11 NET 'No_Conn_CONFIG_PROM_P12' U359-12 # DNC Do Not Connect Pin #12 NET 'CONFIG_PROM_CEO_BAR' U359-13 # PROM CEO_bar pin - No Connection # This pin allows the PROM to pass # CEO to the next device. NET 'No_Conn_CONFIG_PROM_P14' U359-14 # DNC Do Not Connect Pin #14 NET 'No_Conn_CONFIG_PROM_P15' U359-15 # DNC Do Not Connect Pin #15 NET 'No_Conn_CONFIG_PROM_P16' U359-16 # DNC Do Not Connect Pin #16 ## NET 'Config_PROM_TDO' U359-17 # see the "JTAG_Chain" n2p file NET 'BULK_3V3' U359-18 # Config PROM Internal 3.3V NET 'BULK_2V5' U359-19 # Config PROM Output Buf 2.5V NET 'BULK_3V3' U359-20 # Config PROM JTAG Buf 3.3V # # Bypass Capacitors on the Configuration PROM for BSPT_FPGA NET 'BULK_3V3' C441-1 C443-1 # Vcc Int Vcc JTAG 3.3V NET 'BULK_2V5' C442-1 # Vcc Config I/O 2.5V NET 'GROUND' C441-2 C442-2 C443-2 # Bypass Cap Grounds # # Jumper to allow the JTAG Config Instruction to the # Config PROM to cause the Board Support FPGA to Configure. # This is Jumper 4. I.E. Connect the CF_Bar pulse from # the Config PROM to the PROG_B pin on the BSPT FPGA. NET 'CONFIG_PROM_CF_BAR' JMP4-1 # CF_BAR signal from the Config PROM NET 'BSPT_CONFIG_PROG_B' U351-D5 JMP4-2 # PROG_B pin on the BSPT_FPGA # # Pullup Resistors on the BSPT_FPGA Configuration signals NET 'BSPT_CONFIG_INIT_B' R321-1 # Pull up on BSTP Config INIT_B pull to 2.5V NET 'BSPT_CONFIG_DONE' R322-1 # Pull up on BSTP Config DONE pull to 3.3V NET 'BSPT_CONFIG_PROG_B' R323-1 # Pull up on BSTP Config PROG_B pull to 3.3V NET 'BULK_2V5' R321-2 # Pull up to 2.5V NET 'BULK_3V3' R322-2 R323-2 # Pull up to 3.3V # # M2, M1, M0 Configuration Mode Signals for the Board Support FPGA # Set via Jumpers JMP51:JMP56 NET 'BSPT_M2' JMP51-1 JMP52-2 U351-W3 # BSPT M2 Control JMP31-JMP52 NET 'BSPT_M1' JMP53-1 JMP54-2 U351-U4 # BSPT M1 Control JMP33-JMP54 NET 'BSPT_M0' JMP55-1 JMP56-2 U351-V4 # BSPT M0 Control JMP35-JMP56 NET 'GROUND' JMP51-2 JMP53-2 JMP55-2 # Ground the Pull-Down Jumpers NET 'BULK_2V5' JMP52-1 JMP54-1 JMP56-1 # Tie the Pull-Ups to BULK_2V5 # # CMX-0 Nets File # # System-Ace Power and Ground Nets # ----------------------------------- # # # Original Rev. 22-Aug-2012 # Most Recent Rev. 9-May-2012 # # # # This file holds the nets for all of the Power and Ground # connections to the System-Ace chip. This file includes # the power supply bypass capacitors for the System-Ace. # # Recall that the System-Ace will be setup for the 3.3 V # JTAG "Test Interface" connection to the front panel. # This JTAG loop also runs through the JTAG connection to # the TTCDec mezzanine card. This is TSTJTAG. # # Recall also that the Configuration JTAG chain that runs # from the System-Ace to the Board_Support, Base_Function, # and Topological Processor FPGAs is a 2.5 V JTAG string. # This loop is called the CFGJTG. # # Basically: # # 3.3V Vcch supplies the Test JTAG and the Compact Flash ports. # 2.5V Vccl supplies the Configuration JTAG and MPU ports and the core. # # # U321 System-Ace # # C322, C324, C326 47 nFd Bypass capacitors # C321, C323, C325 100 nFd Bypass capacitors # # C328, C330, C332 47 nFd Bypass capacitors # C327, C329, C331 100 nFd Bypass capacitors # # # There are 6 bypass capacitors on the 3.3V supply (3x 47 nFd # and 3x 100 nFd). The 2.5V supply has a similar set of 6 # bypass capacitors. # # # There are a number of pins on the System-Ace that must # be left open - nothing connected to them. These pins are: # # 2, 14, 16, 19, 20, 21, 22, 23, 24, 27, 28, # 29, 30, 31, 32, 34, 36, 38, 40, 71, 74, 79, # 90, 122, 124, 127, 143 # # # System-Ace 3.3 Volt Power Pins VCCH NET 'BULK_3V3' U321-1 U321-17 U321-37 # System-Ace 3.3 V NET 'BULK_3V3' U321-55 U321-73 U321-92 # System-Ace 3.3 V NET 'BULK_3V3' U321-109 U321-128 # System-Ace 3.3 V # System-Ace 2.5 Volt Power Pins VCCL NET 'BULK_2V5' U321-10 U321-15 U321-25 # System-Ace 2.5 V NET 'BULK_2V5' U321-57 U321-84 U321-94 # System-Ace 2.5 V NET 'BULK_2V5' U321-99 U321-126 # System-Ace 2.5 V # System-Ace Ground Pins NET 'GROUND' U321-9 U321-18 U321-26 # System-Ace Ground Pins NET 'GROUND' U321-35 U321-46 U321-54 # System-Ace Ground Pins NET 'GROUND' U321-64 U321-75 U321-83 # System-Ace Ground Pins NET 'GROUND' U321-91 U321-100 U321-110 # System-Ace Ground Pins NET 'GROUND' U321-111 U321-112 U321-120 # System-Ace Ground Pins NET 'GROUND' U321-129 U321-136 U321-144 # System-Ace Ground Pins # 3.3 Volt Bypass Capacitors for the System-Ace NET 'BULK_3V3' C321-2 C322-2 C326-2 # 3.3V terminal NET 'BULK_3V3' C327-1 C330-1 C331-1 # 3.3V terminal NET 'GROUND' C321-1 C322-1 C326-1 # GND terminal NET 'GROUND' C327-2 C330-2 C331-2 # GND terminal # 2.5 Volt Bypass Capacitors for the System-Ace NET 'BULK_2V5' C323-2 C324-2 C325-2 # 2.5V terminal NET 'BULK_2V5' C328-1 C329-1 C332-1 # 2.5V terminal NET 'GROUND' C323-1 C324-1 C325-1 # GND terminal NET 'GROUND' C328-2 C329-2 C332-2 # GND terminal # # CMX-0 Nets File # # # Clock Distribution Nets # --------------------------- # # # Original Rev. 17-Nov-2012 # Most Recent Rev. 16-July-2013 # # # # Starting on 2-July-2013 move the design to using Connor # Winfiled SFX-524G PLLs. # # This file originally held the nets that distribute a single # 40 MHz and a somg;e 320 MHz Clock both locked to the LHC to # the various Logic and GTX Transceivers on the CMX card. # # In the CMX prototype review the clock requirements were # expanded to include 2 phases of 40.08 MHz LHC clock, a # 320.64 MHz LHC clock, and 2 local crystal oscillator based # clocks (as well as the ACE and CAN-Bus micro-processor # clocks). This file now includes the generation and # distribution of both the LHC locked and the local crystal # oscillator based clocks. # # The list of generators, distributors, and consumers of the # various clock signals is best understood by studying the # drawing named "26_clocks_overall_view.pdf" in the circuit # diagrams section of the CMX web site. The clocks handled # by this file will just be listed here: # # 40.08 MHz LHC DeSkew-1 Logic Clock to BSPT, BF, TP, and # reference for the 320.64 MHz clock # # 40.08 MHz LHC DeSkew-2 Logic Clock to the BF and TP # # 320.64 MHz LHC Logic and GTX clock to Bf and TP # # 40.000 MHz Crystal Oscillator #1 GTX Clock to BF # # 40.000 or 100.000 MHz Crystal Oscillator #2 GTX Clock # to BF and TP # # Note that all Logic Clks are LVDS and all GTX Clks are LVPECL. # # # # The major ICs involved in the new Clock Generation and # Distribution system on the CMX card are the following: # # Crystal Oscillator #1 U371 typically 40.000 MHz # Fanout for above U372 NB6L611 # # Crystal Oscillator #2 U373 typically 40.000/100.000 MHz # Fanout for above U374 NB6L611 # # PLL 320.6296 MHz U375 Connor-Winfield SFX-524G-CRN2 # Fanout for above U376 MC100LVEP111 # # PLL 40.0787 MHz DeSkew-1 U377 Connor-Winfield SFX-524G-CRN1 # Fanout for above U378 MC100LVEP111 # # PLL 40.0787 MHz DeSkew-2 U379 Connor-Winfield SFX-524G-CRN1 # Fanout for above U380 NB6L611 # # # First take care of the direct Power and Ground connections # to these IC and to their bypass capacitors. Note that all # of these components are powered from the filtered CLK_3V3 # power plane. # Crystal Oscillator #1 U371 typically 40.000 MHz NET 'CLK_3V3' U371-6 C1421-2 C1422-1 NET 'GROUND' U371-3 C1421-1 C1422-2 # Fanout for above U372 NB6L611 NET 'CLK_3V3' U372-5 U372-8 U372-13 U372-16 NET 'GROUND' U372-7 U372-14 U372-15 U372-17 U372-18 U372-19 U372-20 NET 'CLK_3V3' C1423-1 C1424-2 NET 'GROUND' C1423-2 C1424-1 # Crystal Oscillator #2 U373 typically 40.000/100.000 MHz NET 'CLK_3V3' U373-6 C1425-2 C1426-1 NET 'GROUND' U373-3 C1425-1 C1426-2 # Fanout for above U374 NB6L611 NET 'CLK_3V3' U374-5 U374-8 U374-13 U374-16 NET 'GROUND' U374-7 U374-14 U374-15 U374-17 U374-18 U374-19 U374-20 NET 'CLK_3V3' C1427-1 C1428-2 NET 'GROUND' C1427-2 C1428-1 # PLL 320.6296 MHz U375 Connor-Winfield SFX-524G-CRN2 NET 'CLK_3V3' U375-9 C1429-2 C1430-2 NET 'GROUND' U375-2 U375-8 C1429-1 C1430-1 # Fanout for above U376 MC100LVEP111 NET 'CLK_3V3' U376-1 U376-9 U376-16 U376-25 U376-32 NET 'GROUND' U376-8 U376-33 U376-34 U376-35 U376-36 NET 'CLK_3V3' C1431-1 C1432-2 NET 'GROUND' C1431-2 C1432-1 # PLL 40.0787 MHz DeSkew-1 U377 Connor-Winfield SFX-524G-CRN1 NET 'CLK_3V3' U377-9 C1433-2 C1434-2 NET 'GROUND' U377-2 U377-8 C1433-1 C1434-1 # Fanout for above U378 MC100LVEP111 NET 'CLK_3V3' U378-1 U378-9 U378-16 U378-25 U378-32 NET 'GROUND' U378-8 U378-33 U378-34 U378-35 U378-36 NET 'CLK_3V3' C1435-1 C1436-2 NET 'GROUND' C1435-2 C1436-1 # PLL 40.0787 MHz DeSkew-2 U379 Connor-Winfield SFX-524G-CRN1 NET 'CLK_3V3' U379-9 C1437-2 C1438-2 NET 'GROUND' U379-2 U379-8 C1437-1 C1438-1 # Fanout for above U380 NB6L611 NET 'CLK_3V3' U380-5 U380-8 U380-13 U380-16 NET 'GROUND' U380-7 U380-14 U380-15 U380-17 U380-18 U380-19 U380-20 NET 'CLK_3V3' C1439-1 C1440-2 NET 'GROUND' C1439-2 C1440-1 # # Now include the L30 filter inductor for the CLK_3V3 # and its tantalum and distributed ceramic capacitors. NET 'CLK_3V3' L30-2 # Connection to Clk_Gen Power Bus NET 'BULK_3V3' L30-1 # Connection to Bulk 3.3V Power NET 'CLK_3V3' C1441-1 C1442-2 C1443-1 C1444-2 C1445-1 NET 'GROUND' C1441-2 C1442-1 C1443-2 C1444-1 C1445-2 NET 'CLK_3V3' C1446-1 C1447-1 C1448-1 NET 'GROUND' C1446-2 C1447-2 C1448-2 # # Now include all of the nets associated with the # Crystal Oscillator #1 and its distribution. # Pull-Up on the Crystal Osc #1 Enable pin. NET 'ENABLE_XTAL_OSC_1' U371-1 R471-1 # Xtal Osc #1 Enable Pull-Up NET 'CLK_3V3' R471-2 # Pull-Up Resistor to 3.3V # Couple the Xtal Osc #1 output to its Fanout chip input NET 'XTAL_OSC_1_OUT_DIR' U371-4 R456-2 U372-3 # Xtal Osc #1 DIR Output FO CMP In NET 'XTAL_OSC_1_OUT_CMP' U371-5 R455-2 U372-2 # Xtal Osc #1 CMP Output FO DIR In NET 'GROUND' R455-1 R456-1 # Pull-Down Resistors NET 'TERMINATOR_TIE_U372' U372-1 U372-4 # Connect the U372 Terminator. # The Vbb pin on U372 a NB6L611 fanout pin #6 is No_Conn. NET 'No_Conn_U372_VBB_PIN_6' U372-6 # No Conn U372 Vbb pin #6. # Outputs from the Xtal Osc #1 Fanout, Outputs 0 and 1 NET 'XTAL_OSC_1_FO_0_DIR' U372-12 R401-1 C1401-1 # Xtal Osc #1 Fanout #0 DIR NET 'XTAL_OSC_1_FO_0_CMP' U372-11 R402-1 C1402-1 # Xtal Osc #1 Fanout #0 CMP NET 'GROUND' R401-2 R402-2 # Pull-Down Resistors NET 'XTAL_OSC_1_FO_1_DIR' U372-10 R403-1 C1403-1 # Xtal Osc #1 Fanout #1 DIR NET 'XTAL_OSC_1_FO_1_CMP' U372-9 R404-1 C1404-1 # Xtal Osc #1 Fanout #1 CMP NET 'GROUND' R403-2 R404-2 # Pull-Down Resistors NET 'CLK_40MHz000_XTAL_1_BF_TRNCV_DIR' C1401-2 # 40.000 MHz Crystal Osc #1 NET 'CLK_40MHz000_XTAL_1_BF_TRNCV_CMP' C1402-2 # GTX Clk to the BF FPGA # Transmitter QUAD 118 # # Now include all of the nets associated with the # Crystal Oscillator #2 and its distribution. # Pull-Up on the Crystal Osc #2 Enable pin. NET 'ENABLE_XTAL_OSC_2' U373-1 R472-1 # Xtal Osc #2 Enable Pull-Up NET 'CLK_3V3' R472-2 # Pull-Up Resistor to 3.3V # Couple the Xtal Osc #2 output to its Fanout chip input NET 'XTAL_OSC_2_OUT_DIR' U373-4 R458-2 U374-3 # Xtal Osc #2 DIR Output FO CMP In NET 'XTAL_OSC_2_OUT_CMP' U373-5 R457-2 U374-2 # Xtal Osc #2 CMP Output FO DIR In NET 'GROUND' R457-1 R458-1 # Pull-Down Resistors NET 'TERMINATOR_TIE_U374' U374-1 U374-4 # Connect the U374 Terminator. # The Vbb pin on U374 a NB6L611 fanout pin #6 is No_Conn. NET 'No_Conn_U374_VBB_PIN_6' U374-6 # No Conn U374 Vbb pin #6. # Outputs from the Xtal Osc #2 Fanout, Outputs 0 and 1 NET 'XTAL_OSC_2_FO_0_DIR' U374-12 R405-1 C1405-1 # Xtal Osc #2 Fanout #0 DIR NET 'XTAL_OSC_2_FO_0_CMP' U374-11 R406-1 C1406-1 # Xtal Osc #2 Fanout #0 CMP NET 'GROUND' R405-2 R406-2 # Pull-Down Resistors NET 'XTAL_OSC_2_FO_1_DIR' U374-10 R407-1 C1407-1 # Xtal Osc #2 Fanout #1 DIR NET 'XTAL_OSC_2_FO_1_CMP' U374-9 R408-1 C1408-1 # Xtal Osc #2 Fanout #1 CMP NET 'GROUND' R407-2 R408-2 # Pull-Down Resistors NET 'CLK_100MHz000_XTAL_2_TP_TRNCV_DIR' C1405-2 # 100.000 MHz Crystal Osc #2 NET 'CLK_100MHz000_XTAL_2_TP_TRNCV_CMP' C1406-2 # GTX Clk to the TP FPGA. # Transmitter QUAD 110 NET 'CLK_100MHz000_XTAL_2_BF_TRNCV_DIR' C1407-2 # 100.000 MHz Crystal Osc #2 NET 'CLK_100MHz000_XTAL_2_BF_TRNCV_CMP' C1408-2 # GTX Clk to the BF FPGA # Transmitter QUAD 117 # # Now include all of the nets associated with the # 40.08 MHz DeSkew-2 clock signal and its distribution. # -------=== # Connect the TTCDec DeSkew-2 output from R255 to # the 40.0787 MHz PLL reference clock input NET 'PLL_DESKEW_2_FIN' R255-1 U379-1 # DeSkew 2 PLL FIn pin # Connor-Winfield SFX-524G Reset pin NET 'No_Conn_U379_3' U379-3 # Float this pin --> Not Reseting the PLL. # Connor-Winfield SFX-524G No Connect pins NET 'No_Conn_U379_4' U379-4 # SFX-524G No Connect Pin Number 4. NET 'No_Conn_U379_5' U379-5 # SFX-524G No Connect Pin Number 5. # 40.08 MHz DeSkew-2 PLL Outputs to the U380 Fanout chip NET 'PLL_DESKEW_2_OUT_DIR' U379-6 R469-2 U380-2 # PLL DeSkew 2 Output DIR NET 'PLL_DESKEW_2_OUT_CMP' U379-7 R470-2 U380-3 # PLL DeSkew 2 Output CMP NET 'GROUND' R469-1 R470-1 # Pull-Down Resistors NET 'TERMINATOR_TIE_U380' U380-1 U380-4 # Connect the U380 Terminator. # The Vbb pin on U380 a NB6L611 fanout pin #6 is No_Conn. NET 'No_Conn_U380_VBB_PIN_6' U380-6 # No Conn U380 Vbb pin #6. # Outputs from the PLL DeSkew 2 Fanout, Outputs 0 and 1 NET 'PLL_DESKEW_2_FO_0_DIR' U380-12 R447-1 # DeSkew 2 PLL Fanout #0 DIR NET 'PLL_DESKEW_2_FO_0_CMP' U380-11 R448-1 # DeSkew 2 PLL Fanout #0 CMP NET 'PLL_DESKEW_2_FO_1_DIR' U380-10 R451-1 # DeSkew 2 PLL Fanout #1 DIR NET 'PLL_DESKEW_2_FO_1_CMP' U380-9 R452-1 # DeSkew 2 PLL Fanout #1 CMP # Fanout outputs connected to the consumers of PLL DeSkew 2 clock signals. NET 'CLK_40MHz08_DSKW_2_TP_LOGIC_DIR' R447-2 R449-2 # 40.08 MHz DSK-2 LHC Logic NET 'CLK_40MHz08_DSKW_2_TP_LOGIC_CMP' R448-2 R450-2 # Clk to the Topological FPGA NET 'CLK_40MHz08_DSKW_2_BF_LOGIC_DIR' R451-2 R453-2 # 40.08 MHz DSK-2 LHC Logic NET 'CLK_40MHz08_DSKW_2_BF_LOGIC_CMP' R452-2 R454-2 # Clk to the Base Function FPGA # Ground the attenuator resistors on the PLL DeSkew 2 fanout clock signals. NET 'GROUND' R449-1 R450-1 # Attenuator Pull-Down Resistors NET 'GROUND' R453-1 R454-1 # Attenuator Pull-Down Resistors # # Now include all of the nets associated with the # 40.08 MHz DeSkew-1 clock signal and its distribution. # -------=== # Connect the TTCDec DeSkew-1 output from either R254 or # R256 the 40.0787 MHz DeSkew-1PLL reference clock input. NET 'PLL_DESKEW_1_FIN' R254-1 U377-1 # DeSkew 1 PLL FIn pin NET 'PLL_DESKEW_1_FIN' R256-1 # Connor-Winfield SFX-524G Reset pin NET 'No_Conn_U377_3' U377-3 # Float this pin --> Not Reseting the PLL. # Connor-Winfield SFX-524G No Connect pins NET 'No_Conn_U377_4' U377-4 # SFX-524G No Connect Pin Number 4. NET 'No_Conn_U377_5' U377-5 # SFX-524G No Connect Pin Number 5. # 40.08 MHz DeSkew-1 PLL Outputs to the U378 Fanout chip NET 'PLL_DESKEW_1_OUT_DIR' U377-6 U378-3 # PLL DeSkew 1 Output DIR NET 'PLL_DESKEW_1_OUT_CMP' U377-7 U378-4 # PLL DeSkew 1 Output CMP NET 'PLL_DESKEW_1_OUT_DIR' R465-2 R463-2 # PLL DeSkew 1 Output DIR NET 'PLL_DESKEW_1_OUT_CMP' R466-2 R464-2 # PLL DeSkew 1 Output CMP NET 'GROUND' R465-1 R466-1 # Pull-Down Resistors NET 'CLK_3V3' R463-1 R464-1 # Term to Clk 3.3V # Pull-Down on the Input Select pin of the U378 MC100LVEP111 # Fanout chip ship so that it will use its CLK0 & CLK0_B input # pins. Also No-Conn its Vbb reference pin and its CLK1 pins. NET 'SELECT_INPUT_0_U378_FO' U378-2 R474-2 # U378 Select Pull-Down NET 'GROUND' R474-1 # Ground the Pull-Down NET 'No_Conn_U378_VBB_PIN_5' U378-5 # Unused Vbb Reference NET 'No_Conn_U378_CLK1_PIN_6' U378-6 # Unused CLK1 NET 'No_Conn_U378_CLK1_B_PIN_7' U378-7 # Unused CLK_B # Output 0 from the PLL DeSkew 1 Fanout, to the 320.64 MHz PLL NET 'PLL_DESKEW_1_FO_0_DIR' U378-31 U375-1 # DeSkew 1 PLL Fanout #0 DIR # runs to the 320 MHZ PLL FIN NET 'PLL_DESKEW_1_FO_0_CMP' U378-30 # DeSkew 1 PLL Fanout #0 CMP NET 'PLL_DESKEW_1_FO_0_DIR' R430-2 R432-2 # PLL DeSkew 1 FanOut #0 DIR NET 'PLL_DESKEW_1_FO_0_CMP' R429-2 R431-2 # PLL DeSkew 1 FanOut #0 CMP NET 'GROUND' R430-1 R429-1 # Pull-Down Resistors NET 'CLK_3V3' R432-1 R431-1 # Term to Clk 3.3V # Output 1 and 2 from the PLL DeSkew 1 # Fanout are not connected. NET 'No_Conn_PLL_DESKEW_1_FO_1_DIR' U378-29 # No_Conn PLL DeSkew 1 FanOut #1 DIR NET 'No_Conn_PLL_DESKEW_1_FO_1_CMP' U378-28 # No_Conn PLL DeSkew 1 FanOut #1 CMP NET 'No_Conn_PLL_DESKEW_1_FO_2_DIR' U378-27 # No_Conn PLL DeSkew 1 FanOut #2 DIR NET 'No_Conn_PLL_DESKEW_1_FO_2_CMP' U378-26 # No_Conn PLL DeSkew 1 FanOut #2 CMP # Output 3 from the PLL DeSkew 1 Fanout, to the Topological FPGA NET 'PLL_DESKEW_1_FO_3_DIR' U378-24 R433-1 # DeSkew 1 PLL Fanout #3 DIR NET 'PLL_DESKEW_1_FO_3_CMP' U378-23 R434-1 # DeSkew 1 PLL Fanout #3 CMP # DeSkew 1 Fanout Output 3 connected to the TP FPGA Logic Clock input pin. NET 'CLK_40MHz08_DSKW_1_TP_LOGIC_DIR' R433-2 R435-2 # 40.08 MHz DSK-1 LHC Logic NET 'CLK_40MHz08_DSKW_1_TP_LOGIC_CMP' R434-2 R436-2 # Clk to the Topological FPGA # Ground the attenuator resistors on the PLL DeSkew 1 fanout clock signals. NET 'GROUND' R435-1 R436-1 # Attenuator Pull-Down Resistors # Output 4 from the PLL DeSkew 1 Fanout, to the Base Function FPGA NET 'PLL_DESKEW_1_FO_5_DIR' U378-22 R437-1 # DeSkew 1 PLL Fanout #4 DIR NET 'PLL_DESKEW_1_FO_5_CMP' U378-21 R438-1 # DeSkew 1 PLL Fanout #4 CMP # DeSkew 1 Fanout Output 4 connected to the TP FPGA Logic Clock input pin. NET 'CLK_40MHz08_DSKW_1_BF_LOGIC_DIR' R437-2 R439-2 # 40.08 MHz DSK-1 LHC Logic NET 'CLK_40MHz08_DSKW_1_BF_LOGIC_CMP' R438-2 R440-2 # Clk to the Base Function FPGA # Ground the attenuator resistors on the PLL DeSkew 1 fanout clock signals. NET 'GROUND' R439-1 R440-1 # Attenuator Pull-Down Resistors # Output 5 from the PLL DeSkew 1 # Fanout is not connected. NET 'No_Conn_PLL_DESKEW_1_FO_5_DIR' U378-20 # No_Conn PLL DeSkew 1 FanOut #5 DIR NET 'No_Conn_PLL_DESKEW_1_FO_5_CMP' U378-19 # No_Conn PLL DeSkew 1 FanOut #5 CMP # Output 6 from the PLL DeSkew 1 Fanout, to the Board Support FPGA NET 'PLL_DESKEW_1_FO_6_DIR' U378-18 R441-1 # DeSkew 1 PLL Fanout #6 DIR NET 'PLL_DESKEW_1_FO_6_CMP' U378-17 R442-1 # DeSkew 1 PLL Fanout #6 CMP # DeSkew 1 Fanout Output 6 connected to the TP FPGA Logic Clock input pin. NET 'CLK_40MHz08_DSKW_1_BSPT_LOGIC_DIR' R441-2 R443-2 # 40.08 MHz DSK-1 LHC Logic NET 'CLK_40MHz08_DSKW_1_BSPT_LOGIC_CMP' R442-2 R444-2 # Clk to the BSPT FPGA # Ground the attenuator resistors on the PLL DeSkew 1 fanout clock signals. NET 'GROUND' R443-1 R444-1 # Attenuator Pull-Down Resistors # Output 7 and 8 from the PLL DeSkew 1 # Fanout are not connected. NET 'No_Conn_PLL_DESKEW_1_FO_7_DIR' U378-15 # No_Conn PLL DeSkew 1 FanOut #7 DIR NET 'No_Conn_PLL_DESKEW_1_FO_7_CMP' U378-14 # No_Conn PLL DeSkew 1 FanOut #7 CMP NET 'No_Conn_PLL_DESKEW_1_FO_8_DIR' U378-13 # No_Conn PLL DeSkew 1 FanOut #8 DIR NET 'No_Conn_PLL_DESKEW_1_FO_8_CMP' U378-12 # No_Conn PLL DeSkew 1 FanOut #8 CMP # Output 9 from the PLL DeSkew 1 Fanout, to monitor test points NET 'PLL_DESKEW_1_FO_9_DIR' U378-11 R446-2 # DeSkew 1 PLL Fanout #9 DIR NET 'PLL_DESKEW_1_FO_9_CMP' U378-10 R445-2 # DeSkew 1 PLL Fanout #9 CMP NET 'GROUND' R445-1 R446-1 # Pull-Down Resistors # # Now include all of the nets associated with the # 320.64 MHz clock signal and its distribution. # ---------- # # This PLL based clock signal fans out both as a # LVDS Logic clock to both the BF and TP and BF FPGAs # and fans out as a LVPECL GTX clock to the transceivers # in both the BF and TP FPGAs. # # Connor-Winfield SFX-524G Reset pin NET 'No_Conn_U375_3' U375-3 # Float this pin --> Not Reseting the PLL. # Connor-Winfield SFX-524G No Connect pins NET 'No_Conn_U375_4' U375-4 # SFX-524G No Connect Pin Number 4. NET 'No_Conn_U375_5' U375-5 # SFX-524G No Connect Pin Number 5. # 320.64 MHz PLL Outputs to the U376 Fanout chip NET 'PLL_320MHz64_OUT_DIR' U375-6 U376-3 # PLL 320.64 MHz Output DIR NET 'PLL_320MHz64_OUT_CMP' U375-7 U376-4 # PLL 320.64 MHz Output CMP NET 'PLL_320MHz64_OUT_DIR' R461-2 R459-2 # PLL 320.64 MHz Output DIR NET 'PLL_320MHz64_OUT_CMP' R462-2 R460-2 # PLL 320.64 MHz Output CMP NET 'GROUND' R461-1 R462-1 # Pull-Down Resistors NET 'CLK_3V3' R459-1 R460-1 # Term to Clk 3.3V # Pull-Down on the Input Select pin of the U376 MC100LVEP111 # Fanout chip ship so that it will use its CLK0 & CLK0_B input # pins. Also No-Conn its Vbb reference pin and its CLK1 pins. NET 'SELECT_INPUT_0_U376_FO' U376-2 R473-2 # U376 Select Pull-Down NET 'GROUND' R473-1 # Ground the Pull-Down NET 'No_Conn_U376_VBB_PIN_5' U376-5 # Unused Vbb Reference NET 'No_Conn_U376_CLK1_PIN_6' U376-6 # Unused CLK1 NET 'No_Conn_U376_CLK1_B_PIN_7' U376-7 # Unused CLK_B # Outputs 0 from the 320.64 MHz PLL Fanout is not connected. NET 'No_Conn_PLL_320MHz64_FO_0_DIR' U376-31 # No_Conn 320 Mhz PLL FanOut #0 DIR NET 'No_Conn_PLL_320MHz64_FO_0_CMP' U376-30 # No_Conn 320 Mhz PLL FanOut #0 CMP # Output 1 from the 320.64 MHz PLL Fanout, GTX Clk to the Topological FPGA NET 'PLL_320MHz64_FO_1_DIR' U376-29 R409-1 C1409-1 # 320.64 MHz PLL Fanout #1 DIR NET 'PLL_320MHz64_FO_1_CMP' U376-28 R410-1 C1410-1 # 320.64 MHz PLL Fanout #1 CMP NET 'GROUND' R409-2 R410-2 # Pull-Down Resistors NET 'CLK_320MHz64_LHC_TP_QUAD_117_DIR' C1409-2 # 320.64 MHz PLL LHC Clk NET 'CLK_320MHz64_LHC_TP_QUAD_117_CMP' C1410-2 # to the TP FPGA GTX 117 # Output 2 from the 320.64 MHz PLL Fanout, GTX Clk to the Topological FPGA NET 'PLL_320MHz64_FO_2_DIR' U376-27 R411-1 C1411-1 # 320.64 MHz PLL Fanout #2 DIR NET 'PLL_320MHz64_FO_2_CMP' U376-26 R412-1 C1412-1 # 320.64 MHz PLL Fanout #2 CMP NET 'GROUND' R411-2 R412-2 # Pull-Down Resistors NET 'CLK_320MHz64_LHC_TP_QUAD_114_DIR' C1411-2 # 320.64 MHz PLL LHC Clk NET 'CLK_320MHz64_LHC_TP_QUAD_114_CMP' C1412-2 # to the TP FPGA GTX 114 # Output 3 from the 320.64 MHz PLL Fanout, GTX Clk to the Topological FPGA NET 'PLL_320MHz64_FO_3_DIR' U376-24 R413-1 C1413-1 # 320.64 MHz PLL Fanout #3 DIR NET 'PLL_320MHz64_FO_3_CMP' U376-23 R414-1 C1414-1 # 320.64 MHz PLL Fanout #3 CMP NET 'GROUND' R413-2 R414-2 # Pull-Down Resistors NET 'CLK_320MHz64_LHC_TP_QUAD_111_DIR' C1413-2 # 320.64 MHz PLL LHC Clk NET 'CLK_320MHz64_LHC_TP_QUAD_111_CMP' C1414-2 # to the TP FPGA GTX 111 # Output 4 from the 320.64 MHz PLL Fanout, Logic Clk to the Topological FPGA NET 'PLL_320MHz64_FO_4_DIR' U376-22 R419-1 # 320.64 MHz PLL Fanout #4 DIR NET 'PLL_320MHz64_FO_4_CMP' U376-21 R420-1 # 320.64 MHz PLL Fanout #4 CMP # 320.64 MHz PLL Fanout Output 4 connected to the TP FPGA Logic Clock input pin. NET 'CLK_320MHz64_LHC_TP_LOGIC_DIR' R419-2 R421-2 # 320.64 MHz LHC Logic NET 'CLK_320MHz64_LHC_TP_LOGIC_CMP' R420-2 R422-2 # Clk to the TP FPGA # Ground the attenuator resistors on the 320.64 MHz PLL fanout clock signals. NET 'GROUND' R421-1 R422-1 # Attenuator Pull-Down Resistors # Output 5 from the 320.64 MHz PLL Fanout, GTX Clk to the Base Function FPGA NET 'PLL_320MHz64_FO_5_DIR' U376-20 R415-1 C1415-1 # 320.64 MHz PLL Fanout #5 DIR NET 'PLL_320MHz64_FO_5_CMP' U376-19 R416-1 C1416-1 # 320.64 MHz PLL Fanout #5 CMP NET 'GROUND' R415-2 R416-2 # Pull-Down Resistors NET 'CLK_320MHz64_LHC_BF_QUAD_114_DIR' C1415-2 # 320.64 MHz PLL LHC Clk NET 'CLK_320MHz64_LHC_BF_QUAD_114_CMP' C1416-2 # to the BF FPGA GTX 114 # Output 6 from the 320.64 MHz PLL Fanout, GTX Clk to the Base Function FPGA NET 'PLL_320MHz64_FO_6_DIR' U376-18 R417-1 C1417-1 # 320.64 MHz PLL Fanout #6 DIR NET 'PLL_320MHz64_FO_6_CMP' U376-17 R418-1 C1418-1 # 320.64 MHz PLL Fanout #6 CMP NET 'GROUND' R417-2 R418-2 # Pull-Down Resistors NET 'CLK_320MHz64_LHC_BF_QUAD_111_DIR' C1417-2 # 320.64 MHz PLL LHC Clk NET 'CLK_320MHz64_LHC_BF_QUAD_111_CMP' C1418-2 # to the BF FPGA GTX 111 # Output 7 from the 320.64 MHz PLL Fanout, Logic Clk to the Base Function FPGA NET 'PLL_320MHz64_FO_7_DIR' U376-15 R423-1 # 320.64 MHz PLL Fanout #7 DIR NET 'PLL_320MHz64_FO_7_CMP' U376-14 R424-1 # 320.64 MHz PLL Fanout #7 CMP # 320.64 MHz PLL Fanout Output 7 connected to the BF FPGA Logic Clock input pin. NET 'CLK_320MHz64_LHC_BF_LOGIC_DIR' R423-2 R425-2 # 320.64 MHz LHC Logic NET 'CLK_320MHz64_LHC_BF_LOGIC_CMP' R424-2 R426-2 # Clk to the TP FPGA # Ground the attenuator resistors on the 320.64 MHz PLL fanout clock signals. NET 'GROUND' R425-1 R426-1 # Attenuator Pull-Down Resistors # Outputs 8 from the 320.64 MHz PLL Fanout is not connected. NET 'No_Conn_PLL_320MHz64_FO_8_DIR' U376-13 # No_Conn 320 Mhz PLL FanOut #8 DIR NET 'No_Conn_PLL_320MHz64_FO_8_CMP' U376-12 # No_Conn 320 Mhz PLL FanOut #8 CMP # Output 9 from the 320.64 MHz PLL Fanout, to monitor test points NET 'PLL_320MHz64_FO_9_DIR' U376-11 R428-2 # 320.64 MHz PLL Fanout #9 DIR NET 'PLL_320MHz64_FO_9_CMP' U376-10 R427-2 # 320.64 MHz PLL Fanout #9 CMP NET 'GROUND' R427-1 R428-1 # Pull-Down Resistors # PLL Monitoring Signals # # Each of the 3 PLLs has 2 monitoring signals: # # - Lock Detect logic signal that can be monitored by # one of the Board Support FPGA DeBug signals # # - VCXO Control Voltage analog monitor signal that # is routed to a via where it can be monitored by # an external DVM. # # Note that the following resistors are actually Jumpers # # - R481 jumpers the 320.64 MHz PLL Lock Detect to BSPT_DEBUG_6 # # - R482 jumpers the DeSkew-1 PLL Lock Detect to BSPT_DEBUG_5 # # - R483 jumpers the DeSkew-2 PLL Lock Detect to BSPT_DEBUG_7 # # # There are 3 sections below - one for each PLL. # # # 320.64 MHz PLL U375 Monitoring # # 320.64 MHz PLL Lock-Det and VMon pins. NET 'PLL_320MHz64_LOCK_DET' U375-10 # Lock Status of the 320.64 MHz PLL NET 'PLL_320MHz64_LOCK_DET' R478-1 # U375 to decoupling resistor NET 'PLL_320MHz_LOCK_DET_RES' R478-2 # Decoupling resistor 1 to NET 'PLL_320MHz_LOCK_DET_RES' R481-2 # Jumper resistor to BSPT DeBug_6 NET 'BSPT_DEBUG_6' R481-1 # Monitor the 320.64 MHz PLL Lock Detect # on Board Support FPGA BSPT_DEBUG_6 NET 'PLL_320MHz64_V_MON' R475-2 # to the decoupling resistor R475 NET 'MONITOR_320MHz_VCXO' R475-1 # Via to monitor the 320.64 MHz NET 'MONITOR_320MHz_VCXO' WRP11-1 # PLL VCXO Control Voltage NET 'GROUND' WRP12-1 # Ground Reference Via # # DeSkew-1 PLL U377 40.08 MHz Monitoring # # 40.08 MHz DeSkew-1 PLL Lock-Det and VMon pins. NET 'PLL_DESKEW_1_LOCK_DET' U377-10 # Lock Status of the DeSkew 1 PLL NET 'PLL_DESKEW_1_LOCK_DET' R479-1 # U377 to decoupling resistor NET 'PLL_DESKEW_1_LOCK_DET_RES' R479-2 # Decoupling resistor 1 to NET 'PLL_DESKEW_1_LOCK_DET_RES' R482-1 # Jumper resistor to BSPT DeBug_5 NET 'BSPT_DEBUG_5' R482-2 # Monitor the DeSkew 1 PLL Lock Detect # on Board Support FPGA BSPT_DEBUG_5 NET 'PLL_DESKEW_1_V_MON' R476-2 # to the decoupling resistor R476 NET 'MONITOR_DESKEW_1_VCXO' R476-1 # Via to monitor the DeSkew 1 NET 'MONITOR_DESKEW_1_VCXO' WRP13-1 # PLL VCXO Control Voltage NET 'GROUND' WRP14-1 # Ground Reference Via # # DeSkew-2 PLL U379 40.08 MHz Monitoring # # 40.08 MHz DeSkew-2 PLL Lock-Det and VMon pins. NET 'PLL_DESKEW_2_LOCK_DET' U379-10 # Lock Status of the DeSkew 2 PLL NET 'PLL_DESKEW_2_LOCK_DET' R480-1 # U379 to decoupling resistor NET 'PLL_DESKEW_2_LOCK_DET_RES' R480-2 # Decoupling resistor 1 to NET 'PLL_DESKEW_2_LOCK_DET_RES' R483-1 # Jumper resistor to BSPT DeBug_7 NET 'BSPT_DEBUG_7' R483-2 # Monitor the DeSkew 2 PLL Lock Detect # on Board Support FPGA BSPT_DEBUG_7 NET 'PLL_DESKEW_2_V_MON' R477-2 # to the decoupling resistor R476 NET 'MONITOR_DESKEW_2_VCXO' R477-1 # Via to monitor the DeSkew 2 NET 'MONITOR_DESKEW_2_VCXO' WRP15-1 # PLL VCXO Control Voltage NET 'GROUND' WRP16-1 # Ground Reference Via # # CMX-0 Nets File # # Board Support FPGA Power and Ground Nets # -------------------------------------------- # # # Original Rev. 22-Aug-2012 # Most Recent Rev. 17-May-2013 # # # # This file holds the nets for all of the Power and Ground # connections for the Board Support FPGA. This file includes # the power supply bypass capacitors for the Board Support FPGA. # # Recall that the Board Support FPGA has both 3.3 V and # 2.5 V I/O Banks. # # Recall that we are using 3.3 Volt Aux supply with the BSPT FPGA. # # # # U351 Board Support FPGA XC3S400A in the FG400/FGG400 package # # C351, C352, C353, C354 47 nFd Bypass capacitors Spartan VCCINT # C355, C356, C357, C358 100 nFd Bypass capacitors Spartan VCCINT # # C361, C362, C363 47 nFd Bypass capacitors Spartan VCCAUX # C364, C365, C366 100 nFd Bypass capacitors Spartan VCCAUX # # C367, C368, C369 47 nFd Bypass capacitors Spartan VCCO_0 # C370, C371, C372 100 nFd Bypass capacitors Spartan VCCO_0 # # C373, C374, C375 47 nFd Bypass capacitors Spartan VCCO_1 # C376, C377, C378 100 nFd Bypass capacitors Spartan VCCO_1 # # C379, C380, C381 47 nFd Bypass capacitors Spartan VCCO_2 # C382, C383, C384 100 nFd Bypass capacitors Spartan VCCO_2 # # C385, C386, C387 47 nFd Bypass capacitors Spartan VCCO_3 # C388, C389, C390 100 nFd Bypass capacitors Spartan VCCO_3 # # # Recall that the Board Support XC3S400A Spartan FPGA requires: # # VCCINT 1.200 V nominal 1.140 V min 1.260 V max # # VCCAUX 2.500 V or 3.300 V nominal 2.250 V min 2.750 V max # or 3.000 V min 3.600 V max <-<-<-< # # VCCO 2.500 V and 3.300 V nominal 1.100 V min 3.600 V max # # # Board Support FPGA XC3S400A FG400 Spartan VCCINT Power Pins 1.20 Volts # # On the CMX card the Spartan Board Support # FPGA VCCINT supply is called BSPT_CORE NET 'BSPT_CORE' U351-J10 U351-J12 # Spartan VCCINT Power Pins NET 'BSPT_CORE' U351-K9 U351-K11 # Spartan VCCINT Power Pins NET 'BSPT_CORE' U351-L10 U351-L12 # Spartan VCCINT Power Pins NET 'BSPT_CORE' U351-M9 U351-M11 # Spartan VCCINT Power Pins NET 'BSPT_CORE' U351-N10 # Spartan VCCINT Power Pins # Board Support FPGA XC3S400A FG400 Spartan VCCAUX Power Pins 3.30 Volts # # In the Spartan 3a family the VCCAUX supply powers the: # # Digital Clock Managers, differential drivers, # dedicated configuration pins (PROG_B and DONE), # and the JTAG interface # NET 'BULK_3V3' U351-A13 # Spartan VCCAUX Power Pins NET 'BULK_3V3' U351-E16 # Spartan VCCAUX Power Pins NET 'BULK_3V3' U351-H1 # Spartan VCCAUX Power Pins NET 'BULK_3V3' U351-K13 # Spartan VCCAUX Power Pins NET 'BULK_3V3' U351-L8 # Spartan VCCAUX Power Pins NET 'BULK_3V3' U351-N20 # Spartan VCCAUX Power Pins NET 'BULK_3V3' U351-T5 # Spartan VCCAUX Power Pins NET 'BULK_3V3' U351-Y8 # Spartan VCCAUX Power Pins # Board Support FPGA XC3S400A FG400 Spartan VCCO_0 Power Pins 2.50 Volts # # Board Support FPGA I/O Bank #0 2.5 Volt CMOS I/O NET 'BULK_2V5' U351-B4 U351-B10 U351-B16 # I/O Bank #0 Vcco NET 'BULK_2V5' U351-D7 U351-D13 U351-F10 # I/O Bank #0 Vcco # Board Support FPGA XC3S400A FG400 Spartan VCCO_1 Power Pins 2.50 Volts # # Board Support FPGA I/O Bank #1 2.5 Volt CMOS I/O NET 'BULK_2V5' U351-D19 U351-H16 U351-K19 # I/O Bank #1 Vcco NET 'BULK_2V5' U351-N16 U351-T19 # I/O Bank #1 Vcco # Board Support FPGA XC3S400A FG400 Spartan VCCO_2 Power Pins 2.50 Volts # # Board Support FPGA I/O Bank #2 2.5 Volt CMOS I/O NET 'BULK_2V5' U351-R11 U351-U8 U351-U14 # I/O Bank #2 Vcco NET 'BULK_2V5' U351-W5 U351-W11 U351-W17 # I/O Bank #2 Vcco # Board Support FPGA XC3S400A FG400 Spartan VCCO_3 Power Pins 3.30 Volts # # Board Support FPGA I/O Bank #3 3.3 Volt CMOS I/O NET 'BULK_3V3' U351-E2 U351-H5 U351-L2 # I/O Bank #3 Vcco NET 'BULK_3V3' U351-N5 U351-U2 # I/O Bank #3 Vcco # Board Support FPGA XC3S400A FG400 Ground Pins NET 'GROUND' U351-A1 U351-A11 U351-A20 # Brd Support FPGA Grounds NET 'GROUND' U351-B6 U351-B14 # Brd Support FPGA Grounds NET 'GROUND' U351-C3 U351-C18 # Brd Support FPGA Grounds NET 'GROUND' U351-D9 # Brd Support FPGA Grounds NET 'GROUND' U351-E5 U351-E12 # Brd Support FPGA Grounds NET 'GROUND' U351-F15 # Brd Support FPGA Grounds NET 'GROUND' U351-G2 U351-G19 # Brd Support FPGA Grounds NET 'GROUND' U351-H8 U351-H13 # Brd Support FPGA Grounds NET 'GROUND' U351-J9 U351-J11 # Brd Support FPGA Grounds NET 'GROUND' U351-K1 U351-K10 # Brd Support FPGA Grounds NET 'GROUND' U351-K12 U351-K17 # Brd Support FPGA Grounds NET 'GROUND' U351-L4 U351-L9 # Brd Support FPGA Grounds NET 'GROUND' U351-L11 U351-L20 # Brd Support FPGA Grounds NET 'GROUND' U351-M10 U351-M12 # Brd Support FPGA Grounds NET 'GROUND' U351-N8 U351-N11 U351-N13 # Brd Support FPGA Grounds NET 'GROUND' U351-P2 U351-P19 # Brd Support FPGA Grounds NET 'GROUND' U351-R6 U351-R9 # Brd Support FPGA Grounds NET 'GROUND' U351-T16 # Brd Support FPGA Grounds NET 'GROUND' U351-U12 # Brd Support FPGA Grounds NET 'GROUND' U351-V3 U351-V18 # Brd Support FPGA Grounds NET 'GROUND' U351-W7 U351-W15 # Brd Support FPGA Grounds NET 'GROUND' U351-Y1 U351-Y10 U351-Y20 # Brd Support FPGA Grounds # 1.2 Volt Bypass Capacitors Board Support Spartan VCCINT NET 'BSPT_CORE' C351-1 C352-1 C353-1 C354-2 # 47 nFd 1.2V terminal NET 'BSPT_CORE' C355-1 C356-1 C357-2 C358-1 # 100 nFd 1.2V terminal NET 'GROUND' C351-2 C352-2 C353-2 C354-1 # 47 nFd GND terminal NET 'GROUND' C355-2 C356-2 C357-1 C358-2 # 100 nFd GND terminal # 3.3 Volt Bypass Capacitors Board Support Spartan VCCAUX NET 'BULK_3V3' C361-1 C362-1 C363-1 # 47 nFd 2.5V terminal NET 'BULK_3V3' C364-1 C365-2 C366-2 # 100 nFd 2.5V terminal NET 'GROUND' C361-2 C362-2 C363-2 # 47 nFd GND terminal NET 'GROUND' C364-2 C365-1 C366-1 # 100 nFd GND terminal # 2.5 Volt Bypass Capacitors Board Support I/O Bank #0 Spartan VCCO_0 NET 'BULK_2V5' C367-1 C368-1 C369-1 # 47 nFd 2.5V terminal NET 'BULK_2V5' C370-1 C371-2 C372-2 # 100 nFd 2.5V terminal NET 'GROUND' C367-2 C368-2 C369-2 # 47 nFd GND terminal NET 'GROUND' C370-2 C371-1 C372-1 # 100 nFd GND terminal # 2.5 Volt Bypass Capacitors Board Support I/O Bank #1 Spartan VCCO_1 NET 'BULK_2V5' C373-1 C374-1 C375-1 # 47 nFd 2.5V terminal NET 'BULK_2V5' C376-1 C377-1 C378-1 # 100 nFd 2.5V terminal NET 'GROUND' C373-2 C374-2 C375-2 # 47 nFd GND terminal NET 'GROUND' C376-2 C377-2 C378-2 # 100 nFd GND terminal # 2.5 Volt Bypass Capacitors Board Support I/O Bank #2 Spartan VCCO_2 NET 'BULK_2V5' C379-1 C380-1 C381-1 # 47 nFd 2.5V terminal NET 'BULK_2V5' C382-2 C383-2 C384-2 # 100 nFd 2.5V terminal NET 'GROUND' C379-2 C380-2 C381-2 # 47 nFd GND terminal NET 'GROUND' C382-1 C383-1 C384-1 # 100 nFd GND terminal # 3.3 Volt Bypass Capacitors Board Support I/O Bank #3 Spartan VCCO_3 NET 'BULK_3V3' C385-1 C386-1 C387-1 # 47 nFd 3.3V terminal NET 'BULK_3V3' C388-2 C389-1 C390-1 # 100 nFd 3.3V terminal NET 'GROUND' C385-2 C386-2 C387-2 # 47 nFd GND terminal NET 'GROUND' C388-1 C389-2 C390-2 # 100 nFd GND terminal # # CMX-0 Nets File # # Board Support FPGA On-Card-Bus Nets # ----------------------------------------- # # # Original Rev. 31-Oct-2012 # Most Recent Rev. 7-Apr-2013 # # # # This file holds the nets for all connections of the On-Card-Bus # to the Board Support FPGA. # # This file is NOT the nets for the management of the OCB by the BSPT_FPGA. # # All lines in the OCB are 2.5V logic levels. All of these lines # connect to I/O Back 0 of the Spartan 3A Board Support FPGA. # I/O Bank 1 is operated with a 2.5V VCC IO. # # On the BSPT FPGA, 2.5V I/O pins have been used for the OCB # even through one could use Input-Only pins for things like # address lines. In this way, the BSPT could "master" a cycle # to the BF or TP for testing or something like that. There # were enough 2.5V I/O pins to do this and still have spares. # # On-Card_Bus Connection to BSPT FPGA Bank 0 # ---------------------------------------------- NET 'OCB_GEO_ADRS_1' U351-A4 # L29P-0 2.5V I/O NET 'OCB_GEO_ADRS_2' U351-C4 # L29N-0 2.5V I/O NET 'OCB_GEO_ADRS_3' U351-A5 # L26P-0 2.5V I/O NET 'OCB_D00' U351-B5 # L26N-0 2.5V I/O NET 'OCB_D01' U351-C5 # L28P-0 2.5V I/O NET 'OCB_D02' U351-A6 # L25P-0 2.5V I/O NET 'OCB_D03' U351-C6 # L25N-0 2.5V I/O NET 'OCB_D04' U351-D6 # L28N-0 2.5V I/O NET 'OCB_D05' U351-E6 # L31P-0 2.5V I/O NET 'OCB_D06' U351-F6 # L31N-0 2.5V I/O NET 'OCB_D07' U351-A7 # L24N-0 2.5V I/O NET 'OCB_D08' U351-B7 # L24P-0 2.5V I/O NET 'OCB_D09' U351-C7 # L21P-0 2.5V I/O NET 'OCB_D10' U351-E7 # L27P-0 2.5V I/O NET 'OCB_D11' U351-F7 # L27N-0 2.5V I/O NET 'OCB_D12' U351-A8 # L18N-0 2.5V I/O NET 'OCB_D13' U351-B8 # L20P-0 2.5V I/O NET 'OCB_D14' U351-C8 # L20N-0 2.5V I/O NET 'OCB_D15' U351-D8 # L21N-0 2.5V I/O NET 'OCB_A23' U351-E8 # L23P-0 2.5V I/O NET 'OCB_A22' U351-F8 # L23N-0 2.5V I/O NET 'OCB_A21' U351-A9 # L18P-0 2.5V I/O NET 'OCB_A20' U351-B9 # L19P-0 2.5V I/O NET 'OCB_A19' U351-C9 # L19N-0 2.5V I/O NET 'OCB_A18' U351-E9 # L22P-0 2.5V I/O NET 'OCB_A17' U351-F9 # L22N-0 2.5V I/O NET 'OCB_DS_B' U351-A10 # L16P-0 2.5V I/O NET 'OCB_WRITE_B' U351-C10 # L16N-0 2.5V I/O NET 'OCB_SYS_RESET_B' U351-D10 # L17P-0 2.5V I/O NET 'OCB_GEO_ADRS_0' U351-E10 # L17N-0 2.5V I/O NET 'OCB_GEO_ADRS_4' U351-E11 # L15N-0 2.5V I/O NET 'OCB_GEO_ADRS_5' U351-D11 # L15P-0 2.5V I/O NET 'OCB_GEO_ADRS_6' U351-C11 # L14N-0 2.5V I/O NET 'OCB_A16' U351-B11 # L14P-0 2.5V I/O NET 'OCB_A15' U351-F12 # L12N-0 2.5V I/O NET 'OCB_A14' U351-D12 # L12P-0 2.5V I/O NET 'OCB_A13' U351-C12 # L11N-0 2.5V I/O NET 'OCB_A12' U351-B12 # L13P-0 2.5V I/O NET 'OCB_A11' U351-A12 # L13N-0 2.5V I/O NET 'OCB_A10' U351-F13 # L09N-0 2.5V I/O NET 'OCB_A09' U351-E13 # L09P-0 2.5V I/O NET 'OCB_A08' U351-C13 # L10N-0 2.5V I/O NET 'OCB_A07' U351-B13 # L11P-0 2.5V I/O NET 'OCB_A06' U351-D14 # L10P-0 2.5V I/O NET 'OCB_A05' U351-C14 # L07P-0 2.5V I/O NET 'OCB_A04' U351-A14 # L07N-0 2.5V I/O NET 'OCB_A03' U351-C15 # L06N-0 2.5V I/O NET 'OCB_A02' U351-B15 # L08P-0 2.5V I/O NET 'OCB_A01' U351-A15 # L08N-0 2.5V I/O # # If the OCB signals were all layout out on one layer in # their natural order they would appear as vertical traces # running down on the East side of the BSPT, BF, and TP # FPGAs. In their natural order the signals going from # West to East are: # # GA1:GA3, D00:D15, A23:A17, DS_B, Write_B, Reset_B, # GA0, GA4:GA6, A16:A01 # # # CMX-0 Nets File # # BSPT_FPGA TTCDec Signals Nets # -------------======---------------- # # # Original Rev. 11-Nov-2012 # Most Recent Rev. 20-Jun-2013 Swap BUF_TTC_SUB_ADRS_4 and _5 to help trace layout # # # # This file holds all of the nets that connect the # Board Support FPGA with the TTCDec Mezzanine Card # # # Notes: # # - The TTCDec Output signals are translated to 2.5V CMOS # level and series terminated before being send on a bus # to the BSPT_FPGA (with taps to BF and TP FPGAs as needed). # # # The components referenced in this file are: # # U351 the BSPT_FPGA # # # TTCDec Outputs # # Buffered, Series Terminated, 2.5V TTC Output Bus # Signal Pins on the Board Support FPGA # # These signals will travel north on layer 6 and west on layer 7 NET 'BUF_TTC_BRCST_2' U351-P15 #> T06 # Buffered TTC_BRCST_2 NET 'BUF_TTC_BRCST_3' U351-P14 #> T06 # Buffered TTC_BRCST_3 NET 'BUF_TTC_BRCST_4' U351-N14 #> T06 # Buffered TTC_BRCST_4 NET 'BUF_TTC_BRCST_5' U351-M16 #> T06 # Buffered TTC_BRCST_5 NET 'BUF_TTC_BRCST_6' U351-M15 #> T06 # Buffered TTC_BRCST_6 NET 'BUF_TTC_BRCST_7' U351-M14 #> T06 # Buffered TTC_BRCST_7 NET 'BUF_TTC_BRCST_STR_1' U351-M13 #> T06 # Buffered TTC_BRCST_STR_1 NET 'BUF_TTC_BRCST_STR_2' U351-L15 #> T06 # Buffered TTC_BRCST_STR_2 NET 'BUF_TTC_SIN_ERR_STR' U351-L14 #> T06 # Buffered TTC_SIN_ERR_STR NET 'BUF_TTC_DB_ERR_STR' U351-L13 #> T06 # Buffered TTC_DB_ERR_STR NET 'BUF_TTC_CLK_40_L1A' U351-K14 #> T06 # Buffered TTC_CLK_40_L1A NET 'BUF_TTC_BNCH_CNT_RES' U351-K15 #> T06 # Buffered TTC_BNCH_CNT_RES NET 'BUF_TTC_EV_CNT_RES' U351-K16 #> T06 # Buffered TTC_EV_CNT_RES NET 'BUF_TTC_EV_CNT_H_STR' U351-K18 #> T06 # Buffered TTC_EV_CNT_H_STR NET 'BUF_TTC_EV_CNT_L_STR' U351-K20 #> T06 # Buffered TTC_EV_CNT_L_STR NET 'BUF_TTC_BNCH_CNT_STR' U351-J13 #> T06 # Buffered TTC_BNCH_CNT_STR NET 'BUF_TTC_B_CNT_0' U351-J14 #> T06 # Buffered TTC_B_CNT_0 NET 'BUF_TTC_B_CNT_1' U351-J15 #> T06 # Buffered TTC_B_CNT_1 NET 'BUF_TTC_B_CNT_2' U351-J16 #> T06 # Buffered TTC_B_CNT_2 NET 'BUF_TTC_B_CNT_3' U351-J17 #> T06 # Buffered TTC_B_CNT_3 NET 'BUF_TTC_B_CNT_4' U351-J18 #> T06 # Buffered TTC_B_CNT_4 NET 'BUF_TTC_B_CNT_5' U351-J19 #> T06 # Buffered TTC_B_CNT_5 NET 'BUF_TTC_B_CNT_6' U351-J20 #> T06 # Buffered TTC_B_CNT_6 NET 'BUF_TTC_B_CNT_7' U351-H14 #> T06 # Buffered TTC_B_CNT_7 NET 'BUF_TTC_B_CNT_8' U351-H15 #> T06 # Buffered TTC_B_CNT_8 NET 'BUF_TTC_B_CNT_9' U351-H17 #> T06 # Buffered TTC_B_CNT_9 NET 'BUF_TTC_B_CNT_10' U351-H18 #> T06 # Buffered TTC_B_CNT_10 NET 'BUF_TTC_B_CNT_11' U351-H19 #> T06 # Buffered TTC_B_CNT_11 NET 'BUF_TTC_DQ_0' U351-H20 #> T06 # Buffered TTC_DQ_0 NET 'BUF_TTC_DQ_1' U351-G14 #> T06 # Buffered TTC_DQ_1 NET 'BUF_TTC_DQ_2' U351-G15 #> T06 # Buffered TTC_DQ_2 NET 'BUF_TTC_DQ_3' U351-G16 #> T06 # Buffered TTC_DQ_3 NET 'BUF_TTC_L1_ACCEPT' U351-G17 #> T06 # Buffered TTC_L1_ACCEPT NET 'BUF_TTC_SER_B_CH' U351-G18 #> T06 # Buffered TTC_SER_B_CH NET 'BUF_TTC_D_OUT_STR' U351-G20 #> T06 # Buffered TTC_D_OUT_STR NET 'BUF_TTC_READY' U351-F16 #> T06 # Buffered TTC_READY (STATUS_1) NET 'BUF_TTC_STATUS_2' U351-F17 #> T06 # Buffered TTC_STATUS_2 NET 'BUF_TTC_D_OUT_0' U351-F18 #> T06 # Buffered TTC_D_OUT_0 NET 'BUF_TTC_D_OUT_1' U351-F19 #> T06 # Buffered TTC_D_OUT_1 NET 'BUF_TTC_D_OUT_2' U351-F20 #> T06 # Buffered TTC_D_OUT_2 NET 'BUF_TTC_D_OUT_3' U351-E18 #> T06 # Buffered TTC_D_OUT_3 NET 'BUF_TTC_D_OUT_4' U351-E19 #> T06 # Buffered TTC_D_OUT_4 NET 'BUF_TTC_D_OUT_5' U351-E20 #> T06 # Buffered TTC_D_OUT_5 NET 'BUF_TTC_D_OUT_6' U351-D18 #> T06 # Buffered TTC_D_OUT_6 NET 'BUF_TTC_D_OUT_7' U351-D20 #> T06 # Buffered TTC_D_OUT_7 NET 'BUF_TTC_SUB_ADRS_0' U351-C19 #> T06 # Buffered TTC_SUB_ADRS_0 NET 'BUF_TTC_SUB_ADRS_1' U351-C20 #> T06 # Buffered TTC_SUB_ADRS_1 NET 'BUF_TTC_SUB_ADRS_2' U351-B19 #> T06 # Buffered TTC_SUB_ADRS_2 NET 'BUF_TTC_SUB_ADRS_3' U351-B20 #> T06 # Buffered TTC_SUB_ADRS_3 NET 'BUF_TTC_SUB_ADRS_4' U351-B18 #> T06 # Buffered TTC_SUB_ADRS_4 NET 'BUF_TTC_SUB_ADRS_5' U351-A18 #> T06 # Buffered TTC_SUB_ADRS_5 NET 'BUF_TTC_SUB_ADRS_6' U351-D17 #> T06 # Buffered TTC_SUB_ADRS_6 NET 'BUF_TTC_SUB_ADRS_7' U351-C17 #> T06 # Buffered TTC_SUB_ADRS_7 ##NET 'BUF_TTC_Spare_1_3' U351-xyz # Buffered TTC_Spare_1_3 ##NET 'BUF_TTC_Spare_2_3' U351-xyz # Buffered TTC_Spare_2_3 ##NET 'BUF_TTC_Spare_3_3' U351-xyz # Buffered TTC_Spare_3_3 # # The 3.3V logic level connections with the TTCDec # will be to I/O Bank #3 on the BSPT_FPGA # # Input Control Signals to the TTCDec # # The TTCDec receives 3 control type signals from the # the Board Support FPGA. These are 3.3V CMOS signals. # NET 'TTC_PD' U351-T4 #> T06 # Clock Changeover Mode: Protected or DeBug NET 'TTC_CLK_SEL' U351-U1 #> T06 # Select 40 MHz rock or TTCrx clock source NET 'TTC_RESET_B' U351-T3 #> T06 # Reset the TTCrx ASIC # # I2C Bus Signals to the TTCDec # # The TTCDec has an I2C Bus connection with the Board # Support FPGA. The 2 lines of the I2C Bus are 3.3V CMOS signals. # # These 2 signals have series terminator resistors # R324 and R325 near the Board Support FPGA. # NET 'ST_TTC_SCL' U351-V1 R324-2 # I2C Serial Clock BSPT_FPGA --> Series Term NET 'TTC_SCL' R324-1 #> T06 # I2C Serial Clock Series Term --> TTCDec NET 'ST_TTC_SDA' U351-U3 R325-2 # I2C Serail Data BSPT <-> Series Term NET 'TTC_SDA' R325-1 #> T06 # I2C Serail Data Series Term <-> TTCDec # # Control Enabling of the Outputs on the translator/buffer # chips U151:U154 (only 1/2 of the U154) that drive the # TTCDec Output Bus. NET 'BSPT_TTC_TRNSLT_OE_B' U351-G3 # Control signal from the BSPT # FPGA to the Hardwired Oversight # Logic and then to the TTCDec # Translators. The signal from # U363 in the Oversight Logic to # the TTCDec Translators is # named: TTC_TRNSLT_OE_B. # # Control Enabling the Output of the section of the # translator/buffer chip U154 that drives the Geo_Adrs # onto some Chip_ID lines when the TTCDec is being Reset. # For now this is just sketched to place holder U998. NET 'BSPT_TTC_RESET_TRNSLT_OE_B' U351-G1 # Control signal from the BSPT # FPGA to the Hardwired Oversight # Logic and then to the TTCDec # Translators. The signal from # U358 in the Oversight Logic to # the TTCDec Translators is # named: TTC_RESET_TRNSLT_OE_B. # # CMX-0 Nets File # # # CONFIGURATION Nets # ---------------------- # # # Original Rev. 3-Jan-2013 # Most Recent Rev. 7-Apr-2013 # # # # This file holds most of the nets that are involved with # the CONFIGURATION of the Virtex FPGAs; Base Function and # Topological Processor. # # - Many of these nets involve connections to the System-ACE # chip or the Board Support FPGA. # # - Most of these Virtex FPGA nets are from Bank #0 and # their pin connections are given in: # # .../Base_Fpga_Power/bf_fpga_ff1759_bank_0_and_special_n2p.txt # # .../TP_Fpga_Power/tp_fpga_ff1759_bank_0_and_special_n2p.txt # # # These are all 2.5V CMOS level nets. # # # This file includes Jumpers to separately contor the M2, # M1, M0 pins on both of the Virtex-6 FPGAs. # # This file also includes jumpers that connect the INIT_B # signal from the 2 Virtex-6 FPGAs to the System-ACE # CFGINIT_B input pin. This circuit includes a 4.7k Ohm # pull-up to 2.5V on the CFGINIT_B signal - R334. # # This file also includes connections to the Virtex FPGA # PROG_B and DONE pins. # # Finally there is a list of Virtex Configuration pins # that are not used in the CMX design. # # # The components involved in this Net List file are: # # U1, U2 Virtex FPGAs # U321 System-ACE # U351 Board Support Spartan 3A FPGA # JMP31:JMP36 BF FPGA M2,M1,M0 jumpers # JMP41:JMP46 TP FPGA M2,M1,M0 jumpers # JMP75, JMP76 INIT_B Select Jumpers # R334, R335 4.7k Pull-Up resistors on BF and TP INIT_B # R336, R337 4.7k Pull-Up resistors on BF and TP PROG_B # R338, R339 1.0k Pull-Up resistors on BF and TP DONE # R341, R342 4.7k Pull-Up resistors on BF and TP CCLK # R343, R344 4.7k Pull-Up resistors on BF and TP DIN # R345, R346 4.7k Pull-Up resistors on BF and TP CSI_B # R347, R348 4.7k Pull-Dn resistors on BF and TP RDWR_B # # # Start with the M2, M1, M0 Jumpers that control the # Configuration of the Base Function FPGA. Pin Numbers: AL10, AM11, AL11 NET 'BF_M2' JMP31-1 JMP32-2 # BF M2 Control JMP31 is Pull-Down NET 'BF_M1' JMP33-1 JMP34-2 # BF M1 Control JMP33 is Pull-Down NET 'BF_M0' JMP35-1 JMP36-2 # BF M0 Control JMP35 is Pull-Down NET 'GROUND' JMP31-2 JMP33-2 JMP35-2 # Ground the Pull-Down Jumpers NET 'BULK_2V5' JMP32-1 JMP34-1 JMP36-1 # Tie the Pull-Ups to BULK_2V5 # # Now the M2, M1, M0 Jumpers that control the # Configuration of the Topological FPGA. Pin Numbers: AL10, AM11, AL11 NET 'TP_M2' JMP41-1 JMP42-2 # TP M2 Control JMP41 is Pull-Down NET 'TP_M1' JMP43-1 JMP44-2 # TP M1 Control JMP43 is Pull-Down NET 'TP_M0' JMP45-1 JMP46-2 # TP M0 Control JMP45 is Pull-Down NET 'GROUND' JMP41-2 JMP43-2 JMP45-2 # Ground the Pull-Down Jumpers NET 'BULK_2V5' JMP42-1 JMP44-1 JMP46-1 # Tie the Pull-Ups to BULK_2V5 # # BF and TP PROGRAM_B Pins pin number M11 # # PROGRAM_B is an Input pin with a permanent internal # weak pull-up. Normally the user pulses this pin Low # to initiate configuration. But on the CMX card this # FPGA is only configuraed via JTAG from the System-ACE # and this method does not require pulling PROGRAM_B Low # to initiate configuration. On CMX the Virtex PROGRAM_B # pin will be pulled up and connected to an input pin on # the BSPT FPGA just in case we need to pulse PROGRAM_B. # CMX will use a 4.7k Ohm pull-up to BULK_2V5. # NET 'BF_PROGRAM_B' R336-1 # BF PROG_B Pull-Up NET 'BF_PROGRAM_B' U351-V20 # BF PROG_B connection to the BSPT NET 'TP_PROGRAM_B' R337-1 # TP PROG_B Pull-Up NET 'TP_PROGRAM_B' U351-T15 # TP PROG_B connection to the BSPT NET 'BULK_2V5' R336-2 R337-2 # Tie to 2.5 Volts the Pull-Up Resistors # The PROG_B nets on the Base Function and Topological Processor # FPGAs are connected to pins in their Bank #0 n2p file. # # # BF and TP INIT_B Pins pin number N11 # # Now connect the INIT_B pins from the Base Function and # from the Topological Processor FPGAs to the CFGINIT_B pin # on the System-ACE chip, i.e. pin 78. This is done with # Jumpers JMP75 and JMP76 so that you can control which FPGA # INIT_B signal(s) the System-ACE sees. Seperately pull-up # each of the Virtex FPGA INIT_B pins with a 4.7k Ohm resistor. # From each of the Virtex FPGA INIT_B pins run a line to an # input on the Board Support FPGA so that it/we can monitor # the state of these FPGA INIT_B pins. # NET 'BF_INIT_B' JMP75-1 # BF FPGA INIT_B_0 to Jumper NET 'BF_INIT_B' R334-1 # Pull-Up on the BF INIT_B pin NET 'BF_INIT_B' U351-N12 # BF FPGA INIT_B_0 to Input pin on BSPT NET 'TP_INIT_B' JMP76-1 # TP FPGA INIT_B_0 to Jumper NET 'TP_INIT_B' R335-1 # Pull-Up on the TP INIT_B pin NET 'TP_INIT_B' U351-R10 # TP FPGA INIT_B_0 to Input pin on BSPT NET 'ACE_CFG_INIT_B' JMP75-2 JMP76-2 # Sys-ACE Configuration JTAG INIT input Vccl NET 'BULK_2V5' R334-2 R335-2 # Tie to 2.5 Volts the Pull-Up Resistors # The INIT_B nets on the Base Function and Topological Processor # FPGAs are connected to pins in their Bank #0 n2p file. # # # BF and TP DONE Pins pin number N10 # # DONE is a complicated Bidirectional normally open-drain # pin. DONE can also be setup as a driven output pin. # Its basic function is to indicate that the FPGA has been # successfully Configured. DONE goes HI when the FPGA # has successfully been Configured. The DONE pin needs # to have an external Pull-Up resistor. Xilinx often # uses a strong pull-up current on the DONE pin, # e.g. a 330 Ohm resistor. For now on CMX we will use # a 1k Ohm pull-up resistor. On CMX DONE is routed to # an input pin on the BSPT FPGA. On CMX we should use # the Bit-Gen option that makes DONE an open-drain pin # (not a driven pin). # NET 'BF_CONFIG_DONE' R338-1 # BF DONE Pull-Up NET 'BF_CONFIG_DONE' U351-P12 # BF DONE connection to a BSPT input NET 'TP_CONFIG_DONE' R339-1 # TP DONE Pull-Up NET 'TP_CONFIG_DONE' U351-P10 # TP DONE connection to a BSPT input NET 'BULK_2V5' R338-2 R339-2 # Tie to 2.5 Volts the Pull-Up Resistors # The PROG_B nets on the Base Function and Topological Processor # FPGAs are connected to pins in their Bank #0 n2p file. # # # Unused Virtex Configuration pins in the CMX design # # BF and TP CCLK Pins pin number K10 # # This pin is not used in the Configuration method # that will be used on CMX for this FPGA. This pin # can be either an input or a driven output in other # configuration modes. So far I have found nothing # in the Virtex documentation that say what we should # do with this pin when it is not used. It is not # safe to let a CMOS input just float. On CMX I # will run this to a Pull-Up resistor. # NET 'BF_CCLK' R341-1 # BF CCLK Pull-Up NET 'TP_CCLK' R342-1 # TP CCLK Pull-Up NET 'BULK_2V5' R341-2 R342-2 # Tie to 2.5 Volts the Pull-Up Resistors # The CCLK nets on the Base Function and Topological Processor # FPGAs are connected to pins in their Bank #0 n2p file. # # BF and TP DIN Pins pin number L10 # # This is an input pin for serial mode Configuration data. # This pin is not used in the Configuration method that # will be used on CMX card for this FPGA. So far I have # found nothing in the Virtex documentation that say what # we should do with this pin when it is not used. It is # not safe to let a CMOS input just float. On CMX I # will run this to a Pull-Up resistor. # NET 'BF_DIN' R343-1 # BF DIN Pull-Up NET 'TP_DIN' R344-1 # TP DIN Pull-Up NET 'BULK_2V5' R343-2 R344-2 # Tie to 2.5 Volts the Pull-Up Resistors # The DIN nets on the Base Function and Topological Processor # FPGAs are connected to pins in their Bank #0 n2p file. # # BF and TP DOUT_BUSY Pins pin number AK10 # # This is in Output pin. This signal is not used in # the method that CMX will use to configure this FPGA. # We have no use for this pin in the CMX design. Thus # we will permanently and irrevocably connect nothing # to this pin. This pins will not have a via. # # BF and TP CSI_B Pins pin number T10 # # This is an Input. It is used to enable or disable # SelectMAP data bus during SelectMAP Configuration. # CMX will not use this methode for Configuration. # So far I have found nothing in the Virtex documentation # that say what we should do with this pin when it is not # used. It is not safe to let a CMOS input just float. # On CMX I will run this to a Pull-Up resistor. Pulling # Hi disables the unused SelectMAP Bus. # NET 'BF_CSI_B' R345-1 # BF CSI_B Pull-Up NET 'TP_CSI_B' R346-1 # TP CSI_B Pull-Up NET 'BULK_2V5' R345-2 R346-2 # Tie to 2.5 Volts the Pull-Up Resistors # The CSI_B nets on the Base Function and Topological Processor # FPGAs are connected to pins in their Bank #0 n2p file. # # BF and TP RDWR_B Pins pin number J10 # # This is an Input. It is used to control the direction # of the SelectMAP data bus. CMX will not use this methode # for Configuration. So far I have found nothing in the # Virtex documentation that say what we should do with this # pin when it is not used. It is not safe to let a CMOS # input just float. On CMX I will run this to a Pull-Down # resistor. Pulling Low makes the SelectMAP Bus an input. # NET 'BF_RDWR_B' R347-1 # BF RDWR_B Pull-Down NET 'TP_RDWR_B' R348-1 # TP RDWR_B Pull-Down NET 'GROUND' R347-2 R348-2 # Tie to Ground # The RDWR_B nets on the Base Function and Topological Processor # FPGAs are connected to pins in their Bank #0 n2p file. # # # CMX-0 Nets File # # # BULK_3V3 DC/DC Power Converter # --========------------------------- # # # Original Rev. 20-Dec-2012 # Most Recent Rev. 5-June-2013 # # # # This file holds the nets in the BULK_3V3 # DC/DC Power Converter. # # # From the left this is the 2nd converter. # # Components with Reference Designators in the range # # 1551:1599 are included in the BULK_3V3 Converter. # # # # Define the Connections within the BULK_3V3 Power Converter # ------------------------------------========------------------ # # # Input Power to the Converter: NET 'BULK_5V0' R1551-3 # Power to the Current Sense Resistor NET 'BULK_3V3_CS_TO_L' R1551-2 # Power from the Current Sense NET 'BULK_3V3_CS_TO_L' L1551-1 # Resistor to the Filter Inductor NET 'BULK_3V3_INPUT' L1551-2 # Power feed to the Converter NET 'BULK_3V3_INPUT' C1551-1 # Aluminum Input Cap NET 'BULK_3V3_INPUT' C1553-1 C1554-1 # Taltalum Input Caps NET 'BULK_3V3_INPUT' C1559-1 C1560-1 # Ceramic Input Caps NET 'BULK_3V3_INPUT' C1561-1 C1562-1 # Ceramic Input Caps NET 'BULK_3V3_INPUT' DCDC2-1 # Power Input to the Converter NET 'GROUND' C1551-2 # Aluminum Cap Ground NET 'GROUND' C1553-2 C1554-2 # Taltalum Cap Grounds NET 'GROUND' C1559-2 C1560-2 # Ceramic Cap Grounds NET 'GROUND' C1561-2 C1562-2 # Ceramic Cap Grounds # # Power Output from the Converter: NET 'BULK_3V3' DCDC2-4 # Output Power from the Converter NET 'BULK_3V3' C1567-1 C1568-1 # Ceramic Output Caps NET 'BULK_3V3' C1569-1 C1570-1 # Ceramic Output Caps NET 'BULK_3V3' C1575-1 C1576-1 # Taltalum Output Caps NET 'BULK_3V3' C1577-1 C1578-1 # Taltalum Output Caps NET 'BULK_3V3' C1579-1 C1580-1 # Taltalum Output Caps NET 'GROUND' C1567-2 C1568-2 # Ceramic Cap Grounds NET 'GROUND' C1569-2 C1570-2 # Ceramic Cap Grounds NET 'GROUND' C1575-2 C1576-2 # Taltalum Cap Grounds NET 'GROUND' C1577-2 C1578-2 # Taltalum Cap Grounds NET 'GROUND' C1579-2 C1580-2 # Taltalum Cap Grounds # # DC/DC Converter GROUND Pins NET 'GROUND' DCDC2-2 DCDC2-3 # Converter Grounds # # DC/DC Converter Tracking and Feedback Sense Pins NET 'DCDC_CONV_TRACK' DCDC2-9 # TRACK Pin of BULK_3V3 Converter NET 'BULK_3V3' AKA1551-1 # Positive SENSE Remote Connection NET 'BULK_3V3_SEN_POS' AKA1551-2 DCDC2-5 # Positive SENSE input pin NET 'GROUND' AKA1552-1 # Negative SENSE Remote Connection NET 'BULK_3V3_SEN_NEG' AKA1552-2 DCDC2-6 # Negative SENSE input pin # # DC/DC Converter Output Voltage Rset Resistor # with capacitor across the variable part of the Vout Rset Resistor NET 'BULK_3V3_SEN_NEG' R1555-1 R1555-2 # Want Trim Pot CW Truning to: NET 'BULK_3V3_VAR_FIX' R1555-3 # Reduce the Resistance and NET 'BULK_3V3_VAR_FIX' R1554-1 # Increase the Output Voltage NET 'BULK_3V3_VO_ADJ' R1554-2 DCDC2-7 # Converter Rset Vout Adj pin NET 'BULK_3V3_SEN_NEG' C1582-1 # Capacitor across the NET 'BULK_3V3_VAR_FIX' C1582-2 # Vout Trim Pot Resistor # # DC/DC Converter Transient Response Control Pin NET 'BULK_3V3_SEN_POS' R1556-2 # Transient Response Resistor NET 'BULK_3V3_TRC_PIN' R1556-1 DCDC2-8 # Transient Response Control pin # # DC/DC Converter NO Connect Pins NET 'No_Conn_DCDC2_10_INH' DCDC2-10 # INH / UVLO Pin #10 Not Used NET 'No_Conn_DCDC2_11_SYNC' DCDC2-11 # SYNC Pin #11 Not Used # # Current Sense High-Side Amplifier NET 'BULK_3V3_CS_SRC' R1551-4 R1552-2 # Current Sense Source Input Resistor NET 'BULK_3V3_CS_AMP_P' U1551-8 R1552-1 # Current Sense Amp Positive Input NET 'BULK_3V3_CS_LOAD' R1551-1 R1553-2 # Current Sense Load Input Resistor NET 'BULK_3V3_CS_AMP_N' U1551-1 R1553-1 # Current Sense Amp Negative Input NET 'BULK_3V3_CS_AMP_OUT' U1551-5 # Current Sense Amp Output NET 'BULK_3V3' U1551-2 C1581-2 # Current Sense Amp V+ Power NET 'GROUND' U1551-4 C1581-1 # Current Sense Amp GROUND NET 'No_Conn_BULK_3V3_CS_AMP_P3' U1551-3 # Current Sense Amp No Conn Pin #3 NET 'No_Conn_BULK_3V3_CS_AMP_P6' U1551-6 # Current Sense Amp No Conn Pin #6 NET 'No_Conn_BULK_3V3_CS_AMP_P7' U1551-7 # Current Sense Amp No Conn Pin #7 # # CMX-0 Nets File # # BSPT_FPGA System-ACE Nets # -------------==========-------- # # # Original Rev. 13-Nov-2012 # Most Recent Rev. 7-July-2013 # # # # This file holds all of the nets that connect the # Board Support FPGA with the System-ACE chip. # # # Notes: # # - In the System-ACE documents this is typically called # the MPU connection to the System-ACE. # # - All of these MPU connections with the System-ACE # are 2.5V CMOS signal levels. # # - Note that the BSPT FPGA supplies the 20 MHz clock # to the MPU Port of the System-ACE. In this way # the activities in the BSPT FPGA that talk to the # MPU Port can be synchronous with the clock that # goes to the ACE MPU Port. This is a 20 MHz # 2.5V CMOS signal. # # - After these MPU connections this file will then # include some FPGA Configuration management signal # connections with the System-ACE. These are also # handled by the Board Support FPGA and are 2.5V # signals. # # - The MPU signals between the System-ACE and the BSPT # FPGA are series terminated near the BSPT. The # bi-directional MPU data lines are series terminated # at both ends. # # # The components referenced in this file include: # # U321 the System-ACE # U351 the BSPT_FPGA # # N361:N366 8 Resistor 47 Ohm Networks # # # All of these BSPT pins are 2.5V I/O except for # 3 pins that are 2.5V Input-Only: # # ACE_MPIRQ is U351-P9 2.5V In-Only # ACE_MPBRDY is U351-N9 2.5V In-Only # ACE_CFG_INIT_B is U351-P8 2.5V In-Only # # # A rational order in which to land the System-ACE signals # in Bank #2 of the BSPT FPGA starting in the S.W. corner # is the following: # # BSPT_ACE_CLK, ACE_ERRLED_B, ACE_STATLED_B, # ACE_CFG_MODE, # ACE_CFG_ADRS_2, ACE_CFG_ADRS_1, ACE_CFG_ADRS_0, # ACE_CFG_INIT_B, # ACE_MPOE_B, ACE_MPWE_B, # ACE_MP_ADRS_0, ACE_MP_ADRS_1, ACE_MP_ADRS_2, ACE_MP_ADRS_3, # ACE_MP_DATA_00, ACE_MP_DATA_01, ACE_MP_DATA_02, ACE_MP_DATA_03, # ACE_MP_DATA_04, ACE_MP_DATA_05, ACE_MP_DATA_06, ACE_MP_DATA_07, # ACE_MP_DATA_08, ACE_MP_DATA_09, ACE_MP_DATA_10, ACE_MP_DATA_11, # ACE_MP_DATA_12, ACE_MP_DATA_13, ACE_MP_DATA_14, ACE_MP_DATA_15, # ACE_MP_ADRS_4, ACE_MP_ADRS_5, ACE_MP_ADRS_6, ACE_MPCE_B' # ACE_MPIRQ, ACE_MPBRDY, # ACE_RESET_B' # # # The signals that need series termination between the # System-ACE and the BSPT FPGA are the following: # # BSPT_ACE_CLK, # # ACE_MPOE_B, ACE_MPWE_B, ACE_MPCE_B', ACE_MPIRQ, ACE_MPBRDY # # ACE_MP_ADRS_0, ACE_MP_ADRS_1, ACE_MP_ADRS_2, ACE_MP_ADRS_3, # ACE_MP_ADRS_4, ACE_MP_ADRS_5, ACE_MP_ADRS_6, # # ACE_MP_DATA_00, ACE_MP_DATA_01, ACE_MP_DATA_02, ACE_MP_DATA_03, # ACE_MP_DATA_04, ACE_MP_DATA_05, ACE_MP_DATA_06, ACE_MP_DATA_07, # ACE_MP_DATA_08, ACE_MP_DATA_09, ACE_MP_DATA_10, ACE_MP_DATA_11, # ACE_MP_DATA_12, ACE_MP_DATA_13, ACE_MP_DATA_14, ACE_MP_DATA_15 # # # MPU Connections between BSPT_FPGA and the System-ACE # ------------------------------------------------------ # # System-ACE Clock Generated by the BSPT FPGA 20 MHz 2.5V CMOS NET 'BSPT_ACE_CLK' U351-V14 # 20 MHz Clock signal to the System-ACE # # Define some Control, Status, and LED pins on the System-ACE NET 'ACE_RESET_B' U351-W14 # System-ACE RESET input Vccl Int_PU NET 'ACE_STATLED_B' U351-T6 # System-ACE Status LED output pin open-drain NET 'ACE_ERRLED_B' U351-U6 # System-ACE Error LED output pin open-drain # # Define the MPU interface pins on the System-ACE # NET 'BSPT_ACE_MPCE_B' U351-W6 # System-ACE MP Chip Enable _B input Vccl Int_PU NET 'BSPT_ACE_MPWE_B' U351-R7 # System-ACE MP Write Enable _B input Vccl Int_PU NET 'BSPT_ACE_MPOE_B' U351-W8 # System-ACE MP Output Enable _B input Vccl Int_PU NET 'BSPT_ACE_MPIRQ' U351-N9 # System-ACE MP Interrupt Request output Vccl In-Only NET 'BSPT_ACE_MPBRDY' U351-P9 # System-ACE MP Data Buffer Ready output Vccl In-Only NET 'BSPT_ACE_MP_ADRS_0' U351-Y13 # System-ACE MP Address 0 input Vccl NET 'BSPT_ACE_MP_ADRS_1' U351-T14 # System-ACE MP Address 1 input Vccl NET 'BSPT_ACE_MP_ADRS_2' U351-W13 # System-ACE MP Address 2 input Vccl NET 'BSPT_ACE_MP_ADRS_3' U351-V9 # System-ACE MP Address 3 input Vccl NET 'BSPT_ACE_MP_ADRS_4' U351-W9 # System-ACE MP Address 4 input Vccl NET 'BSPT_ACE_MP_ADRS_5' U351-Y9 # System-ACE MP Address 5 input Vccl NET 'BSPT_ACE_MP_ADRS_6' U351-T8 # System-ACE MP Address 6 input Vccl NET 'BSPT_ACE_MP_DATA_00' U351-V13 # System-ACE MP Data 00 in/out Vccl NET 'BSPT_ACE_MP_DATA_01' U351-U13 # System-ACE MP Data 01 in/out Vccl NET 'BSPT_ACE_MP_DATA_02' U351-T13 # System-ACE MP Data 02 in/out Vccl NET 'BSPT_ACE_MP_DATA_03' U351-R13 # System-ACE MP Data 03 in/out Vccl NET 'BSPT_ACE_MP_DATA_04' U351-Y12 # System-ACE MP Data 04 in/out Vccl NET 'BSPT_ACE_MP_DATA_05' U351-W12 # System-ACE MP Data 05 in/out Vccl NET 'BSPT_ACE_MP_DATA_06' U351-T12 # System-ACE MP Data 06 in/out Vccl NET 'BSPT_ACE_MP_DATA_07' U351-R12 # System-ACE MP Data 07 in/out Vccl NET 'BSPT_ACE_MP_DATA_08' U351-Y11 # System-ACE MP Data 08 in/out Vccl NET 'BSPT_ACE_MP_DATA_09' U351-V11 # System-ACE MP Data 09 in/out Vccl NET 'BSPT_ACE_MP_DATA_10' U351-T10 # System-ACE MP Data 10 in/out Vccl NET 'BSPT_ACE_MP_DATA_11' U351-U10 # System-ACE MP Data 11 in/out Vccl NET 'BSPT_ACE_MP_DATA_12' U351-V10 # System-ACE MP Data 12 in/out Vccl NET 'BSPT_ACE_MP_DATA_13' U351-W10 # System-ACE MP Data 13 in/out Vccl NET 'BSPT_ACE_MP_DATA_14' U351-T9 # System-ACE MP Data 14 in/out Vccl NET 'BSPT_ACE_MP_DATA_15' U351-U9 # System-ACE MP Data 15 in/out Vccl # # Define signals that control FPGA Configuration by the System-ACE # NET 'ACE_CFG_INIT_B' U351-P8 # Sys-ACE Configuration JTAG INIT input Vccl NET 'ACE_CFG_ADRS_0' U351-T7 # Sys-ACE Config Address Select 0 input Vccl Init_PD NET 'ACE_CFG_ADRS_1' U351-Y7 # Sys-ACE Config Address Select 1 input Vccl Init_PD NET 'ACE_CFG_ADRS_2' U351-V7 # Sys-ACE Config Address Select 2 input Vccl Init_PD NET 'ACE_CFG_MODE' U351-U7 # Sys-ACE Config Mode Pin input Vccl Init_PU # # Define the connections through the Series Terminator # Resistor Networks N361 : N364 # # Resistor Network N361 Clock and Control Signals: NET 'GROUND' N361-16 # Guard NET 'GROUND' N361-1 # Guard NET 'BSPT_ACE_MPCE_B' N361-15 # BSPT ACE Clock Output to NET 'ACE_MPCE_B' N361-2 # run to the System-ACE NET 'GROUND' N361-14 # Guard the Clock signal NET 'GROUND' N361-3 # Guard the Clock signal NET 'BSPT_ACE_MPWE_B' N361-13 # MPWE_B from the BSPT NET 'ACE_MPWE_B' N361-4 # to the System-ACE NET 'GROUND' N361-12 # Guard NET 'GROUND' N361-5 # Guard NET 'BSPT_ACE_MPOE_B' N361-11 # MPOE_B from the BSPT NET 'ACE_MPOE_B' N361-6 # to the System-ACE NET 'GROUND' N361-10 # Guard NET 'GROUND' N361-7 # Guard NET 'BSPT_ACE_CLK' N361-9 # MPCE_B from the BSPT NET 'ACE_CLOCK' N361-8 # to the System-ACE # Resistor Network N362 MPU Address Lines: NET 'BSPT_ACE_MP_ADRS_6' N362-16 # MP_ADRS_6 from BSPT NET 'ACE_MP_ADRS_6' N362-1 # to the System-ACE NET 'BSPT_ACE_MP_ADRS_5' N362-15 # MP_ADRS_5 from BSPT NET 'ACE_MP_ADRS_5' N362-2 # to the System-ACE NET 'BSPT_ACE_MP_ADRS_4' N362-14 # MP_ADRS_4 from BSPT NET 'ACE_MP_ADRS_4' N362-3 # to the System-ACE NET 'BSPT_ACE_MP_ADRS_3' N362-13 # MP_ADRS_3 from BSPT NET 'ACE_MP_ADRS_3' N362-4 # to the System-ACE NET 'GROUND' N362-12 # Guard NET 'GROUND' N362-5 # Guard NET 'BSPT_ACE_MP_ADRS_2' N362-11 # MP_ADRS_2 from BSPT NET 'ACE_MP_ADRS_2' N362-6 # to the System-ACE NET 'BSPT_ACE_MP_ADRS_0' N362-10 # MP_ADRS_0 from BSPT NET 'ACE_MP_ADRS_0' N362-7 # to the System-ACE NET 'BSPT_ACE_MP_ADRS_1' N362-9 # MP_ADRS_1 from BSPT NET 'ACE_MP_ADRS_1' N362-8 # to the System-ACE # Resistor Network N363 Hi Order MPU Data Lines: # at the BSPT FPGA end of the data lines: NET 'BSPT_ACE_MP_DATA_15' N363-16 # MP_DATA_15 BSPT NET 'LINE_ACE_MP_DATA_15' N363-1 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_14' N363-15 # MP_DATA_14 BSPT NET 'LINE_ACE_MP_DATA_14' N363-2 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_13' N363-14 # MP_DATA_13 BSPT NET 'LINE_ACE_MP_DATA_13' N363-3 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_12' N363-13 # MP_DATA_12 BSPT NET 'LINE_ACE_MP_DATA_12' N363-4 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_11' N363-12 # MP_DATA_11 BSPT NET 'LINE_ACE_MP_DATA_11' N363-5 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_10' N363-11 # MP_DATA_10 BSPT NET 'LINE_ACE_MP_DATA_10' N363-6 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_09' N363-10 # MP_DATA_09 BSPT NET 'LINE_ACE_MP_DATA_09' N363-7 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_08' N363-9 # MP_DATA_08 BSPT NET 'LINE_ACE_MP_DATA_08' N363-8 # to/from the System-ACE # Resistor Network N364 Low Order MPU Data Lines # at the BSPT FPGA end of the data lines: NET 'BSPT_ACE_MP_DATA_07' N364-16 # MP_DATA_07 BSPT NET 'LINE_ACE_MP_DATA_07' N364-1 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_06' N364-15 # MP_DATA_06 BSPT NET 'LINE_ACE_MP_DATA_06' N364-2 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_05' N364-14 # MP_DATA_05 BSPT NET 'LINE_ACE_MP_DATA_05' N364-3 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_04' N364-13 # MP_DATA_04 BSPT NET 'LINE_ACE_MP_DATA_04' N364-4 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_03' N364-12 # MP_DATA_03 BSPT NET 'LINE_ACE_MP_DATA_03' N364-5 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_02' N364-11 # MP_DATA_02 BSPT NET 'LINE_ACE_MP_DATA_02' N364-6 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_01' N364-10 # MP_DATA_01 BSPT NET 'LINE_ACE_MP_DATA_01' N364-7 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_00' N364-9 # MP_DATA_00 BSPT NET 'LINE_ACE_MP_DATA_00' N364-8 # to/from the System-ACE # # CMX-0 Nets File # # System-Ace MPU, i.e. Board Support, and Other # ------------------------------------------------- # # # Original Rev. 12-Nov-2012 # Most Recent Rev. 22-July-2013 # # # # This file holds most of the nets for the Xilinx Syste-ACE # except for: power, ground, JTAG, and those that directly # connect to the Compact Flash Socket. # # Recall the power supply setup to the System-ACE chip: # # 3.3V Vcch supplies the Test JTAG and the Compact Flash ports. # 2.5V Vccl supplies the Configuration JTAG and MPU ports and the core. # # # Components involved in this net list: # # U321 the Xilinx System-ACE chip # # JMP81 and R308 control ACE_POR_BYPASS # # N365 and N366 series terminators at # the ACE end of data lines # # R309 and R310 series terminator resistors # # R311 and R312 Pull-Up resistors # # # # Connect the System-ACE a 20 MHz Clock # # This is a 20 MHz 2.5V CMOS clock that comes from # the board support FPGA. This is a divide by 2 # of the 40 MHz clock that the BSPT FPGA receives # from the Clock Generation and Distribution circuits. # The operations in the BSPT FPGA that talk to the # System-ACE MPU Port must be synchronized to this # 20 MHz clock. I.E. use good synchronous design # in the BSPT FPGA with Clock Enable and everything # running from 40 MHz. # NET 'ACE_CLOCK' U321-93 # System-ACE Clock input Vccl # # Define some Control, Status, and LED pins on the System-ACE # NET 'ACE_RESET_B' U321-33 # System-ACE RESET input Vccl Int_PU NET 'ACE_STATLED_B' U321-95 # System-ACE Status LED output pin open-drain NET 'ACE_ERRLED_B' U321-96 # System-ACE Error LED output pin open-drain # # Define the MPU interface pins on the System-ACE # NET 'ACE_MPCE_B' U321-42 # System-ACE MP Chip Enable _B input Vccl Int_PU NET 'ACE_MPWE_B' U321-76 # System-ACE MP Write Enable _B input Vccl Int_PU NET 'ACE_MPOE_B' U321-77 # System-ACE MP Output Enable _B input Vccl Int_PU NET 'ACE_MPIRQ' U321-41 # System-ACE MP Interrupt Request output Vccl NET 'ACE_MPBRDY' U321-39 # System-ACE MP Data Buffer Ready output Vccl NET 'ACE_MP_ADRS_0' U321-70 # System-ACE MP Address 0 input Vccl NET 'ACE_MP_ADRS_1' U321-69 # System-ACE MP Address 1 input Vccl NET 'ACE_MP_ADRS_2' U321-68 # System-ACE MP Address 2 input Vccl NET 'ACE_MP_ADRS_3' U321-67 # System-ACE MP Address 3 input Vccl NET 'ACE_MP_ADRS_4' U321-45 # System-ACE MP Address 4 input Vccl NET 'ACE_MP_ADRS_5' U321-44 # System-ACE MP Address 5 input Vccl NET 'ACE_MP_ADRS_6' U321-43 # System-ACE MP Address 6 input Vccl NET 'ACE_MP_DATA_00' U321-66 # System-ACE MP Data 00 in/out Vccl NET 'ACE_MP_DATA_01' U321-65 # System-ACE MP Data 01 in/out Vccl NET 'ACE_MP_DATA_02' U321-63 # System-ACE MP Data 02 in/out Vccl NET 'ACE_MP_DATA_03' U321-62 # System-ACE MP Data 03 in/out Vccl NET 'ACE_MP_DATA_04' U321-61 # System-ACE MP Data 04 in/out Vccl NET 'ACE_MP_DATA_05' U321-60 # System-ACE MP Data 05 in/out Vccl NET 'ACE_MP_DATA_06' U321-59 # System-ACE MP Data 06 in/out Vccl NET 'ACE_MP_DATA_07' U321-58 # System-ACE MP Data 07 in/out Vccl NET 'ACE_MP_DATA_08' U321-56 # System-ACE MP Data 08 in/out Vccl NET 'ACE_MP_DATA_09' U321-53 # System-ACE MP Data 09 in/out Vccl NET 'ACE_MP_DATA_10' U321-52 # System-ACE MP Data 10 in/out Vccl NET 'ACE_MP_DATA_11' U321-51 # System-ACE MP Data 11 in/out Vccl NET 'ACE_MP_DATA_12' U321-50 # System-ACE MP Data 12 in/out Vccl NET 'ACE_MP_DATA_13' U321-49 # System-ACE MP Data 13 in/out Vccl NET 'ACE_MP_DATA_14' U321-48 # System-ACE MP Data 14 in/out Vccl NET 'ACE_MP_DATA_15' U321-47 # System-ACE MP Data 15 in/out Vccl # # Define some signals that control the # FPGA Configuration by the system-ACE # NET 'ACE_CFG_INIT_B' U321-78 # Sys-ACE Configuration JTAG INIT input Vccl NET 'ACE_CFG_ADRS_0' U321-86 # Sys-ACE Config Address Select 0 input Vccl NET 'ACE_CFG_ADRS_1' U321-87 # Sys-ACE Config Address Select 1 input Vccl NET 'ACE_CFG_ADRS_2' U321-88 # Sys-ACE Config Address Select 2 input Vccl NET 'ACE_CFG_MODE' U321-89 # Sys-ACE Config Mode Pin input Vccl # # Define some miscellaneous pins on the System-ACE # NET 'ACE_POR_BYPASS' U321-108 # Sys-ACE Power-On Reset Bypass input Vcch NET 'ACE_POR_BYPASS' JMP81-1 R308-1 # Control the ACE_POR_BYPASS NET 'GROUND' JMP81-2 # Ground for the ACE_POR_BYPASS NET 'BULK_3V3' R308-2 # BULK_3V3 for R308 pull-up NET 'BOARD_POWER_OK_B' U321-72 # Sys-ACE ACE_POR_RESET the input pin # for the external Power-On-Reset signal # input Vcch 3.3V input # # Defining all of the un-connected pins to the System-ACE # # I give them unique single point net-name just as a way to # help detect other errors, i.e. all pins are assigned to some net. # NET 'No_Conn_ACE_PIN_2' U321-2 # No Connect to System-ACE Pin #2 NET 'No_Conn_ACE_PIN_14' U321-14 # No Connect to System-ACE Pin #14 NET 'No_Conn_ACE_PIN_16' U321-16 # No Connect to System-ACE Pin #16 NET 'No_Conn_ACE_PIN_19' U321-19 # No Connect to System-ACE Pin #19 NET 'No_Conn_ACE_PIN_20' U321-20 # No Connect to System-ACE Pin #20 NET 'No_Conn_ACE_PIN_21' U321-21 # No Connect to System-ACE Pin #21 NET 'No_Conn_ACE_PIN_22' U321-22 # No Connect to System-ACE Pin #22 NET 'No_Conn_ACE_PIN_23' U321-23 # No Connect to System-ACE Pin #23 NET 'No_Conn_ACE_PIN_24' U321-24 # No Connect to System-ACE Pin #24 NET 'No_Conn_ACE_PIN_27' U321-27 # No Connect to System-ACE Pin #27 NET 'No_Conn_ACE_PIN_28' U321-28 # No Connect to System-ACE Pin #28 NET 'No_Conn_ACE_PIN_29' U321-29 # No Connect to System-ACE Pin #29 NET 'No_Conn_ACE_PIN_30' U321-30 # No Connect to System-ACE Pin #30 NET 'No_Conn_ACE_PIN_31' U321-31 # No Connect to System-ACE Pin #31 NET 'No_Conn_ACE_PIN_32' U321-32 # No Connect to System-ACE Pin #32 NET 'No_Conn_ACE_PIN_34' U321-34 # No Connect to System-ACE Pin #34 NET 'No_Conn_ACE_PIN_36' U321-36 # No Connect to System-ACE Pin #36 NET 'No_Conn_ACE_PIN_38' U321-38 # No Connect to System-ACE Pin #38 NET 'No_Conn_ACE_PIN_40' U321-40 # No Connect to System-ACE Pin #40 NET 'No_Conn_ACE_PIN_71' U321-71 # No Connect to System-ACE Pin #71 NET 'No_Conn_ACE_PIN_74' U321-74 # No Connect to System-ACE Pin #74 # ACE_POR_TEST_B pin output Vcch NET 'No_Conn_ACE_PIN_79' U321-79 # No Connect to System-ACE Pin #79 NET 'No_Conn_ACE_PIN_90' U321-90 # No Connect to System-ACE Pin #90 NET 'No_Conn_ACE_PIN_122' U321-122 # No Connect to System-ACE Pin #122 NET 'No_Conn_ACE_PIN_124' U321-124 # No Connect to System-ACE Pin #124 NET 'No_Conn_ACE_PIN_127' U321-127 # No Connect to System-ACE Pin #127 NET 'No_Conn_ACE_PIN_143' U321-143 # No Connect to System-ACE Pin #143 # # Now connect the Pull-Up Resistors R311 and R312 # on the ACE_STATLED_B and ACE_ERRLED_B LED lines: # NET 'ACE_ERRLED_B' R311-1 # Pull-up on Error LED open-drain NET 'ACE_STATLED_B' R312-1 # Pull-up on Status LED open-drain NET 'BULK_2V5' R311-2 R312-2 # Pull-ups to BULK_2V5 supply # # Now the Series Terminator Resistors for the 2 # Control Signals that flow from the System-ACE # to the BSPT FPGA, i.e. MPIRQ and MPBRDY NET 'ACE_MPIRQ' R310-1 # MPIRQ from the ACE NET 'BSPT_ACE_MPIRQ' R310-2 # to the BSPT FPGA NET 'ACE_MPBRDY' R309-1 # MPBRDY from the ACE NET 'BSPT_ACE_MPBRDY' R309-2 # to the BSPT FPGA # # Now finally include the nets to the Series Terminator # Reaistor Networks at the ACE end of the MPU Data Lines: # Resistor Network N365 Low Order MPU Data Lines: # at the System-ACE end of the data lines: NET 'LINE_ACE_MP_DATA_00' N365-16 # MP_DATA_00 BSPT NET 'ACE_MP_DATA_00' N365-1 # to/from the System-ACE NET 'LINE_ACE_MP_DATA_01' N365-15 # MP_DATA_01 BSPT NET 'ACE_MP_DATA_01' N365-2 # to/from the System-ACE NET 'LINE_ACE_MP_DATA_02' N365-14 # MP_DATA_02 BSPT NET 'ACE_MP_DATA_02' N365-3 # to/from the System-ACE NET 'LINE_ACE_MP_DATA_03' N365-13 # MP_DATA_03 BSPT NET 'ACE_MP_DATA_03' N365-4 # to/from the System-ACE NET 'LINE_ACE_MP_DATA_04' N365-12 # MP_DATA_04 BSPT NET 'ACE_MP_DATA_04' N365-5 # to/from the System-ACE NET 'LINE_ACE_MP_DATA_05' N365-11 # MP_DATA_05 BSPT NET 'ACE_MP_DATA_05' N365-6 # to/from the System-ACE NET 'LINE_ACE_MP_DATA_06' N365-10 # MP_DATA_06 BSPT NET 'ACE_MP_DATA_06' N365-7 # to/from the System-ACE NET 'LINE_ACE_MP_DATA_07' N365-9 # MP_DATA_07 BSPT NET 'ACE_MP_DATA_07' N365-8 # to/from the System-ACE # Resistor Network N366 Hi Order MPU Data Lines # at the System-ACE end of the data lines: NET 'LINE_ACE_MP_DATA_08' N366-16 # MP_DATA_08 BSPT NET 'ACE_MP_DATA_08' N366-1 # to/from the System-ACE NET 'LINE_ACE_MP_DATA_09' N366-15 # MP_DATA_09 BSPT NET 'ACE_MP_DATA_09' N366-2 # to/from the System-ACE NET 'LINE_ACE_MP_DATA_10' N366-14 # MP_DATA_10 BSPT NET 'ACE_MP_DATA_10' N366-3 # to/from the System-ACE NET 'LINE_ACE_MP_DATA_11' N366-13 # MP_DATA_11 BSPT NET 'ACE_MP_DATA_11' N366-4 # to/from the System-ACE NET 'LINE_ACE_MP_DATA_12' N366-12 # MP_DATA_12 BSPT NET 'ACE_MP_DATA_12' N366-5 # to/from the System-ACE NET 'LINE_ACE_MP_DATA_13' N366-11 # MP_DATA_13 BSPT NET 'ACE_MP_DATA_13' N366-6 # to/from the System-ACE NET 'LINE_ACE_MP_DATA_14' N366-10 # MP_DATA_14 BSPT NET 'ACE_MP_DATA_14' N366-7 # to/from the System-ACE NET 'LINE_ACE_MP_DATA_15' N366-9 # MP_DATA_15 BSPT NET 'ACE_MP_DATA_15' N366-8 # to/from the System-ACE # # CMX-0 Nets File # # CAN Bus Monitoring Nets # --===================-------- # # # Original Rev. 13-Nov-2012 # Most Recent Rev. 23-Sept-2013 # # # # This file holds all of the nets that are involved with # the CAN Bus interface and the CAN Bus based monitoring # of the CMX card. # # # Notes: # # - U271 CAN Bus Microprocessor MB90F594 is a 5V part # # - U272 CAN Bus Interface Chip NXP PCA 82C250 is a 5V part # # - U273 RS-232 Interface MAX3232 will be powered by 5V # # - U274 4 MHz Crystal Oscillaror ECS-3691-040 is a 5V part # # - U275 Diode Temperature Sensor MAX1668 is a 5V part # # - U278 Reference for ADC REF 3140 will be powered by 5V # # - U279:U281 Analog Multiplesers 74HC4053 will be powered by 5V # # - U282 Quad-NAND uProc Reset & MODE 74LVC38A will be powered by 5V # # - U283 Octal 2V5 to 5V0 Translator TXB 0108 PW 2V5 and 5V0 # # - U274 Start Up Supervisor TPS3808 is a 5V part # # # # # # The components referenced in this file are: # # U271 CAN-Bus Microprocessor # U272 CAN-Bus Interface # U273 RS-232 Interface for the CAN-Bus Microprocessor # U274 4 MHz Crystal Oscillator # U275 MAX1668 Diode Temperature Sensor Interface # U276 MMBT3904 Diode Temp Sensor on MiniPOD Transmitters # U277 MMBT3904 Diode Temp Sensor on MiniPOD Receivers # U278 Reference for the CAN-Bus uProc ADC 4.096 Volt # U279 Tripple 2-Input Analog Multiplesers # U280 Tripple 2-Input Analog Multiplesers # U281 Tripple 2-Input Analog Multiplesers # U282 Quad-NAND for uProc Reset & MODE signals # U283 Octal 2.5V --> 5.0V Translator for Geo Adrs # U274 Start Up Supervisor for CAN uProc TPS3808 # # #------------------------------------------------ # # U272 CAN-Bus Interface Transceiver # #------------------------------------------------ # # CAN-Bus Interface U272 Connection to the Backplane Pins NET 'CAN_POS' U272-7 # Backplane CAN Bus Direct connection NET 'CAN_NEG' U272-6 # Backplane CAN Bus Complement connection # # CAN-Bus Interface U272 Slope Control Resistors Connections NET 'CAN_BUS_SLOPE' U272-8 # CAN-Bus Slope Control Pin NET 'CAN_BUS_SLOPE' R501-2 # CAN-Bus Slope Pull-Down Resistor NET 'CAN_BUS_SLOPE' R502-2 # CAN-Bus Slope Pull-Up Resistor NET 'GROUND' R501-1 # CAN-Bus Slope Pull-Down Resistor Ground NET 'BULK_5V0_S' R502-1 # CAN-Bus Slope Pull-Up Resistor BULK_5V0 # # CAN-Bus Microprocessor to Bus Interface Chip NET 'CAN_TRANS_DATA' U271-74 U272-1 # Data from Microprocessor to Bus NET 'CAN_REC_DATA' U272-4 U271-75 # Data from Bus to Microprocessor # # Power and Ground connection to U272 # the CAN-Bus Transceiver Chip NXP PCA 82C250 # and to its associated bypass capacitors NET 'BULK_5V0_S' U272-3 # Vcc +5 Volt for CAN_Bus Transceiver NET 'GROUND' U272-2 # Ground for CAN_Bus Transceiver NET 'BULK_5V0_S' C221-1 C222-1 # Vcc +5 Volt bypass capacitors NET 'GROUND' C221-2 C222-2 # Ground for bypass capacitors NET 'BULK_5V0_S' C591-1 C592-1 # Vcc +5 Volt Tant bypass capacitors NET 'GROUND' C591-2 C592-2 # Ground for Tant bypass capacitors #------------------------------------------------ # # U274 4 MHz Clock Oscillator # #------------------------------------------------ # # Connections to the 4 MHz Crystal Oscillator # for the CAN-Bus Microprocessor NET 'CAN_CLK_4_MHZ' U274-3 U271-82 # Clock signal to Microprocessor # pin X0 (82). Note that pin X1 # (83) on the Microprocessor NET 'No_Conn_CAN_PROC_X1_83' U271-83 # must Not be Connected. # See mezzanine Clock pin below. NET 'BULK_5V0_S' U274-4 C490-1 # Vcc +5 Volt for 4 MHz Xtal Osc. # and its Bypass Capacitor NET 'GROUND' U274-2 C490-2 # Ground for Xtal Osc. NET 'No_Conn_4_MHZ_OSC' U274-1 # No Connection - Float this pin # to Enable the 4 MHz Xtal Osc. #------------------------------------------------ # # U275 Diode Temperature Sensor Interface # #------------------------------------------------ # # Nets to the MAX1668 Diode Temperature Sensors # # MAX1668 DXP1-DXN1 Inputs NET 'BF_SI_TEMP_DXP' U275-1 # Base Function Silicon Temperature NET 'BF_SI_TEMP_DXN' U275-2 # BF DXP and DXN FPGA Pins # MAX1668 DXP2-DXN2 Inputs NET 'TP_SI_TEMP_DXP' U275-3 # Topological Silicon Temperature NET 'TP_SI_TEMP_DXN' U275-4 # TP DXP and DXN FPGA Pins # MAX1668 DXP3-DXN3 Inputs NET 'TRANS_TEMP_DXP3' U275-5 U276-1 # Transmitter MiniPOD Temperature NET 'TRANS_TEMP_DXP3' U276-3 # Sensor mmbt3904 Base-Collector NET 'TRANS_TEMP_DXN3' U275-6 U276-2 # connected to DXP, emitter to DXN # MAX1668 DXP4-DXN4 Inputs NET 'REC_TEMP_DXP4' U275-7 U277-1 # Receiver MiniPOD Temperature NET 'REC_TEMP_DXP4' U277-3 # Sensor mmbt3904 Base-Collector NET 'REC_TEMP_DXN4' U275-8 U277-2 # connected to DXP, emitter to DXN # # MAX1668 Temp Sensor Interface Data, Clock, Alarm, Adrs NET 'TEMP_SMB_DATA' U275-13 U271-30 # MAX1668 Diode Temp Sensor Data NET 'TEMP_SMB_DATA' R532-2 # Pull-Up on Temp Sense Data NET 'TEMP_SMB_CLK' U275-14 U271-29 # Data and CLK to the CAN-Bus Proc NET 'TEMP_SMB_CLK' R533-2 # Pull-Up on Temp Sense Clock NET 'TEMP_SMB_ALARM' U275-12 U271-76 # MAX1668 Temp Seneor Alarm NET 'TEMP_SMB_ALARM' R531-2 # Pull-Up on Temp Sense Alarm NET 'BULK_5V0_S' R531-1 R532-1 R533-1 # Pull-Up Resistors to +5V NET 'GROUND' U275-10 U275-11 # Ground MAX1668 Temp Sensor Adrs_0 Adrs_1 # # Power and Ground connection to U275 # the Diode Temperature Sensor Interface MAX1668 NET 'BULK_5V0_S' R548-2 # BULK +5 Volt for Diode Temp Sensor IF NET 'TEMP_SENSOR_5V0' R548-1 # Filtered +5V for Diode Temp Sensor IF NET 'TEMP_SENSOR_5V0' U275-9 U275-15 # Filtered +5V for Diode Temp Sensor IF NET 'TEMP_SENSOR_5V0' C491-1 C594-1 # Bypass U275 Diode Temp Sensor IF NET 'GROUND' C491-2 C594-2 NET 'GROUND' U275-16 # Ground for Diode Temp Sensor Interface #------------------------------------------------------------ # # U271 CAN-Bus uProcessor Power, Ground, Bypass # #------------------------------------------------------------ # # Power and Ground connection to U271 # the CAN-Bus microcontroller NET 'BULK_5V0_S' U271-58 U271-68 # High current buffer power NET 'BULK_5V0_S' U271-23 U271-84 # Digital section power NET 'BULK_5V0_S' R547-1 # Bulk 5V for Analog section power NET 'CAN_ADC_5V0' R547-2 U271-34 # Filtered Analog section power NET 'CAN_ADC_5V0' C478-1 C593-2 # Bypass Filtered Analog section power NET 'GROUND' C478-2 C593-1 # Bypass Grounds NET 'GROUND' U271-53 U271-63 # High current buffer ground NET 'GROUND' U271-73 # High current buffer ground NET 'GROUND' U271-37 # Analog section ground NET 'GROUND' U271-11 U271-42 # Digital section ground NET 'GROUND' U271-81 # Digital section ground NET 'BULK_5V0_S' C477-1 # CPU Bypass Caps on BULK_5V0_S NET 'BULK_5V0_S' C479-1 C480-1 # CPU Bypass Caps on BULK_5V0_S NET 'BULK_5V0_S' C481-1 C482-1 # CPU Bypass Caps on BULK_5V0_S NET 'GROUND' C477-2 # CPU Bypass Cap Grounds NET 'GROUND' C479-2 C480-2 # CPU Bypass Cap Grounds NET 'GROUND' C481-2 C482-2 # CPU Bypass Cap Grounds # # Voltage Stabilization Capacitor for the internal # CAN-Bus supply C483 100 nFd. NET 'CAN_PROC_STAB_CAP' U271-27 C483-1 # CAN_Bus Internal Voltage # NET 'GROUND' C483-2 # Stabilization Capacitor # # Tantalum Bypass on the BULK_5V0_S in the CAN-Bus Area. NET 'BULK_5V0_S' C486-1 C500-1 # Tantalum Bypass on +5V power NET 'GROUND' C486-2 C500-2 # to the CAN-Bus uP circuits. #-------------------------------------------------------- # # U278 4.096 Volt Reference for CAN-Bus uProc ADC # #-------------------------------------------------------- # # Analog Reference for the CAN-Bus micro-controller NET 'BULK_5V0_S' U278-1 C484-1 # +5V power to the Reference NET 'REF_TO_CAN_BUS_ADC' U278-2 # +4.096 Volt Reference to NET 'REF_TO_CAN_BUS_ADC' U271-35 # AVRH pin the the CAN-Bus uP NET 'REF_TO_CAN_BUS_ADC' C485-1 # with Bypass Cap. NET 'GROUND' U278-3 C484-2 # Ground Ref Chip and its Bypass NET 'GROUND' U271-36 C485-2 # Ground AVRL pin on CAN-Bus uP # and the Ref Voltage Bypass Cap #-------------------------------------------------------- # # U273 RS-232 Interface to/from CAN-Bus uProcessor # #-------------------------------------------------------- # # RS-232 Transceiver Connections Front-Panel to CAN-Bus uProcessor # # MAX3232 RS-232 Receiver - Data to the CAN-Bus uProcessor # RS-232 Data enters CMX on J12 pin 14 # RS-232 Data enters CAN-Bus uP on its pin 16 NET 'FP_RS_232_DATA_INPUT' J12-14 U273-13 # RS-232 Data from Front-Panel # to the RS-232 Receiver Input NET 'RS_232_DATA_TO_CAN_PROC' U273-12 U271-16 # RS-232 Data from RS-232 # I/F Chip to the CAN-Bus # uProcessor Input NET 'RS_232_DATA_TO_CAN_PROC' R534-1 # Pull-Up on the RS-232 # data to the CAN uProc NET 'BULK_5V0_S' R534-2 # Pull-Up to +5V # # MAX3232 RS-232 Transmitter - Data from the CAN-Bus uProcessor # RS-232 Data leaves CAN-Bus uP on its pin 14 # RS-232 Data leaves CMX on J12 pin 13 NET 'RS_232_DATA_FROM_CAN_PROC' U271-14 U273-11 # RS-232 Data from the # CAN-Bus uProcessor # to RS-232 I/F Chip NET 'FP_RS_232_DATA_OUTPUT' U273-14 J12-13 # RS-232 Data from the RS-232 # Transmitter Output to the # Front-Panel J12 Connector NET 'GROUND' U273-10 # Transmitter #2 Input Grounded # # Receive the RS-232 Level RESET Signal from the uProc FLASH Programmer # NET 'FP_RS_232_PRGMR_RESET' J12-12 U273-8 # RS-232 level uProc RESET # signal from the FLASH # Programmer for the uProc. NET 'FP_CMOS_PRGMR_RESET' U273-9 U282-13 # The received now CMOS RESET # signal from the FLASH # Programmer goes to the uProc # RESET logic in U282. # # MAX3232 Internal Power Supply Capacitors # NET 'MAX_PS_C1_POS' C471-1 U273-1 # Internal Power Supply C1 NET 'MAX_PS_C1_NEG' C471-2 U273-3 # NET 'MAX_PS_C2_POS' C472-1 U273-4 # Internal Power Supply C2 NET 'MAX_PS_C2_NEG' C472-2 U273-5 # NET 'MAX_PS_C3_POS' C473-1 U273-2 # Internal Power Supply C3 NET 'GROUND' C473-2 # NET 'MAX_PS_C4_POS' C474-1 U273-6 # Internal Power Supply C4 NET 'GROUND' C474-2 # # # Power and Ground to the MAX3232 chip for CAN-Bus RS-232 # NET 'BULK_5V0_S' U273-16 # +5.0V Power to the MAX3232 NET 'GROUND' U273-15 # Ground to the MAX3232 NET 'BULK_5V0_S' C475-1 C476-2 # Power ByPass Capacitor NET 'GROUND' C475-2 C476-1 # # # Un-Connected pins on the MAX3232 # RS-232 Interface Chip: NET 'No_Conn_RS_232_T_U273_PIN_7' U273-7 # Unused Transmitter #------------------------------------------------------------------ # # U279:U281 Analog Multiplexers Power, Ground, Bypass # #------------------------------------------------------------------ # # Power and Ground to the Analog Multiplexers # Ground the following pins on the Multiplexers: # Ground, Vee, Enable_B NET 'BULK_5V0_S' U279-16 C487-1 # +5V power to Mux U279 NET 'BULK_5V0_S' U280-16 C488-1 # +5V power to Mux U280 NET 'BULK_5V0_S' U281-16 C489-1 # +5V power to Mux U281 NET 'GROUND' U279-6 U279-7 U279-8 # Ground to Mux U279 NET 'GROUND' U280-6 U280-7 U280-8 # Ground to Mux U280 NET 'GROUND' U281-6 U281-7 U281-8 # Ground to Mux U281 NET 'GROUND' C487-2 C488-2 C489-2 # Ground to Bypass Caps #------------------------------------------------------------------ # # U279:U281 Analog Multiplexers Outputs # #------------------------------------------------------------------ # # Connect the Analog Multiplexer Outputs # to the CAN-Bus uProcessor ADC Input # These connections are through RC Filters. NET 'A_MUX_0_TO_FILT' U281-15 R521-2 # MUX 0 Output to RC Filter InpuT NET 'CAN_ADC_CH_0_IN' U271-38 R521-1 # RC Filter to CAN-Bus ADC Ch 0 Input NET 'CAN_ADC_CH_0_IN' C671-2 # C of the RC Filter for Ch 0 NET 'GROUND' C671-1 # Ground of the C in the RC Filter NET 'A_MUX_1_TO_FILT' U281-14 R522-2 # MUX 1 Output to RC Filter InpuT NET 'CAN_ADC_CH_1_IN' U271-39 R522-1 # RC Filter to CAN-Bus ADC Ch 1 Input NET 'CAN_ADC_CH_1_IN' C672-2 # C of the RC Filter for Ch 1 NET 'GROUND' C672-1 # Ground of the C in the RC Filter NET 'A_MUX_2_TO_FILT' U281-4 R523-2 # MUX 2 Output to RC Filter InpuT NET 'CAN_ADC_CH_2_IN' U271-40 R523-1 # RC Filter to CAN-Bus ADC Ch 2 Input NET 'CAN_ADC_CH_2_IN' C673-2 # C of the RC Filter for Ch 2 NET 'GROUND' C673-1 # Ground of the C in the RC Filter NET 'A_MUX_3_TO_FILT' U280-15 R524-2 # MUX 3 Output to RC Filter InpuT NET 'CAN_ADC_CH_3_IN' U271-41 R524-1 # RC Filter to CAN-Bus ADC Ch 3 Input NET 'CAN_ADC_CH_3_IN' C674-2 # C of the RC Filter for Ch 3 NET 'GROUND' C674-1 # Ground of the C in the RC Filter NET 'A_MUX_4_TO_FILT' U280-14 R525-2 # MUX 4 Output to RC Filter InpuT NET 'CAN_ADC_CH_4_IN' U271-43 R525-1 # RC Filter to CAN-Bus ADC Ch 4 Input NET 'CAN_ADC_CH_4_IN' C675-2 # C of the RC Filter for Ch 4 NET 'GROUND' C675-1 # Ground of the C in the RC Filter NET 'A_MUX_5_TO_FILT' U280-4 R526-2 # MUX 5 Output to RC Filter InpuT NET 'CAN_ADC_CH_5_IN' U271-44 R526-1 # RC Filter to CAN-Bus ADC Ch 5 Input NET 'CAN_ADC_CH_5_IN' C676-2 # C of the RC Filter for Ch 5 NET 'GROUND' C676-1 # Ground of the C in the RC Filter NET 'A_MUX_6_TO_FILT' U279-15 R527-2 # MUX 6 Output to RC Filter InpuT NET 'CAN_ADC_CH_6_IN' U271-45 R527-1 # RC Filter to CAN-Bus ADC Ch 6 Input NET 'CAN_ADC_CH_6_IN' C677-2 # C of the RC Filter for Ch 6 NET 'GROUND' C677-1 # Ground of the C in the RC Filter NET 'A_MUX_7_TO_FILT' U279-14 R528-2 # MUX 7 Output to RC Filter InpuT NET 'CAN_ADC_CH_7_IN' U271-46 R528-1 # RC Filter to CAN-Bus ADC Ch 7 Input NET 'CAN_ADC_CH_7_IN' C678-2 # C of the RC Filter for Ch 7 NET 'GROUND' C678-1 # Ground of the C in the RC Filter #------------------------------------------------------------------ # # U279:U281 Analog Multiplexers Selection Control # #------------------------------------------------------------------ # # Connect a CAN-Bus uProcessor I/O Port Output # to control the Analog Multiplexers. All 8 # channels of the 2 Input Muxes are controlled # in parallel. NET 'A_MUX_SELECT_CONTROL' U279-9 U279-10, U279-11 # Analog Mux Select Control NET 'A_MUX_SELECT_CONTROL' U280-9 U280-10, U280-11 # HI --> Y1 Inputs ( Amps) NET 'A_MUX_SELECT_CONTROL' U281-9 U281-10, U281-11 # LOW --> Y0 Inputs (Volts) # from CAN-Bus uProcessor NET 'A_MUX_SLCT_CTRL_UPROC' U271-69 # signal P84 PWM1P3 pin 69 # NET 'A_MUX_SLCT_CTRL_UPROC' JMP85-2 # through link JMP85 NET 'A_MUX_SELECT_CONTROL' JMP85-1 # uProc --> A-Mux # NET 'A_MUX_SELECT_CONTROL' R536-2 # with pull-down R536 NET 'GROUND' R536-1 # on the Mux side #------------------------------------------------------------------ # # U279:U281 Analog Multiplexers Inputs # #------------------------------------------------------------------ # # Connect Inputs to the Analog Multiplexers NET 'MON_BSPT_CORE_V' U281-2 # MON_BSPT_CORE_V U281 1Y0 ADC Ch 0 NET 'MON_BF_CORE_V' U281-12 # MON_BF_CORE_V U281 2Y0 ADC Ch 1 NET 'MON_GTX_AVTT_V' U281-5 # MON_GTX_AVTT_V U281 3Y0 ADC Ch 2 NET 'MON_GTX_AVCC_V' U280-2 # MON_GTX_AVCC_V U280 1Y0 ADC Ch 3 NET 'MON_TP_CORE_V' U280-12 # MON_TP_CORE_V U280 2Y0 ADC Ch 4 NET 'MON_BULK_3V3_V' U280-5 # MON_BULK_3V3_V U280 3Y0 ADC Ch 5 NET 'MON_BULK_2V5_V' U279-2 # MON_BULK_2V5_V U279 1Y0 ADC Ch 6 NET 'MON_BULK_5V0_V' U279-12 # MON_BULK_5V0_V U279 2Y0 ADC Ch 7 NET 'MON_BSPT_CORE_I' U281-1 # MON_BSPT_CORE_I U281 1Y1 ADC Ch 0 NET 'MON_BF_CORE_I' U281-13 # MON_BF_CORE_I U281 2Y1 ADC Ch 1 NET 'MON_GTX_AVTT_I' U281-3 # MON_GTX_AVTT_I U281 3Y1 ADC Ch 2 NET 'MON_GTX_AVCC_I' U280-1 # MON_GTX_AVCC_I U280 1Y1 ADC Ch 3 NET 'MON_TP_CORE_I' U280-13 # MON_TP_CORE_I U280 2Y1 ADC Ch 4 NET 'MON_BULK_3V3_I' U280-3 # MON_BULK_3V3_I U280 3Y1 ADC Ch 5 NET 'MON_BULK_2V5_I' U279-1 # MON_BULK_2V5_I U279 1Y1 ADC Ch 6 NET 'MON_VREF_P_V' U279-13 # Monitor BF I/O Ref U279 2Y1 ADC Ch 7 NET 'GROUND' U279-3 U279-5 # Ground both unused Mux Inputs # U279 3Y0 and U279 3Y1 #------------------------------------------------------------------ # # U283 Geographic Address 2V5 --> 5V0 Translator # #------------------------------------------------------------------ # # Connect the 7-bit Geographic Address # through the U283 2V5 to 5V0 Translator # and then to the CAN-Bus uProcessor. NET 'OCB_GEO_ADRS_0' U283-3 # 2V5 Geo_Adrs_0 into the translator NET 'OCB_GEO_ADRS_1' U283-4 # 2V5 Geo_Adrs_1 into the translator NET 'OCB_GEO_ADRS_2' U283-5 # 2V5 Geo_Adrs_2 into the translator NET 'OCB_GEO_ADRS_3' U283-6 # 2V5 Geo_Adrs_3 into the translator NET 'OCB_GEO_ADRS_4' U283-7 # 2V5 Geo_Adrs_4 into the translator NET 'OCB_GEO_ADRS_5' U283-8 # 2V5 Geo_Adrs_5 into the translator NET 'OCB_GEO_ADRS_6' U283-9 # 2V5 Geo_Adrs_6 into the translator NET 'V5_GEO_ADRS_0' U283-18 U271-54 # 5V0 Geo_Adrs_0 to uProc P70/PWM1P0 NET 'V5_GEO_ADRS_1' U283-17 U271-55 # 5V0 Geo_Adrs_1 to uProc P71/PWM1M0 NET 'V5_GEO_ADRS_2' U283-16 U271-56 # 5V0 Geo_Adrs_2 to uProc P72/PWM2P0 NET 'V5_GEO_ADRS_3' U283-15 U271-57 # 5V0 Geo_Adrs_3 to uProc P73/PWM2M0 NET 'V5_GEO_ADRS_4' U283-14 U271-60 # 5V0 Geo_Adrs_4 to uProc P75/PWM1M1 NET 'V5_GEO_ADRS_5' U283-13 U271-61 # 5V0 Geo_Adrs_5 to uProc P76/PWM2P1 NET 'V5_GEO_ADRS_6' U283-12 U271-62 # 5V0 Geo_Adrs_6 to uProc P77/PWM2M1 # # Tie HI P74/PWM1P1 the uProcessor input that they skipped NET 'HI_TO_U271_59' R542-2 U271-59 # HI to P74/PWM1P1 skipped uProcessor pin NET 'BULK_5V0_S' R542-1 # Pull-up resistor to 5V0 # # Tie LOW the Input to the Unused Section of the Tranalator NET 'LOW_TO_U283_1' R540-2 U283-1 # LOW to unused translator section input NET 'GROUND' R540-1 # Ground the pull-down resistor NET 'No_Conn_U283_20' U283-20 # Unused translator section output # # Tie HI the Translator OE pin NET 'HI_TO_U283_10' R541-2 U283-10 # HI to Translator Output Enable pin NET 'BULK_2V5' R541-1 # Pull-up resistor to 2.5V # # Power and Ground to U283 - the TXB 0108 PW Octal 2V5 to 5V0 Translator NET 'BULK_2V5' U283-2 C495-2 C496-1 # 2V5 Power to U283 an its bypass caps. # This is "Side A" power. NET 'BULK_5V0_S' U283-19 C494-1 C497-2 # 5V0 Power to U283 an its bypass caps. # This is "Side B" power. NET 'GROUND' U283-11 # Ground to U283 an its bypass caps. NET 'GROUND' C495-1 C496-2 # Ground the 2V5 bypass NET 'GROUND' C494-2 C497-1 # Ground the 5V0 bypass NET 'BULK_2V5' C498-1 # Tant Bypass of 2V5 NET 'BULK_5V0_S' C499-1 # Tant Bypass of 5V0 NET 'GROUND' C498-2 C499-2 # Ground Tant Bypasses #------------------------------------------------------------ # # U271 CAN-Bus uProcessor "Module Type" 4-Bits # #------------------------------------------------------------ # # Tie LOW: P80/PWM1P2 P81/PWM1M2 P83/PWM2M2 pins: 64, 65, 67 NET 'LOW_TO_U271_64' R543-2 U271-64 # LOW to P80/PWM1P2 pin 64 Module Type Bit NET 'LOW_TO_U271_65' R544-2 U271-65 # LOW to P81/PWM1M2 pin 65 Module Type Bit NET 'LOW_TO_U271_67' R546-2 U271-67 # LOW to P83/PWM2M2 pin 67 Module Type Bit # Tie HI: P82/PWM2P2 pin: 66 NET 'HI_TO_U271_66' R545-2 U271-66 # HI to P82/PWM2P2 pin 66 Module Type Bit # Connect the pull-up and pull-down resistors NET 'BULK_5V0_S' R545-1 # Pull-up resistor to 5V0 NET 'GROUND' R543-1 R544-1 R546-1 # Pull-down to ground #------------------------------------------------------------ # # U271 CAN-Bus uProcessor Tie LOW Unused Pins # #------------------------------------------------------------ # # Tie LOW: P85/PWM1M3 P86/PWM2P3 P87/PWM2M3 # U271 pins: 70, 71, 72 # # Note that in this group of 4 signals, P84/PWM1P3 pin 69 is used # as the control signal to the Analog Multiplexers. NET 'LOW_TO_U271_70' R550-1 U271-70 # LOW to P85/PWM1M3 pin 70 Unused Pin NET 'LOW_TO_U271_71' R551-1 U271-71 # LOW to P86/PWM2P3 pin 71 Unused Pin NET 'LOW_TO_U271_72' R552-1 U271-72 # LOW to P87/PWM2M3 pin 72 Unused Pin NET 'GROUND' R550-2 R551-2 R552-2 # Pull-down to ground # Tie LOW: P24/INT4 P25/INT5 P26/INT6 P27/INT7 # U271 pins: 5, 6, 7, 8 NET 'LOW_TO_U271_5' R561-1 U271-5 # LOW to P24/INT4 pin 5 Unused Pin NET 'LOW_TO_U271_6' R560-1 U271-6 # LOW to P25/INT5 pin 6 Unused Pin NET 'LOW_TO_U271_7' R559-1 U271-7 # LOW to P26/INT6 pin 7 Unused Pin NET 'LOW_TO_U271_8' R558-1 U271-8 # LOW to P27/INT7 pin 8 Unused Pin NET 'GROUND' R558-2 R559-2 R560-2 R561-2 # Pull-down to ground # Tie LOW: P93/INT1 P94/INT2 P95/INT3 # U271 pins: 78, 79, 80 # # Note that in this group of 4 signals, P92/INT0 pin 76 is used # for the Alarm signal signal from the diode temp sensor interface chip. NET 'LOW_TO_U271_78' R553-1 U271-78 # LOW to P93/INT1 pin 78 Unused Pin NET 'LOW_TO_U271_79' R554-1 U271-79 # LOW to P94/INT2 pin 79 Unused Pin NET 'LOW_TO_U271_80' R555-1 U271-80 # LOW to P95/INT3 pin 80 Unused Pin NET 'GROUND' R553-2 R554-2 R555-2 # Pull-down to ground # Tie LOW: P35/SCK0 P37/SIN1 # U271 pins: 15, 17 # # Note that in this group of 4 signals, P34/SOT0 pin 14 and # P36/SIN0 pin 16 are used for the RS-232 communications. NET 'LOW_TO_U271_15' R557-1 U271-15 # LOW to P35/SCK0 pin 15 Unused Pin NET 'LOW_TO_U271_17' R556-1 U271-17 # LOW to P37/SIN1 pin 17 Unused Pin NET 'GROUND' R556-2 R557-2 # Pull-down to ground #--------------------------------------------------------------------------- # # U282 74LVC38A Reset and Mode Conrol for the CAN-Bus uProcessor # #--------------------------------------------------------------------------- # # # First list the RESET logic for the CAN-Bus uProcessor. # # The RESET signal can come from: # # - The U284 Power-Up Supervisor releases its low active # reset output signal once the +5V power is stable. # This part can also receive an input that will # force its reset output to the active state. # # - The Front-Panel J12 connector can receive a Hi # active RS-232 level reset signal from the uProcessor # FLASH memory programmer. This RS-232 reset signal # is converted to 5V CMOS by the U273 RS-232 transceiver. # # If either of these reset signals is in the active state # then a Low active Reset is sent to the HST_B pin 52 and # the RST_B pin 77 on the CAN-Bus uProcessor and to # pin 52 on the mezzanine connector J15. # # # List the U284 Start-Up Supervisor: NET 'BULK_5V0_S' R563-1 # +5V Power for the U284 TPS3808 NET 'UPROC_SUP_POW' R563-2 # Filtered power for U284 TPS3808 NET 'UPROC_SUP_POW' C281-2 C284-2 # Bypass the Filtered power NET 'UPROC_SUP_POW' U284-6 U284-5 # U284 TPS3808 Vdd and Sense Pins NET 'GROUND' C281-1 C284-1 # Ground the power filter caps. NET 'GROUND' U284-2 # U284 TPS3808 GROUND connection NET 'UPROC_SUP_TIME_CAP' U284-4 C283-2 # U284 TPS3808 Timing capacitor NET 'GROUND' C283-1 # Ground the Timing capacitor NET 'UPROC_SUP_MR_B' U284-3 C282-1 # U284 TPS3808 Manual_Reset_B NET 'GROUND' C282-2 # Ground the Manual Reset cap. NET 'UPROC_SUP_LETS_GO' U284-1 R535-1 # U284 TPS3808 RESET_B output # goes to the U282 uProc Reset Logic. NET 'BULK_5V0_S' R535-2 # Pull-Up to +5V NET 'UPROC_SUP_LETS_GO' U282-12 # uProc Power-Up Supervisor input # to the overall CAN uProc Reset Logic # The received Front-Panel RS-232 level # reset signal enters U282 on its pin 1. NET 'NAND_MIXED_RESETS' U282-11 R537-1 # Combine the two sources of uProc Reset. NET 'NAND_MIXED_RESETS' U282-10 U282-9 # and send to the inverter. NET 'BULK_5V0_S' R537-2 # Pull-Up to +5V NET 'UPROC_RESET_B' U282-8 # uProcessor Reset_B signal NET 'UPROC_RESET_B' R538-1 R539-1 # Pull-Ups on uProc Reset signal # to the uProc Mezzanine Conn # J15 pin 52 see below. NET 'UPROC_RESET_B' U271-52 # to the uProc HST_B pin NET 'UPROC_RESET_B' U271-77 # to the uProc RST_B pin NET 'BULK_5V0_S' R538-2 R539-2 # Pull-Ups to +5V # # Now the U282 CAN-Bus uProccesor MODE Control Logic # # Front-Panel connector J12 pin 11 can be pulled LOW to switch # the Mode of the uProc from normal Operate to Program. # Normally J12 pin 11 is held HI by a pull-up resistor. # # To switch between Normal Operate and Program # we must change the state of 4 signals as shown in # the following table: # # Normal # Operate Program # ------- ------- # P00 pin 85 HI LOW # P01 pin 86 HI LOW # Mode_0 pin 49 HI LOW # Mode_1 pin 50 HI HI # Mode_2 pin 51 LOW HI # # HI and LOW refer to the voltage level on these pins. # Note that Mode_1 is always HI. # NET 'FP_UPROC_MODE_CTRL' J12-11 # Front-Panel J12 Mode Control Pin NET 'FP_UPROC_MODE_CTRL' U282-1 U282-2 # Input to the U282 uProc Mode Logic NET 'FP_UPROC_MODE_CTRL' C285-1 R564-1 # Pull-Up and Filter Cap on Mode # Control front-panel signal. NET 'BULK_5V0_S' R564-2 # Pull-up to +5V NET 'GROUND' C285-2 # Ground the Filter Cap. NET 'RCVD_UPROC_MODE_CTRL' U282-3 # Received uProc Mode Control Signal NET 'RCVD_UPROC_MODE_CTRL' U282-4 U282-5 # Pass to the output inverter stage NET 'RCVD_UPROC_MODE_CTRL' R565-1 R566-1 # Pull-Up hard to +5V NET 'RCVD_UPROC_MODE_CTRL' U271-51 # - Connect to uProc MODE_2 pin # - Connect to uProc Mez Conn # J15 pin 62 see below NET 'BULK_5V0_S' R565-2 R566-2 # Pull-Ups to +5V NET 'UPROC_MODE_CONTROL' U282-6 # uProcessor Mode Control this is # inverted RCVD_UPROC_MODE_CTR NET 'UPROC_MODE_CONTROL' R567-1 R568-1 # Pull-Up hard to +5V # Now connect to uProc: NET 'UPROC_MODE_CONTROL' U271-85 # - Connect to uProc P00 pin # - Connect Mez Conn J15 pin 58 below NET 'UPROC_MODE_CONTROL' U271-86 # - Connect to uProc P01 pin # - Connect Mez Conn J15 pin 60 below NET 'UPROC_MODE_CONTROL' U271-49 # - Connect to uProc MODE_0 pin # - Connect Mez Conn J15 pin 56 # see uProc Mezzane Conn below NET 'BULK_5V0_S' R567-2 R568-2 # Pull-Ups to +5V # # Tie the uProcessor MODE_1 signal HI with R562 NET 'UPROC_MODE_1' U271-50 R562-1 # Pull-Up of uProc MODE_1 pin NET 'BULK_5V0_S' R562-2 # Pull-Ups to +5V # # Finally list the Power and Ground to U282 - the 74LVC38A Quad-NAND NET 'BULK_5V0_S' U282-14 C492-2 C493-2 # Power to U282 an its bypass caps. NET 'GROUND' U282-7 C492-1 C493-1 # Ground to U282 an its bypass caps. #------------------------------------------------------------------ # # J15 Can-Bus uProcessor Mezzanine Connector to the West # --= #------------------------------------------------------------------ # NET 'GROUND' J15-1 J15-2 # NET 'REF_TO_CAN_BUS_ADC' J15-3 J15-4 # NET 'GROUND' J15-5 J15-6 # NET 'A_MUX_0_TO_FILT' J15-7 J15-8 # NET 'GROUND' J15-9 J15-10 # NET 'A_MUX_1_TO_FILT' J15-11 J15-12 # NET 'GROUND' J15-13 J15-14 # NET 'A_MUX_2_TO_FILT' J15-15 J15-16 # NET 'GROUND' J15-17 J15-18 # NET 'A_MUX_3_TO_FILT' J15-19 J15-20 # NET 'GROUND' J15-21 J15-22 # NET 'A_MUX_4_TO_FILT' J15-23 J15-24 # NET 'GROUND' J15-25 J15-26 # NET 'A_MUX_5_TO_FILT' J15-27 J15-28 # NET 'GROUND' J15-29 J15-30 # NET 'A_MUX_6_TO_FILT' J15-31 J15-32 # NET 'GROUND' J15-33 J15-34 # NET 'A_MUX_7_TO_FILT' J15-35 J15-36 # NET 'GROUND' J15-37 J15-38 # NET 'GROUND' J15-39 J15-40 # NET 'A_MUX_SELECT_CONTROL' J15-41 J15-42 # NET 'GROUND' J15-43 J15-44 # NET 'V5_GEO_ADRS_0' J15-45 # NET 'V5_GEO_ADRS_1' J15-47 # NET 'V5_GEO_ADRS_2' J15-49 # NET 'V5_GEO_ADRS_3' J15-51 # NET 'V5_GEO_ADRS_4' J15-53 # NET 'V5_GEO_ADRS_5' J15-55 # NET 'V5_GEO_ADRS_6' J15-57 # NET 'RS_232_DATA_TO_CAN_PROC' J15-46 # NET 'RS_232_DATA_FROM_CAN_PROC' J15-48 # NET 'GROUND' J15-50 # NET 'UPROC_RESET_B' J15-52 # uProc Reset Signals NET 'GROUND' J15-54 # NET 'UPROC_MODE_CONTROL' J15-56 # uProc MODE_0 NET 'UPROC_MODE_CONTROL' J15-58 # uProc P00 NET 'UPROC_MODE_CONTROL' J15-60 # uProc P01 NET 'RCVD_UPROC_MODE_CTRL' J15-62 # uProc MODE_2 ##NET '' J15-59 # ##NET '' J15-61 # NET 'GROUND' J15-63 J15-64 # #------------------------------------------------------------------ # # J16 Can-Bus uProcessor Mezzanine Connector to the East # --= #------------------------------------------------------------------ # NET 'GROUND' J16-1 J16-2 # NET 'GROUND' J16-3 # NET 'TEMP_SMB_ALARM' J16-4 # NET 'GROUND' J16-5 # NET 'TEMP_SMB_DATA' J16-6 # NET 'GROUND' J16-7 # NET 'TEMP_SMB_CLK' J16-8 # NET 'GROUND' J16-9 J16-10 # NET 'BULK_3V3' J16-11 J16-12 # NET 'BULK_5V0_S' J16-13 J16-14 # NET 'BULK_3V3' J16-15 J16-16 # NET 'BULK_5V0_S' J16-17 J16-18 # NET 'BULK_3V3' J16-19 J16-20 # NET 'BULK_5V0_S' J16-21 J16-22 # NET 'BULK_3V3' J16-23 J16-24 # NET 'BULK_5V0_S' J16-25 J16-26 # NET 'BULK_3V3' J16-27 J16-28 # NET 'BULK_5V0_S' J16-29 J16-30 # NET 'BULK_3V3' J16-31 J16-32 # NET 'BULK_5V0_S' J16-33 J16-34 # NET 'GROUND' J16-35 J16-36 # NET 'CAN_TRANS_DATA' J16-38 # NET 'GROUND' J16-39 J16-40 # NET 'CAN_REC_DATA' J16-42 # NET 'GROUND' J16-43 J16-44 # ##NET '' J16-37 # ##NET '' J16-41 # ##NET '' J16-46 # ##NET '' J16-50 # NET 'SPARE_J16_48_SR_41' J16-48 SR41-2 # Spare J16 pin 48 to smd pads NET 'SPARE_J16_52_SR_42' J16-52 SR42-2 # Spare J16 pin 52 to smd pads NET 'SPARE_J16_45_SR_43' J16-45 SR43-1 # Spare J16 pin 45 to smd pads NET 'SPARE_J16_47_SR_44' J16-47 SR44-1 # Spare J16 pin 47 to smd pads NET 'SPARE_J16_49_SR_45' J16-49 SR45-1 # Spare J16 pin 49 to smd pads NET 'SPARE_J16_51_SR_46' J16-51 SR46-1 # Spare J16 pin 51 to smd pads NET 'BULK_2V5' J16-53 # NET 'BULK_2V5' J16-54 # NET 'BULK_2V5' J16-57 # NET 'BULK_2V5' J16-58 # NET 'BULK_2V5' J16-61 # NET 'GROUND' J16-55 J16-56 # NET 'GROUND' J16-59 J16-60 # NET 'CAN_CLK_4_MHZ' J16-62 # NET 'GROUND' J16-63 J16-64 # #------------------------------------------------------------ # # U271 CAN-Bus uProcessor NOT CONNECTED Pins # #------------------------------------------------------------ # NET 'No_Conn_U271_1' U271-1 # P20 NET 'No_Conn_U271_2' U271-2 # P21 NET 'No_Conn_U271_3' U271-3 # P22 NET 'No_Conn_U271_4' U271-4 # P23 NET 'No_Conn_U271_9' U271-9 # P30 NET 'No_Conn_U271_10' U271-10 # P31 NET 'No_Conn_U271_12' U271-12 # P32 NET 'No_Conn_U271_13' U271-13 # P33 NET 'No_Conn_U271_18' U271-18 # P40/SCK1 NET 'No_Conn_U271_19' U271-19 # P41/SOT1 NET 'No_Conn_U271_20' U271-20 # P42/SOT2 NET 'No_Conn_U271_21' U271-21 # P43/SCK2 NET 'No_Conn_U271_22' U271-22 # P44/SIN2 NET 'No_Conn_U271_24' U271-24 # P45/SIN3 NET 'No_Conn_U271_25' U271-25 # P46/SCK3 NET 'No_Conn_U271_26' U271-26 # P47/SOT3 NET 'No_Conn_U271_28' U271-28 # P50/PPG0 NET 'No_Conn_U271_31' U271-31 # P53/PPG3 NET 'No_Conn_U271_32' U271-32 # P54/PPG4 NET 'No_Conn_U271_33' U271-33 # P55/PPG5/ADTG NET 'No_Conn_U271_47' U271-47 # P56/TIN NET 'No_Conn_U271_48' U271-48 # P57/TOT/WOT NET 'No_Conn_U271_87' U271-87 # P02/IN2 NET 'No_Conn_U271_88' U271-88 # P03/IN3 NET 'No_Conn_U271_89' U271-89 # P04/IN4 NET 'No_Conn_U271_90' U271-90 # P05/IN5 NET 'No_Conn_U271_91' U271-91 # P06/OUT0 NET 'No_Conn_U271_92' U271-92 # P07/OUT1 NET 'No_Conn_U271_93' U271-93 # P10/OUT2 NET 'No_Conn_U271_94' U271-94 # P11/OUT3 NET 'No_Conn_U271_95' U271-95 # P12/OUT4 NET 'No_Conn_U271_96' U271-96 # P13/OUT5 NET 'No_Conn_U271_97' U271-97 # P14/RX1 NET 'No_Conn_U271_98' U271-98 # P15/TX1 NET 'No_Conn_U271_99' U271-99 # P16/SGO NET 'No_Conn_U271_100' U271-100 # P17/SGA # # CMX-0 Nets File # # ByPass Capacitors Base Function GTX_AVCC and GTX_AVTT # -------------------===============----------------------- # # # Original Rev. 15-Nov-2012 # Most Recent Rev. 03-Oct-2013 # # # # This file holds the nets for ALL of Base Function FPGA # GTX_AVCC and GTX_AVTT bypass Capacitors. # # # This net list file includes nets to the following components: # # C1:C48 220 nFd 0603 bypass capacitors # C49:C58 4.7 uFd 0603 bypass capacitors # C59:C62 33 uFd Tant B bypass capacitors # C63,C64 330 uFd Tant D bypass capacitors # # # 220 nFd Bypass Capacitors on the GTX_AVCC supply # NET 'BF_GTX_AVCC' C3-1 C4-2 C7-1 C8-2 NET 'GROUND' C3-2 C4-1 C7-2 C8-1 NET 'BF_GTX_AVCC' C11-1 C12-2 C15-1 C16-2 NET 'GROUND' C11-2 C12-1 C15-2 C16-1 NET 'BF_GTX_AVCC' C19-1 C20-2 C23-1 C24-1 NET 'GROUND' C19-2 C20-1 C23-2 C24-2 NET 'BF_GTX_AVCC' C25-1 C29-1 C30-1 NET 'GROUND' C25-2 C29-2 C30-2 NET 'BF_GTX_AVCC' C33-1 C34-1 C37-1 C38-1 NET 'GROUND' C33-2 C34-2 C37-2 C38-2 NET 'BF_GTX_AVCC' C41-1 C42-1 C46-1 NET 'GROUND' C41-2 C42-2 C46-2 # # 220 nFd Bypass Capacitors on the GTX_AVTT supply # NET 'BF_GTX_AVTT' C1-1 C2-2 C5-1 C6-2 NET 'GROUND' C1-2 C2-1 C5-2 C6-1 NET 'BF_GTX_AVTT' C9-1 C10-2 C13-1 C14-2 NET 'GROUND' C9-2 C10-1 C13-2 C14-1 NET 'BF_GTX_AVTT' C17-1 C18-2 C21-1 C22-2 NET 'GROUND' C17-2 C18-1 C21-2 C22-1 NET 'BF_GTX_AVTT' C26-1 NET 'GROUND' C26-2 NET 'BF_GTX_AVTT' C27-1 C28-1 C31-1 C32-1 NET 'GROUND' C27-2 C28-2 C31-2 C32-2 NET 'BF_GTX_AVTT' C35-1 C36-1 C39-1 C40-1 NET 'GROUND' C35-2 C36-2 C39-2 C40-2 NET 'BF_GTX_AVTT' C43-1 C44-1 C45-1 C48-2 NET 'GROUND' C43-2 C44-2 C45-2 C48-1 NET 'BF_GTX_AVTT' C47-1 NET 'GROUND' C47-2 # # 4.7 uFd Bypass Capacitors both GTX_AVCC and GTX_AVTT # NET 'BF_GTX_AVCC' C50-1 C52-2 C54-2 C56-2 C58-2 NET 'GROUND' C50-2 C52-1 C54-1 C56-1 C58-1 NET 'BF_GTX_AVTT' C49-1 C51-1 C53-2 C55-2 C57-2 NET 'GROUND' C49-2 C51-2 C53-1 C55-1 C57-1 # # 33 uFd Bypass Capacitors both GTX_AVCC and GTX_AVTT # NET 'BF_GTX_AVCC' C60-1 C62-1 NET 'GROUND' C60-2 C62-2 NET 'BF_GTX_AVTT' C59-1 C61-1 NET 'GROUND' C59-2 C61-2 # # 330 uFd Bypass Capacitors both GTX_AVCC and GTX_AVTT # NET 'BF_GTX_AVCC' C63-1 NET 'GROUND' C63-2 NET 'BF_GTX_AVTT' C64-1 NET 'GROUND' C64-2 # # CMX-0 Nets File # # Front-Panel Access Signals #1 and #2 # --------------==============------------ # # # Original Rev. 17-June-2013 # Most Recent Rev. 23-Sept-2013 # # # # This file holds the nets for the Front Panel # Access Signals #1 and #2. # # The source of these two Front Panel Access Signals # is DeBug signals from either the Board Support FPGA, # the Base Function FPGA, or the Topological Processing FPGA. # # The source of these Front Panel Access Signals is # selected with jumpers R365 through R370. # # These two Front Panel Access Signals are 3.3V CMOS # level with 100 Ohm back terminator resistors. These # signals are driven by a 74LVC04A chip. # # Front Panel Access Signal #1 is J12 pin #15. # Front Panel Access Signal #2 is J12 pin #16. # # Note that J12 pins 1, 3, 5, 7, and 9 are Grounds. # # # Resistor Jumpers R365 through R370 to select # the source of the two Front Panel Access Signals. # Select the source of FP Access Signal #1 NET 'BSPT_DEBUG_8' R365-1 # BSPT source for FP Access Signal 1 NET 'BF_DEBUG_8' R366-1 # BF source for FP Access Signal 1 NET 'TP_DEBUG_8' R369-1 # TP source for FP Access Signal 1 # Select the source of FP Access Signal #2 NET 'BSPT_DEBUG_9' R367-2 # BSPT source for FP Access Signal 2 NET 'BF_DEBUG_9' R368-2 # BF source for FP Access Signal 2 NET 'TP_DEBUG_9' R370-2 # TP source for FP Access Signal 2 # Selected FP Access Signals to the Driver Inputs NET 'SELECTED_FP_ACCESS_1' R365-2 R366-2 R369-2 # Selected FP Access 1 NET 'SELECTED_FP_ACCESS_1' R361-1 # Pull-Up on FP Access 1 NET 'SELECTED_FP_ACCESS_1' U323-13 # Driver input for FP Access 1 NET 'SELECTED_FP_ACCESS_2' R367-1 R368-1 R370-1 # Selected FP Access 2 NET 'SELECTED_FP_ACCESS_2' R362-1 # Pull-Up on FP Access 2 NET 'SELECTED_FP_ACCESS_2' U323-11 # Driver input for FP Access 2 NET 'BULK_3V3' R361-2 R362-2 # 3V3 to the Pull-Ups # Driver output pins to the J12 FP Access Signal Pins NET 'FP_ACCESS_1_DRIVE' U323-12 R363-2 # FP Access 1 to Series Term NET 'FP_ACCESS_SIGNAL_1' J12-15 R363-1 # FP Access Signal #1 NET 'FP_ACCESS_2_DRIVE' U323-10 R364-2 # FP Access 2 to Series Term NET 'FP_ACCESS_SIGNAL_2' J12-16 R364-1 # FP Access Signal #2 # # CMX-0 Nets File # # DCI and GTX Calibration Resistors # --===-----===============------------- # # # Original Rev. 16-Nov-2012 # Most Recent Rev. 31-Dec-2012 # # # # This file holds the nets for ALL of the # # - DCI Resistors for the 400 Backplane inputs # # - GTX Termination Calibration Resistors # # for both the Base Function and Topological Processor FPGAs. # # # # This net list file includes nets to the following components: # # U1 Base Function FPGA # # U2 Topological Progessor FPGA # # R191:R198 DCI Resistors on the Base Function FPGA # # R199 GTX Termination Calibration Resistor # on the Base Function FPGA # # R200 GTX Termination Calibration Resistor on # on the Topological Processor FPGA # # # # Connect the 8 DCI Resistors # # Recall that the VRN pin is pulled up to VCCO # and that the VRP pin is pulled down to ground. # # These are ?? Ohm resistors. # NET 'P0TO3_DCI_P' R191-1 NET 'GROUND' R191-2 NET 'P0TO3_DCI_N' R192-1 NET 'BULK_2V5' R192-2 NET 'P4TO7_DCI_P' R193-1 NET 'GROUND' R193-2 NET 'P4TO7_DCI_N' R194-1 NET 'BULK_2V5' R194-2 NET 'P8TO11_DCI_P' R195-1 NET 'GROUND' R195-2 NET 'P8TO11_DCI_N' R196-1 NET 'BULK_2V5' R196-2 NET 'P12TO15_DCI_P' R197-1 NET 'GROUND' R197-2 NET 'P12TO15_DCI_N' R198-1 NET 'BULK_2V5' R198-2 # # Connect the GTX Termination Calibration resistor # for the Base Function FPGA # # This is a precision 100 Ohm resistor. # See Chapter 5 page 274 of the # Virtex-6GTX User Guide. # # The other half of these connections is in: # # ..../Base_Fpga_Assign/highspeed_transmitters_fpga_n2r.txt # NET 'BF_MGTRREF' R199-1 # Base Function FPGA MGTRREF pin NET 'BF_GTX_AVTT' R199-2 # Base Function FPGA MGTAVTTRCAL pin # # Connect the GTX Termination Calibration resistor # for the Topological Processor FPGA # # This is a precision 100 Ohm resistor. # See Chapter 5 page 274 of the # Virtex-6GTX User Guide. # # The other half of these connections is in: # # ..../TP_Fpga_Assign/highspeed_receivers_fpga_n2r.txt # NET 'TP_MGTRREF' R200-1 # Topological FPGA MGTRREF pin NET 'TP_GTX_AVTT' R200-2 # Topological FPGA MGTAVTTRCAL pin # # CMX-0 Nets File # # ByPass Capacitors Topological Processor GTX_AVCC and GTX_AVTT # --------------------=====================------------------------ # # # Original Rev. 17-Nov-2012 # Most Recent Rev. 07-Aug-2013 # # # # This file holds the nets for ALL of Topological Processor # FPGA GTX_AVCC and GTX_AVTT bypass Capacitors. # # # This net list file includes nets to the following components: # # C801:C848 220 nFd 0603 bypass capacitors # C849:C858 4.7 uFd 0603 bypass capacitors # C859:C862 33 uFd Tant B bypass capacitors # C863,C864 330 uFd Tant D bypass capacitors # # # 220 nFd Bypass Capacitors on the TP_GTX_AVCC supply # NET 'TP_GTX_AVCC' C803-1 C804-2 C807-1 C808-2 NET 'GROUND' C803-2 C804-1 C807-2 C808-1 NET 'TP_GTX_AVCC' C811-1 C812-2 C815-1 C816-2 NET 'GROUND' C811-2 C812-1 C815-2 C816-1 NET 'TP_GTX_AVCC' C819-1 C820-2 C823-1 C824-1 NET 'GROUND' C819-2 C820-1 C823-2 C824-2 NET 'TP_GTX_AVCC' C825-1 C829-1 C830-1 NET 'GROUND' C825-2 C829-2 C830-2 NET 'TP_GTX_AVCC' C833-1 C834-1 C837-1 C838-1 NET 'GROUND' C833-2 C834-2 C837-2 C838-2 NET 'TP_GTX_AVCC' C841-1 C842-1 C846-1 NET 'GROUND' C841-2 C842-2 C846-2 # # 220 nFd Bypass Capacitors on the TP_GTX_AVTT supply # NET 'TP_GTX_AVTT' C801-1 C802-2 C805-1 C806-2 NET 'GROUND' C801-2 C802-1 C805-2 C806-1 NET 'TP_GTX_AVTT' C809-1 C810-2 C813-1 C814-2 NET 'GROUND' C809-2 C810-1 C813-2 C814-1 NET 'TP_GTX_AVTT' C817-1 C818-2 C821-1 C822-2 NET 'GROUND' C817-2 C818-1 C821-2 C822-1 NET 'TP_GTX_AVTT' C826-1 NET 'GROUND' C826-2 NET 'TP_GTX_AVTT' C827-1 C828-1 C831-1 C832-1 NET 'GROUND' C827-2 C828-2 C831-2 C832-2 NET 'TP_GTX_AVTT' C835-1 C836-1 C839-1 C840-1 NET 'GROUND' C835-2 C836-2 C839-2 C840-2 NET 'TP_GTX_AVTT' C843-1 C844-1 C845-1 C848-2 NET 'GROUND' C843-2 C844-2 C845-2 C848-1 NET 'TP_GTX_AVTT' C847-1 NET 'GROUND' C847-2 # # 4.7 uFd Bypass Capacitors both TP_GTX_AVCC and TP_GTX_AVTT # NET 'TP_GTX_AVCC' C850-1 C852-2 C854-2 C856-2 C858-2 NET 'GROUND' C850-2 C852-1 C854-1 C856-1 C858-1 NET 'TP_GTX_AVTT' C849-1 C851-1 C853-2 C855-2 C857-2 NET 'GROUND' C849-2 C851-2 C853-1 C855-1 C857-1 # # 33 uFd Bypass Capacitors both TP_GTX_AVCC and TP_GTX_AVTT # NET 'TP_GTX_AVCC' C860-1 C862-1 NET 'GROUND' C860-2 C862-2 NET 'TP_GTX_AVTT' C859-1 C861-1 NET 'GROUND' C859-2 C861-2 # # 330 uFd Bypass Capacitors both TP_GTX_AVCC and TP_GTX_AVTT # NET 'TP_GTX_AVCC' C863-1 NET 'GROUND' C863-2 NET 'TP_GTX_AVTT' C864-1 NET 'GROUND' C864-2 # # CMX-0 Nets File # # MiniPod High-Speed Optical Control and Monitor Nets # -=======------------------------------------------------ # # # Original Rev. 1-Dec-2012 # Most Recent Rev. 16-Jan-2013 # # # # This file holds the nets for all of the Control and Monitor # connections to the 5 MiniPod High-Speed Optical Components. # # Recall that there are 2 MiniPod Transmitters, MP1 and MP2, # that are associated with the Base Function FPGA. # # Recall that there are 3 MiniPod Receivers, MP3, MP4, and MP5 # that are associated with the Topological Processor FPGA. # # All of the MiniPod components receive a Two Wire Serial # Control and Monitoring Bus. There are separate TWS Buses # for the Base Function MiniPod Transmitters and for the # Topological Processor MiniPod Receivers. These 2 TWS # Buses run to the Board Support FPGA. # # In addition there is a separate Interrupt_B signal from # each of the 5 MiniPod components that runs to the Board # Support FPGA. From the Board Support FPGA there is a # Reset_B signal that runs to the 2 MiniPod Transmitters # and a separate Reset_B signal that runs to the 3 MiniPod # Receivers. # # NOTE: At the end of this file "reserve" each of the 7 # No Connections pins on each MiniPod device with # a single point net specification. # # # The components that are involved with these nets include: # # # # # Transmitters for the Base Function FPGA # # Control and Monitoring of MiniPods 1 and 2 # ------------------ # # MiniPods 1,2 TWS Bus NET 'MP12_SDA' MP1-D4 MP2-D4 # MiniPods 1,2 TWS Data pins NET 'MP12_SCL' MP1-E6 MP2-E6 # MiniPods 1,2 TWS Clock pins # # MiniPods 1,2 Reset_B Signal NET 'MP12_RESET_B' MP1-E4 MP2-E4 # MiniPods 1,2 Reset_B # # MiniPod #1 Connections for Interrupt_B and Address 1:3 NET 'MP1_INTRPT_B' MP1-D6 R741-1 # MP1 Interrupt_B and its Pull-Up NET 'BULK_3V3' R741-2 # MP1 Interrupt_B Pull-Up Resistor NET 'MP1_ADRS_0' MP1-G3 R701-1 # MP1 Adrs_0 and its Pull-Down NET 'GROUND' R701-2 # MP1 Adrs_0 Pull-Down Resistor NET 'MP1_ADRS_1' MP1-E3 R711-1 # MP1 Adrs_1 and its Pull-Down NET 'GROUND' R711-2 # MP1 Adrs_1 Pull-Down Resistor NET 'MP1_ADRS_2' MP1-C3 R721-1 # MP1 Adrs_2 and its Pull-Down NET 'GROUND' R721-2 # MP1 Adrs_2 Pull-Down Resistor # # MiniPod #2 Connections for Interrupt_B and Address 1:3 NET 'MP2_INTRPT_B' MP2-D6 R742-1 # MP2 Interrupt_B and its Pull-Up NET 'BULK_3V3' R742-2 # MP2 Interrupt_B Pull-Up Resistor NET 'MP2_ADRS_0' MP2-G3 R702-1 # MP2 Adrs_0 and its Pull-Down NET 'BULK_3V3' R702-2 # MP2 Adrs_0 Pull-Up Resistor NET 'MP2_ADRS_1' MP2-E3 R712-1 # MP2 Adrs_1 and its Pull-Down NET 'GROUND' R712-2 # MP2 Adrs_1 Pull-Down Resistor NET 'MP2_ADRS_2' MP2-C3 R722-1 # MP2 Adrs_2 and its Pull-Down NET 'GROUND' R722-2 # MP2 Adrs_2 Pull-Down Resistor # # Receivers for the Topological Processor FPGA # # Control and Monitoring of MiniPods 3,4, 5 # ----------------- # # MiniPods 3,4,5 TWS Bus NET 'MP345_SDA' MP3-D4 MP4-D4 MP5-D4 # MiniPods 3,4,5 TWS Data pins NET 'MP345_SCL' MP3-E6 MP4-E6 MP5-E6 # MiniPods 3,4,5 TWS Clock pins # # MiniPods 3,4,5 Reset_B Signal NET 'MP345_RESET_B' MP3-E4 MP4-E4 MP5-E4 # MiniPods 3,4,5 Reset_B # # MiniPod #3 Connections for Interrupt_B and Address 1:3 NET 'MP3_INTRPT_B' MP3-D6 R743-1 # MP3 Interrupt_B and its Pull-Up NET 'BULK_3V3' R743-2 # MP3 Interrupt_B Pull-Up Resistor NET 'MP3_ADRS_0' MP3-G3 R703-1 # MP3 Adrs_0 and its Pull-Down NET 'GROUND' R703-2 # MP3 Adrs_0 Pull-Down Resistor NET 'MP3_ADRS_1' MP3-E3 R713-1 # MP3 Adrs_1 and its Pull-Down NET 'GROUND' R713-2 # MP3 Adrs_1 Pull-Down Resistor NET 'MP3_ADRS_2' MP3-C3 R723-1 # MP3 Adrs_2 and its Pull-Down NET 'GROUND' R723-2 # MP3 Adrs_2 Pull-Down Resistor # # MiniPod #4 Connections for Interrupt_B and Address 1:3 NET 'MP4_INTRPT_B' MP4-D6 R744-1 # MP4 Interrupt_B and its Pull-Up NET 'BULK_3V3' R744-2 # MP4 Interrupt_B Pull-Up Resistor NET 'MP4_ADRS_0' MP4-G3 R704-1 # MP4 Adrs_0 and its Pull-Down NET 'BULK_3V3' R704-2 # MP4 Adrs_0 Pull-Up Resistor NET 'MP4_ADRS_1' MP4-E3 R714-1 # MP4 Adrs_1 and its Pull-Down NET 'GROUND' R714-2 # MP4 Adrs_1 Pull-Down Resistor NET 'MP4_ADRS_2' MP4-C3 R724-1 # MP4 Adrs_2 and its Pull-Down NET 'GROUND' R724-2 # MP4 Adrs_2 Pull-Down Resistor # # MiniPod #5 Connections for Interrupt_B and Address 1:3 NET 'MP5_INTRPT_B' MP5-D6 R745-1 # MP5 Interrupt_B and its Pull-Up NET 'BULK_3V3' R745-2 # MP5 Interrupt_B Pull-Up Resistor NET 'MP5_ADRS_0' MP5-G3 R705-1 # MP5 Adrs_0 and its Pull-Down NET 'GROUND' R705-2 # MP5 Adrs_0 Pull-Down Resistor NET 'MP5_ADRS_1' MP5-E3 R715-1 # MP5 Adrs_1 and its Pull-Down NET 'BULK_3V3' R715-2 # MP5 Adrs_1 Pull-Up Resistor NET 'MP5_ADRS_2' MP5-C3 R725-1 # MP5 Adrs_2 and its Pull-Down NET 'GROUND' R725-2 # MP5 Adrs_2 Pull-Down Resistor # # NO CONNECTION Pin on the MiniPods # # # NO Connect Pins on MP1 Single Point Nets NET 'No_Conn_MP1_PIN_C7' MP1-C7 # Reserved Do Not Connect NET 'No_Conn_MP1_PIN_D5' MP1-D5 # Reserved Do Not Connect NET 'No_Conn_MP1_PIN_E5' MP1-E5 # Reserved Do Not Connect NET 'No_Conn_MP1_PIN_E7' MP1-E7 # Reserved Do Not Connect NET 'No_Conn_MP1_PIN_F5' MP1-F5 # Reserved Do Not Connect NET 'No_Conn_MP1_PIN_F6' MP1-F6 # Reserved Do Not Connect NET 'No_Conn_MP1_PIN_G7' MP1-G7 # Reserved Do Not Connect # # NO Connect Pins on MP2 Single Point Nets NET 'No_Conn_MP2_PIN_C7' MP2-C7 # Reserved Do Not Connect NET 'No_Conn_MP2_PIN_D5' MP2-D5 # Reserved Do Not Connect NET 'No_Conn_MP2_PIN_E5' MP2-E5 # Reserved Do Not Connect NET 'No_Conn_MP2_PIN_E7' MP2-E7 # Reserved Do Not Connect NET 'No_Conn_MP2_PIN_F5' MP2-F5 # Reserved Do Not Connect NET 'No_Conn_MP2_PIN_F6' MP2-F6 # Reserved Do Not Connect NET 'No_Conn_MP2_PIN_G7' MP2-G7 # Reserved Do Not Connect # # NO Connect Pins on MP3 Single Point Nets NET 'No_Conn_MP3_PIN_C7' MP3-C7 # Reserved Do Not Connect NET 'No_Conn_MP3_PIN_D5' MP3-D5 # Reserved Do Not Connect NET 'No_Conn_MP3_PIN_E5' MP3-E5 # Reserved Do Not Connect NET 'No_Conn_MP3_PIN_E7' MP3-E7 # Reserved Do Not Connect NET 'No_Conn_MP3_PIN_F5' MP3-F5 # Reserved Do Not Connect NET 'No_Conn_MP3_PIN_F6' MP3-F6 # Reserved Do Not Connect NET 'No_Conn_MP3_PIN_G7' MP3-G7 # Reserved Do Not Connect # # NO Connect Pins on MP4 Single Point Nets NET 'No_Conn_MP4_PIN_C7' MP4-C7 # Reserved Do Not Connect NET 'No_Conn_MP4_PIN_D5' MP4-D5 # Reserved Do Not Connect NET 'No_Conn_MP4_PIN_E5' MP4-E5 # Reserved Do Not Connect NET 'No_Conn_MP4_PIN_E7' MP4-E7 # Reserved Do Not Connect NET 'No_Conn_MP4_PIN_F5' MP4-F5 # Reserved Do Not Connect NET 'No_Conn_MP4_PIN_F6' MP4-F6 # Reserved Do Not Connect NET 'No_Conn_MP4_PIN_G7' MP4-G7 # Reserved Do Not Connect # # NO Connect Pins on MP5 Single Point Nets NET 'No_Conn_MP5_PIN_C7' MP5-C7 # Reserved Do Not Connect NET 'No_Conn_MP5_PIN_D5' MP5-D5 # Reserved Do Not Connect NET 'No_Conn_MP5_PIN_E5' MP5-E5 # Reserved Do Not Connect NET 'No_Conn_MP5_PIN_E7' MP5-E7 # Reserved Do Not Connect NET 'No_Conn_MP5_PIN_F5' MP5-F5 # Reserved Do Not Connect NET 'No_Conn_MP5_PIN_F6' MP5-F6 # Reserved Do Not Connect NET 'No_Conn_MP5_PIN_G7' MP5-G7 # Reserved Do Not Connect # # CMX-0 Nets File # # MiniPod High-Speed Optical Power and Ground Nets # -=======--------------------------------------------- # # # Original Rev. 1-Dec-2012 # Most Recent Rev. 15-Aug-2013 # # # # This file holds the nets for all of the Power and Ground # connections to the High-Speed Optical MiniPod Transmitters # and Receivers. # # Recall that there are 2 MiniPod Transmitters, MP1 and MP2, # that are associated with the Base Function FPGA. # # Recall that there are 3 MiniPod Receivers, MP3, MP4, and MP5 # that are associated with the Topological Processor FPGA. # # All of the MiniPod components receive both filtered 2.5V # and filtered 3.3V power supplies. There is individual # power filtering for each MiniPod component. # # # The components that are involved with these nets include: # # MP1, MP2 Base Function MiniPod Transmitters # MP3:MP5 Topological MiniPod Receivers # # # C681:C685 Input Capacitor 47 nFd 2.5V Filter # C691:C695 Input Capacitor 100 nFd 2.5V Filter # C701:C705 Input Capacitor 33 uFd 2.5V Filter # # L11:L15 Inductor 4.7 uH 2.5V Filter # # C711:C715 Output Capacitor 47 nFd 2.5V Filter # C721:C725 Output Capacitor 100 nFd 2.5V Filter # C731:C735 Output Capacitor 33 uFd 2.5V Filter # # R731:R735 Output Tant Cap Series Resistor 0.5 Ohm 2.5V Filter # # # C741:C745 Input Capacitor 47 nFd 3.3V Filter # C751:C755 Input Capacitor 100 nFd 3.3V Filter # C761:C765 Input Capacitor 33 uFd 3.3V Filter # # L21:L25 Inductor 4.7 uH 3.3V Filter # # C771:C775 Output Capacitor 47 nFd 3.3V Filter # C781:C785 Output Capacitor 100 nFd 3.3V Filter # C791:C795 Output Capacitor 33 uFd 3.3V Filter # # R791:R795 Output Tant Cap Series Resistor 0.5 Ohm 3.3V Filter # # # Ground Connections to the 5 MiniPod Sockets # # # List the Ground connections to MP1 # NET 'GROUND' MP1-A1 MP1-A3 MP1-A5 MP1-A7 MP1-A9 NET 'GROUND' MP1-B1 MP1-B3 MP1-B5 MP1-B7 MP1-B9 NET 'GROUND' MP1-C1 MP1-C2 MP1-C8 MP1-C9 NET 'GROUND' MP1-D3 MP1-D7 NET 'GROUND' MP1-E1 MP1-E2 MP1-E8 MP1-E9 NET 'GROUND' MP1-F3 MP1-F7 NET 'GROUND' MP1-G1 MP1-G2 MP1-G8 MP1-G9 NET 'GROUND' MP1-H1 MP1-H3 MP1-H5 MP1-H7 MP1-H9 NET 'GROUND' MP1-J1 MP1-J3 MP1-J5 MP1-J7 MP1-J9 # # List the Ground connections to MP2 # NET 'GROUND' MP2-A1 MP2-A3 MP2-A5 MP2-A7 MP2-A9 NET 'GROUND' MP2-B1 MP2-B3 MP2-B5 MP2-B7 MP2-B9 NET 'GROUND' MP2-C1 MP2-C2 MP2-C8 MP2-C9 NET 'GROUND' MP2-D3 MP2-D7 NET 'GROUND' MP2-E1 MP2-E2 MP2-E8 MP2-E9 NET 'GROUND' MP2-F3 MP2-F7 NET 'GROUND' MP2-G1 MP2-G2 MP2-G8 MP2-G9 NET 'GROUND' MP2-H1 MP2-H3 MP2-H5 MP2-H7 MP2-H9 NET 'GROUND' MP2-J1 MP2-J3 MP2-J5 MP2-J7 MP2-J9 # # List the Ground connections to MP3 # NET 'GROUND' MP3-A1 MP3-A3 MP3-A5 MP3-A7 MP3-A9 NET 'GROUND' MP3-B1 MP3-B3 MP3-B5 MP3-B7 MP3-B9 NET 'GROUND' MP3-C1 MP3-C2 MP3-C8 MP3-C9 NET 'GROUND' MP3-D3 MP3-D7 NET 'GROUND' MP3-E1 MP3-E2 MP3-E8 MP3-E9 NET 'GROUND' MP3-F3 MP3-F7 NET 'GROUND' MP3-G1 MP3-G2 MP3-G8 MP3-G9 NET 'GROUND' MP3-H1 MP3-H3 MP3-H5 MP3-H7 MP3-H9 NET 'GROUND' MP3-J1 MP3-J3 MP3-J5 MP3-J7 MP3-J9 # # List the Ground connections to MP4 # NET 'GROUND' MP4-A1 MP4-A3 MP4-A5 MP4-A7 MP4-A9 NET 'GROUND' MP4-B1 MP4-B3 MP4-B5 MP4-B7 MP4-B9 NET 'GROUND' MP4-C1 MP4-C2 MP4-C8 MP4-C9 NET 'GROUND' MP4-D3 MP4-D7 NET 'GROUND' MP4-E1 MP4-E2 MP4-E8 MP4-E9 NET 'GROUND' MP4-F3 MP4-F7 NET 'GROUND' MP4-G1 MP4-G2 MP4-G8 MP4-G9 NET 'GROUND' MP4-H1 MP4-H3 MP4-H5 MP4-H7 MP4-H9 NET 'GROUND' MP4-J1 MP4-J3 MP4-J5 MP4-J7 MP4-J9 # # List the Ground connections to MP5 # NET 'GROUND' MP5-A1 MP5-A3 MP5-A5 MP5-A7 MP5-A9 NET 'GROUND' MP5-B1 MP5-B3 MP5-B5 MP5-B7 MP5-B9 NET 'GROUND' MP5-C1 MP5-C2 MP5-C8 MP5-C9 NET 'GROUND' MP5-D3 MP5-D7 NET 'GROUND' MP5-E1 MP5-E2 MP5-E8 MP5-E9 NET 'GROUND' MP5-F3 MP5-F7 NET 'GROUND' MP5-G1 MP5-G2 MP5-G8 MP5-G9 NET 'GROUND' MP5-H1 MP5-H3 MP5-H5 MP5-H7 MP5-H9 NET 'GROUND' MP5-J1 MP5-J3 MP5-J5 MP5-J7 MP5-J9 # Power Connections to MP1 # ----- # # List the 2.5 Volt power connections to MP1 NET 'MP1_2V5' MP1-F4 MP1-G4 MP1-G5 MP1-G6 NET 'BULK_2V5' L11-1 C681-1 C691-2 C701-1 NET 'GROUND' C681-2 C691-1 C701-2 NET 'MP1_2V5' L11-2 C711-2 C721-1 C731-1 NET 'GROUND' C711-1 C721-2 R731-1 NET 'MP1_2V5_FLT_RES' C731-2 R731-2 # # List the 3.3 Volt power connections to MP1 NET 'MP1_3V3' MP1-C4 MP1-C5 MP1-C6 NET 'BULK_3V3' L21-1 C741-1 C751-2 C761-1 NET 'GROUND' C741-2 C751-1 C761-2 NET 'MP1_3V3' L21-2 C771-2 C781-1 C791-1 NET 'GROUND' C771-1 C781-2 R791-1 NET 'MP1_3V3_FLT_RES' C791-2 R791-2 # Power Connections to MP2 # ----- # # List the 2.5 Volt power connections to MP2 NET 'MP2_2V5' MP2-F4 MP2-G4 MP2-G5 MP2-G6 NET 'BULK_2V5' L12-1 C682-1 C692-2 C702-1 NET 'GROUND' C682-2 C692-1 C702-2 NET 'MP2_2V5' L12-2 C712-2 C722-1 C732-1 NET 'GROUND' C712-1 C722-2 R732-1 NET 'MP2_2V5_FLT_RES' C732-2 R732-2 # # List the 3.3 Volt power connections to MP2 NET 'MP2_3V3' MP2-C4 MP2-C5 MP2-C6 NET 'BULK_3V3' L22-1 C742-1 C752-2 C762-1 NET 'GROUND' C742-2 C752-1 C762-2 NET 'MP2_3V3' L22-2 C772-2 C782-1 C792-1 NET 'GROUND' C772-1 C782-2 R792-1 NET 'MP2_3V3_FLT_RES' C792-2 R792-2 # Power Connections to MP3 # ----- # # List the 2.5 Volt power connections to MP3 NET 'MP3_2V5' MP3-F4 MP3-G4 MP3-G5 MP3-G6 NET 'BULK_2V5' L13-1 C683-1 C693-2 C703-1 NET 'GROUND' C683-2 C693-1 C703-2 NET 'MP3_2V5' L13-2 C713-2 C723-1 C733-1 NET 'GROUND' C713-1 C723-2 R733-1 NET 'MP3_2V5_FLT_RES' C733-2 R733-2 # # List the 3.3 Volt power connections to MP3 NET 'MP3_3V3' MP3-C4 MP3-C5 MP3-C6 NET 'BULK_3V3' L23-1 C743-1 C753-2 C763-1 NET 'GROUND' C743-2 C753-1 C763-2 NET 'MP3_3V3' L23-2 C773-2 C783-1 C793-1 NET 'GROUND' C773-1 C783-2 R793-1 NET 'MP3_3V3_FLT_RES' C793-2 R793-2 # Power Connections to MP4 # ----- # # List the 2.5 Volt power connections to MP4 NET 'MP4_2V5' MP4-F4 MP4-G4 MP4-G5 MP4-G6 NET 'BULK_2V5' L14-1 C684-1 C694-2 C704-1 NET 'GROUND' C684-2 C694-1 C704-2 NET 'MP4_2V5' L14-2 C714-2 C724-1 C734-1 NET 'GROUND' C714-1 C724-2 R734-1 NET 'MP4_2V5_FLT_RES' C734-2 R734-2 # # List the 3.3 Volt power connections to MP4 NET 'MP4_3V3' MP4-C4 MP4-C5 MP4-C6 NET 'BULK_3V3' L24-1 C744-1 C754-2 C764-1 NET 'GROUND' C744-2 C754-1 C764-2 NET 'MP4_3V3' L24-2 C774-2 C784-1 C794-1 NET 'GROUND' C774-1 C784-2 R794-1 NET 'MP4_3V3_FLT_RES' C794-2 R794-2 # Power Connections to MP5 # ----- # # List the 2.5 Volt power connections to MP5 NET 'MP5_2V5' MP5-F4 MP5-G4 MP5-G5 MP5-G6 NET 'BULK_2V5' L15-1 C685-1 C695-2 C705-1 NET 'GROUND' C685-2 C695-1 C705-2 NET 'MP5_2V5' L15-2 C715-2 C725-1 C735-1 NET 'GROUND' C715-1 C725-2 R735-1 NET 'MP5_2V5_FLT_RES' C735-2 R735-2 # # List the 3.3 Volt power connections to MP5 NET 'MP5_3V3' MP5-C4 MP5-C5 MP5-C6 NET 'BULK_3V3' L25-1 C745-1 C755-2 C765-1 NET 'GROUND' C745-2 C755-1 C765-2 NET 'MP5_3V3' L25-2 C775-2 C785-1 C795-1 NET 'GROUND' C775-1 C785-2 R795-1 NET 'MP5_3V3_FLT_RES' C795-2 R795-2 # # Finally Ground the Mounting Screw "pins" # on all 5 MiniPOD components. Recall that # the mounting screws are terminal pins on # the MiniPOD component. NET 'GROUND' MP1-SCRW1 MP1-SCRW2 # Ground MiniPOD 1 Mounting Screws. NET 'GROUND' MP2-SCRW1 MP2-SCRW2 # Ground MiniPOD 1 Mounting Screws. NET 'GROUND' MP3-SCRW1 MP3-SCRW2 # Ground MiniPOD 1 Mounting Screws. NET 'GROUND' MP4-SCRW1 MP4-SCRW2 # Ground MiniPOD 1 Mounting Screws. NET 'GROUND' MP5-SCRW1 MP5-SCRW2 # Ground MiniPOD 1 Mounting Screws. # # CMX-0 Nets File # # TTCDec Signals, Power, and Ground Nets # -======----------------------------------- # # # Original Rev. 22-Sept-2012 # Most Recent Rev. 3-Sept-2013 # # # # This file holds the nets for all of the Signal, Power, and # Ground connections for the TTCDec mezzanine card. # # # Recall that the TTCDec mezzanine has two physical connectors. # Both of these connectors have been included in the geometry for # this component. The pin numbers of these 2 connectors are: # H1_1 : H1_64 and H2_1 : H2_64. # # Recall that pins 61 : 64 are the 4 center blade pins # in each connector and these are Ground pins. # # Recall that the TTCDec mezzanine uses only 3.3 V power. # # This file includes the power supply bypass capacitors for # the TTCDec mezzanine card. # # # The components referenced in this file are: # # TTC_Mez the TTCDec Mezzanine Card # # C431, C432 47 nFd Bypass capacitors BULK_3V3 # C433, C434 100 nFd Bypass capacitors BULK_3V3 # # # Input Control Signals to the TTCDec # # The TTCDec receives 3 control type signals from the # the Board Support FPGA. These are 3.3V CMOS signals. # NET 'TTC_PD' TTC_Mez-H1_42 # Clock Changeover Mode: Protected or DeBug NET 'TTC_CLK_SEL' TTC_Mez-H1_44 # Select 40 MHz rock or TTCrx clock source NET 'TTC_RESET_B' TTC_Mez-H1_29 # Reset the TTCrx ASIC # # I2C Bus Signals to the TTCDec # # The TTCDec has an I2C Bus connection with the Board # Support FPGA. The 2 lines of the I2C Bus are 3.3V CMOS signals. # NET 'TTC_SCL' TTC_Mez-H1_43 # I2C Serial Clock BSPT_FPGA --> TTCDec NET 'TTC_SDA' TTC_Mez-H1_45 # I2C serail data bi-directional BSPT <-> TTCDec # # TTCDec Output Signals going to Translator-Buffer Inputs # NET 'TTC_BRCST_2' TTC_Mez-H2_26 U151-2 # TTC_BRCST_2 TTC to Trnsltr NET 'TTC_BRCST_3' TTC_Mez-H2_27 U151-3 # TTC_BRCST_3 TTC to Trnsltr NET 'TTC_BRCST_4' TTC_Mez-H2_28 U151-5 # TTC_BRCST_4 TTC to Trnsltr NET 'TTC_BRCST_5' TTC_Mez-H2_29 U151-6 # TTC_BRCST_5 TTC to Trnsltr NET 'TTC_BRCST_6' TTC_Mez-H2_32 U151-8 # TTC_BRCST_6 TTC to Trnsltr NET 'TTC_BRCST_7' TTC_Mez-H2_31 U151-9 # TTC_BRCST_7 TTC to Trnsltr NET 'TTC_BRCST_STR_1' TTC_Mez-H2_25 U151-11 # TTC_BRCST_STR_1 TTC to Trnsltr NET 'TTC_BRCST_STR_2' TTC_Mez-H2_30 U151-12 # TTC_BRCST_STR_2 TTC to Trnsltr NET 'TTC_SIN_ERR_STR' TTC_Mez-H2_1 U151-13 # TTC_SIN_ERR_STR TTC to Trnsltr NET 'TTC_DB_ERR_STR' TTC_Mez-H2_2 U151-14 # TTC_DB_ERR_STR TTC to Trnsltr NET 'TTC_CLK_40_L1A' TTC_Mez-H2_6 U151-16 # TTC_CLK_40_L1A TTC to Trnsltr NET 'TTC_BNCH_CNT_RES' TTC_Mez-H2_33 U151-17 # TTC_BNCH_CNT_RES TTC to Trnsltr NET 'TTC_EV_CNT_RES' TTC_Mez-H2_34 U151-19 # TTC_EV_CNT_RES TTC to Trnsltr NET 'TTC_EV_CNT_H_STR' TTC_Mez-H2_37 U151-20 # TTC_EV_CNT_H_STR TTC to Trnsltr NET 'TTC_EV_CNT_L_STR' TTC_Mez-H2_40 U151-22 # TTC_EV_CNT_L_STR TTC to Trnsltr NET 'TTC_BNCH_CNT_STR' TTC_Mez-H2_39 U151-23 # TTC_BNCH_CNT_STR TTC to Trnsltr NET 'TTC_B_CNT_0' TTC_Mez-H2_44 U152-2 # TTC_B_CNT_0 TTC to Trnsltr NET 'TTC_B_CNT_1' TTC_Mez-H2_43 U152-3 # TTC_B_CNT_1 TTC to Trnsltr NET 'TTC_B_CNT_2' TTC_Mez-H2_46 U152-5 # TTC_B_CNT_2 TTC to Trnsltr NET 'TTC_B_CNT_3' TTC_Mez-H2_45 U152-6 # TTC_B_CNT_3 TTC to Trnsltr NET 'TTC_B_CNT_4' TTC_Mez-H2_48 U152-8 # TTC_B_CNT_4 TTC to Trnsltr NET 'TTC_B_CNT_5' TTC_Mez-H2_47 U152-9 # TTC_B_CNT_5 TTC to Trnsltr NET 'TTC_B_CNT_6' TTC_Mez-H2_52 U152-11 # TTC_B_CNT_6 TTC to Trnsltr NET 'TTC_B_CNT_7' TTC_Mez-H2_51 U152-12 # TTC_B_CNT_7 TTC to Trnsltr NET 'TTC_B_CNT_8' TTC_Mez-H2_54 U152-13 # TTC_B_CNT_8 TTC to Trnsltr NET 'TTC_B_CNT_9' TTC_Mez-H2_53 U152-14 # TTC_B_CNT_9 TTC to Trnsltr NET 'TTC_B_CNT_10' TTC_Mez-H2_56 U152-16 # TTC_B_CNT_10 TTC to Trnsltr NET 'TTC_B_CNT_11' TTC_Mez-H2_55 U152-17 # TTC_B_CNT_11 TTC to Trnsltr NET 'TTC_DQ_0' TTC_Mez-H1_3 U152-19 # TTC_DQ_0 TTC to Trnsltr NET 'TTC_DQ_1' TTC_Mez-H1_4 U152-20 # TTC_DQ_1 TTC to Trnsltr NET 'TTC_DQ_2' TTC_Mez-H1_5 U152-22 # TTC_DQ_2 TTC to Trnsltr NET 'TTC_DQ_3' TTC_Mez-H1_6 U152-23 # TTC_DQ_3 TTC to Trnsltr NET 'TTC_L1_ACCEPT' TTC_Mez-H2_38 U153-2 # TTC_L1_ACCEPT TTC to Trnsltr NET 'TTC_Spare_1_3' U153-3 # TTC_Spare_1_3 TTC to Trnsltr NET 'TTC_SER_B_CH' TTC_Mez-H2_60 U153-5 # TTC_SER_B_CH TTC to Trnsltr NET 'TTC_Spare_2_3' U153-6 # TTC_Spare_2_3 TTC to Trnsltr NET 'TTC_D_OUT_STR' TTC_Mez-H1_1 U153-8 # TTC_D_OUT_STR TTC to Trnsltr NET 'TTC_Spare_3_3' U153-9 # TTC_Spare_3_3 TTC to Trnsltr NET 'TTC_READY' TTC_Mez-H1_30 U153-11 # TTC_READY (STATUS_1) TTC to Trnsltr NET 'TTC_STATUS_2' TTC_Mez-H1_32 U153-12 # TTC_STATUS_2 TTC to Trnsltr NET 'TTC_D_OUT_0' TTC_Mez-H1_19 U153-13 # TTC_D_OUT_0 TTC to Trnsltr NET 'TTC_D_OUT_1' TTC_Mez-H1_20 U153-14 # TTC_D_OUT_1 TTC to Trnsltr NET 'TTC_D_OUT_2' TTC_Mez-H1_21 U153-16 # TTC_D_OUT_2 TTC to Trnsltr NET 'TTC_D_OUT_3' TTC_Mez-H1_22 U153-17 # TTC_D_OUT_3 TTC to Trnsltr NET 'TTC_D_OUT_4' TTC_Mez-H1_23 U153-19 # TTC_D_OUT_4 TTC to Trnsltr NET 'TTC_D_OUT_5' TTC_Mez-H1_24 U153-20 # TTC_D_OUT_5 TTC to Trnsltr NET 'TTC_D_OUT_6' TTC_Mez-H1_25 U153-22 # TTC_D_OUT_6 TTC to Trnsltr NET 'TTC_D_OUT_7' TTC_Mez-H1_26 U153-23 # TTC_D_OUT_7 TTC to Trnsltr NET 'TTC_SUB_ADRS_0' TTC_Mez-H1_9 U154-2 # TTC_SUB_ADRS_0 TTC to Trnsltr NET 'TTC_SUB_ADRS_1' TTC_Mez-H1_10 U154-3 # TTC_SUB_ADRS_1 TTC to Trnsltr NET 'TTC_SUB_ADRS_2' TTC_Mez-H1_11 U154-5 # TTC_SUB_ADRS_2 TTC to Trnsltr NET 'TTC_SUB_ADRS_3' TTC_Mez-H1_12 U154-6 # TTC_SUB_ADRS_3 TTC to Trnsltr NET 'TTC_SUB_ADRS_4' TTC_Mez-H1_13 U154-8 # TTC_SUB_ADRS_4 TTC to Trnsltr NET 'TTC_SUB_ADRS_5' TTC_Mez-H1_14 U154-9 # TTC_SUB_ADRS_5 TTC to Trnsltr NET 'TTC_SUB_ADRS_6' TTC_Mez-H1_15 U154-11 # TTC_SUB_ADRS_6 TTC to Trnsltr NET 'TTC_SUB_ADRS_7' TTC_Mez-H1_16 U154-12 # TTC_SUB_ADRS_7 TTC to Trnsltr # # DIRECTION and OUTPUT_ENABLE_B signals on the U151:U154 Translators # # The Direction of the Translator/Buffer chips for the TTCDec # Output Bus is set by Jumper 28. JMP28 pulls the Direction # control pin to these buffers LOW. Direction "B" --> "A". NET 'TTC_TRNSLT_DIR' U151-1 U151-24 # Direction of the TTCDec Output NET 'TTC_TRNSLT_DIR' U152-1 U152-24 # Bus Translators / Buffers NET 'TTC_TRNSLT_DIR' U153-1 U153-24 # Want to Receive 3.3V on "B" NET 'TTC_TRNSLT_DIR' U154-1 # Drive 2.5V on "A". B-->A NET 'TTC_TRNSLT_DIR' JMP28-1 # Thus Direction must be LOW NET 'GROUND' JMP28-2 # Ground end of the DIR Jumper NET 'TTC_TRNSLT_OE_B' U151-25 U151-48 # Output_Enable_B of the TTCDec NET 'TTC_TRNSLT_OE_B' U152-25 U152-48 # Output Translator/Buffer chips. NET 'TTC_TRNSLT_OE_B' U153-25 U153-48 # Only want to enable these Drivers NET 'TTC_TRNSLT_OE_B' U154-48 # if BOARD_POWER_OK & BSPT_DONE # are asserted and BSPT_FPGA # says it is OK to do so. # NOTE that Direction and OE_B control # of the section of U154 that is used to put # the Geo Adrs onto some CHIP_ID lines is shown below. # # TTCDec Translator-Buffer Outputs going to Series Terminator Resistor Networks # NET 'TB_TTC_BRCST_2' U151-47 N151-1 # TTC_BRCST_2 Trnsltr to STerm NET 'TB_TTC_BRCST_3' U151-46 N151-2 # TTC_BRCST_3 Trnsltr to STerm NET 'TB_TTC_BRCST_4' U151-44 N151-3 # TTC_BRCST_4 Trnsltr to STerm NET 'TB_TTC_BRCST_5' U151-43 N151-4 # TTC_BRCST_5 Trnsltr to STerm NET 'TB_TTC_BRCST_6' U151-41 N151-5 # TTC_BRCST_6 Trnsltr to STerm NET 'TB_TTC_BRCST_7' U151-40 N151-6 # TTC_BRCST_7 Trnsltr to STerm NET 'TB_TTC_BRCST_STR_1' U151-38 N151-7 # TTC_BRCST_STR_1 Trnsltr to STerm NET 'TB_TTC_BRCST_STR_2' U151-37 N151-8 # TTC_BRCST_STR_2 Trnsltr to STerm NET 'TB_TTC_SIN_ERR_STR' U151-36 N152-1 # TTC_SIN_ERR_STR Trnsltr to STerm NET 'TB_TTC_DB_ERR_STR' U151-35 N152-2 # TTC_DB_ERR_STR Trnsltr to STerm NET 'TB_TTC_CLK_40_L1A' U151-33 N152-3 # TTC_CLK_40_L1A Trnsltr to STerm NET 'TB_TTC_BNCH_CNT_RES' U151-32 N152-4 # TTC_BNCH_CNT_RES Trnsltr to STerm NET 'TB_TTC_EV_CNT_RES' U151-30 N152-5 # TTC_EV_CNT_RES Trnsltr to STerm NET 'TB_TTC_EV_CNT_H_STR' U151-29 N152-6 # TTC_EV_CNT_H_STR Trnsltr to STerm NET 'TB_TTC_EV_CNT_L_STR' U151-27 N152-7 # TTC_EV_CNT_L_STR Trnsltr to STerm NET 'TB_TTC_BNCH_CNT_STR' U151-26 N152-8 # TTC_BNCH_CNT_STR Trnsltr to STerm NET 'TB_TTC_B_CNT_0' U152-47 N153-1 # TTC_B_CNT_0 Trnsltr to STerm NET 'TB_TTC_B_CNT_1' U152-46 N153-2 # TTC_B_CNT_1 Trnsltr to STerm NET 'TB_TTC_B_CNT_2' U152-44 N153-3 # TTC_B_CNT_2 Trnsltr to STerm NET 'TB_TTC_B_CNT_3' U152-43 N153-4 # TTC_B_CNT_3 Trnsltr to STerm NET 'TB_TTC_B_CNT_4' U152-41 N153-5 # TTC_B_CNT_4 Trnsltr to STerm NET 'TB_TTC_B_CNT_5' U152-40 N153-6 # TTC_B_CNT_5 Trnsltr to STerm NET 'TB_TTC_B_CNT_6' U152-38 N153-7 # TTC_B_CNT_6 Trnsltr to STerm NET 'TB_TTC_B_CNT_7' U152-37 N153-8 # TTC_B_CNT_7 Trnsltr to STerm NET 'TB_TTC_B_CNT_8' U152-36 N154-1 # TTC_B_CNT_8 Trnsltr to STerm NET 'TB_TTC_B_CNT_9' U152-35 N154-2 # TTC_B_CNT_9 Trnsltr to STerm NET 'TB_TTC_B_CNT_10' U152-33 N154-3 # TTC_B_CNT_10 Trnsltr to STerm NET 'TB_TTC_B_CNT_11' U152-32 N154-4 # TTC_B_CNT_11 Trnsltr to STerm NET 'TB_TTC_DQ_0' U152-30 N154-5 # TTC_DQ_0 Trnsltr to STerm NET 'TB_TTC_DQ_1' U152-29 N154-6 # TTC_DQ_1 Trnsltr to STerm NET 'TB_TTC_DQ_2' U152-27 N154-7 # TTC_DQ_2 Trnsltr to STerm NET 'TB_TTC_DQ_3' U152-26 N154-8 # TTC_DQ_3 Trnsltr to STerm NET 'TB_TTC_L1_ACCEPT' U153-47 N155-1 # TTC_L1_ACCEPT Trnsltr to STerm NET 'TB_TTC_Spare_1_3' U153-46 N155-2 # TTC_Spare_1_3 Trnsltr to STerm NET 'TB_TTC_SER_B_CH' U153-44 N155-3 # TTC_SER_B_CH Trnsltr to STerm NET 'TB_TTC_Spare_2_3' U153-43 N155-4 # TTC_Spare_2_3 Trnsltr to STerm NET 'TB_TTC_D_OUT_STR' U153-41 N155-5 # TTC_D_OUT_STR Trnsltr to STerm NET 'TB_TTC_Spare_3_3' U153-40 N155-6 # TTC_Spare_3_3 Trnsltr to STerm NET 'TB_TTC_READY' U153-38 N155-7 # TTC_READY (STATUS_1) Trnsltr to STerm NET 'TB_TTC_STATUS_2' U153-37 N155-8 # TTC_STATUS_2 Trnsltr to STerm NET 'TB_TTC_D_OUT_0' U153-36 N156-1 # TTC_D_OUT_0 Trnsltr to STerm NET 'TB_TTC_D_OUT_1' U153-35 N156-2 # TTC_D_OUT_1 Trnsltr to STerm NET 'TB_TTC_D_OUT_2' U153-33 N156-3 # TTC_D_OUT_2 Trnsltr to STerm NET 'TB_TTC_D_OUT_3' U153-32 N156-4 # TTC_D_OUT_3 Trnsltr to STerm NET 'TB_TTC_D_OUT_4' U153-30 N156-5 # TTC_D_OUT_4 Trnsltr to STerm NET 'TB_TTC_D_OUT_5' U153-29 N156-6 # TTC_D_OUT_5 Trnsltr to STerm NET 'TB_TTC_D_OUT_6' U153-27 N156-7 # TTC_D_OUT_6 Trnsltr to STerm NET 'TB_TTC_D_OUT_7' U153-26 N156-8 # TTC_D_OUT_7 Trnsltr to STerm NET 'TB_TTC_SUB_ADRS_0' U154-47 N157-1 # TTC_SUB_ADRS_0 Trnsltr to STerm NET 'TB_TTC_SUB_ADRS_1' U154-46 N157-2 # TTC_SUB_ADRS_1 Trnsltr to STerm NET 'TB_TTC_SUB_ADRS_2' U154-44 N157-3 # TTC_SUB_ADRS_2 Trnsltr to STerm NET 'TB_TTC_SUB_ADRS_3' U154-43 N157-4 # TTC_SUB_ADRS_3 Trnsltr to STerm NET 'TB_TTC_SUB_ADRS_4' U154-41 N157-5 # TTC_SUB_ADRS_4 Trnsltr to STerm NET 'TB_TTC_SUB_ADRS_5' U154-40 N157-6 # TTC_SUB_ADRS_5 Trnsltr to STerm NET 'TB_TTC_SUB_ADRS_6' U154-38 N157-7 # TTC_SUB_ADRS_6 Trnsltr to STerm NET 'TB_TTC_SUB_ADRS_7' U154-37 N157-8 # TTC_SUB_ADRS_7 Trnsltr to STerm # # TTCDec Outputs # # Buffered, Series Terminated, 2.5V TTC Output Bus Signals # NET 'BUF_TTC_BRCST_2' N151-16 # Buffered TTC_BRCST_2 NET 'BUF_TTC_BRCST_3' N151-15 # Buffered TTC_BRCST_3 NET 'BUF_TTC_BRCST_4' N151-14 # Buffered TTC_BRCST_4 NET 'BUF_TTC_BRCST_5' N151-13 # Buffered TTC_BRCST_5 NET 'BUF_TTC_BRCST_6' N151-12 # Buffered TTC_BRCST_6 NET 'BUF_TTC_BRCST_7' N151-11 # Buffered TTC_BRCST_7 NET 'BUF_TTC_BRCST_STR_1' N151-10 # Buffered TTC_BRCST_STR_1 NET 'BUF_TTC_BRCST_STR_2' N151-9 # Buffered TTC_BRCST_STR_2 NET 'BUF_TTC_SIN_ERR_STR' N152-16 # Buffered TTC_SIN_ERR_STR NET 'BUF_TTC_DB_ERR_STR' N152-15 # Buffered TTC_DB_ERR_STR NET 'BUF_TTC_CLK_40_L1A' N152-14 # Buffered TTC_CLK_40_L1A NET 'BUF_TTC_BNCH_CNT_RES' N152-13 # Buffered TTC_BNCH_CNT_RES NET 'BUF_TTC_EV_CNT_RES' N152-12 # Buffered TTC_EV_CNT_RES NET 'BUF_TTC_EV_CNT_H_STR' N152-11 # Buffered TTC_EV_CNT_H_STR NET 'BUF_TTC_EV_CNT_L_STR' N152-10 # Buffered TTC_EV_CNT_L_STR NET 'BUF_TTC_BNCH_CNT_STR' N152-9 # Buffered TTC_BNCH_CNT_STR NET 'BUF_TTC_B_CNT_0' N153-16 # Buffered TTC_B_CNT_0 NET 'BUF_TTC_B_CNT_1' N153-15 # Buffered TTC_B_CNT_1 NET 'BUF_TTC_B_CNT_2' N153-14 # Buffered TTC_B_CNT_2 NET 'BUF_TTC_B_CNT_3' N153-13 # Buffered TTC_B_CNT_3 NET 'BUF_TTC_B_CNT_4' N153-12 # Buffered TTC_B_CNT_4 NET 'BUF_TTC_B_CNT_5' N153-11 # Buffered TTC_B_CNT_5 NET 'BUF_TTC_B_CNT_6' N153-10 # Buffered TTC_B_CNT_6 NET 'BUF_TTC_B_CNT_7' N153-9 # Buffered TTC_B_CNT_7 NET 'BUF_TTC_B_CNT_8' N154-16 # Buffered TTC_B_CNT_8 NET 'BUF_TTC_B_CNT_9' N154-15 # Buffered TTC_B_CNT_9 NET 'BUF_TTC_B_CNT_10' N154-14 # Buffered TTC_B_CNT_10 NET 'BUF_TTC_B_CNT_11' N154-13 # Buffered TTC_B_CNT_11 NET 'BUF_TTC_DQ_0' N154-12 # Buffered TTC_DQ_0 NET 'BUF_TTC_DQ_1' N154-11 # Buffered TTC_DQ_1 NET 'BUF_TTC_DQ_2' N154-10 # Buffered TTC_DQ_2 NET 'BUF_TTC_DQ_3' N154-9 # Buffered TTC_DQ_3 NET 'BUF_TTC_L1_ACCEPT' N155-16 # Buffered TTC_L1_ACCEPT NET 'BUF_TTC_Spare_1_3' N155-15 # Buffered TTC_Spare_1_3 NET 'BUF_TTC_SER_B_CH' N155-14 # Buffered TTC_SER_B_CH NET 'BUF_TTC_Spare_2_3' N155-13 # Buffered TTC_Spare_2_3 NET 'BUF_TTC_D_OUT_STR' N155-12 # Buffered TTC_D_OUT_STR NET 'BUF_TTC_Spare_3_3' N155-11 # Buffered TTC_Spare_3_3 NET 'BUF_TTC_READY' N155-10 # Buffered TTC_READY (STATUS_1) NET 'BUF_TTC_STATUS_2' N155-9 # Buffered TTC_STATUS_2 NET 'BUF_TTC_D_OUT_0' N156-16 # Buffered TTC_D_OUT_0 NET 'BUF_TTC_D_OUT_1' N156-15 # Buffered TTC_D_OUT_1 NET 'BUF_TTC_D_OUT_2' N156-14 # Buffered TTC_D_OUT_2 NET 'BUF_TTC_D_OUT_3' N156-13 # Buffered TTC_D_OUT_3 NET 'BUF_TTC_D_OUT_4' N156-12 # Buffered TTC_D_OUT_4 NET 'BUF_TTC_D_OUT_5' N156-11 # Buffered TTC_D_OUT_5 NET 'BUF_TTC_D_OUT_6' N156-10 # Buffered TTC_D_OUT_6 NET 'BUF_TTC_D_OUT_7' N156-9 # Buffered TTC_D_OUT_7 NET 'BUF_TTC_SUB_ADRS_0' N157-16 # Buffered TTC_SUB_ADRS_0 NET 'BUF_TTC_SUB_ADRS_1' N157-15 # Buffered TTC_SUB_ADRS_1 NET 'BUF_TTC_SUB_ADRS_2' N157-14 # Buffered TTC_SUB_ADRS_2 NET 'BUF_TTC_SUB_ADRS_3' N157-13 # Buffered TTC_SUB_ADRS_3 NET 'BUF_TTC_SUB_ADRS_4' N157-12 # Buffered TTC_SUB_ADRS_4 NET 'BUF_TTC_SUB_ADRS_5' N157-11 # Buffered TTC_SUB_ADRS_5 NET 'BUF_TTC_SUB_ADRS_6' N157-10 # Buffered TTC_SUB_ADRS_6 NET 'BUF_TTC_SUB_ADRS_7' N157-9 # Buffered TTC_SUB_ADRS_7 # # CHIP_ID Signals # # Loaded Into the TTCDec over TTC_D_OUT(7:0) and TTC_SUB_ADRS(7:0) # During a TTCDec Reset # # These 16 bits CHIP_ID(13:0) and MASTER_MODE(1:0) # must be loaded into the TTC_D_OUT(7:0) and # TTC_SUB_ADRS(7:0) when the TTCDec is Reset. # # These 16 bits come from the 7 Geographic Address lines # and from 9 pairs of jumpers. # # The 7 Geographic Address signals are driven onto the # TTC_D_OUT(7:6) and TTC_SUB_ADRS(4:0) as follows # # GEO_ADRS_0 ---> D_OUT_6 = CHIP_ID_6 # GEO_ADRS_1 ---> D_OUT_7 = CHIP_ID_7 # GEO_ADRS_2 ---> SUB_ADRS_0 = CHIP_ID_8 # GEO_ADRS_3 ---> SUB_ADRS_1 = CHIP_ID_9 # GEO_ADRS_4 ---> SUB_ADRS_2 = CHIP_ID_10 # GEO_ADRS_5 ---> SUB_ADRS_3 = CHIP_ID_11 # GEO_ADRS_6 ---> SUB_ADRS_4 = CHIP_ID_12 # # The driver for these 7 signals is the unused 1/2 of # the 4 translator chips listed above for the TTCDec # output signals. This translator has its "A" side # setup as 2.5V receivers. Its "B" side is 3.3V # drivers. Its Direction is always A --> B. Its "B" # side output drivers are enabled when BUF_TTC_READY # is voltage low. # # The 9 pairs of jumpers are bridged across the # TTC_D_OUT(5:0) and TTC_SUB_ADRS(7:5) as follows # # Jumper to # ------------ # Pull Pull # Low High # ----- ----- # JMP10 JMP11 ---> D_OUT_0 = CHIP_ID_0 # JMP12 JMP13 ---> D_OUT_1 = CHIP_ID_1 # JMP14 JMP15 ---> D_OUT_2 = CHIP_ID_2 # JMP16 JMP17 ---> D_OUT_3 = CHIP_ID_3 # JMP18 JMP19 ---> D_OUT_4 = CHIP_ID_4 # JMP20 JMP21 ---> D_OUT_5 = CHIP_ID_5 # JMP22 JMP23 ---> SUB_ADRS_5 = CHIP_ID_13 # JMP24 JMP25 ---> SUB_ADRS_6 = MASTER_MODE_0 # JMP26 JMP27 ---> SUB_ADRS_7 = MASTER_MODE_1 # # Connect the 7 Geographic Address lines to the 2.5V inputs # of the unused half of U154. These Geo Adrs lines become # CHIP_ID(12:6) NET 'OCB_GEO_ADRS_0' U154-35 # TTCDec Reset -> drive D_OUT_6 -> CHIP_ID_6 NET 'OCB_GEO_ADRS_1' U154-33 # TTCDec Reset -> drive D_OUT_7 -> CHIP_ID_7 NET 'OCB_GEO_ADRS_2' U154-32 # TTCDec Reset -> drive SUB_ADRS_0 -> CHIP_ID_8 NET 'OCB_GEO_ADRS_3' U154-30 # TTCDec Reset -> drive SUB_ADRS_1 -> CHIP_ID_9 NET 'OCB_GEO_ADRS_4' U154-29 # TTCDec Reset -> drive SUB_ADRS_2 -> CHIP_ID_10 NET 'OCB_GEO_ADRS_5' U154-27 # TTCDec Reset -> drive SUB_ADRS_3 -> CHIP_ID_11 NET 'OCB_GEO_ADRS_6' U154-26 # TTCDec Reset -> drive SUB_ADRS_4 -> CHIP_ID_12 # # Connect the 3.3V output of these translators to the D_OUT(7:6) # and the SUB_ADRS(4:0) connections on the TTCDec Mezzanine. NET 'TTC_D_OUT_6' U154-14 # TTCDec Reset -> GA_0 -> D_OUT_6 -> CHIP_ID_6 NET 'TTC_D_OUT_7' U154-16 # TTCDec Reset -> GA_1 -> D_OUT_7 -> CHIP_ID_7 NET 'TTC_SUB_ADRS_0' U154-17 # TTCDec Reset -> GA_2 -> SUB_ADRS_0 -> CHIP_ID_8 NET 'TTC_SUB_ADRS_1' U154-19 # TTCDec Reset -> GA_3 -> SUB_ADRS_1 -> CHIP_ID_9 NET 'TTC_SUB_ADRS_2' U154-20 # TTCDec Reset -> GA_4 -> SUB_ADRS_2 -> CHIP_ID_10 NET 'TTC_SUB_ADRS_3' U154-22 # TTCDec Reset -> GA_5 -> SUB_ADRS_3 -> CHIP_ID_11 NET 'TTC_SUB_ADRS_4' U154-23 # TTCDec Reset -> GA_6 -> SUB_ADRS_4 -> CHIP_ID_12 # # Connect the JUMPERS, actually 4.7k Ohm resistors, that drive # D_OUT(5:0) and SUB_ADRS(7:5) when the TTCDec is Reset. NET 'TTC_D_OUT_0' JMP10-2 JMP11-1 # TTCDec Reset D_OUT_0 -> CHIP_ID_0 NET 'TTC_D_OUT_1' JMP12-2 JMP13-1 # TTCDec Reset D_OUT_1 -> CHIP_ID_1 NET 'TTC_D_OUT_2' JMP14-2 JMP15-1 # TTCDec Reset D_OUT_2 -> CHIP_ID_2 NET 'TTC_D_OUT_3' JMP16-2 JMP17-1 # TTCDec Reset D_OUT_3 -> CHIP_ID_3 NET 'TTC_D_OUT_4' JMP18-2 JMP19-1 # TTCDec Reset D_OUT_4 -> CHIP_ID_4 NET 'TTC_D_OUT_5' JMP20-2 JMP21-1 # TTCDec Reset D_OUT_5 -> CHIP_ID_5 NET 'TTC_SUB_ADRS_5' JMP22-2 JMP23-1 # TTCDec Reset SUB_ADRS_5 -> CHIP_ID_13 NET 'TTC_SUB_ADRS_6' JMP24-2 JMP25-1 # TTCDec Reset SUB_ADRS_6 -> MASTER_MODE_0 NET 'TTC_SUB_ADRS_7' JMP26-2 JMP27-1 # TTCDec Reset SUB_ADRS_7 -> MASTER_MODE_1 # # Now tie these Jumpers to 3.3V or Ground as appropriate NET 'BULK_3V3' JMP11-2 JMP13-2 JMP15-2 # Tie Pull-Up Jumpers to 3V3 NET 'BULK_3V3' JMP17-2 JMP19-2 JMP21-2 # Tie Pull-Up Jumpers to 3V3 NET 'BULK_3V3' JMP23-2 JMP25-2 JMP27-2 # Tie Pull-Up Jumpers to 3V3 NET 'GROUND' JMP10-1 JMP12-1 JMP14-1 # Tie Pull-down Jumpers to Ground NET 'GROUND' JMP16-1 JMP18-1 JMP20-1 # Tie Pull-down Jumpers to Ground NET 'GROUND' JMP22-1 JMP24-1 JMP26-1 # Tie Pull-down Jumpers to Ground # # DIRECTION and OUTPUT_ENABLE_B signals for the section # of U154 that is used to put the Geographic Address on # to some of the CHIP_ID lines. # # The Direction of the section of the Translator/Buffer U154 # that puts Geo_Adrs onto CHIP_ID. Receive Geo_Adrs on # the 2.5V side "A". Drive this onto 3.3V side "B". # Thus want "A"-->"B" translation. This required the # Direction control signal to be HI. NET 'TTC_RESET_TRNSLT_DIR' U154-24 # Pull HI the Direction control pin NET 'TTC_RESET_TRNSLT_DIR' R257-1 # on this section of U154, i.e. NET 'BULK_2V5' R257-2 # Geo_Adrs to Chip_ID # The Output_Enable_B of the section of U154 that sends # the Geo_Adrs signals to the TTCDec CHIP_ID inputs # should only be asserted when the TTCDec is being Reset # and both Board_Power_OK and BSPT_DONE are asserted. NET 'TTC_RESET_TRNSLT_OE_B' U154-25 # Output_Enable_B of the translator # that send Geo_Adrs to TTCDec CHIP_ID # # Backplane TTC Clock Buffer and Input to the TTCDec Mezzanine # NET 'TTC_POS' C251-2 # Backplane Pin to TTC Clock Coupling Capacitor NET 'TTC_NEG' C252-2 # Backplane Pin to TTC Clock Coupling Capacitor NET 'CAP_BUF_IN_DIR' C251-1 U155-3 # Coupling Cap to Buff In DIR NET 'CAP_BUF_IN_CMP' C252-1 U155-2 # Coupling Cap to Buff In CMP NET 'BUF_TERM_BIAS' U155-1 U155-4 # Input Termination and Bias NET 'BUF_TERM_BIAS' U155-6 C253-1 # Input Termination and Bias NET 'GROUND' C253-2 # Ground Bias Filter Cap NET 'BUF_TO_TTC_IN_DIR' U155-11 TTC_Mez-H1_35 # Buffer Out to TTCDec In DIR NET 'BUF_TO_TTC_IN_CMP' U155-12 TTC_Mez-H1_37 # Buffer Out to TTCDec In CMP NET 'BUF_TO_TTC_IN_DIR' R251-1 # Pull-Down on the TTC Buf Output NET 'BUF_TO_TTC_IN_CMP' R252-1 # Pull-Down on the TTC Buf Output NET 'GROUND' R251-2 R252-2 # Ground "Vee" end of Pull-Down Resistors NET 'GROUND' U155-7 U155-14 U155-15 # Grounds to Buffer VEE NET 'GROUND' U155-17 U155-18 U155-19 U155-20 # Grounds to Buffer DAP pad NET 'TTC_BUF_VCC' U155-5 U155-8 U155-13 U155-16 # TTC Buffer Vcc Power NET 'TTC_BUF_VCC' C254-1 C255-2 C256-2 C257-1 # TTC Buffer Vcc Bypass NET 'GROUND' C254-2 C255-1 C256-1 C257-2 # Buf Vcc Bypass Ground NET 'TTC_BUF_VCC' R253-2 # TTC Buffer Vcc Source NET 'BULK_3V3' R253-1 # TTC Buffer Vcc Source # # TTCDec Mezzanine Clock Output to Clock Generator Input # # Possible Useful 40 Mhz Clock Outputs from the TTCDec NET 'TTC_CLK_40_DES_1' TTC_Mez-H2_5 R256-2 # TTC_CLK_40_DES_1 Output NET 'TTC_CLK_40_DES_1_PLL_2' TTC_Mez-H2_20 R254-2 # TTC_CLK_40_DES_1_PLL_2 Output NET 'TTC_CLK_40_DES_2_PLL_2' TTC_Mez-H2_17 R255-2 # TTC_CLK_40_DES_2_PLL_2 Output # Select the Reference for the Clocks for the DeSkew 1 # and DeSkew 3 clock signals on CMX by installing: # # either R254 or R256 to select the DeSkew 1 source # and R255 to select the DeSkew 2 source. # # Feedback from the TTCDec PLL Output 1 to the PLL Feedback Input NET 'TTC_CLK_40_DES_1_FBIN' TTC_Mez-H2_16 TTC_Mez-H2_12 # Feedback TTCDec PLL #1 NET 'TTC_CLK_40_DES_2_FBIN' TTC_Mez-H2_13 TTC_Mez-H2_9 # Feedback TTCDec PLL #2 # # TTCDec Mezzanine Card Power Pins 3.30 Volts # NET 'BULK_3V3' TTC_Mez-H1_46 TTC_Mez-H1_48 # TTCDec Power NET 'BULK_3V3' TTC_Mez-H1_50 TTC_Mez-H1_52 # TTCDec Power NET 'BULK_3V3' TTC_Mez-H1_54 TTC_Mez-H1_56 # TTCDec Power NET 'BULK_3V3' TTC_Mez-H1_58 TTC_Mez-H1_60 # TTCDec Power # # TTCDec Mezzanine Card Ground Pins # NET 'GROUND' TTC_Mez-H1_2 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H1_7 TTC_Mez-H1_8 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H1_17 TTC_Mez-H1_18 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H1_27 TTC_Mez-H1_28 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H1_31 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H1_33 TTC_Mez-H1_34 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H1_36 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H1_38 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H1_39 TTC_Mez-H1_40 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H1_41 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H1_47 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H1_59 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H1_61 TTC_Mez-H1_62 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H1_63 TTC_Mez-H1_64 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H2_3 TTC_Mez-H2_4 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H2_7 TTC_Mez-H2_8 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H2_10 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H2_11 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H2_14 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H2_15 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H2_18 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H2_19 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H2_21 TTC_Mez-H2_22 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H2_23 TTC_Mez-H2_24 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H2_35 TTC_Mez-H2_36 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H2_41 TTC_Mez-H2_42 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H2_49 TTC_Mez-H2_50 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H2_57 TTC_Mez-H2_58 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H2_59 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H2_61 TTC_Mez-H2_62 # TTCDec Ground Pins NET 'GROUND' TTC_Mez-H2_63 TTC_Mez-H2_64 # TTCDec Ground Pins # # Ground the 3 TTCDec Mezzanine Card Mounting Screws NET 'GROUND' TTC_Mez-SCRW1 # Ground TTCDec Mounting Screw NET 'GROUND' TTC_Mez-SCRW2 # Ground TTCDec Mounting Screw NET 'GROUND' TTC_Mez-SCRW3 # Ground TTCDec Mounting Screw # # 3.3 Volt Bypass Capacitors for the TTCDec Mezzanine Card # NET 'BULK_3V3' C431-2 C433-1 # 47 nFd 3.3V terminal NET 'BULK_3V3' C432-2 C434-1 # 100 nFd 3.3V terminal NET 'GROUND' C431-1 C433-2 # 47 nFd GND terminal NET 'GROUND' C432-1 C434-2 # 100 nFd GND terminal # # Power and Ground pins on the U151:U154 Translators # # Power and ByPass for U151 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U151-7 U151-18 # U355 3.3V Vccb power NET 'BULK_2V5' U151-31 U151-42 # U355 2.5V Vcca power NET 'GROUND' U151-4 U151-10 # U355 Ground connections NET 'GROUND' U151-15 U151-21 # U355 Ground connections NET 'GROUND' U151-28 U151-34 # U355 Ground connections NET 'GROUND' U151-39 U151-45 # U355 Ground connections NET 'BULK_3V3' C262-1 C263-1 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C261-2 C264-2 # ByPass Cap 2.5V Vcca power NET 'GROUND' C262-2 C263-2 # ByPass Cap Ground connections NET 'GROUND' C261-1 C264-1 # ByPass Cap Ground connections # Power and ByPass for U152 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U152-7 U152-18 # U355 3.3V Vccb power NET 'BULK_2V5' U152-31 U152-42 # U355 2.5V Vcca power NET 'GROUND' U152-4 U152-10 # U355 Ground connections NET 'GROUND' U152-15 U152-21 # U355 Ground connections NET 'GROUND' U152-28 U152-34 # U355 Ground connections NET 'GROUND' U152-39 U152-45 # U355 Ground connections NET 'BULK_3V3' C266-1 C267-1 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C265-2 C268-2 # ByPass Cap 2.5V Vcca power NET 'GROUND' C266-2 C267-2 # ByPass Cap Ground connections NET 'GROUND' C265-1 C268-1 # ByPass Cap Ground connections # Power and ByPass for U153 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U153-7 U153-18 # U355 3.3V Vccb power NET 'BULK_2V5' U153-31 U153-42 # U355 2.5V Vcca power NET 'GROUND' U153-4 U153-10 # U355 Ground connections NET 'GROUND' U153-15 U153-21 # U355 Ground connections NET 'GROUND' U153-28 U153-34 # U355 Ground connections NET 'GROUND' U153-39 U153-45 # U355 Ground connections NET 'BULK_3V3' C270-1 C271-1 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C269-2 C272-2 # ByPass Cap 2.5V Vcca power NET 'GROUND' C270-2 C271-2 # ByPass Cap Ground connections NET 'GROUND' C269-1 C272-1 # ByPass Cap Ground connections # Power and ByPass for U154 74AVCAH164245 power is BULK_2V5 and BULK_3V3 NET 'BULK_3V3' U154-7 U154-18 # U355 3.3V Vccb power NET 'BULK_2V5' U154-31 U154-42 # U355 2.5V Vcca power NET 'GROUND' U154-4 U154-10 # U355 Ground connections NET 'GROUND' U154-15 U154-21 # U355 Ground connections NET 'GROUND' U154-28 U154-34 # U355 Ground connections NET 'GROUND' U154-39 U154-45 # U355 Ground connections NET 'BULK_3V3' C274-1 C275-1 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C273-2 C276-2 # ByPass Cap 2.5V Vcca power NET 'GROUND' C274-2 C275-2 # ByPass Cap Ground connections NET 'GROUND' C273-1 C276-1 # ByPass Cap Ground connections # # CMX-0 Nets File # # ByPass Capacitors Base Function BULK_2V5 Supply # ----------------------------------------------------- # # # Original Rev. 15-Nov-2012 # Most Recent Rev. 3-Aug-2013 # # # # This file holds the nets for ALL of Base Function FPGA # BULK_2V5 supply bypass Capacitors. # -------- # # # The BULK_2V5 is used for the VCCAUX and VCC0 on the FPGA. # ======== ====== ==== # # # This net list file includes the following components: # # C101 every_3rd C170 220 nFd 0603 # C102 every_3rd C171 4.7 uFd 0603 # C103 every_3rd C172 33 uFd Tant B # # # # See the list of "Randomly Added Wherever They Will Fit" # BULK_2V5 bypass capacitors at the end of the organized list. # # # # 220 nFd Bypass Capacitors on the BULK_2V5 for VCCAUX and VCCO # NET 'BULK_2V5' C101-1 C104-1 C107-1 C110-1 NET 'GROUND' C101-2 C104-2 C107-2 C110-2 NET 'BULK_2V5' C113-1 C116-1 C119-1 C122-1 NET 'GROUND' C113-2 C116-2 C119-2 C122-2 NET 'BULK_2V5' C125-1 C128-1 C131-1 C134-1 NET 'GROUND' C125-2 C128-2 C131-2 C134-2 NET 'BULK_2V5' C137-1 C140-1 C143-1 C146-1 NET 'GROUND' C137-2 C140-2 C143-2 C146-2 NET 'BULK_2V5' C149-1 C152-1 C155-1 C158-1 NET 'GROUND' C149-2 C152-2 C155-2 C158-2 NET 'BULK_2V5' C161-1 C164-1 C167-1 C170-1 NET 'GROUND' C161-2 C164-2 C167-2 C170-2 # # 4.7 uFd Bypass Capacitors on the BULK_2V5 for VCCAUX and VCCO # NET 'BULK_2V5' C102-1 C105-1 C108-1 C111-1 NET 'GROUND' C102-2 C105-2 C108-2 C111-2 NET 'BULK_2V5' C114-1 C117-1 C120-1 C123-1 NET 'GROUND' C114-2 C117-2 C120-2 C123-2 NET 'BULK_2V5' C126-1 C129-1 C132-1 C135-1 NET 'GROUND' C126-2 C129-2 C132-2 C135-2 NET 'BULK_2V5' C138-1 C141-1 C144-1 C147-1 NET 'GROUND' C138-2 C141-2 C144-2 C147-2 NET 'BULK_2V5' C150-1 C153-1 C156-1 C159-1 NET 'GROUND' C150-2 C153-2 C156-2 C159-2 NET 'BULK_2V5' C162-1 C165-1 C168-1 C171-1 NET 'GROUND' C162-2 C165-2 C168-2 C171-2 # # 33 uFd Bypass Capacitors on the BULK_2V5 for VCCAUX and VCCO # NET 'BULK_2V5' C103-1 C106-1 C109-1 C112-1 NET 'GROUND' C103-2 C106-2 C109-2 C112-2 NET 'BULK_2V5' C115-1 C118-1 C121-1 C124-1 NET 'GROUND' C115-2 C118-2 C121-2 C124-2 NET 'BULK_2V5' C127-1 C130-1 C133-1 C136-1 NET 'GROUND' C127-2 C130-2 C133-2 C136-2 NET 'BULK_2V5' C139-1 C142-1 C145-1 C148-1 NET 'GROUND' C139-2 C142-2 C145-2 C148-2 NET 'BULK_2V5' C151-1 C154-1 C157-1 C160-1 NET 'GROUND' C151-2 C154-2 C157-2 C160-2 NET 'BULK_2V5' C163-1 C166-1 C169-1 C172-1 NET 'GROUND' C163-2 C166-2 C169-2 C172-2 # # Randomly Added Wherever They Will Fit # ------------------------------------- # # BULK_2V5 Bypass Capacitors # NET 'BULK_2V5' C199-1 C200-1 NET 'GROUND' C199-2 C200-2 # # CMX-0 Nets File # # # BULK_2V5 DC/DC Power Converter # --========------------------------- # # # Original Rev. 20-Dec-2012 # Most Recent Rev. 9-June-2013 # # # # This file holds the nets in the BULK_2V5 # DC/DC Power Converter. # # # This is the converter closest to the front panel. # # Components with Reference Designators in the range # # 1501:1549 are included in the BULK_2V5 Converter. # # # # Define the Connections within the BULK_2V5 Power Converter # ------------------------------------========------------------ # # # Input Power to the Converter: NET 'BULK_5V0' R1501-3 # Power to the Current Sense Resistor NET 'BULK_2V5_CS_TO_L' R1501-2 # Power from the Current Sense NET 'BULK_2V5_CS_TO_L' L1501-1 # Resistor to the Filter Inductor NET 'BULK_2V5_INPUT' L1501-2 # Power feed to the Converter NET 'BULK_2V5_INPUT' C1501-1 # Aluminum Input Cap NET 'BULK_2V5_INPUT' C1503-1 C1504-1 # Taltalum Input Caps NET 'BULK_2V5_INPUT' C1509-1 C1510-1 # Ceramic Input Caps NET 'BULK_2V5_INPUT' C1511-1 C1512-1 # Ceramic Input Caps NET 'BULK_2V5_INPUT' DCDC1-1 # Power Input to the Converter NET 'GROUND' C1501-2 # Aluminum Cap Ground NET 'GROUND' C1503-2 C1504-2 # Taltalum Cap Grounds NET 'GROUND' C1509-2 C1510-2 # Ceramic Cap Grounds NET 'GROUND' C1511-2 C1512-2 # Ceramic Cap Grounds # # Power Output from the Converter: NET 'BULK_2V5' DCDC1-4 # Output Power from the Converter NET 'BULK_2V5' C1517-1 C1518-1 # Ceramic Output Caps NET 'BULK_2V5' C1519-1 C1520-1 # Ceramic Output Caps NET 'BULK_2V5' C1525-1 C1526-1 # Taltalum Output Caps NET 'BULK_2V5' C1527-1 C1528-1 # Taltalum Output Caps NET 'GROUND' C1517-2 C1518-2 # Ceramic Cap Grounds NET 'GROUND' C1519-2 C1520-2 # Ceramic Cap Grounds NET 'GROUND' C1525-2 C1526-2 # Taltalum Cap Grounds NET 'GROUND' C1527-2 C1528-2 # Taltalum Cap Grounds # # DC/DC Converter GROUND Pins NET 'GROUND' DCDC1-2 DCDC1-3 # Converter Grounds # # DC/DC Converter Tracking and Feedback Sense Pins NET 'DCDC_CONV_TRACK' DCDC1-9 # TRACK Pin of BULK_2V5 Converter NET 'BULK_2V5' AKA1501-1 # Positive SENSE Remote Connection NET 'BULK_2V5_SEN_POS' AKA1501-2 DCDC1-5 # Positive SENSE input pin NET 'GROUND' AKA1502-1 # Negative SENSE Remote Connection NET 'BULK_2V5_SEN_NEG' AKA1502-2 DCDC1-6 # Negative SENSE input pin # # DC/DC Converter Output Voltage Rset Resistor NET 'BULK_2V5_SEN_NEG' R1505-1 R1505-2 # Want Trim Pot CW Truning to: NET 'BULK_2V5_VAR_FIX' R1505-3 # Reduce the Resistance and NET 'BULK_2V5_VAR_FIX' R1504-1 # Increase the Output Voltage NET 'BULK_2V5_VO_ADJ' R1504-2 DCDC1-7 # Converter Rset Vout Adj pin NET 'BULK_2V5_SEN_NEG' C1532-1 # Capacitor across the NET 'BULK_2V5_VAR_FIX' C1532-2 # Vout Trim Pot Resistor # # DC/DC Converter Transient Response Control Pin NET 'BULK_2V5_SEN_POS' R1506-2 # Transient Response Resistor NET 'BULK_2V5_TRC_PIN' R1506-1 DCDC1-8 # Transient Response Control pin # # DC/DC Converter NO Connect Pins NET 'No_Conn_DCDC1_10_INH' DCDC1-10 # INH / UVLO Pin #10 Not Used NET 'No_Conn_DCDC1_11_SYNC' DCDC1-11 # SYNC Pin #11 Not Used # # Current Sense High-Side Amplifier NET 'BULK_2V5_CS_SRC' R1501-4 R1502-2 # Current Sense Source Input Resistor NET 'BULK_2V5_CS_AMP_P' U1501-8 R1502-1 # Current Sense Amp Positive Input NET 'BULK_2V5_CS_LOAD' R1501-1 R1503-2 # Current Sense Load Input Resistor NET 'BULK_2V5_CS_AMP_N' U1501-1 R1503-1 # Current Sense Amp Negative Input NET 'BULK_2V5_CS_AMP_OUT' U1501-5 # Current Sense Amp Output NET 'BULK_3V3' U1501-2 C1531-2 # Current Sense Amp V+ Power NET 'GROUND' U1501-4 C1531-1 # Current Sense Amp GROUND NET 'No_Conn_BULK_2V5_CS_AMP_P3' U1501-3 # Current Sense Amp No Conn Pin #3 NET 'No_Conn_BULK_2V5_CS_AMP_P6' U1501-6 # Current Sense Amp No Conn Pin #6 NET 'No_Conn_BULK_2V5_CS_AMP_P7' U1501-7 # Current Sense Amp No Conn Pin #7 # # CMX-0 Nets File # # MiniPOD High-Speed Optical Receiver DC-Blocking Capacitors # -=======----------------------------------------------------- # # # Original Rev. 5-Dec-2012 # Most Recent Rev. 9-Oct-2013 # # # # This file holds the nets for all of the DC-Blocking Capacitors # on the MiniPOD Receiver signals that run from the MP3, MP4, and # MP5 receivers to the Topological Processor FPGA. # # # # The components that are involved with these nets include: # # C1001:C1072 DC-Blocking Caps # # Cap_100_nFd_0201 # Ceramic Capacitor 100 nFd 6.3 Volt # X5R Ceramic 0201 Size SMD # # # MP3, MP4, MP5 12 channel MiniPOD Receivers # # # # # Currently the following channels have a DIR <--> CMP # polarity flip in their differential signal routing. # # MP3 also known as Receiver 1 has flips in: # # Data 0 Fiber 0 QUAD_112_REC_0 # Data 1 Fiber 1 QUAD_110_REC_0 # Data 2 Fiber 2 QUAD_112_REC_3 # Data 3 Fiber 3 QUAD_110_REC_3 # Data 4 Fiber 4 QUAD_112_REC_1 # Data 5 Fiber 5 QUAD_110_REC_2 # Data 6 Fiber 6 QUAD_112_REC_2 # Data 7 Fiber 7 QUAD_110_REC_1 # Data 8 Fiber 8 QUAD_111_REC_3 # Data 9 Fiber 9 QUAD_111_REC_0 # Data 10 Fiber 10 QUAD_111_REC_2 # Data 11 Fiber 11 QUAD_111_REC_1 # # # MP4 also known as Receiver 2 has flips in: # # Data 0 Fiber 0 QUAD_115_REC_3 # Data 1 Fiber 1 QUAD_113_REC_0 # Data 2 Fiber 2 QUAD_115_REC_0 # Data 3 Fiber 3 QUAD_113_REC_3 # Data 4 Fiber 4 QUAD_115_REC_1 # Data 5 Fiber 5 QUAD_113_REC_2 # Data 6 Fiber 6 QUAD_115_REC_2 # Data 7 Fiber 7 QUAD_113_REC_1 # Data 8 Fiber 8 QUAD_114_REC_3 # Data 9 Fiber 9 QUAD_114_REC_0 # Data 10 Fiber 10 QUAD_114_REC_2 # Data 11 Fiber 11 QUAD_114_REC_1 # # # MP5 also known as Receiver 3 has flips in: # # Data 0 Fiber 0 QUAD_118_REC_3 # Data 1 Fibrt 1 QUAD_116_REC_0 # Data 2 Fiber 2 QUAD_118_REC_0 # Data 3 Fiber 3 QUAD_116_REC_1 # Data 4 Fiber 4 QUAD_118_REC_1 # Data 5 Fiber 5 QUAD_116_REC_2 # Data 6 Fiber 6 QUAD_118_REC_2 # Data 7 Fiber 7 QUAD_116_REC_3 # Data 8 Fiber 8 QUAD_117_REC_3 # Data 9 Fiber 9 QUAD_117_REC_0 # Data 10 Fiber 10 QUAD_117_REC_2 # Data 11 Fiber 11 QUAD_117_REC_1 # # # In the follwoing net list the polarity flips can be # see by capacitor reference designators appearing out # of order, e.g. C1007, C1008 C1008, C1007. # # # # MiniPOD Receiver MP3 DC-Blocking Capacitors # ----- NET 'HSOUT_R1_D0_P' C1001-1 # MP3 Rec D0 Out Dir NET 'HSOUT_R1_D0_N' C1002-1 # MP3 Rec D0 Out Cmp NET 'MP3_F00_QUAD_112_REC_0_DIR' C1002-2 # MP3 Fiber 00 Topological Direct Input NET 'MP3_F00_QUAD_112_REC_0_CMP' C1001-2 # MP3 Fiber 00 Topological Complement Input NET 'HSOUT_R1_D2_P' C1004-1 # MP3 Rec D2 Out Dir NET 'HSOUT_R1_D2_N' C1003-1 # MP3 Rec D2 Out Cmp NET 'MP3_F02_QUAD_112_REC_3_DIR' C1003-2 # MP3 Fiber 02 Topological Direct Input NET 'MP3_F02_QUAD_112_REC_3_CMP' C1004-2 # MP3 Fiber 02 Topological Complement Input NET 'HSOUT_R1_D4_P' C1005-1 # MP3 Rec D4 Out Dir NET 'HSOUT_R1_D4_N' C1006-1 # MP3 Rec D4 Out Cmp NET 'MP3_F04_QUAD_112_REC_1_DIR' C1006-2 # MP3 Fiber 04 Topological Direct Input NET 'MP3_F04_QUAD_112_REC_1_CMP' C1005-2 # MP3 Fiber 04 Topological Complement Input NET 'HSOUT_R1_D6_P' C1007-1 # MP3 Rec D6 Out Dir NET 'HSOUT_R1_D6_N' C1008-1 # MP3 Rec D6 Out Cmp NET 'MP3_F06_QUAD_112_REC_2_DIR' C1008-2 # MP3 Fiber 06 Topological Direct Input NET 'MP3_F06_QUAD_112_REC_2_CMP' C1007-2 # MP3 Fiber 06 Topological Complement Input NET 'HSOUT_R1_D1_P' C1009-2 # MP3 Rec D1 Out Dir NET 'HSOUT_R1_D1_N' C1010-2 # MP3 Rec D1 Out Cmp NET 'MP3_F01_QUAD_110_REC_0_DIR' C1010-1 # MP3 Fiber 01 Topological Direct Input NET 'MP3_F01_QUAD_110_REC_0_CMP' C1009-1 # MP3 Fiber 01 Topological Complement Input NET 'HSOUT_R1_D3_P' C1012-2 # MP3 Rec D3 Out Dir NET 'HSOUT_R1_D3_N' C1011-2 # MP3 Rec D3 Out Cmp NET 'MP3_F03_QUAD_110_REC_3_DIR' C1011-1 # MP3 Fiber 03 Topological Direct Input NET 'MP3_F03_QUAD_110_REC_3_CMP' C1012-1 # MP3 Fiber 03 Topological Complement Input NET 'HSOUT_R1_D5_P' C1014-2 # MP3 Rec D5 Out Dir NET 'HSOUT_R1_D5_N' C1013-2 # MP3 Rec D5 Out Cmp NET 'MP3_F05_QUAD_110_REC_2_DIR' C1013-1 # MP3 Fiber 05 Topological Direct Input NET 'MP3_F05_QUAD_110_REC_2_CMP' C1014-1 # MP3 Fiber 05 Topological Complement Input NET 'HSOUT_R1_D7_P' C1015-2 # MP3 Rec D7 Out Dir NET 'HSOUT_R1_D7_N' C1016-2 # MP3 Rec D7 Out Cmp NET 'MP3_F07_QUAD_110_REC_1_DIR' C1016-1 # MP3 Fiber 07 Topological Direct Input NET 'MP3_F07_QUAD_110_REC_1_CMP' C1015-1 # MP3 Fiber 07 Topological Complement Input NET 'HSOUT_R1_D8_P' C1017-1 # MP3 Rec D8 Out Dir NET 'HSOUT_R1_D8_N' C1018-1 # MP3 Rec D8 Out Cmp NET 'MP3_F08_QUAD_111_REC_3_DIR' C1018-2 # MP3 Fiber 08 Topological Direct Input NET 'MP3_F08_QUAD_111_REC_3_CMP' C1017-2 # MP3 Fiber 08 Topological Complement Input NET 'HSOUT_R1_D9_P' C1024-1 # MP3 Rec D9 Out Dir NET 'HSOUT_R1_D9_N' C1023-1 # MP3 Rec D9 Out Cmp NET 'MP3_F09_QUAD_111_REC_0_DIR' C1023-2 # MP3 Fiber 09 Topological Direct Input NET 'MP3_F09_QUAD_111_REC_0_CMP' C1024-2 # MP3 Fiber 09 Topological Complement Input NET 'HSOUT_R1_D10_P' C1019-1 # MP3 Rec D10 Out Dir NET 'HSOUT_R1_D10_N' C1020-1 # MP3 Rec D10 Out Cmp NET 'MP3_F10_QUAD_111_REC_2_DIR' C1020-2 # MP3 Fiber 10 Topological Direct Input NET 'MP3_F10_QUAD_111_REC_2_CMP' C1019-2 # MP3 Fiber 10 Topological Complement Input NET 'HSOUT_R1_D11_P' C1021-1 # MP3 Rec D11 Out Dir NET 'HSOUT_R1_D11_N' C1022-1 # MP3 Rec D11 Out Cmp NET 'MP3_F11_QUAD_111_REC_1_DIR' C1022-2 # MP3 Fiber 11 Topological Direct Input NET 'MP3_F11_QUAD_111_REC_1_CMP' C1021-2 # MP3 Fiber 11 Topological Complement Input # # MiniPOD Receiver MP4 DC-Blocking Capacitors # ----- NET 'HSOUT_R2_D0_P' C1025-1 # MP4 Rec D0 Out Dir NET 'HSOUT_R2_D0_N' C1026-1 # MP4 Rec D0 Out Cmp NET 'MP4_F00_QUAD_115_REC_3_DIR' C1026-2 # MP4 Fiber 00 Topological Direct Input NET 'MP4_F00_QUAD_115_REC_3_CMP' C1025-2 # MP4 Fiber 00 Topological Complement Input NET 'HSOUT_R2_D2_P' C1028-1 # MP4 Rec D2 Out Dir NET 'HSOUT_R2_D2_N' C1027-1 # MP4 Rec D2 Out Cmp NET 'MP4_F02_QUAD_115_REC_0_DIR' C1027-2 # MP4 Fiber 02 Topological Direct Input NET 'MP4_F02_QUAD_115_REC_0_CMP' C1028-2 # MP4 Fiber 02 Topological Complement Input NET 'HSOUT_R2_D4_P' C1029-1 # MP4 Rec D4 Out Dir NET 'HSOUT_R2_D4_N' C1030-1 # MP4 Rec D4 Out Cmp NET 'MP4_F04_QUAD_115_REC_1_DIR' C1030-2 # MP4 Fiber 04 Topological Direct Input NET 'MP4_F04_QUAD_115_REC_1_CMP' C1029-2 # MP4 Fiber 04 Topological Complement Input NET 'HSOUT_R2_D6_P' C1031-1 # MP4 Rec D6 Out Dir NET 'HSOUT_R2_D6_N' C1032-1 # MP4 Rec D6 Out Cmp NET 'MP4_F06_QUAD_115_REC_2_DIR' C1032-2 # MP4 Fiber 06 Topological Direct Input NET 'MP4_F06_QUAD_115_REC_2_CMP' C1031-2 # MP4 Fiber 06 Topological Complement Input NET 'HSOUT_R2_D1_P' C1033-2 # MP4 Rec D1 Out Dir NET 'HSOUT_R2_D1_N' C1034-2 # MP4 Rec D1 Out Cmp NET 'MP4_F01_QUAD_113_REC_0_DIR' C1034-1 # MP4 Fiber 01 Topological Direct Input NET 'MP4_F01_QUAD_113_REC_0_CMP' C1033-1 # MP4 Fiber 01 Topological Complement Input NET 'HSOUT_R2_D3_P' C1036-2 # MP4 Rec D3 Out Dir NET 'HSOUT_R2_D3_N' C1035-2 # MP4 Rec D3 Out Cmp NET 'MP4_F03_QUAD_113_REC_3_DIR' C1035-1 # MP4 Fiber 03 Topological Direct Input NET 'MP4_F03_QUAD_113_REC_3_CMP' C1036-1 # MP4 Fiber 03 Topological Complement Input NET 'HSOUT_R2_D5_P' C1038-2 # MP4 Rec D5 Out Dir NET 'HSOUT_R2_D5_N' C1037-2 # MP4 Rec D5 Out Cmp NET 'MP4_F05_QUAD_113_REC_2_DIR' C1037-1 # MP4 Fiber 05 Topological Direct Input NET 'MP4_F05_QUAD_113_REC_2_CMP' C1038-1 # MP4 Fiber 05 Topological Complement Input NET 'HSOUT_R2_D7_P' C1039-2 # MP4 Rec D7 Out Dir NET 'HSOUT_R2_D7_N' C1040-2 # MP4 Rec D7 Out Cmp NET 'MP4_F07_QUAD_113_REC_1_DIR' C1040-1 # MP4 Fiber 07 Topological Direct Input NET 'MP4_F07_QUAD_113_REC_1_CMP' C1039-1 # MP4 Fiber 07 Topological Complement Input NET 'HSOUT_R2_D8_P' C1041-1 # MP4 Rec D8 Out Dir NET 'HSOUT_R2_D8_N' C1042-1 # MP4 Rec D8 Out Cmp NET 'MP4_F08_QUAD_114_REC_3_DIR' C1042-2 # MP4 Fiber 08 Topological Direct Input NET 'MP4_F08_QUAD_114_REC_3_CMP' C1041-2 # MP4 Fiber 08 Topological Complement Input NET 'HSOUT_R2_D9_P' C1048-1 # MP4 Rec D9 Out Dir NET 'HSOUT_R2_D9_N' C1047-1 # MP4 Rec D9 Out Cmp NET 'MP4_F09_QUAD_114_REC_0_DIR' C1047-2 # MP4 Fiber 09 Topological Direct Input NET 'MP4_F09_QUAD_114_REC_0_CMP' C1048-2 # MP4 Fiber 09 Topological Complement Input NET 'HSOUT_R2_D10_P' C1043-1 # MP4 Rec D10 Out Dir NET 'HSOUT_R2_D10_N' C1044-1 # MP4 Rec D10 Out Cmp NET 'MP4_F10_QUAD_114_REC_2_DIR' C1044-2 # MP4 Fiber 10 Topological Direct Input NET 'MP4_F10_QUAD_114_REC_2_CMP' C1043-2 # MP4 Fiber 10 Topological Complement Input NET 'HSOUT_R2_D11_P' C1045-1 # MP4 Rec D11 Out Dir NET 'HSOUT_R2_D11_N' C1046-1 # MP4 Rec D11 Out Cmp NET 'MP4_F11_QUAD_114_REC_1_DIR' C1046-2 # MP4 Fiber 11 Topological Direct Input NET 'MP4_F11_QUAD_114_REC_1_CMP' C1045-2 # MP4 Fiber 11 Topological Complement Input # # MiniPOD Receiver MP5 DC-Blocking Capacitors # ----- NET 'HSOUT_R3_D0_P' C1049-1 # MP5 Rec D0 Out Dir NET 'HSOUT_R3_D0_N' C1050-1 # MP5 Rec D0 Out Cmp NET 'MP5_F00_QUAD_118_REC_3_DIR' C1050-2 # MP5 Fiber 00 Topological Direct Input NET 'MP5_F00_QUAD_118_REC_3_CMP' C1049-2 # MP5 Fiber 00 Topological Complement Input NET 'HSOUT_R3_D2_P' C1052-1 # MP5 Rec D2 Out Dir NET 'HSOUT_R3_D2_N' C1051-1 # MP5 Rec D2 Out Cmp NET 'MP5_F02_QUAD_118_REC_0_DIR' C1051-2 # MP5 Fiber 02 Topological Direct Input NET 'MP5_F02_QUAD_118_REC_0_CMP' C1052-2 # MP5 Fiber 02 Topological Complement Input NET 'HSOUT_R3_D4_P' C1053-1 # MP5 Rec D4 Out Dir NET 'HSOUT_R3_D4_N' C1054-1 # MP5 Rec D4 Out Cmp NET 'MP5_F04_QUAD_118_REC_1_DIR' C1054-2 # MP5 Fiber 04 Topological Direct Input NET 'MP5_F04_QUAD_118_REC_1_CMP' C1053-2 # MP5 Fiber 04 Topological Complement Input NET 'HSOUT_R3_D6_P' C1055-1 # MP5 Rec D6 Out Dir NET 'HSOUT_R3_D6_N' C1056-1 # MP5 Rec D6 Out Cmp NET 'MP5_F06_QUAD_118_REC_2_DIR' C1056-2 # MP5 Fiber 06 Topological Direct Input NET 'MP5_F06_QUAD_118_REC_2_CMP' C1055-2 # MP5 Fiber 06 Topological Complement Input NET 'HSOUT_R3_D1_P' C1057-2 # MP5 Rec D1 Out Dir NET 'HSOUT_R3_D1_N' C1058-2 # MP5 Rec D1 Out Cmp NET 'MP5_F01_QUAD_116_REC_0_DIR' C1058-1 # MP5 Fiber 01 Topological Direct Input NET 'MP5_F01_QUAD_116_REC_0_CMP' C1057-1 # MP5 Fiber 01 Topological Complement Input NET 'HSOUT_R3_D3_P' C1060-2 # MP5 Rec D3 Out Dir NET 'HSOUT_R3_D3_N' C1059-2 # MP5 Rec D3 Out Cmp NET 'MP5_F03_QUAD_116_REC_1_DIR' C1059-1 # MP5 Fiber 03 Topological Direct Input NET 'MP5_F03_QUAD_116_REC_1_CMP' C1060-1 # MP5 Fiber 03 Topological Complement Input NET 'HSOUT_R3_D5_P' C1062-2 # MP5 Rec D5 Out Dir NET 'HSOUT_R3_D5_N' C1061-2 # MP5 Rec D5 Out Cmp NET 'MP5_F05_QUAD_116_REC_2_DIR' C1061-1 # MP5 Fiber 05 Topological Direct Input NET 'MP5_F05_QUAD_116_REC_2_CMP' C1062-1 # MP5 Fiber 05 Topological Complement Input NET 'HSOUT_R3_D7_P' C1063-2 # MP5 Rec D7 Out Dir NET 'HSOUT_R3_D7_N' C1064-2 # MP5 Rec D7 Out Cmp NET 'MP5_F07_QUAD_116_REC_3_DIR' C1064-1 # MP5 Fiber 07 Topological Direct Input NET 'MP5_F07_QUAD_116_REC_3_CMP' C1063-1 # MP5 Fiber 07 Topological Complement Input NET 'HSOUT_R3_D8_P' C1065-1 # MP5 Rec D8 Out Dir NET 'HSOUT_R3_D8_N' C1066-1 # MP5 Rec D8 Out Cmp NET 'MP5_F08_QUAD_117_REC_3_DIR' C1066-2 # MP5 Fiber 08 Topological Direct Input NET 'MP5_F08_QUAD_117_REC_3_CMP' C1065-2 # MP5 Fiber 08 Topological Complement Input NET 'HSOUT_R3_D9_P' C1072-1 # MP5 Rec D9 Out Dir NET 'HSOUT_R3_D9_N' C1071-1 # MP5 Rec D9 Out Cmp NET 'MP5_F09_QUAD_117_REC_0_DIR' C1071-2 # MP5 Fiber 09 Topological Direct Input NET 'MP5_F09_QUAD_117_REC_0_CMP' C1072-2 # MP5 Fiber 09 Topological Complement Input NET 'HSOUT_R3_D10_P' C1067-1 # MP5 Rec D10 Out Dir NET 'HSOUT_R3_D10_N' C1068-1 # MP5 Rec D10 Out Cmp NET 'MP5_F10_QUAD_117_REC_2_DIR' C1068-2 # MP5 Fiber 10 Topological Direct Input NET 'MP5_F10_QUAD_117_REC_2_CMP' C1067-2 # MP5 Fiber 10 Topological Complement Input NET 'HSOUT_R3_D11_P' C1069-1 # MP5 Rec D11 Out Dir NET 'HSOUT_R3_D11_N' C1070-1 # MP5 Rec D11 Out Cmp NET 'MP5_F11_QUAD_117_REC_1_DIR' C1070-2 # MP5 Fiber 11 Topological Direct Input NET 'MP5_F11_QUAD_117_REC_1_CMP' C1069-2 # MP5 Fiber 11 Topological Complement Input # # CMX-0 Nets File # # MiniPod High-Speed Optical Control and Monitor Nets # -=======------------------------------------------------ # # # Original Rev. 4-Dec-2012 # Most Recent Rev. 25-Mar-2013 # # # # This file holds the Board Control FPGA end of all of the # nets for the Control and Monitor of both the 5 MiniPod # High-Speed Optical Components and the 4 Low-Speed SFP # optical comoonents. # # High-Speed MiniPod Optical Components: # # Recall that there are 2 MiniPod Transmitters, MP1 and MP2, # that are associated with the Base Function FPGA. # # Recall that there are 3 MiniPod Receivers, MP3, MP4, and MP5 # that are associated with the Topological Processor FPGA. # # All of the MiniPod components receive a Two Wire Serial # Control and Monitoring Bus. There are separate TWS Buses # for the Base Function MiniPod Transmitters and for the # Topological Processor MiniPod Receivers. These 2 TWS # Buses run to the Board Support FPGA. # # In addition there is a separate Interrupt_B signal from # each of the 5 MiniPod components that runs to the Board # Support FPGA. From the Board Support FPGA there is a # Reset_B signal that runs to the 2 MiniPod Transmitters # and a separate Reset_B signal that runs to the 3 MiniPod # Receivers. # # # Low-Speed SFP Optical Components # # # # The components that are involved with these nets include: # # # # # # Low-Spped Optical Component Control and Monitoring Nets # ---------------------------------------------------------- # # SFP1 Control and Monitoring Signals NET 'SFP1_TX_FAULT' U351-G6 # SFP1 Transmitter Fault 3.3V Input-Only NET 'SFP1_TX_DISABLE' U351-L1 # SFP1 Transmitter Disable 3.3V Output NET 'SFP1_MOD_SER_DATA' U351-M5 # SFP1 2 Wire Serial Data 3.3V I/O NET 'SFP1_MOD_SER_CLK' U351-M4 # SFP1 2 Wire Serial Clock 3.3V Output NET 'SFP1_MOD_PRESENT' U351-H7 # SFP1 Module Present->Low 3.3V Input-Only # SFP2 Control and Monitoring Signals NET 'SFP2_TX_FAULT' U351-J7 # SFP2 Transmitter Fault 3.3V Input-Only NET 'SFP2_TX_DISABLE' U351-M3 # SFP2 Transmitter Disable 3.3V Output NET 'SFP2_MOD_SER_DATA' U351-M2 # SFP2 2 Wire Serial Data 3.3V I/O NET 'SFP2_MOD_SER_CLK' U351-M1 # SFP2 2 Wire Serial Clock 3.3V Output NET 'SFP2_MOD_PRESENT' U351-K7 # SFP2 Module Present->Low 3.3V Input-Only # SFP3 Control and Monitoring Signals NET 'SFP3_TX_FAULT' U351-K6 # SFP3 Transmitter Fault 3.3V Input-Only NET 'SFP3_TX_DISABLE' U351-N2 # SFP3 Transmitter Disable 3.3V Output NET 'SFP3_MOD_SER_DATA' U351-N1 # SFP3 2 Wire Serial Data 3.3V I/O NET 'SFP3_MOD_SER_CLK' U351-P4 # SFP3 2 Wire Serial Clock 3.3V Output NET 'SFP3_MOD_PRESENT' U351-K5 # SFP3 Module Present->Low 3.3V Input-Only # SFP4 Control and Monitoring Signals NET 'SFP4_TX_FAULT' U351-L7 # SFP4 Transmitter Fault 3.3V Input-Only NET 'SFP4_TX_DISABLE' U351-P3 # SFP4 Transmitter Disable 3.3V Output NET 'SFP4_MOD_SER_DATA' U351-P1 # SFP4 2 Wire Serial Data 3.3V I/O NET 'SFP4_MOD_SER_CLK' U351-R5 # SFP4 2 Wire Serial Clock 3.3V Output NET 'SFP4_MOD_PRESENT' U351-L6 # SFP4 Module Present->Low 3.3V Input-Only # # High-Spped Optical Component Control and Monitoring Nets # ----------------------------------------------------------- # # # MiniPods 1 and 2 Transmitters for the Base Function FPGA # ------------------ # MiniPods 1,2 TWS Serial Data NET 'MP12_SDA' U351-R4 # SDA connection to the BSPT 3.3V I/O NET 'MP12_SDA' R371-1 # Pull-Up for default Serial Data state NET 'BULK_3V3' R371-2 # Pull-Up to 3.3V connection # MiniPods 1,2 TWS Serail Clock NET 'MP12_SCL' U351-T1 # SCL connection to the BSPT 3.3V Output NET 'MP12_SCL' R372-1 # Pull-Up for default Serial Clock state NET 'BULK_3V3' R372-2 # Pull-Up to 3.3V connection # # MiniPods 1,2 Reset_B Signal NET 'MP12_RESET_B' U351-T2 # MiniPods 1,2 Reset_B 3.3V Output NET 'MP12_RESET_B' R373-1 # Pull-Up for default RESET_B state NET 'BULK_3V3' R373-2 # Pull-Up to 3.3V connection # # MiniPod #1 Connections for Interrupt_B NET 'MP1_INTRPT_B' U351-P7 # MP1 Interrupt_B 3.3V In-Only pin # # MiniPod #2 Connections for Interrupt_B NET 'MP2_INTRPT_B' U351-P6 # MP2 Interrupt_B 3.3V In-Only pin # # MiniPods 3,4,5 Receivers for the Topological Processor FPGA # ---------------- # MiniPods 3,4,5 TWS Serial Data NET 'MP345_SDA' U351-R1 # SDA connection to the BSPT 3.3V I/O NET 'MP345_SDA' R374-1 # Pull-Up for default Serial Data state NET 'BULK_3V3' R374-2 # Pull-Up to 3.3V connection # MiniPods 3,4,5 TWS Serail Clock NET 'MP345_SCL' U351-R2 # SCL connection to the BSPT 3.3V Output NET 'MP345_SCL' R375-1 # Pull-Up for default Serial Clock state NET 'BULK_3V3' R375-2 # Pull-Up to 3.3V connection # # MiniPods 3,4,5 Reset_B Signal NET 'MP345_RESET_B' U351-R3 # MiniPods 3,4,5 Reset_B 3.3V Output NET 'MP345_RESET_B' R376-1 # Pull-Up for default RESET_B state NET 'BULK_3V3' R376-2 # Pull-Up to 3.3V connection # # MiniPod #3 Connections for Interrupt_B NET 'MP3_INTRPT_B' U351-P5 # MP3 Interrupt_B 3.3V In-Only pin # # MiniPod #4 Connections for Interrupt_B NET 'MP4_INTRPT_B' U351-N7 # MP4 Interrupt_B 3.3V In-Only pin # # MiniPod #5 Connections for Interrupt_B NET 'MP5_INTRPT_B' U351-N6 # MP5 Interrupt_B 3.3V In-Only pin # # CMX-0 Nets File # # # GTX_AVTT DC/DC Power Converter # --========------------------------- # # # Original Rev. 20-Dec-2012 # Most Recent Rev. 16-June-2013 # # # # This file holds the nets in the GTX_AVTT # DC/DC Power Converter. # # # From the left this is the 5th converter. # # Components with Reference Designators in the range # # 1701:1749 are included in the GTX_AVTT Converter. # # # # Define the Connections within the GTX_AVTT Power Converter # ------------------------------------========------------------ # # # Input Power to the Converter: NET 'BULK_5V0' R1701-3 # Power to the Current Sense Resistor NET 'GTX_AVTT_CS_TO_L' R1701-2 # Power from the Current Sense NET 'GTX_AVTT_CS_TO_L' L1701-1 # Resistor to the Filter Inductor NET 'GTX_AVTT_INPUT' L1701-2 # Power feed to the Converter NET 'GTX_AVTT_INPUT' C1701-1 # Aluminum Input Cap NET 'GTX_AVTT_INPUT' C1703-1 C1704-1 # Taltalum Input Caps NET 'GTX_AVTT_INPUT' C1709-1 C1710-1 # Ceramic Input Caps NET 'GTX_AVTT_INPUT' C1711-1 C1712-1 # Ceramic Input Caps NET 'GTX_AVTT_INPUT' DCDC5-2 # Power Input to the Converter NET 'GROUND' C1701-2 # Aluminum Cap Ground NET 'GROUND' C1703-2 C1704-2 # Taltalum Cap Grounds NET 'GROUND' C1709-2 C1710-2 # Ceramic Cap Grounds NET 'GROUND' C1711-2 C1712-2 # Ceramic Cap Grounds # # Power Output from the Converter: NET 'GTX_AVTT' DCDC5-5 # Output Power from the Converter NET 'GTX_AVTT' C1717-1 C1718-1 # Ceramic Output Caps NET 'GTX_AVTT' C1719-1 C1720-1 # Ceramic Output Caps NET 'GTX_AVTT' C1725-1 C1726-1 # Taltalum Output Caps NET 'GTX_AVTT' C1727-1 C1728-1 # Taltalum Output Caps NET 'GTX_AVTT' C1729-1 C1730-1 # Taltalum Output Caps NET 'GROUND' C1717-2 C1718-2 # Ceramic Cap Grounds NET 'GROUND' C1719-2 C1720-2 # Ceramic Cap Grounds NET 'GROUND' C1725-2 C1726-2 # Taltalum Cap Grounds NET 'GROUND' C1727-2 C1728-2 # Taltalum Cap Grounds NET 'GROUND' C1729-2 C1730-2 # Taltalum Cap Grounds # # Power Output Filter Chokes NET 'GTX_AVTT' L1702-1 L1703-1 # Power into Output Chokes NET 'TP_GTX_AVTT' L1702-2 # TP Power from Output Choke NET 'BF_GTX_AVTT' L1703-2 # BF Power from Output Choke # # DC/DC Converter GROUND Pins NET 'GROUND' DCDC5-3 DCDC5-4 # Converter Grounds # # DC/DC Converter Tracking and Feedback Sense Pins NET 'DCDC_CONV_TRACK' DCDC5-10 # TRACK Pin of GTX_AVTT Converter NET 'GTX_AVTT' AKA1701-1 # Positive SENSE Remote Connection NET 'GTX_AVTT_SEN_POS' AKA1701-2 DCDC5-6 # Positive SENSE input pin NET 'GROUND' AKA1702-1 # Negative SENSE Remote Connection NET 'GTX_AVTT_SEN_NEG' AKA1702-2 DCDC5-7 # Negative SENSE input pin # # DC/DC Converter Output Voltage Rset Resistor # with capacitor across the variable part of the Vout Rset Resistor NET 'GTX_AVTT_SEN_NEG' R1705-1 R1705-2 # Want Trim Pot CW Truning to: NET 'GTX_AVTT_VAR_FIX' R1705-3 # Reduce the Resistance and NET 'GTX_AVTT_VAR_FIX' R1704-1 # Increase the Output Voltage NET 'GTX_AVTT_VO_ADJ' R1704-2 DCDC5-8 # Converter Rset Vout Adj pin NET 'GTX_AVTT_SEN_NEG' C1732-1 # Capacitor across the NET 'GTX_AVTT_VAR_FIX' C1732-2 # Vout Trim Pot Resistor # # DC/DC Converter Transient Response Control Pin NET 'GTX_AVTT_SEN_POS' R1706-2 # Transient Response Resistor NET 'GTX_AVTT_TRC_PIN' R1706-1 DCDC5-9 # Transient Response Control pin # # DC/DC Converter NO Connect Pins NET 'No_Conn_DCDC5_10_INH' DCDC5-11 # INH / UVLO Pin #10 Not Used NET 'No_Conn_DCDC5_11_SYNC' DCDC5-1 # SYNC Pin #11 Not Used # # Current Sense High-Side Amplifier NET 'GTX_AVTT_CS_SRC' R1701-4 R1702-2 # Current Sense Source Input Resistor NET 'GTX_AVTT_CS_AMP_P' U1701-8 R1702-1 # Current Sense Amp Positive Input NET 'GTX_AVTT_CS_LOAD' R1701-1 R1703-2 # Current Sense Load Input Resistor NET 'GTX_AVTT_CS_AMP_N' U1701-1 R1703-1 # Current Sense Amp Negative Input NET 'GTX_AVTT_CS_AMP_OUT' U1701-5 # Current Sense Amp Output NET 'BULK_3V3' U1701-2 C1731-2 # Current Sense Amp V+ Power NET 'GROUND' U1701-4 C1731-1 # Current Sense Amp GROUND NET 'No_Conn_GTX_AVTT_CS_AMP_P3' U1701-3 # Current Sense Amp No Conn Pin #3 NET 'No_Conn_GTX_AVTT_CS_AMP_P6' U1701-6 # Current Sense Amp No Conn Pin #6 NET 'No_Conn_GTX_AVTT_CS_AMP_P7' U1701-7 # Current Sense Amp No Conn Pin #7 # # CMX-0 Nets File # # # TP_CORE DC/DC Power Converter # --=======------------------------- # # # Original Rev. 20-Dec-2012 # Most Recent Rev. 18-June-2013 # # # # This file holds the nets in the TP_CORE # DC/DC Power Converter. # # # From the left this is the 3rd converter. # # Components with Reference Designators in the range # # 1601:1649 are included in the TP_CORE Converter. # # # # Define the Connections within the TP_CORE Power Converter # ------------------------------------=======------------------- # # # Input Power to the Converter: NET 'BULK_5V0' R1601-3 # Power to the Current Sense Resistor NET 'TP_CORE_CS_TO_L' R1601-2 # Power from the Current Sense NET 'TP_CORE_CS_TO_L' L1601-1 # Resistor to the Filter Inductor NET 'TP_CORE_INPUT' L1601-2 # Power feed to the Converter NET 'TP_CORE_INPUT' C1601-1 C1602-1 # Aluminum Input Caps NET 'TP_CORE_INPUT' C1603-1 C1604-1 # Taltalum Input Caps NET 'TP_CORE_INPUT' C1605-1 C1606-1 # Taltalum Input Caps NET 'TP_CORE_INPUT' C1607-1 C1608-1 # Taltalum Input Caps NET 'TP_CORE_INPUT' C1609-1 C1610-2 # Ceramic Input Caps NET 'TP_CORE_INPUT' C1611-1 C1612-2 # Ceramic Input Caps NET 'TP_CORE_INPUT' C1613-1 C1614-2 # Ceramic Input Caps NET 'TP_CORE_INPUT' C1615-1 C1616-2 # Ceramic Input Caps NET 'TP_CORE_INPUT' DCDC3-2 DCDC3-6 # Power Input to the Converter NET 'GROUND' C1601-2 C1602-2 # Aluminum Cap Grounds NET 'GROUND' C1603-2 C1604-2 # Taltalum Cap Grounds NET 'GROUND' C1605-2 C1606-2 # Taltalum Cap Grounds NET 'GROUND' C1607-2 C1608-2 # Taltalum Cap Grounds NET 'GROUND' C1609-2 C1610-1 # Ceramic Cap Grounds NET 'GROUND' C1611-2 C1612-1 # Ceramic Cap Grounds NET 'GROUND' C1613-2 C1614-1 # Ceramic Cap Grounds NET 'GROUND' C1615-2 C1616-1 # Ceramic Cap Grounds # # Power Output from the Converter: NET 'TP_CORE' DCDC3-5 DCDC3-9 # Output Power from the Converter NET 'TP_CORE' C1617-1 C1618-2 # Ceramic Output Caps NET 'TP_CORE' C1619-1 C1620-2 # Ceramic Output Caps NET 'TP_CORE' C1621-1 C1622-2 # Ceramic Output Caps NET 'TP_CORE' C1623-1 C1624-2 # Ceramic Output Caps NET 'TP_CORE' C1625-1 C1626-1 # Taltalum Output Caps NET 'TP_CORE' C1627-1 C1628-1 # Taltalum Output Caps NET 'TP_CORE' C1629-1 C1630-1 # Taltalum Output Caps NET 'GROUND' C1617-2 C1618-1 # Ceramic Cap Grounds NET 'GROUND' C1619-2 C1620-1 # Ceramic Cap Grounds NET 'GROUND' C1621-2 C1622-1 # Ceramic Cap Grounds NET 'GROUND' C1623-2 C1624-1 # Ceramic Cap Grounds NET 'GROUND' C1625-2 C1626-2 # Taltalum Cap Grounds NET 'GROUND' C1627-2 C1628-2 # Taltalum Cap Grounds NET 'GROUND' C1629-2 C1630-2 # Taltalum Cap Grounds # # DC/DC Converter GROUND Pins NET 'GROUND' DCDC3-3 DCDC3-4 # Converter Grounds NET 'GROUND' DCDC3-7 DCDC3-8 # Converter Grounds # # DC/DC Converter Tracking and Feedback Sense Pins # # In this converter there is jumper JMP79 that isolates its # Track pin from the Track bus that spans all 7 converters. NET 'TP_CORE_TRACK' DCDC3-14 JMP79-1 # Converter Track pin to Jumper NET 'DCDC_CONV_TRACK' JMP79-2 # Jumper JMP79 to the Track Bus NET 'TP_CORE' AKA1601-1 # Positive SENSE Remote Connection NET 'TP_CORE_SEN_POS' AKA1601-2 DCDC3-10 # Positive SENSE input pin NET 'GROUND' AKA1602-1 # Negative SENSE Remote Connection NET 'TP_CORE_SEN_NEG' AKA1602-2 DCDC3-11 # Negative SENSE input pin # # DC/DC Converter Output Voltage Rset Resistor # with capacitor across the variable part of the Vout Rset Resistor # # NOTE: Ground Ref. NET 'GROUND' R1605-1 R1605-2 # Want Trim Pot CW Truning to: NET 'TP_CORE_VAR_FIX' R1605-3 # Reduce the Resistance and NET 'TP_CORE_VAR_FIX' R1604-1 # Increase the Output Voltage NET 'TP_CORE_VO_ADJ' R1604-2 DCDC3-12 # Converter Rset Vout Adj pin NET 'GROUND' C1632-1 # Capacitor across the NET 'TP_CORE_VAR_FIX' C1632-2 # Vout Trim Pot Resistor # # DC/DC Converter Transient Response Control Pin NET 'TP_CORE_SEN_POS' R1606-2 # Transient Response Resistor NET 'TP_CORE_TRC_PIN' R1606-1 DCDC3-13 # Transient Response Control pin # # DC/DC Converter INH/UVLO pin # Jumper JMP78 can pull the Inhibit pin to Ground. NET 'TP_CORE_INH' DCDC3-1 JMP78-2 # INH/UVLO Pin #1 to jumper NET 'GROUND' JMP78-1 # JMP78 runs to Ground # NOTE: The 30 Amp TP_Core DC/DC Converter does not have a SYNC input. # # Current Sense High-Side Amplifier NET 'TP_CORE_CS_SRC' R1601-4 R1602-2 # Current Sense Source Input Resistor NET 'TP_CORE_CS_AMP_P' U1601-8 R1602-1 # Current Sense Amp Positive Input NET 'TP_CORE_CS_LOAD' R1601-1 R1603-2 # Current Sense Load Input Resistor NET 'TP_CORE_CS_AMP_N' U1601-1 R1603-1 # Current Sense Amp Negative Input NET 'TP_CORE_CS_AMP_OUT' U1601-5 # Current Sense Amp Output NET 'BULK_3V3' U1601-2 C1631-2 # Current Sense Amp V+ Power NET 'GROUND' U1601-4 C1631-1 # Current Sense Amp GROUND NET 'No_Conn_TP_CORE_CS_AMP_P3' U1601-3 # Current Sense Amp No Conn Pin #3 NET 'No_Conn_TP_CORE_CS_AMP_P6' U1601-6 # Current Sense Amp No Conn Pin #6 NET 'No_Conn_TP_CORE_CS_AMP_P7' U1601-7 # Current Sense Amp No Conn Pin #7 # # CMX-0 Nets File # # # GTX_AVCC DC/DC Power Converter # --========------------------------- # # # Original Rev. 20-Dec-2012 # Most Recent Rev. 16-June-2013 # # # # This file holds the nets in the GTX_AVCC # DC/DC Power Converter. # # # From the left this is the 4th converter. # # Components with Reference Designators in the range # # 1651:1699 are included in the GTX_AVCC Converter. # # # # Define the Connections within the GTX_AVCC Power Converter # ------------------------------------========------------------ # # # Input Power to the Converter: NET 'BULK_5V0' R1651-3 # Power to the Current Sense Resistor NET 'GTX_AVCC_CS_TO_L' R1651-2 # Power from the Current Sense NET 'GTX_AVCC_CS_TO_L' L1651-1 # Resistor to the Filter Inductor NET 'GTX_AVCC_INPUT' L1651-2 # Power feed to the Converter NET 'GTX_AVCC_INPUT' C1651-1 # Aluminum Input Cap NET 'GTX_AVCC_INPUT' C1653-1 C1654-1 # Taltalum Input Caps NET 'GTX_AVCC_INPUT' C1659-1 C1660-1 # Ceramic Input Caps NET 'GTX_AVCC_INPUT' C1661-1 C1662-1 # Ceramic Input Caps NET 'GTX_AVCC_INPUT' DCDC4-2 # Power Input to the Converter NET 'GROUND' C1651-2 # Aluminum Cap Ground NET 'GROUND' C1653-2 C1654-2 # Taltalum Cap Grounds NET 'GROUND' C1659-2 C1660-2 # Ceramic Cap Grounds NET 'GROUND' C1661-2 C1662-2 # Ceramic Cap Grounds # # Power Output from the Converter: NET 'GTX_AVCC' DCDC4-5 # Output Power from the Converter NET 'GTX_AVCC' C1667-1 C1668-1 # Ceramic Output Caps NET 'GTX_AVCC' C1669-1 C1670-1 # Ceramic Output Caps NET 'GTX_AVCC' C1675-1 C1676-1 # Taltalum Output Caps NET 'GTX_AVCC' C1677-1 C1678-1 # Taltalum Output Caps NET 'GTX_AVCC' C1679-1 C1680-1 # Taltalum Output Caps NET 'GROUND' C1667-2 C1668-2 # Ceramic Cap Grounds NET 'GROUND' C1669-2 C1670-2 # Ceramic Cap Grounds NET 'GROUND' C1675-2 C1676-2 # Taltalum Cap Grounds NET 'GROUND' C1677-2 C1678-2 # Taltalum Cap Grounds NET 'GROUND' C1679-2 C1680-2 # Taltalum Cap Grounds # # Power Output Filter Chokes NET 'GTX_AVCC' L1652-1 L1653-1 # Power into Output Chokes NET 'TP_GTX_AVCC' L1652-2 # TP Power from Output Choke NET 'BF_GTX_AVCC' L1653-2 # BF Power from Output Choke # # DC/DC Converter GROUND Pins NET 'GROUND' DCDC4-3 DCDC4-4 # Converter Grounds # # DC/DC Converter Tracking and Feedback Sense Pins NET 'DCDC_CONV_TRACK' DCDC4-10 # TRACK Pin of GTX_AVCC Converter NET 'GTX_AVCC' AKA1651-1 # Positive SENSE Remote Connection NET 'GTX_AVCC_SEN_POS' AKA1651-2 DCDC4-6 # Positive SENSE input pin NET 'GROUND' AKA1652-1 # Negative SENSE Remote Connection NET 'GTX_AVCC_SEN_NEG' AKA1652-2 DCDC4-7 # Negative SENSE input pin # # DC/DC Converter Output Voltage Rset Resistor # with capacitor across the variable part of the Vout Rset Resistor NET 'GTX_AVCC_SEN_NEG' R1655-1 R1655-2 # Want Trim Pot CW Truning to: NET 'GTX_AVCC_VAR_FIX' R1655-3 # Reduce the Resistance and NET 'GTX_AVCC_VAR_FIX' R1654-1 # Increase the Output Voltage NET 'GTX_AVCC_VO_ADJ' R1654-2 DCDC4-8 # Converter Rset Vout Adj pin NET 'GTX_AVCC_SEN_NEG' C1682-1 # Capacitor across NET 'GTX_AVCC_VAR_FIX' C1682-2 # Vout Trim Pot # # DC/DC Converter Transient Response Control Pin NET 'GTX_AVCC_SEN_POS' R1656-2 # Transient Response Resistor NET 'GTX_AVCC_TRC_PIN' R1656-1 DCDC4-9 # Transient Response Control pin # # DC/DC Converter NO Connect Pins NET 'No_Conn_DCDC4_10_INH' DCDC4-11 # INH / UVLO Pin #10 Not Used NET 'No_Conn_DCDC4_11_SYNC' DCDC4-1 # SYNC Pin #11 Not Used # # Current Sense High-Side Amplifier NET 'GTX_AVCC_CS_SRC' R1651-4 R1652-2 # Current Sense Source Input Resistor NET 'GTX_AVCC_CS_AMP_P' U1651-8 R1652-1 # Current Sense Amp Positive Input NET 'GTX_AVCC_CS_LOAD' R1651-1 R1653-2 # Current Sense Load Input Resistor NET 'GTX_AVCC_CS_AMP_N' U1651-1 R1653-1 # Current Sense Amp Negative Input NET 'GTX_AVCC_CS_AMP_OUT' U1651-5 # Current Sense Amp Output NET 'BULK_3V3' U1651-2 C1681-2 # Current Sense Amp V+ Power NET 'GROUND' U1651-4 C1681-1 # Current Sense Amp GROUND NET 'No_Conn_GTX_AVCC_CS_AMP_P3' U1651-3 # Current Sense Amp No Conn Pin #3 NET 'No_Conn_GTX_AVCC_CS_AMP_P6' U1651-6 # Current Sense Amp No Conn Pin #6 NET 'No_Conn_GTX_AVCC_CS_AMP_P7' U1651-7 # Current Sense Amp No Conn Pin #7 # # CMX-0 Nets File # # # BF_CORE DC/DC Power Converter # --=======------------------------- # # # Original Rev. 20-Dec-2012 # Most Recent Rev. 20-Jan-2013 # # # # This file holds the nets in the BF_CORE # DC/DC Power Converter. # # # From the left this is the 6th converter. # # Components with Reference Designators in the range # # 1751:1799 are included in the BF_CORE Converter. # # # # Define the Connections within the BF_CORE Power Converter # ------------------------------------=======------------------- # # # Input Power to the Converter: NET 'BULK_5V0' R1751-3 # Power to the Current Sense Resistor NET 'BF_CORE_CS_TO_L' R1751-2 # Power from the Current Sense NET 'BF_CORE_CS_TO_L' L1751-1 # Resistor to the Filter Inductor NET 'BF_CORE_INPUT' L1751-2 # Power feed to the Converter NET 'BF_CORE_INPUT' C1751-1 C1752-1 # Aluminum Input Caps NET 'BF_CORE_INPUT' C1753-1 C1754-1 # Taltalum Input Caps NET 'BF_CORE_INPUT' C1755-1 C1756-1 # Taltalum Input Caps NET 'BF_CORE_INPUT' C1757-1 C1758-1 # Taltalum Input Caps NET 'BF_CORE_INPUT' C1759-1 C1760-2 # Ceramic Input Caps NET 'BF_CORE_INPUT' C1761-1 C1762-2 # Ceramic Input Caps NET 'BF_CORE_INPUT' C1763-1 C1764-2 # Ceramic Input Caps NET 'BF_CORE_INPUT' C1765-1 C1766-2 # Ceramic Input Caps NET 'BF_CORE_INPUT' DCDC6-2 DCDC6-6 # Power Input to the Converter NET 'GROUND' C1751-2 C1752-2 # Aluminum Cap Grounds NET 'GROUND' C1753-2 C1754-2 # Taltalum Cap Grounds NET 'GROUND' C1755-2 C1756-2 # Taltalum Cap Grounds NET 'GROUND' C1757-2 C1758-2 # Taltalum Cap Grounds NET 'GROUND' C1759-2 C1760-1 # Ceramic Cap Grounds NET 'GROUND' C1761-2 C1762-1 # Ceramic Cap Grounds NET 'GROUND' C1763-2 C1764-1 # Ceramic Cap Grounds NET 'GROUND' C1765-2 C1766-1 # Ceramic Cap Grounds # # Power Output from the Converter: NET 'BF_CORE' DCDC6-5 DCDC6-9 # Output Power from the Converter NET 'BF_CORE' C1767-1 C1768-2 # Ceramic Output Caps NET 'BF_CORE' C1769-1 C1770-2 # Ceramic Output Caps NET 'BF_CORE' C1771-1 C1772-2 # Ceramic Output Caps NET 'BF_CORE' C1773-1 C1774-2 # Ceramic Output Caps NET 'BF_CORE' C1775-1 C1776-1 # Taltalum Output Caps NET 'BF_CORE' C1777-1 C1778-1 # Taltalum Output Caps NET 'BF_CORE' C1779-1 C1780-1 # Taltalum Output Caps NET 'GROUND' C1767-2 C1768-1 # Ceramic Cap Grounds NET 'GROUND' C1769-2 C1770-1 # Ceramic Cap Grounds NET 'GROUND' C1771-2 C1772-1 # Ceramic Cap Grounds NET 'GROUND' C1773-2 C1774-1 # Ceramic Cap Grounds NET 'GROUND' C1775-2 C1776-2 # Taltalum Cap Grounds NET 'GROUND' C1777-2 C1778-2 # Taltalum Cap Grounds NET 'GROUND' C1779-2 C1780-2 # Taltalum Cap Grounds # # DC/DC Converter GROUND Pins NET 'GROUND' DCDC6-3 DCDC6-4 # Converter Grounds NET 'GROUND' DCDC6-7 DCDC6-8 # Converter Grounds # # DC/DC Converter Tracking and Feedback Sense Pins NET 'DCDC_CONV_TRACK' DCDC6-14 # TRACK Pin of BF_CORE Converter NET 'BF_CORE' AKA1751-1 # Positive SENSE Remote Connection NET 'BF_CORE_SEN_POS' AKA1751-2 DCDC6-10 # Positive SENSE input pin NET 'GROUND' AKA1752-1 # Negative SENSE Remote Connection NET 'BF_CORE_SEN_NEG' AKA1752-2 DCDC6-11 # Negative SENSE input pin # # DC/DC Converter Output Voltage Rset Resistor # with capacitor across the variable part of the Vout Rset Resistor # # NOTE: Ground Ref. NET 'GROUND' R1755-1 R1755-2 # Want Trim Pot CW Truning to: NET 'BF_CORE_VAR_FIX' R1755-3 # Reduce the Resistance and NET 'BF_CORE_VAR_FIX' R1754-1 # Increase the Output Voltage NET 'BF_CORE_VO_ADJ' R1754-2 DCDC6-12 # Converter Rset Vout Adj pin NET 'GROUND' C1782-1 # Capacitor across the NET 'BF_CORE_VAR_FIX' C1782-2 # Vout Trim Pot Resistor # # DC/DC Converter Transient Response Control Pin NET 'BF_CORE_SEN_POS' R1756-2 # Transient Response Resistor NET 'BF_CORE_TRC_PIN' R1756-1 DCDC6-13 # Transient Response Control pin # # DC/DC Converter NO Connect Pins NOTE: No SYNC Input NET 'No_Conn_DCDC6_10_INH' DCDC6-1 # INH / UVLO Pin #1 Not Used # # Current Sense High-Side Amplifier NET 'BF_CORE_CS_SRC' R1751-4 R1752-2 # Current Sense Source Input Resistor NET 'BF_CORE_CS_AMP_P' U1751-8 R1752-1 # Current Sense Amp Positive Input NET 'BF_CORE_CS_LOAD' R1751-1 R1753-2 # Current Sense Load Input Resistor NET 'BF_CORE_CS_AMP_N' U1751-1 R1753-1 # Current Sense Amp Negative Input NET 'BF_CORE_CS_AMP_OUT' U1751-5 # Current Sense Amp Output NET 'BULK_3V3' U1751-2 C1781-2 # Current Sense Amp V+ Power NET 'GROUND' U1751-4 C1781-1 # Current Sense Amp GROUND NET 'No_Conn_BF_CORE_CS_AMP_P3' U1751-3 # Current Sense Amp No Conn Pin #3 NET 'No_Conn_BF_CORE_CS_AMP_P6' U1751-6 # Current Sense Amp No Conn Pin #6 NET 'No_Conn_BF_CORE_CS_AMP_P7' U1751-7 # Current Sense Amp No Conn Pin #7 # # CMX-0 Nets File # # # BSPT_CORE DC/DC Power Converter # --=========------------------------- # # # Original Rev. 20-Dec-2012 # Most Recent Rev. 16-June-2013 # # # # This file holds the nets in the BSPT_CORE # DC/DC Power Converter. # # # From the left this is the 5th converter. # # Components with Reference Designators in the range # # 1801:1849 are included in the BSPT_CORE Converter. # # # # Define the Connections within the BSPT_CORE Power Converter # ------------------------------------=========------------------ # # # Input Power to the Converter: NET 'BULK_5V0' R1801-3 # Power to the Current Sense Resistor NET 'BSPT_CORE_CS_TO_L' R1801-2 # Power from the Current Sense NET 'BSPT_CORE_CS_TO_L' L1801-1 # Resistor to the Filter Inductor NET 'BSPT_CORE_INPUT' L1801-2 # Power feed to the Converter NET 'BSPT_CORE_INPUT' C1801-1 # Aluminum Input Cap NET 'BSPT_CORE_INPUT' C1803-1 C1804-1 # Taltalum Input Caps NET 'BSPT_CORE_INPUT' C1809-1 C1810-1 # Ceramic Input Caps NET 'BSPT_CORE_INPUT' C1811-1 C1812-1 # Ceramic Input Caps NET 'BSPT_CORE_INPUT' DCDC7-2 # Power Input to the Converter NET 'GROUND' C1801-2 # Aluminum Cap Ground NET 'GROUND' C1803-2 C1804-2 # Taltalum Cap Grounds NET 'GROUND' C1809-2 C1810-2 # Ceramic Cap Grounds NET 'GROUND' C1811-2 C1812-2 # Ceramic Cap Grounds # # Power Output from the Converter: NET 'BSPT_CORE' DCDC7-5 # Output Power from the Converter NET 'BSPT_CORE' C1817-1 C1818-1 # Ceramic Output Caps NET 'BSPT_CORE' C1819-1 C1820-1 # Ceramic Output Caps NET 'BSPT_CORE' C1825-1 C1826-1 # Taltalum Output Caps NET 'BSPT_CORE' C1827-1 C1828-1 # Taltalum Output Caps NET 'BSPT_CORE' C1829-1 C1830-1 # Taltalum Output Caps NET 'GROUND' C1817-2 C1818-2 # Ceramic Cap Grounds NET 'GROUND' C1819-2 C1820-2 # Ceramic Cap Grounds NET 'GROUND' C1825-2 C1826-2 # Taltalum Cap Grounds NET 'GROUND' C1827-2 C1828-2 # Taltalum Cap Grounds NET 'GROUND' C1829-2 C1830-2 # Taltalum Cap Grounds # # DC/DC Converter GROUND Pins NET 'GROUND' DCDC7-3 DCDC7-4 # Converter Grounds # # DC/DC Converter Tracking and Feedback Sense Pins NET 'DCDC_CONV_TRACK' DCDC7-10 # TRACK Pin of BSPT_CORE Converter NET 'BSPT_CORE' AKA1801-1 # Positive SENSE Remote Connection NET 'BSPT_CORE_SEN_POS' AKA1801-2 DCDC7-6 # Positive SENSE input pin NET 'GROUND' AKA1802-1 # Negative SENSE Remote Connection NET 'BSPT_CORE_SEN_NEG' AKA1802-2 DCDC7-7 # Negative SENSE input pin # # DC/DC Converter Output Voltage Rset Resistor # with capacitor across the variable part of the Vout Rset Resistor NET 'BSPT_CORE_SEN_NEG' R1805-1 R1805-2 # Want Trim Pot CW Truning to: NET 'BSPT_CORE_VAR_FIX' R1805-3 # Reduce the Resistance and NET 'BSPT_CORE_VAR_FIX' R1804-1 # Increase the Output Voltage NET 'BSPT_CORE_VO_ADJ' R1804-2 DCDC7-8 # Converter Rset Vout Adj pin NET 'BSPT_CORE_SEN_NEG' C1832-1 # Capacitor across the NET 'BSPT_CORE_VAR_FIX' C1832-2 # Vout Trim Pot Resistor # # DC/DC Converter Transient Response Control Pin NET 'BSPT_CORE_SEN_POS' R1806-2 # Transient Response Resistor NET 'BSPT_CORE_TRC_PIN' R1806-1 DCDC7-9 # Transient Response Control pin # # DC/DC Converter NO Connect Pins NET 'No_Conn_DCDC7_10_INH' DCDC7-11 # INH / UVLO Pin #10 Not Used NET 'No_Conn_DCDC7_11_SYNC' DCDC7-1 # SYNC Pin #11 Not Used # # Current Sense High-Side Amplifier NET 'BSPT_CORE_CS_SRC' R1801-4 R1802-2 # Current Sense Source Input Resistor NET 'BSPT_CORE_CS_AMP_P' U1801-8 R1802-1 # Current Sense Amp Positive Input NET 'BSPT_CORE_CS_LOAD' R1801-1 R1803-2 # Current Sense Load Input Resistor NET 'BSPT_CORE_CS_AMP_N' U1801-1 R1803-1 # Current Sense Amp Negative Input NET 'BSPT_CORE_CS_AMP_OUT' U1801-5 # Current Sense Amp Output NET 'BULK_3V3' U1801-2 C1831-2 # Current Sense Amp V+ Power NET 'GROUND' U1801-4 C1831-1 # Current Sense Amp GROUND NET 'No_Conn_BSPT_CORE_CS_AMP_P3' U1801-3 # Current Sense Amp No Conn Pin #3 NET 'No_Conn_BSPT_CORE_CS_AMP_P6' U1801-6 # Current Sense Amp No Conn Pin #6 NET 'No_Conn_BSPT_CORE_CS_AMP_P7' U1801-7 # Current Sense Amp No Conn Pin #7 # # CMX-0 Nets File # # # Power Reference Supplies Nets # ---------=========----------------- # # # # Original Rev. 30-Dec-2012 # Most Recent Rev. 16-Jan-2013 # # # # This file contains the nets for the 3 analog Reference # supplies on the CMX card. --------- # # The Reference type supplies on the CMX are: # # - The 1.250 Volt reference for the Base Function FPGA's # System Monitor # # - The 1.250 Volt reference for the Topological FPGA's # System Monitor # # - The 0.75 to 1.75 Volt Adjustable Reference for the # Base Function FPGA Select I/O Banks that receive the # 400 backplane processor input signals. # # # Reference Designators for these Reference Supplies # are in the range 1901:1949. # # # Base Function FPGA System Monitor Reference 1.250 Volt NET 'BULK_2V5' C1901-2 # Base Function System Monitor NET 'GROUND' C1901-1 # BULK_2V5 Filter Capacitor NET 'BULK_2V5' L1901-1 # 2.5V power filter input NET 'BF_SM_AVDD' L1901-2 # Filtered 2.5V for BF SM NET 'GROUND' L1902-1 # Ground filter input NET 'BF_SM_AVSS' L1902-2 # Filtered Ground for BF SM NET 'BF_SM_AVDD' C1902-1 C1903-1 # BF SM 2.5V Filter Caps NET 'GROUND' C1902-2 C1903-2 # Ground BF SM 2.5V Filter Caps NET 'BF_SM_AVDD' C1904-1 C1906-1 # Base Function System Monitor NET 'BF_SM_AVSS' C1904-2 C1906-2 # AVDD Filter Caps NET 'BF_SM_VREFP' C1905-1 # Base Function System Monitor NET 'BF_SM_AVSS' C1905-2 # VREF Filter Cap NET 'BF_SM_AVDD' U1901-1 # Base Function System Monitor NET 'BF_SM_VREFP' U1901-2 # 1.250 Volt Reference Supply NET 'BF_SM_AVSS' U1901-3 # Input, Output, Common # # Topological Function FPGA System Monitor Reference 1.250 Volt NET 'BULK_2V5' C1911-2 # Topological Function System Monitor NET 'GROUND' C1911-1 # BULK_2V5 Filter Capacitor NET 'BULK_2V5' L1911-1 # 2.5V power filter input NET 'TP_SM_AVDD' L1911-2 # Filtered 2.5V for TP SM NET 'GROUND' L1912-1 # Ground filter input NET 'TP_SM_AVSS' L1912-2 # Filtered Ground for TP SM NET 'TP_SM_AVDD' C1912-1 C1913-1 # TP SM 2.5V Filter Caps NET 'GROUND' C1912-2 C1913-2 # Ground TP SM 2.5V Filter Caps NET 'TP_SM_AVDD' C1914-1 C1916-1 # Topological Function System Monitor NET 'TP_SM_AVSS' C1914-2 C1916-2 # AVDD Filter Caps NET 'TP_SM_VREFP' C1915-1 # Topological Function System Monitor NET 'TP_SM_AVSS' C1915-2 # VREF Filter Cap NET 'TP_SM_AVDD' U1911-1 # Topological Function System Monitor NET 'TP_SM_VREFP' U1911-2 # 1.250 Volt Reference Supply NET 'TP_SM_AVSS' U1911-3 # Input, Output, Common # # Adjustable Reference 0.75 to 1.75 Volt for the # 400 Backplane Processor Input Signals NET 'BULK_3V3' C1921-1 C1922-1 # BULK_3V3 Bypass Caps NET 'GROUND' C1921-2 C1922-2 # Ground the Bypass Filter Caps NET 'BULK_3V3' U1921-1 # Input Terminal on the REF3112 NET 'REF_TO_ADJ_REF' U1921-2 # 1.250V Reference Output Terminal NET 'GROUND' U1921-3 # Ground Terminal on the REF3112 NET 'REF_TO_ADJ_REF' R1921-3 C1923-2 # Hi Side of the Trim Pot CW NET 'LOW_TO_ADJ_REF' R1921-1 R1922-2 # Low Side of the Trim Pot CCW NET 'CNT_TO_ADJ_REF' R1921-2 C1924-2 # Center of the Trim Pot Wiper NET 'GROUND' C1923-1 C1924-1 # Ground the Filter Capacitors NET 'GROUND' R1922-1 # Ground the Low Side Resistors NET 'FEEDBACK_OP_AMP' R1923-2 R1924-1 # Gain 1.4 Feedback Resistors NET 'GROUND' R1923-1 # Ground the Feedback Resistor NET 'FEEDBACK_OP_AMP' U1922-2 # Op-Amp Pin #2 -IN NET 'CNT_TO_ADJ_REF' U1922-3 # Op-Amp Pin #3 +IN NET 'GROUND' U1922-4 # Op-Amp Pin #4 V- Ground NET 'OUTPUT_OP_AMP' U1922-6 # Op-Amp Pin #6 Output NET 'BULK_3V3' U1922-7 # Op-Amp Pin #7 V+ BULK_3V3 NET 'No_Conn_OP_AMP_P1' U1922-1 # No Connect to Pin #1 of the Op-Amp NET 'No_Conn_OP_AMP_P5' U1922-5 # No Connect to Pin #5 of the Op-Amp NET 'No_Conn_OP_AMP_P8' U1922-8 # No Connect to Pin #8 of the Op-Amp NET 'OUTPUT_OP_AMP' R1924-2 R1925-2 # Op-Amp Output to FB and Series Res NET 'VREF_P' R1925-1 # Adjustable Ref to Base Function NET 'OUTPUT_OP_AMP' U1923-3 # Op-Amp Output Clamp at +2.4V Max NET 'GROUND' U1923-1 U1923-2 # Ground the Output Clamp NET 'BULK_3V3' C1925-2 # BULK_3V3 Bypass Caps NET 'GROUND' C1925-1 # Ground the Bypass Filter Caps # # CMX-0 Nets File # # Power Supervisor Board Power OK Logic # ----------------------------------------- # # # Original Rev. 8-Apr-2013 # Most Recent Rev. 14-May-2013 # # # # This file holds all of the nets that are part of # the logic that generates the: BOARD_POWER_OK, # BOARD_POWER_OK_B, and BOARD_POWER_OK_LED_B # signals. # # This all starts from the PRE_BOARD_POWER_OK # signal that comes from the wire-or of the # comparator outputs in the Power Supply Supervisor # section of the net list, i.e. U1861 & U1862. # # This logic is located next to (and is kind of part of) # the Hardwired Oversight Logic. # # # BOARD_POWER_OK is voltage HI only when all supplies are OK. # # BOARD_POWER_OK_B is voltage LOW only when all supplies are OK. # # BOARD_POWER_LED_B is voltage LOW only when all supplies are OK. # # # # # # Components Referenced in this Net List: # # U365 74LVC04A Inverter/Driver for BOARD_POWER_OK signals # # R394 4.7k Ohm Pull-Up to 3V3 for the PRE_BOARD_POWER_OK signal # # C459, C460 47 nFd and 100 nFd bypass on # the 3.3V supply for U365 # # NET 'PRE_BOARD_POWER_OK' U365-1 # Input to the first Inv/Drv NET 'PRE_BOARD_POWER_OK' R394-1 # Pull-Up on PRE_BOARD_POWER_OK NET 'BULK_3V3' R394-2 # Pull-Up connection to BULK_3V3 NET 'BRD_PWR_OK_MID_B' U365-2 # Buff and Inv PRE_BOARD_POWER_OK NET 'BRD_PWR_OK_MID_B' U365-5 # Input to the BOARD_POWER_OK Driver NET 'BOARD_POWER_OK' U365-6 # BOARD_POWER_OK signal # Voltage HI when all power # supplies are running OK. NET 'BRD_PWR_OK_MID_B' U365-3 # Input to the BOARD_POWER_MID Inv NET 'BRD_PWR_OK_MID' U365-4 # BOARD_POWER_MID signal NET 'BRD_PWR_OK_MID' U365-11 # Input to the BOARD_POWER_OK_B Driver NET 'BOARD_POWER_OK_B' U365-10 # BOARD_POWER_OK_B signal # Voltage HI when any power # supply is not running OK. # Voltage LOW when all are OK. NET 'BRD_PWR_OK_MID' U365-9 # Input to the BOARD_POWER_LED_B Driver NET 'BOARD_POWER_LED_B' U365-8 # BOARD_POWER_LED signal # Voltage LOW when all are OK. # Power and Ground for U365 BUL_3V3 power NET 'BULK_3V3' U365-14 NET 'GROUND' U365-7 # Bypass Capacitors on BULK_3V3 for U365 NET 'BULK_3V3' C459-1 C460-1 # ByPass Cap 3.3V power for U365 NET 'GROUND' C459-2 C460-2 # ByPass Cap Ground connections # # CMX-0 Nets File # # # Power Supply Start-Up Supervisors Nets # ----------------========--------------------- # # # Original Rev. 21-Dec-2012 # Most Recent Rev. 17-July-2013 # # # # The CMX card uses a TPS3808 supervisor to control # the start-up of the DCDC converters. This ensures # that the input +5V is stable and has been stable for # about 1 second before beginning the ramp up of the # DC/DC Converter outputs. # # # # TPS3808 Converter Start-Up Supervisor: # ---------------------------------------- NET 'BULK_5V0' R1851-1 # +5V Power for the TPS3808 NET 'POW_UP_FLTRD_POW' R1851-2 # Filtered power for TPS3808 NET 'POW_UP_FLTRD_POW' C1851-2 C1854-2 # Bypass the Filtered power NET 'POW_UP_FLTRD_POW' U1851-6 U1851-5 # TPS3808 Vdd and Sense Pins NET 'GROUND' C1851-1 C1854-1 # Ground the power filter caps. NET 'GROUND' U1851-2 # TPS3808 GROUND connection NET 'POW_UP_TIME_CAP' U1851-4 C1853-2 # TPS3808 Timing capacitor NET 'GROUND' C1853-1 # Ground the Timing capacitor NET 'POW_UP_SUPR_MR_B' U1851-3 C1852-1 # TPS3808 Manual_Reset_B NET 'GROUND' C1852-2 # Ground the Manual Reset cap. NET 'DCDC_CONV_TRACK' U1851-1 # TPS3808 RESET_B output # Holds converter's TRACK # signal LOW until power supply # start up is allowed to begin. # # CMX-0 Nets File # # ByPass Capacitors Base Function REFERENCE Supply # -----------------------------------===========--------- # # # Original Rev. 2-Jan-2013 # Most Recent Rev. 8-May-2013 # # # # This file holds the nets for ALL of Base Function FPGA # Select I/O Reference supply bypass Capacitors. # ----------- # # # This Reference supply is used for the Select I/O Banks # that receive the 400 Backplane Processor signals. # # # This net list file includes the following components: # # C173:C182 are 100 nFd 0603 # C183:C192 are 220 nFd 0603 # C193:C196 are 4.7 uFd 0805 # # # 100 nFd Bypass Capacitors on the Reference Supply # NET 'VREF_P' C173-1 C174-1 C175-1 C176-1 C177-1 NET 'GROUND' C173-2 C174-2 C175-2 C176-2 C177-2 NET 'VREF_P' C178-1 C179-1 C180-1 C181-1 C182-1 NET 'GROUND' C178-2 C179-2 C180-2 C181-2 C182-2 # # 220 nFd Bypass Capacitors on the Reference Supply # NET 'VREF_P' C183-1 C184-1 C185-1 C186-1 C187-1 NET 'GROUND' C183-2 C184-2 C185-2 C186-2 C187-2 NET 'VREF_P' C188-1 C189-1 C190-1 C191-1 C192-1 NET 'GROUND' C188-2 C189-2 C190-2 C191-2 C192-2 # # 4.7 uFd Bypass Capacitors on the Reference Supply # NET 'VREF_P' C193-1 C194-1 C195-1 C196-1 NET 'GROUND' C193-2 C194-2 C195-2 C196-2 # # CMX-0 Nets File # # ByPass Capacitors TOPOLOGICAL FPGA VCCINT Core Supply # -------------------=============------========------------- # # # Original Rev. 4-Jan-2013 # Most Recent Rev. 4-Jan-2013 # # # # This file holds the nets for ALL of Base Function FPGA # TP_CORE supply bypass Capacitors. # ========= # # This net list file includes nets to the following components: # # C871:C878 220 nFd 0603 # C879:C886 4.7 uFd 0603 # C887:C892 33 uFd Tant B # C893:C896 330 uFd Tant D plus 6 more 330 uFd Tantalums # located at the DC/DC Converter # # # 220 nFd Bypass Capacitors on the TP_CORE supply # NET 'TP_CORE' C871-1 C872-1 C873-1 C874-1 NET 'GROUND' C871-2 C872-2 C873-2 C874-2 NET 'TP_CORE' C875-2 C876-2 C877-2 C878-2 NET 'GROUND' C875-1 C876-1 C877-1 C878-1 # # 4.7 uFd Bypass Capacitors on the TP_CORE supply # NET 'TP_CORE' C879-1 C880-1 C881-1 C882-1 NET 'GROUND' C879-2 C880-2 C881-2 C882-2 NET 'TP_CORE' C883-2 C884-2 C885-2 C886-2 NET 'GROUND' C883-1 C884-1 C885-1 C886-1 # # 33 uFd Bypass Capacitors on the TP_CORE supply # NET 'TP_CORE' C887-1 C888-1 C889-1 NET 'GROUND' C887-2 C888-2 C889-2 NET 'TP_CORE' C890-1 C891-1 C892-1 NET 'GROUND' C890-2 C891-2 C892-2 # # 330 uFd Bypass Capacitors on the TP_CORE supply # NET 'TP_CORE' C893-1 C894-1 C895-1 C896-1 NET 'GROUND' C893-2 C894-2 C895-2 C896-2 # # CMX-0 Nets File # # ByPass Capacitors TOPOLOGICAL Processor BULK_2V5 Supply # ------------------------------------------------------------- # # # Original Rev. 4-Jan-2013 # Most Recent Rev. 4-Jan-2013 # # # # This file holds the nets for ALL of Base Function FPGA # BULK_2V5 supply bypass Capacitors. # -------- # # # The BULK_2V5 is used for the VCCAUX and VCC0 on the FPGA. # ======== ====== ==== # # # This net list file includes the following components: # # C901 every_3rd C946 220 nFd 0603 # C902 every_3rd C947 4.7 uFd 0603 # C903 every_3rd C948 33 uFd Tant B # # # 220 nFd Bypass Capacitors on the BULK_2V5 for VCCAUX and VCCO # NET 'BULK_2V5' C901-1 C904-1 C907-1 C910-1 NET 'GROUND' C901-2 C904-2 C907-2 C910-2 NET 'BULK_2V5' C913-1 C916-1 C919-1 C922-1 NET 'GROUND' C913-2 C916-2 C919-2 C922-2 NET 'BULK_2V5' C925-1 C928-1 C931-1 C934-1 NET 'GROUND' C925-2 C928-2 C931-2 C934-2 NET 'BULK_2V5' C937-1 C940-1 C943-1 C946-1 NET 'GROUND' C937-2 C940-2 C943-2 C946-2 ##NET 'BULK_2V5' C949-2 C952-2 C955-2 C958-2 ##NET 'GROUND' C949-1 C952-1 C955-1 C958-1 ##NET 'BULK_2V5' C961-2 C964-2 C967-2 C970-2 ##NET 'GROUND' C961-1 C964-1 C967-1 C970-1 # # 4.7 uFd Bypass Capacitors on the BULK_2V5 for VCCAUX and VCCO # NET 'BULK_2V5' C902-1 C905-1 C908-1 C911-1 NET 'GROUND' C902-2 C905-2 C908-2 C911-2 NET 'BULK_2V5' C914-1 C917-1 C920-1 C923-1 NET 'GROUND' C914-2 C917-2 C920-2 C923-2 NET 'BULK_2V5' C926-1 C929-1 C932-1 C935-1 NET 'GROUND' C926-2 C929-2 C932-2 C935-2 NET 'BULK_2V5' C938-1 C941-1 C944-1 C947-1 NET 'GROUND' C938-2 C941-2 C944-2 C947-2 ##NET 'BULK_2V5' C950-2 C953-2 C956-2 C959-2 ##NET 'GROUND' C950-1 C953-1 C956-1 C959-1 ##NET 'BULK_2V5' C962-2 C965-2 C968-2 C971-2 ##NET 'GROUND' C962-1 C965-1 C968-1 C971-1 # # 33 uFd Bypass Capacitors on the BULK_2V5 for VCCAUX and VCCO # NET 'BULK_2V5' C903-1 C906-1 C909-1 C912-1 NET 'GROUND' C903-2 C906-2 C909-2 C912-2 NET 'BULK_2V5' C915-1 C918-1 C921-1 C924-1 NET 'GROUND' C915-2 C918-2 C921-2 C924-2 NET 'BULK_2V5' C927-1 C930-1 C933-1 C936-1 NET 'GROUND' C927-2 C930-2 C933-2 C936-2 NET 'BULK_2V5' C939-1 C942-1 C945-1 C948-1 NET 'GROUND' C939-2 C942-2 C945-2 C948-2 ##NET 'BULK_2V5' C951-1 C954-1 C957-1 C960-1 ##NET 'GROUND' C951-2 C954-2 C957-2 C960-2 ##NET 'BULK_2V5' C963-1 C966-1 C969-1 C972-1 ##NET 'GROUND' C963-2 C966-2 C969-2 C972-2 # # CMX-0 Nets File # # Power Entry and BULK_5V0 Distribution # ----------------------------------------- # # # Original Rev. 11-Jan-2013 # Most Recent Rev. 2-Aug-2013 # # # # This file holds the nets for the Backplane Power Entry, # the main 5V Fuse and Transient Voltage Suppressor, and # some of the BULK_5V0 distribution. # # # Components References in this Nets file include: # # F1 Fuse for BULK_5V0 20 Amp Solder Lug # F2 Fuse for BULK_5V0_S 3 Amp SMD # # DZ1 DZ1 DZ1 Transient Voltage Suppressor # # WRP1, WRP2, WRP3, WRP4 Backplane power to 20 Amp fuse F4 # # WRP5, WRP6, WRP7, WRP8 BULK_5V0 power from 20 Amp fuse F4 # # # The net connections to the J9 Back Plane Power Connector # are given in the file: # # /Net_Lists/Connectors_Backplane/backplane_connector_9_n2p.txt # # # Distribution of the Backplane +5 Volt Power NET 'BK_PLN_5V0' F2-2 # Input power to the BULK_5V0_S Fuse. NET 'BULK_5V0_S' F2-1 # Bulk 5V South fused power NET 'BULK_5V0_S' DZ1-1 # BULK 5V South Transient Voltage Suppressor NET 'GROUND' DZ1-2 # Ground connection on the TVS NET 'BK_PLN_5V0' WRP1-1 # Backplane Power to the NET 'BK_PLN_5V0' WRP2-1 # main 20 Amp fuse F1 NET 'BK_PLN_5V0' WRP3-1 # NET 'BK_PLN_5V0' WRP4-1 # NET 'BULK_5V0' WRP5-1 # BULK_5V0 Power from NET 'BULK_5V0' WRP6-1 # the main 20 Amp fuse F1 NET 'BULK_5V0' WRP7-1 # NET 'BULK_5V0' WRP8-1 # NET 'BULK_5V0' DZ2-1 # BULK 5V Transient Voltage Suppressor NET 'GROUND' DZ2-2 # Ground connection on the TVS NET 'BULK_5V0' DZ3-1 # BULK 5V North Transient Voltage Suppressor NET 'GROUND' DZ3-2 # Ground connection on the TVS # # CMX-0 Nets File # # Virtex FPGA Special Pins # -======---------------------- # # # Original Rev. 24-Jan-2013 # Most Recent Rev. 28-Jan-2013 # # # # The purpose of this file is to provide a description of # the special Bank #0 pins on the Virtex FPGAs that # are not described and connected to a net in some other # part of the overall CMX design. # # Recall that all of the Bank #0 pins are assigned net-names # in the files: # # .../Base_Fpga_Power/bf_fpga_ff1759_bank_0_and_special_n2p.txt # .../TP_Fpga_Power/tp_fpga_ff1759_bank_0_and_special_n2p.txt # # # Once defined in the above file, many of these special # Bank #0 pins, e.g. the System-Monitor pins and Configuration # pins, are then included elsewhere in the overall CMX design. # # This file will describe all of the special pins that have # not been included elsewhere. The intent is to provide a # rational for how we are handling each of these pins in the # CMX design.. # # BF and TP HSWAPEN Pins pin number P10 # # The HSWAPEN pin controls whether or not pull-up # resistors are connected to all normal Select I/O pins # Pre-Configuration. # # - Bank #0 pins are not part of this setup. # # - HSWAPEN LOW --> Pull-Up during Pre-Configuration # # - HSWAPEN HI --> Tri-State all Select I/O pins # during Pre-Configuration # # - In most places the Xilinx Documentation says that # HSWAPEN controls what happens during Configuration # but what they mean is during Pre-Configuration, # i.e. during the time between when power is turned # ON and the device is first configured. Only after # that is the HSWAPEN controlling what happens strictly # during configuration. # # - The HSWAPEN pin itself always has a weak pull-up # resistor connected to it. Ah but the book says # that this pull-up on the HSWAPEN pin does not always # provide a reliable 1. They say that the HSWAPEN # pin should be connected to either enable or disable # this feature. # # - In general the Xilinx books appear to recommend # enabling these Select I/O pin pull-up during # Configuration. # # - I'm not certain what to do with the HSWAPEN pin # on the CMX card - thus bring it to a pair of jumpers. # # - I believe that the value of this pre-configuration # pull-up current with 2.5V I/O is 80 uAmps. # I.E. no problem is this FPGA pin happens to be # driven by an external device but just right to # define a valid logic level if this FPGA pin runs # only to input pins on external devices. # NET 'BF_HSWAPEN' JMP37-1 JMP38-2 # BF HSWAPEN Control Jumpers NET 'TP_HSWAPEN' JMP47-1 JMP48-2 # TP HSWAPEN Control Jumpers NET 'GROUND' JMP37-2 JMP47-2 # Tie Jumpers to GROUND NET 'BULK_2V5' JMP38-1 JMP48-1 # Tie Jumpers to 2.5 Volts # The HSWAPEN nets on the Base Function and Topological Processor # FPGAs are connected to pins in their Bank #0 n2p file. # # # BF and TP BF_VBATT Pins pin number R10 # # VBATT is a power supply pin for the Decryptor Key memory. # The book says that when VBATT is not used to connect # this pin to either VccAUX or to GROUND. CMX will not # use the Decryptor Key VBATT supply. CMX will # permanently and irrevocably Ground this pin. # # BF and TP BF_VFS Pins pin number AH10 # # VFS is a power supply pin for programming the EFUSE. # The book says to Ground the VFS pin when it is not # being used. CMX will not use the EFUSE. Thus CMX # will permanently and irrevocably Ground this pin. # # # CMX-0 Nets File # # Front-Panel LED Nets # -------------------------- # # # Original Rev. 26-Feb-2013 # Most Recent Rev. 1-July-2013 # # # # This file holds the nets for the Front-Panel LEDs. # # # The BSPT drives 9 of the 10 front panel LEDs. The only LED # that BSPT does not drive is the BOARD_POWER_OK LED. # # Each LED has a pull-up resistor from its Anode to 3.3V. # The Drive signals from the BSPT FPGA go to the LED Cathodes. # The LED illuminates when the BSPT Drive signal is LOW. # These Drive signals are from the FPGA's 3.3V I/O Bank #3. # These 3.3V LED Drive signals can be Open Drain. # The LED series resistors on CMX should result in a 2 mA LED current. # The LED components are labeled from 1 at the Top # through 5 at the Bottom. # Each LED component has a Left and a Right LED. # Each of these 10 LEDs has a Red and a Green section. # LED 1 Left is the BOARD_POWER_OK LED. # The Drive signals for the other 9 LEDs come from the BSPT FPGA. # The LED component used on the CMX card is Dialight No. 592-3030-313F. # The expected Forward Voltage of both the Red and Green sections is 2 Volts. # Thus a series resistor in the range of 650 to 800 Ohms is right for 2 mA. # The 20 series resistors are Reference Designators R271 : R290. # # For both the Left and Right LED in each assembly the pin numbers are: # # Pad Connections: 4 Green Cathode 3 Green Anode # 2 Red Anode 1 Red Cathode # # The LED Reference Designators are: LED_Dual_1 : LED_Dual_5. # The series resistor Reference Designators are: R271 : R290. # # # Board Support FPGA LED Drive connections to the LED Cathodes NET 'No_Conn_LED_1R_RED_DRV' LED_Dual_1-R1 # Drive signal to LED 1 Right Red NET 'LED_1R_GREEN_DRV' LED_Dual_1-R4 # Drive signal to LED 1 Right Green NET 'No_Conn_LED_2L_RED_DRV' LED_Dual_2-L1 # Drive signal to LED 2 Left Red NET 'LED_2L_GREEN_DRV' LED_Dual_2-L4 # Drive signal to LED 2 Left Green NET 'No_Conn_LED_2R_RED_DRV' LED_Dual_2-R1 # Drive signal to LED 2 Right Red NET 'LED_2R_GREEN_DRV' LED_Dual_2-R4 # Drive signal to LED 2 Right Green NET 'LED_3L_RED_DRV' LED_Dual_3-L1 # Drive signal to LED 3 Left Red NET 'LED_3L_GREEN_DRV' LED_Dual_3-L4 # Drive signal to LED 3 Left Green NET 'LED_3R_RED_DRV' LED_Dual_3-R1 # Drive signal to LED 3 Right Red NET 'LED_3R_GREEN_DRV' LED_Dual_3-R4 # Drive signal to LED 3 Right Green NET 'LED_4L_RED_DRV' LED_Dual_4-L1 # Drive signal to LED 4 Left Red NET 'LED_4L_GREEN_DRV' LED_Dual_4-L4 # Drive signal to LED 4 Left Green NET 'LED_4R_RED_DRV' LED_Dual_4-R1 # Drive signal to LED 4 Right Red NET 'LED_4R_GREEN_DRV' LED_Dual_4-R4 # Drive signal to LED 4 Right Green NET 'LED_5L_RED_DRV' LED_Dual_5-L1 # Drive signal to LED 5 Left Red NET 'LED_5L_GREEN_DRV' LED_Dual_5-L4 # Drive signal to LED 5 Left Green NET 'LED_5R_RED_DRV' LED_Dual_5-R1 # Drive signal to LED 5 Right Red NET 'LED_5R_GREEN_DRV' LED_Dual_5-R4 # Drive signal to LED 5 Right Green # # Series Resistor connections to the LED Anodes NET 'LED_1L_RED_ANODE' LED_Dual_1-L2 R271-1 # LED 1 Left Red Anode and Resistor NET 'LED_1L_GREEN_ANODE' LED_Dual_1-L3 R272-1 # LED 1 Left Green Anode and Resistor NET 'LED_1R_RED_ANODE' LED_Dual_1-R2 R273-1 # LED 1 Right Red Anode and Resistor NET 'LED_1R_GREEN_ANODE' LED_Dual_1-R3 R274-1 # LED 1 Right Green Anode and Resistor NET 'LED_2L_RED_ANODE' LED_Dual_2-L2 R275-1 # LED 2 Left Red Anode and Resistor NET 'LED_2L_GREEN_ANODE' LED_Dual_2-L3 R276-1 # LED 2 Left Green Anode and Resistor NET 'LED_2R_RED_ANODE' LED_Dual_2-R2 R277-1 # LED 2 Right Red Anode and Resistor NET 'LED_2R_GREEN_ANODE' LED_Dual_2-R3 R278-1 # LED 2 Right Green Anode and Resistor NET 'LED_3L_RED_ANODE' LED_Dual_3-L2 R279-1 # LED 3 Left Red Anode and Resistor NET 'LED_3L_GREEN_ANODE' LED_Dual_3-L3 R280-1 # LED 3 Left Green Anode and Resistor NET 'LED_3R_RED_ANODE' LED_Dual_3-R2 R281-1 # LED 3 Right Red Anode and Resistor NET 'LED_3R_GREEN_ANODE' LED_Dual_3-R3 R282-1 # LED 3 Right Green Anode and Resistor NET 'LED_4L_RED_ANODE' LED_Dual_4-L2 R283-1 # LED 4 Left Red Anode and Resistor NET 'LED_4L_GREEN_ANODE' LED_Dual_4-L3 R284-1 # LED 4 Left Green Anode and Resistor NET 'LED_4R_RED_ANODE' LED_Dual_4-R2 R285-1 # LED 4 Right Red Anode and Resistor NET 'LED_4R_GREEN_ANODE' LED_Dual_4-R3 R286-1 # LED 4 Right Green Anode and Resistor NET 'LED_5L_RED_ANODE' LED_Dual_5-L2 R287-1 # LED 5 Left Red Anode and Resistor NET 'LED_5L_GREEN_ANODE' LED_Dual_5-L3 R288-1 # LED 5 Left Green Anode and Resistor NET 'LED_5R_RED_ANODE' LED_Dual_5-R2 R289-1 # LED 5 Right Red Anode and Resistor NET 'LED_5R_GREEN_ANODE' LED_Dual_5-R3 R290-1 # LED 5 Right Green Anode and Resistor # # BOARD_POWER_OK Connection to LED 1 Left NET 'BOARD_POWER_LED_B' LED_Dual_1-L4 # Illuminate the Top Left Green LED # when the Board Power is OK. # # Connect the LED Series Resistors to the BULK_3V3 supply. NET 'BULK_3V3' R271-2 R272-2 R273-2 R274-2 R275-2 # BULK_3V3 LED Power NET 'BULK_3V3' R276-2 R277-2 R278-2 R279-2 R280-2 # BULK_3V3 LED Power NET 'BULK_3V3' R281-2 R282-2 R283-2 R284-2 R285-2 # BULK_3V3 LED Power NET 'BULK_3V3' R286-2 R287-2 R288-2 R289-2 R290-2 # BULK_3V3 LED Power # # CMX-0 Nets File # # Board Support FPGA - All Other Nets # ------------------------------------- # # # Original Rev. 26-Feb-2013 # Rev. 20-Jun-2013 Swap TP_TO_FROM_BSPT_3 and _4 to help trace layout # Rev. 21-Jun-2013 Move BF <--> TP: REQ, LED, To/From, and BSPT_DeBug # Rev: 10-Jul-2013 Reorder debug pin assignment for straight route near # debug connector # Rev: 11-Sep-2013 Add connections from unused 3V3 pins to SR Comps. # Most Recent Rev: 20-Sep-2013 Add JMP101:JMP105 for the 5-bit CMX Card Serial Number. # # # # # This file holds All of the Other nets that connect to the # Board Support FPGA. # # Specifically this file holds the BSPT connections for: # # 1. The "package pins" on BSPT FPGA, e.g. SUSPEND, AWAKE, PUDC_B # # 2. The LED associated pins, i.e. control signals from BF & TP # drive signals to the LEDs # # 3. VME/OCB Management signals, i.e. control of sending DTACK_B # control of data buffer direction and OE_B # # 4. Management of the Cable LVDS, i.e. direction request signals from the BF # FPGA, control signals to the Cable LVDS # Translators and Transceivers via the # Hardwired Oversight Logic # # 5. Management of the CTP LVDS, i.e. direction request signals from the BF and TP # FPGAs, control signals to the CTP LVDS # Translators and Transceivers via the # Hardwired Oversight Logic # # 6. An input pin for the ALLOW_BUSSED_IO signal 3.3V level # so that the BSPT FPGA can know if the Hardwired Oversight # Logic thinks that conditions are OK for nornal CMX # operation. # # 6. A jumper controlled input to BSPT that unambiguously # indicates whether or not the Topological Processor FPGA # is installed on this card. TP_FPGA_INSTALLED_B # # 7. DeBug, Spare Signals to Header J14 - 10 signals 2.5V logic level. # # 8. Spare connections: BF to/from BSPT and TP to/from BSPT # 8 each to/from BF and TP. All 2.5V signal. All I/O pins # on the BSPT FPGA. # # 9. The No_Conn pins on the BSPT FPGA, i.e. FPGA pins that # are not used on CMX. # # # # The "groups" of signals that connect to the Board Support # FPGA are organized into the following 6 nets files: # # bspt_fpga_configuration_n2p.txt # bspt_fpga_on_card_bus_nets_n2p.txt # bspt_fpga_optical_ctrl_monit_n2p.txt # bspt_fpga_power_and_ground_n2p.txt # bspt_fpga_system_ace_nets_n2p.txt # bspt_fpga_TTCDec_signals_n2p.txt # # # # The following 3 files each include a few connections to the # Board Support FPGA: # # clock_gen_and_dist_nets_n2p.txt # configuration_nets_n2p.txt # jtag_chains_n2p.txt # # # # Recall the setup of the BSPT I/O Bank Voltages that is # used on the CMX card: # # - I/O Banks #0, #1, #2 are all 2.5V CMOS logic signals. # # - I/O Bank #3 has a 3.3V CMOS logic signals. # # - The VCCAUX supply to the BSPT is 3.3 Volts and thus # the BSPT signals: SUSPEND, DONE, PROG_B, and JTAG # are all 3.3V levels. Recall that the Spartan 3A will # need the CONFIG VCCAUX=3.3" constraint. # # # # # The parts referenced in this file include: # # U351 BSPT_FPGA # JMP57 BSPT PUDC_B Control # R326 Pull-Up on BSPT PUDC_B pin # JMP49 Topological Processor Installed Jumper # R327 Pull-Up on TP_Installed Jumper # # # Board Support FPGA "Package Pins": SUSPEND, AWAKE, PUDC_B # ---------------------------------- # The Suspend feature of the Spartan 3A FPGA must be enabled # in the bit-stream otherwise it is not possible to use this # feature. The dedicated SUSPEND pin R15 will be grounded # in the CMX design. NET 'GROUND' U351-R15 # Ground the dedicated SUSPEND pin. # Because the Suspend feature will not be used the Dual purpose # pin U13 IO_L22P_2/AWAKE is a normal Bank #2 I/O pins and # may be used for 2.5V logic on the CMX card. # The PUDC_B pin, aka Pull-Up During Configure, is similar to # the HSWAP_EN pin on the Virtex parts. If PUDC_B is LOW then # before the device is initially configured and during each # subsequent configuration process a Pull-Up Resistor will # be placed on all I/O and all Input pins that are not actively # being used by the selected configuration process. The intent # of this is to keep these CMOS signals at a defined and valid # logic level. The strength of these pull-up resistors is: # 5.1k to 24k for 3.3V I/O banks, 6.2k to 33k for 2.5V I/O Banks. # # The state of the PUDC_B pin will be controlled by jumper JMP57. # Install JMP57 to pull PUDC_B LOW and thus enable the pull-up # resistors before and during BSPT configuration. # # Note that the IO_L32N_0/PUDC_B pin B2 will not be used # on the CMX card for normal I/O. NET 'BSPT_PUDC_B' U351-B2 # Control the IO_L32N_0/PUDC_B pin NET 'BSPT_PUDC_B' JMP57-1 R326-1 # Control the BSPT PUDC_B pin NET 'GROUND' JMP57-2 # Ground for the PUDC_B jumper NET 'BULK_2V5' R326-2 # BULK_2V5 for R326 pull-up # # The LED associated pins on BSPT FPGA: # ------------------------------------- # Both the Base Function and the Topological Processor # FPGAs provide 5 LED Illumination Request signals each # to the BSPT FPGA. These are 2.5V inputs to the BSPT # FPGA. BF or TP sets one of these lines HI when it wants # the LED that BSPT FPGA is currently associating with that # request line to be illuminated. These are all 2.5V I/O # pins on the BSPT FPGA used as inputs in this application. # LED Request #0 through #4 from the BF FPGA NET 'BF_LED_REQ_0' U351-Y16 # L28P-2 2.5V I/O used as Input NET 'BF_LED_REQ_1' U351-V17 # L31P-2 2.5V I/O used as Input NET 'BF_LED_REQ_2' U351-Y17 # L30P-2 2.5V I/O used as Input NET 'BF_LED_REQ_3' U351-Y18 # L30N-2 2.5V I/O used as Input NET 'BF_LED_REQ_4' U351-W20 # L01P-1 2.5V I/O used as Input # LED Request #0 through #4 from the TP FPGA NET 'TP_LED_REQ_0' U351-P20 # L10N-1 2.5V I/O used as Input NET 'TP_LED_REQ_1' U351-N15 # L12P-1 2.5V I/O used as Input NET 'TP_LED_REQ_2' U351-N17 # L12N-1 2.5V I/O used as Input NET 'TP_LED_REQ_3' U351-N18 # L13P-1 2.5V I/O used as Input NET 'TP_LED_REQ_4' U351-N19 # L13N-1 2.5V I/O used as Input # # The BSPT drives 9 of the 10 LEDs. The only LED that # BSPT does not drive is the BOARD_POWER_OK LED. # # Each LED has a pull-up resistor from its Anode to 3.3V. # The Drive signals from the BSPT FPGA go to the LED Cathodes. # The LED illuminates when the BSPT Drive signal is LOW. # These Drive signals are from the 3.3V I/O Bank #3. # These 3.3V LED Drive signals can be Open Drain. # The LED series resistors on CMX should result in a 2 mA LED current. # The LED components are labeled from 1 at the Top # through 5 at the Bottom. # Each LED component has a Left and a Right LED. # Each of these 10 LEDs has a Red and a Green section. # LED 1 Left is the BOARD_POWER_OK LED. # The Drive signals for the other 9 LEDs come from the BSPT FPGA. # NET 'LED_1R_GREEN_DRV' U351-H6 # Drive signal to LED 1 Right Green NET 'LED_2L_GREEN_DRV' U351-H4 # Drive signal to LED 2 Left Green NET 'LED_2R_GREEN_DRV' U351-H3 # Drive signal to LED 2 Right Green NET 'LED_3L_GREEN_DRV' U351-H2 # Drive signal to LED 3 Left Green NET 'LED_3L_RED_DRV' U351-J6 # Drive signal to LED 3 Left Red NET 'LED_3R_GREEN_DRV' U351-J5 # Drive signal to LED 3 Right Green NET 'LED_3R_RED_DRV' U351-J4 # Drive signal to LED 3 Right Red NET 'LED_4L_GREEN_DRV' U351-J3 # Drive signal to LED 4 Left Green NET 'LED_4L_RED_DRV' U351-J2 # Drive signal to LED 4 Left Red NET 'LED_4R_GREEN_DRV' U351-J1 # Drive signal to LED 4 Right Green NET 'LED_4R_RED_DRV' U351-K4 # Drive signal to LED 4 Right Red NET 'LED_5L_GREEN_DRV' U351-K3 # Drive signal to LED 5 Left Green NET 'LED_5L_RED_DRV' U351-K2 # Drive signal to LED 5 Left Red NET 'LED_5R_GREEN_DRV' U351-L5 # Drive signal to LED 5 Right Green NET 'LED_5R_RED_DRV' U351-L3 # Drive signal to LED 5 Right Red # VME/OCB Management Signals from BSPT FPGA: # ------------------------------------------ # # All 10 of the following signals come from the # On-Card-Bus Management function in the BSPT must control: # # - Control sending the VME DTACK_B signal from the CMX card. # This is a 3.3V control signal that passes through # Hardwired Oversight Logic on its way to the DTACK_B # VME driver chip. # # Before the BSPT FPGA is configured this signal must be # pulled HI. Once the CMX is ready for VME acces then # this signal should be taken LOW to request that the CMX # card assert its DTACK_B VME signal. NET 'BSPT_SEND_VME_DTACK_B' U351-D2 # L03N-3 3.3V Output # - Control the Direction of the VME Data Bus Transceiver # U352. This is a 3.3V control signal that runs directly # to the U352 VME Transceiver. # # Before the BSPT FPGA is configured this signal will be # pulled HI. Once the CMX is ready for VME acces then # this signal should be taken LOW for VME Writes and must # go HI for VME Reads. This signal must alwasy be in # the same state as the OCB_D_BUS_TRNSLT_DIR signal. NET 'VME_D_BUS_TRNCVR_DIR' U351-D3 # L01N-3 3.3V Output # - Control the Output_Enable_B of the VME Data Bus # Transceiver U352. This is a 3.3V control signal that # passes through Hardwired Oversight Logic on its way to # the U352 VME Transceiver. # # Before the BSPT FPGA is configured this signal must be # pulled HI. Once the CMX is ready for VME acces then # this signal should be taken LOW when this card is the # target of a VME Read or Write. NET 'BSPT_VME_D_BUS_TRNCVR_OE_B' U351-D1 # L05P-3 3.3V Output # - Control the Direction of the OCB Data Bus Translator # U355. This is a 2.5 control signal that runs directly # to the U355 OCB Translator. # # Before the BSPT FPGA is configured this signal will be # pulled HI. Once the CMX is ready for VME acces then # this signal should be taken LOW for VME Writes and must # go HI for VME Reads. This signal must alwasy be in # the same state as the VME_D_BUS_TRNCVR_DIR signal. NET 'OCB_D_BUS_TRNSLT_DIR' U351-A16 # L05N-0 2.5V Output # - Control the Output_Enable_B of the OCB Data Bus # Translator U355. This is a 2.5V control signal that # runs directly to the U355 OCB Translator. # # Before the BSPT FPGA is configured this signal must be # pulled HI. Once the CMX is ready for VME acces then # this signal should be taken LOW when this card is the # target of a VME Read or Write. NET 'OCB_D_BUS_TRNSLT_OE_B' U351-E15 # L03N-0 2.5V Output # - Control the LE signal to the U354 VME Receiver and to # the half of the U353 VME Receiver that is used for # "Address type" information. This is a 3.3V control # signal that runs directly to U354 and to the Address # section of the U353 Receiver. # # Before the BSPT FPGA is configured this LE signal will # be pulled HI. Once the CMX is ready for VME acces then # this LE signal can either remain HI to keep these # receivers transparent or else this LE signal may go LOW # at times so that these VME Receivers will "Hold" their # address information if this type of operation is desired. NET 'VME_ADRS_RECVR_LE' U351-C2 # L02N-3 3.3V Output # - Control the LE signal to the half of the U353 VME # Receiver that handles "Control type" information. # This LE signal must always hold this VME Receiver in # its transparent state. This is a 3.3V control signal # that runs directly to this section of the U353 Receiver. # # Before the BSPT FPGA is configured this LE signal will # be pulled HI. Once the CMX is ready for VME acces then # this LE signal should continue to be held HI to keep # this receiver's latch transparent. NET 'VME_CTRL_RECVR_LE' U351-D4 # L01P-3 3.3V Output # - Control the OE_B signal to all sections of both the # U353 and U354 Receivers for the VME Address and Control # type signals. This is a 3.3V control signal that runs # directly to the U353 and U354 chips. # # Before the BSPT FPGA is configured this signal must # be pulled HI. Once the CMX is ready for VME acces then # this signal should be taken LOW and stay LOW to enable # the output of these VME Receivers. NET 'VME_ADRS_AND_CTRL_RECVR_OE_B' U351-C1 # L03P-3 3.3V Output # - Control the DIR signal to all sections of both the # U356 and the U357 Translators for the OCB Address and # Control type signals. This is a 2.5V control that # goes directly to the U356 and U357 chips. # # Before the BSPT FPGA is configured this signal will # be pulled HI. Once the CMX is ready for VME acces then # this signal should be taken LOW and stay LOW to select # the B input to A output direction. NET 'OCB_ADRS_AND_CTRL_TRNSLT_DIR' U351-D15 # L06P-0 2.5V Output # - Control the OE_B signal to all sections of both the # U356 and the U357 Translators for the OCB Address and # Control type signals. This is a 3.3V control signal # that passes through Hardwired Oversight Logic before # it goes to U356 and U357. # # Before the BSPT FPGA is configured this signal must # be pulled HI. Once the CMX is ready for VME acces then # this signal should be taken LOW and stay LOW to enable # the translator outputs. NET 'BSPT_OCB_ADRS_AND_CTRL_TRNSLT_OE_B' U351-E3 # L10P-3 3.3V Output # Thus in total there are 10 OCB/VME Management signals # coming from the BSPT FPGA. 3 of these control signals # are 2.5V level. 7 of these control signals are 3.3V # level. 3 of these control signals have external # Hardwired Oversight Logic. # Management of the Backplane # LVDS Transceivers and Translators: # -------------------------------------- # # Recall that there are 3 Backplane Cables connected to # each CMX card. These cables from the top to the bottom are: # # Cable #1 consists of signals M_00 thru M_26 plus M_81 # Cable #2 consists of signals M_27 thru M_53 plus M_82 # Cable #3 consists of signals M_54 thru M_80 plus M_83 # # After passing through VLDS Transceivers and 3.3V <--> 2.5V # Translators the 28 signals on each of these cables are # connected to Select I/O pins on the Base Function FPGA. # The Translators and the VLDS Transceivers for each cable # can independently be setup to either receive signals from # the cable or to send signals onto the cable. The Base # Function FPGA requests the direction of these Transltors # and LVDS Transceivers with 3 direction request lines - # one line to request the direction of each Cable. # # The firmware in the Base Function FPGA must obey # 2 rules while managing the direction of the Backplane # LVDS Cables: # # - When BF requests that the Translators and LVDS # Transceivers for a given Backplane Cable are # either Inputs or Outputs it must also make certain # that its I/O pins associated with the 28 signals # for that Cable are also correctly setup as Inputs # or Outputs to match the direction of the Translators # and LVDS Transceivers. # # - When the BF does not want to use a given Backplane # cable it must request the direction of that cable # to be Input. # # The signal that the BF FPGA uses to request the # direction of the Translators and LVDS Transceivers # associated with a give Backplane Cable is called: # # BF_REQ_CABLE_n_INPUT # # # The BF FPGA sets this 2.5V CMOS signal HI when it wants # that Backplane Cable to be an Input. This signal is called # a Request because it must pass through the Board Support # FPGA where it becomes the actual control lines that run # to the Translator and LVDS Transceiver chips. For protection # of the components in these circuits the Output_Enable_B # line to the Translator chips passes through Hardwired # Oversignt Logic before it reaches the Translator chips. # # Logic in the Board Support FPGA confirms that the Base # Function FPGA is Configured before allowing the # BF_REQ_CABLE_n_INPUT request signal to manage the # control lines that run to the Translators and LVDS # Transceivers. # # Until the Base Function FPGA is Configured the logic in # the BSPT FPGA forces the Translators and LVDS Transceivers # to the following states: # # The LVDS Transceivers are set as Drivers # The Translators are set in the send data out direction # The Translators have their outputs disabled (3-stated) # # # The Hardwired Oversight Logic confirms: # that the Board_Power_OK signals is asserted and # that the BSPT_CONFIG_DONE signal is asserted and # that the CMX SAFE Jumper is installed and # that the BSPT_RUNNING_OK_B signal is asserted Low # before it allows any of the Translator Outputs to be enabled. # # From the BSPT FPGA there are 3 control signals that manage # the Translators and LVDS Transceivers for each of the 3 # cables. These signals are: # # CABLE_n_TRNCVR_DIR # CABLE_n_TRNSLT_DIR # CABLE_n_TRNSLT_OE_B # # # CABLE_n_TRNCVR_DIR is a 3.3V CMOS level signal that # runs directly to both the DRV_ENB and REC_ENB_B pin of the # DS91M040 LVDS Transceiver chips. Logic in the BSPT FPGA # must hold this signal HI until it confirms that the Base # Function FPGA is Configured and has rationally taken control # of requesting the direction that it wants on the 3 LVDS Cables. # Note that the level on CABLE_n_TRNCVR_DIR must always # match the level on CABLE_n_TRNSLT_DIR. # # CABLE_n_TRNSLT_DIR is a 2.5V CMOS level signal that # runs directly to the DIR pins on the 74AVCAH164245 Translator # chips. Before the Base Function FPGA is Configured, logic in # the BSPT FPGA should hold this signal either Hi. # Note that the level on CABLE_n_TRNSLT_DIR must always # match the level on CABLE_n_TRNCVR_DIR. # # CABLE_n_TRNSLT_OE_B is a 3.3V CMOS level signal that # passes through Hardwired Oversight Logic before running to # the OE_B pins on the 74AVCAH164245 Translator chips. Before # the Base Function FPGA is Configured, logic in the BSPT FPGA # must set this signal Hi. # # The current state of all 12 of the following signals may be # examined in a VME visible read only register in the BSPT FPGA. NET 'BF_REQ_CABLE_1_INPUT' U351-V15 # 2.5V I/O input to the BSPT # Hi --> BF Requests this LVDS # Cable to be an Input NET 'CABLE_1_TRNCVR_DIR' U351-W2 # 3.3V output from the BSPT # Hi --> LVDS Driver is Enabled NET 'CABLE_1_TRNSLT_DIR' U351-A17 # 2.5V output from the BSPT # Hi --> Translator direction for # LVDS Cables Output NET 'BSPT_CABLE_1_TRNSLT_OE_B' U351-E1 # 3.3V output from the BSPT # HI --> Disables the # Translator Outputs NET 'BF_REQ_CABLE_2_INPUT' U351-Y15 # 2.5V I/O input to the BSPT # Hi --> BF Requests this LVDS # Cable to be an Input NET 'CABLE_2_TRNCVR_DIR' U351-W1 # 3.3V output from the BSPT # Hi --> LVDS Driver is Enabled NET 'CABLE_2_TRNSLT_DIR' U351-D16 # 2.5V output from the BSPT # Hi --> Translator direction for # LVDS Cables Output NET 'BSPT_CABLE_2_TRNSLT_OE_B' U351-F4 # 3.3V output from the BSPT # HI --> Disables the # Translator Outputs NET 'BF_REQ_CABLE_3_INPUT' U351-W16 # 2.5V I/O input to the BSPT # Hi --> BF Requests this LVDS # Cable to be an Input NET 'CABLE_3_TRNCVR_DIR' U351-V2 # 3.3V output from the BSPT # Hi --> LVDS Driver is Enabled NET 'CABLE_3_TRNSLT_DIR' U351-C16 # 2.5V output from the BSPT # Hi --> Translator direction for # LVDS Cables Output NET 'BSPT_CABLE_3_TRNSLT_OE_B' U351-F3 # 3.3V output from the BSPT # HI --> Disables the # Translator Outputs # Management of the Front Panel CTP # LVDS Transceivers and Translators: # -------------------------------------- # # Recall that there are 2 Front Panel CTP Connection on each # CMX card. These connectors, top then bottom are: # # Connector J10 is signals CTP_00 thru CTP_31 plus CTP_64 # Connector J11 is signals CTP_32 thru CTP_63 plus CTP_65 # # After passing through VLDS Transceivers and 3.3V <--> 2.5V # Translators the 33 signals on each of these 2 CTP Connectors # are routed to Select I/O pins on the Base Function FPGA and # to Select I/O pin on the Topological Processor FPGA. # # Each CTP Connector has one set of LVDS Transceivers and # 2 sets of Translators. One set of Translators is associated # with the BF FPGA and the other set is associated with the # TP FPGA. # # The Translators and the VLDS Transceivers for each CTP # Connector can independently be setup to either receive # signals from the connector or to send signals to the CTP # Connector. When sending signals to the CTP Connector, # to prevent conflicting signals, either just the BF # Translators or else just the TP Translators may have # their outputs enabled. # # The Base Function and Topological Processor FPGAs each # can request the direction of these Transltors and LVDS # Transceivers with 2 direction request lines - one line # from each of these FPGAs to request the direction of # each of the CTP Connectors. # # The firmware in the BF and TP FPGAs must obey 2 rules # when requesting the direction of the CTP Connectors: # # - When one of these FPGAs requests that the Translators # and LVDS Transceivers for a given CTP Connector are # either Inputs or Outputs it must also make certain # that its I/O pins associated with the 33 signals # for that CTP Connector are also correctly setup as # Inputs or Outputs to match the direction of the # Translators and LVDS Transceivers. # # - When one of these FPGAs does not want to use a given # CTP Connector then it must request the direction # that CTP Connector to be an Input. # # The signal that the BF or TP FPGA uses to request the # direction of the Translators and LVDS Transceivers # associated with a give CTP Connector is called: # # BF_REQ_CTP_n_INPUT or # TP_REQ_CTP_n_INPUT # # # The FPGA sets this 2.5V CMOS signal HI when it wants that # CTP Connector to be an Input. This signal is called # a Request because it must pass through the Board Support # FPGA where it becomes the actual control lines that run # to the Translator and LVDS Transceiver chips. For protection # of the components in these circuits the Output_Enable_B # line to the Translator chips passes through Hardwired # Oversignt Logic before it reaches the Translator chips. # # Logic in the Board Support FPGA confirms that the BF or TP # FPGA is Configured before allowing the xy_REQ_CTP_n_INPUT # request signal to manage the control lines that run to the # Translators and LVDS Transceivers. # # Until the BF and TP FPGAs are Configured the logic in the # BSPT FPGA forces the Translators and LVDS Transceivers to # the following states: # # The LVDS Transceivers are set as LVDS Output Drivers # The Translators are set in the send data out to the CTP # The Translators have their outputs disabled (3-stated) # # From the TP_FPGA_INSTALLED_B jumper the BSPT logic knows # whether or not the TP FPGA is actually installed on a given # CMX card. When the TP is not installed then: # # Its TP_REQ_CTP_n_INPUT signals are ignored. # The DIR control signal to the Translators associated with # the TP FPGA are forced HI thus setting their direction # to be output. # The OE_B control signal to the Translators associated with # the TP FPGA are forced HI thus disabling the Translator # outputs. # # The Hardwired Oversight Logic confirms: # that the Board_Power_OK signals is asserted and # that the BSPT_CONFIG_DONE signal is asserted and # that the CMX SAFE Jumper is installed and # that the BSPT_RUNNING_OK_B signal is asserted Low # before it allows any of the Translator Outputs to be enabled. # # # From the BSPT FPGA there are 5 control signals that manage # the Translators and LVDS Transceivers for each of the two # CTP Connectora. These signals are: # # CTP_n_TRNCVR_DIR # CTP_n_BF_TRNSLT_DIR # CTP_n_BF_TRNSLT_OE_B # CTP_n_TP_TRNSLT_DIR # CTP_n_TP_TRNSLT_OE_B # # # CTP_n_TRNCVR_DIR is a 3.3V CMOS level signal that # runs directly to both the DRV_ENB and REC_ENB_B pin of the # DS91M040 LVDS Transceiver chips. Logic in the BSPT FPGA # must hold this signal HI until it confirms that the Base # Function FPGA (and if installed the TP FPGA) is Configured # and has rationally taken control of requesting the direction # that it wants on the 2 CTP Connectors to be. # # CTP_n_BF_TRNSLT_DIR and CTP_n_TP_TRNSLT_DIR are # 2.5V CMOS level signals that run directly to the DIR pins on # the 74AVCAH164245 Translator chips. Before the Base Function # FPGA (and if installed the TP FPGA) is Configured, logic # in the BSPT FPGA should hold this signal either Hi. When # the TP FPGA is NOT installed then the Direction signal to # its Translators should always be Hi. # # CTP_n_BF_TRNSLT_OE_B and CTP_n_TP_TRNSLT_OE_B are # 3.3V CMOS level signals that passes through Hardwired Oversight # Logic before running to the OE_B pins on the 74AVCAH164245 # Translator chips. Before the Base Function FPGA (and if # installed the TP FPGA) is Configured, logic in the BSPT FPGA # must set this signal Hi. When the TP FPGA is NOT installed # then the OE_B signal to its Translators must always be Hi. # # The current state of all 14 of the following signals may be # examined in a VME visible read only register in the BSPT FPGA. NET 'BF_REQ_CTP_1_INPUT' U351-P11 # 2.5V input only to the BSPT # Hi --> BF Requests this CTP # Connector to be an Input NET 'TP_REQ_CTP_1_INPUT' U351-P13 # 2.5V input only to the BSPT # Hi --> BF Requests this CTP # Connector to be an Input NET 'CTP_1_TRNCVR_DIR' U351-N4 # 3.3V output from the BSPT # Hi --> LVDS Driver is Enabled NET 'CTP_1_BF_TRNSLT_DIR' U351-Y5 # 2.5V output from the BSPT # Hi --> Translator direction # for CTP Connector Output NET 'BSPT_CTP_1_BF_TRNSLT_OE_B' U351-F2 # 3.3V output from the BSPT # HI --> Disables the # Translator Outputs NET 'CTP_1_TP_TRNSLT_DIR' U351-V5 # 2.5V output from the BSPT # Hi --> Translator direction # for CTP Connector Output NET 'BSPT_CTP_1_TP_TRNSLT_OE_B' U351-F1 # 3.3V output from the BSPT # HI --> Disables the # Translator Outputs NET 'BF_REQ_CTP_2_INPUT' U351-T11 # 2.5V input only to the BSPT # Hi --> BF Requests this CTP # Connector to be an Input NET 'TP_REQ_CTP_2_INPUT' U351-R14 # 2.5V input only to the BSPT # Hi --> BF Requests this CTP # Connector to be an Input NET 'CTP_2_TRNCVR_DIR' U351-N3 # 3.3V output from the BSPT # Hi --> LVDS Driver is Enabled NET 'CTP_2_BF_TRNSLT_DIR' U351-U5 # 2.5V output from the BSPT # Hi --> Translator direction # for CTP Connector Output NET 'BSPT_CTP_2_BF_TRNSLT_OE_B' U351-G5 # 3.3V output from the BSPT # HI --> Disables the # Translator Outputs NET 'CTP_2_TP_TRNSLT_DIR' U351-Y6 # 2.5V output from the BSPT # Hi --> Translator direction # for CTP Connector Output NET 'BSPT_CTP_2_TP_TRNSLT_OE_B' U351-G4 # 3.3V output from the BSPT # HI --> Disables the # Translator Outputs # BSPT Running OK Output Signal # --------------------------------- # # Besides just knowing that the BSPT FPGA is configured # we are also sending the Hardwired Overight Logic a signal # from the BSPT FPGA that tells this logic that from the # BSPT's point of view everything is OK and thus the # oversight logic is allowed to enable the bus type # operations. Note that this is a LOW active signal to # make it the opposite of the non-configured default pulled # high state of this ouput pin. The high state of this # pin is only 2.5V but it is going to a real TTL chip # that is guaranteed to see anything above 2.0V as a HI. NET 'BSPT_RUNNING_OK_B' U351-A3 # L30P-0 2.5V I/O Output # # Topological Processor FPGA Installed Jumper # ----------------------------------------------- # # This jumper JMP49 unambiguously indicates to the BSPT # whether or not the Topological Processor FPGA is installed # on this card. This signal, TP_FPGA_INSTALLED_B, has a # pull-up resistor to BULK_2V5 and jumper JMP49 to Ground. # # The TP_FPGA_INSTALLED_B signal is Low active. # Low means that the TP FPGA is installed. # # This jumper is to be installed only on cards that # have a Topological Processor FPGA installed on them. NET 'TP_FPGA_INSTALLED_B' U351-G8 # IP-0 2.5V In-Only # TP_FPGA_INSTALLED_B signal NET 'TP_FPGA_INSTALLED_B' JMP49-1 R327-1 # Control TP_FPGA_INSTALLED_B NET 'GROUND' JMP49-2 # Ground for the jumper NET 'BULK_2V5' R327-2 # BULK_2V5 for R327 pull-up # # Input for the ALLOW_BUSSED_IO signal # --------------------------------------- # # The BSPT receives the 3.3V ALLOW_BUSSED_IO so that it can # if the Hardwired Oversight Logic thinks that conditions # are OK for nornal card operation. NET 'ALLOW_BUSSED_IO' U351-G7 # Receive the ALLOW_BUSSED_IO # signal 3.3V Input-Only pin # # DeBug Signals - Spare Signals # ----------------------------------- # # Run 10 signals from the BSPT FPGA to Header J14. # These signals are are DeBug work or for emergency # connections between the FPGAs. These are 2.5V I/O pins. NET 'BSPT_DEBUG_0' U351-T17 # L03P-1 2.5V I/O DeBug Signal 0 NET 'BSPT_DEBUG_1' U351-P17 # L07N-1 2.5V I/O DeBug Signal 1 NET 'BSPT_DEBUG_2' U351-U17 # L31N-2 2.5V I/O DeBug Signal 2 NET 'BSPT_DEBUG_3' U351-R16 # L03N-1 2.5V I/O DeBug Signal 3 NET 'BSPT_DEBUG_4' U351-V16 # L29P-2 2.5V I/O DeBug Signal 4 NET 'BSPT_DEBUG_5' U351-P16 # L07P-1 2.5V I/O DeBug Signal 5 NET 'BSPT_DEBUG_6' U351-U16 # L29N-2 2.5V I/O DeBug Signal 6 NET 'BSPT_DEBUG_7' U351-R18 # L08P-1 2.5V I/O DeBug Signal 7 NET 'BSPT_DEBUG_8' U351-U15 # L27P-2 2.5V I/O DeBug Signal 8 NET 'BSPT_DEBUG_9' U351-R17 # L08N-1 2.5V I/O DeBug Signal 9 # # SFP Optical Component Reseived Signal Lost Monitor Signals # ---------------------------------------------------------------- # # These are monitor signals from the 4 SFP optical components. # They indicate voltage HI when the SFP receiver optical signal is lost. # # The need for these SFP Receiver Signal Lost signals was added # late in the CMX design when the review committee added the idea # of doing S-Link output from the CMX. # # Note that normally these would be 3.3V CMOS signal but we are # basically out of 3.3V I/O pins on the BSPT - so we are using only # 2.5V pull-ups on these SFP open-drain signals so they will appear # as 2.5V signals to the BSPT. # NET 'SFP1_RX_LOST' U351-Y2 # SFP1 Receiver Signal Lost BSPT Bank 2 2.5V I/O NET 'SFP2_RX_LOST' U351-Y3 # SFP2 Receiver Signal Lost BSPT Bank 2 2.5V I/O NET 'SFP3_RX_LOST' U351-W4 # SFP3 Receiver Signal Lost BSPT Bank 2 2.5V I/O NET 'SFP4_RX_LOST' U351-Y4 # SFP4 Receiver Signal Lost BSPT Bank 2 2.5V I/O # # Clock Signal to the Board Support FPGA # ---------------------------------------- # # Connect the 40.08 MHz DeSkew #1 LVDS Clock Signal # to the Board Support FPGA. This is the only clock # signal to the Board Support FPGA. NET 'CLK_40MHz08_DSKW_1_BSPT_LOGIC_DIR' U351-U11 # Clock 40.08 MHz NET 'CLK_40MHz08_DSKW_1_BSPT_LOGIC_CMP' U351-V12 # DeSkew #1 LHC Locked # # Spare connections: BF to/from BSPT and TP to/from BSPT # 8 each to/from BF and TP. All 2.5V signal. All I/O pins # on the BSPT FPGA. NET 'BF_TO_FROM_BSPT_0' U351-V19 # L02P-1 2.5V I/O NET 'BF_TO_FROM_BSPT_1' U351-U19 # L06P-1 2.5V I/O NET 'BF_TO_FROM_BSPT_2' U351-U20 # L06N-1 2.5V I/O NET 'BF_TO_FROM_BSPT_3' U351-T18 # L05P-1 2.5V I/O NET 'BF_TO_FROM_BSPT_4' U351-T20 # L05N-1 2.5V I/O NET 'BF_TO_FROM_BSPT_5' U351-R19 # L09P-1 2.5V I/O NET 'BF_TO_FROM_BSPT_6' U351-R20 # L09N-1 2.5V I/O NET 'BF_TO_FROM_BSPT_7' U351-P18 # L10P-1 2.5V I/O NET 'TP_TO_FROM_BSPT_0' U351-M20 # L17N-1 2.5V I/O NET 'TP_TO_FROM_BSPT_1' U351-M19 # L17P-1 2.5V I/O NET 'TP_TO_FROM_BSPT_2' U351-M18 # L14N-1 2.5V I/O NET 'TP_TO_FROM_BSPT_3' U351-M17 # L14P-1 2.5V I/O NET 'TP_TO_FROM_BSPT_4' U351-L19 # L18P-1 2.5V I/O NET 'TP_TO_FROM_BSPT_5' U351-L18 # L18N-1 2.5V I/O NET 'TP_TO_FROM_BSPT_6' U351-L17 # L20N-1 2.5V I/O NET 'TP_TO_FROM_BSPT_7' U351-L16 # L16N-1 2.5V I/O # # Inputs for the 5-bit CMX Card Serial Number # ---------------------------------------------- # # Jumpers JMP101:JMP105 set the 5-bit CMX Card Serial Number. # These 5 jumper run from from BSPT Input-Only pins to ground. # # There are no pull-up resistors on these lines - thus the # pull-ups internal to the BSPT for these pins must be # turned on. From the Spartan 3A data sheet these internal # pull-ups should be in the range of 5.1 to 33.1 k Ohm. NET 'CMX_SERIAL_NUM_1' JMP101-1 U351-G13 # Bit 1 of the CMX Card Seril Number NET 'CMX_SERIAL_NUM_2' JMP102-1 U351-G12 # Bit 2 of the CMX Card Seril Number NET 'CMX_SERIAL_NUM_3' JMP103-1 U351-G11 # Bit 3 of the CMX Card Seril Number NET 'CMX_SERIAL_NUM_4' JMP104-1 U351-G10 # Bit 4 of the CMX Card Seril Number NET 'CMX_SERIAL_NUM_5' JMP105-1 U351-G9 # Bit 5 of the CMX Card Seril Number NET 'GROUND' JMP101-2 JMP102-2 # Ground the other NET 'GROUND' JMP103-2 JMP104-2 # side of the NET 'GROUND' JMP105-2 # jumper # # No_Conn and SPR_Conn pins on the BSPT FPGA # ------------------------------------------------ # # The following list assigns a unique net-name to each of # the unused pins on the BSPT FPGA. In theory the BGA layout # vias for all of these pins may be removed. In theory these # pins do not need to appear in the UCF pin constraints. # # Note that a few of these pin have been routed out to not # installed "SR" components so that we can attach white wires # to them if necessary. These pins have net names of the # type SPR_Conn_BSPT_Pin i.e. a spare connection. NET 'SPR_Conn_BSPT_Pin_A2' U351-A2 SR37-1 # Spare Conn BSPT Pin A2 Bank 0 2.5V I/O NET 'No_Conn_BSPT_Pin_B3' U351-B3 # No Connect BSPT Pin B3 Bank 0 2.5V I/O NET 'No_Conn_BSPT_Pin_B17' U351-B17 # No Connect BSPT Pin B17 Bank 0 2.5V I/O NET 'No_Conn_BSPT_Pin_H9' U351-H9 # No Connect BSPT Pin H9 Bank 0 2.5V In-Only NET 'No_Conn_BSPT_Pin_H10' U351-H10 # No Connect BSPT Pin H10 Bank 0 2.5V In-Only NET 'No_Conn_BSPT_Pin_F11' U351-F11 # No Connect BSPT Pin F11 Bank 0 2.5V In-Only NET 'No_Conn_BSPT_Pin_H11' U351-H11 # No Connect BSPT Pin H11 Bank 0 2.5V In-Only NET 'No_Conn_BSPT_Pin_H12' U351-H12 # No Connect BSPT Pin H12 Bank 0 2.5V In-Only NET 'No_Conn_BSPT_Pin_E14' U351-E14 # No Connect BSPT Pin E14 Bank 0 2.5V In-Only NET 'No_Conn_BSPT_Pin_F14' U351-F14 # No Connect BSPT Pin F14 Bank 0 2.5V In-Only NET 'No_Conn_BSPT_Pin_U18' U351-U18 # No Connect BSPT Pin U18 Bank 1 2.5V I/O NET 'No_Conn_BSPT_Pin_V6' U351-V6 # No Connect BSPT Pin V6 Bank 2 2.5V I/O NET 'No_Conn_BSPT_Pin_V8' U351-V8 # No Connect BSPT Pin V8 Bank 2 2.5V I/O NET 'No_Conn_BSPT_Pin_R8' U351-R8 # No Connect BSPT Pin R8 Bank 2 2.5V In-Only NET 'SPR_Conn_BSPT_Pin_B1' U351-B1 SR33-1 # Spare Conn BSPT Pin B1 Bank 3 3.3V I/O NET 'SPR_Conn_BSPT_Pin_J8' U351-J8 SR32-1 # Spare Conn BSPT Pin J8 Bank 3 3.3V In-Only NET 'SPR_Conn_BSPT_Pin_K8' U351-K8 SR31-1 # Spare Conn BSPT Pin K8 Bank 3 3.3V In-Only NET 'SPR_Conn_BSPT_Pin_M6' U351-M6 SR36-2 # Spare Conn BSPT Pin M6 Bank 3 3.3V In-Only NET 'SPR_Conn_BSPT_Pin_M7' U351-M7 SR35-2 # Spare Conn BSPT Pin M7 Bank 3 3.3V In-Only NET 'SPR_Conn_BSPT_Pin_M8' U351-M8 SR34-2 # Spare Conn BSPT Pin M8 Bank 3 3.3V In-Only # # CMX-0 Nets File # # Hardwired Oversight Logic # ----------------------------- # # # Original Rev. 26-Feb-2013 # Most Recent Rev. 24-Sept-2013 # # # # This file holds all of the nets that are part of the # Hirdwired Oversight Logig. The main function of # this hardwired logic are to prevent the CMX card from # doing certain things before all of its power supplies # are up and running and before its Board Support FPGA # has had a chance to configure so that its logic can # start to manage some of the CMX card's functions. # # - The Hardwired oversight logic required the following # 4 signals to be in the proper state before it will # allow certain functions to take place on the CMX card: # # BOARD_POWER_OK must be asserted HI # BSPT_CONFIG_DONE must be asserted HI # BSPT_RUNNING_OK_B must be asserted LOW # CMX_SAFE_JUMPER_B must be asserted LOW # # Only when all 4 of these signals are in the proper # state does the hardwired oversight logic assert its # ALLOW_BUSSED_IO signal. The ALLOW_BUSSED_IO signal must # be asserted HI for the following types of functions # to be allowed on the CMX. # # - The hardired oversight logic prevents the CMX card from # "hanging" the VME crate bus by blocking the CMX card's # DTACK_B signal from being asserted and by blocking the # CMX card's data bus transceivers from placing data on # the VME data lines. The ALLOW_BUSSED_IO signal must be # asserted for DTACK_B and VME Data Transceivers to be # enabled. # # - The ALLOW_BUSSED_IO signal must be asserted for the # output buffers on the Translators for the Backplane # LVDS signals to be enabled # # - The ALLOW_BUSSED_IO signal must be asserted for the # output buffers on the Translators for the front panel # CTP signals to be enabled. # # - The ALLOW_BUSSED_IO signal must be asserted for the # output buffers on the Translators for the TTCDec # signals to be asserted. # # # # NOTE: As of the 6-May-2013 version of this file we will # use a private driver chip, U358, for the backplane # DTACK_B signal. The Hardwired Oversight Logic # functions that had been on U358 have now been # moved to U366. We will have one spare section in # U366, (which could be used for clean on-board # logic signals) and we have 3 spare sections in # the U358 DTACK_B driver which may be dirty # because it drives the high current backplane # trace. # # 10-Sept-2013 Add "tie downs" for the unused # input pins on the Hardwired Oversight Logic # chips. U358, U365, and U366 have unused input # pins. These connections are at the very end # of this net list file. The unused input pins # are tied to ground where possible and tied # to BULK_3V3 where no easy route to ground was # available. # # 24-Sept-2013 switch to using 2 sections of U358 # to drive the VME DTACK_B signal. Use the original # 4,5,6 section and add in parallel to it the # 1,2,3 section. # # # # First we include the nets for the CMX_SAFE_JUMPER_B signal # and the nets for the logic that makes up the ALLOW_BUSSED_IO # signal. NET 'CMX_SAFE_JUMPER_B' JMP59-1 R328-1 # CMX_SAFE_JUMPER_B signal NET 'GROUND' JMP59-2 # Ground for the jumper NET 'BULK_3V3' R328-2 # BULK_3V3 for R328 pull-up # Now show all of the input signal that are # used to make the ALLOW_BUSSED_IO Signal # Note that there is a pull-up resistor R395 # on the BSPT_RUNNING_OK_B signal. NET 'CMX_SAFE_JUMPER_B' U364-4 U364-5 # CMX_SAFE_JUMPER_B Input NET 'BSPT_RUNNING_OK_B' U364-2 R395-2 # BSPT_RUNNING_OK_B Input NET 'BSPT_RUNNING_OK_B' U364-1 # BSPT_RUNNING_OK_B Input NET 'BOARD_POWER_OK' U364-12 # NAND input NET 'BSPT_CONFIG_DONE' U364-13 # NAND input NET 'BPOK_NAND_BSPTCD' U364-9 U364-10 U364-11 # NET 'BPOK_NAND_BSPTCD' R382-1 # Pull-Up on BPOK_NAND_BSPTCD NET 'BULK_3V3' R382-2 R395-1 # BULK_3V3 for R382 and # R395 pull-up resistors # # Make the ALLOW_BUSSED_IO Signal # NET 'ALLOW_BUSSED_IO' U364-3 # Allow from BSPT_RUNNING_OK_B NET 'ALLOW_BUSSED_IO' U364-6 # Allow from CMX_SAFE_JUMPER_B NET 'ALLOW_BUSSED_IO' U364-8 # Allow from BOARD_POWER_OK # and BSPT_CONFIG_DONE NET 'ALLOW_BUSSED_IO' R381-1 # ALLOW_BUSSED_IO Pull-Up NET 'BULK_3V3' R381-2 # 3.3 VOLT to the Pull-Up # # Distribute the ALLOW_BUSSED_IO Signal to all Enable Gates NET 'ALLOW_BUSSED_IO' U358-1 # Allow to NET 'ALLOW_BUSSED_IO' U358-4 # Allow to NET 'ALLOW_BUSSED_IO' U361-1 # Allow to NET 'ALLOW_BUSSED_IO' U361-4 # Allow to NET 'ALLOW_BUSSED_IO' U361-10 # Allow to NET 'ALLOW_BUSSED_IO' U361-13 # Allow to NET 'ALLOW_BUSSED_IO' U363-1 # Allow to NET 'ALLOW_BUSSED_IO' U363-4 # Allow to NET 'ALLOW_BUSSED_IO' U363-10 # Allow to NET 'ALLOW_BUSSED_IO' U363-13 # Allow to NET 'ALLOW_BUSSED_IO' U366-1 # Allow to NET 'ALLOW_BUSSED_IO' U366-10 # Allow to NET 'ALLOW_BUSSED_IO' U366-13 # Allow to # # Oversight of the CTP Translator OE_B Control Signals # NET 'BSPT_CTP_1_BF_TRNSLT_OE_B' U360-1 NET 'INV_CTP_1_BF_TRNSLT_OE_B' U360-2 U361-2 NET 'CTP_1_BF_TRNSLT_OE_B' U361-3 NET 'CTP_1_BF_TRNSLT_OE_B' R386-1 # NET 'BULK_2V5' R386-2 # 2.5 V to the Pull-Up NET 'BSPT_CTP_2_BF_TRNSLT_OE_B' U360-3 NET 'INV_CTP_2_BF_TRNSLT_OE_B' U360-4 U361-5 NET 'CTP_2_BF_TRNSLT_OE_B' U361-6 NET 'CTP_2_BF_TRNSLT_OE_B' R387-1 # NET 'BULK_2V5' R387-2 # 2.5 V to the Pull-Up NET 'BSPT_CTP_1_TP_TRNSLT_OE_B' U360-5 NET 'INV_CTP_1_TP_TRNSLT_OE_B' U360-6 U361-9 NET 'CTP_1_TP_TRNSLT_OE_B' U361-8 NET 'CTP_1_TP_TRNSLT_OE_B' R388-1 # NET 'BULK_2V5' R388-2 # 2.5 V to the Pull-Up NET 'BSPT_CTP_2_TP_TRNSLT_OE_B' U360-13 NET 'INV_CTP_2_TP_TRNSLT_OE_B' U360-12 U361-12 NET 'CTP_2_TP_TRNSLT_OE_B' U361-11 NET 'CTP_2_TP_TRNSLT_OE_B' R389-1 # NET 'BULK_2V5' R389-2 # 2.5 V to the Pull-Up # # Oversight of the LVDS-Cable Translator OE_B Control Signals # NET 'BSPT_CABLE_1_TRNSLT_OE_B' U360-11 NET 'INV_CABLE_1_TRNSLT_OE_B' U360-10 U363-2 NET 'CABLE_1_TRNSLT_OE_B' U363-3 NET 'CABLE_1_TRNSLT_OE_B' R383-1 # NET 'BULK_2V5' R383-2 # 2.5 V to the Pull-Up NET 'BSPT_CABLE_2_TRNSLT_OE_B' U360-9 NET 'INV_CABLE_2_TRNSLT_OE_B' U360-8 U363-5 NET 'CABLE_2_TRNSLT_OE_B' U363-6 NET 'CABLE_2_TRNSLT_OE_B' R384-1 # NET 'BULK_2V5' R384-2 # 2.5 V to the Pull-Up NET 'BSPT_CABLE_3_TRNSLT_OE_B' U362-1 NET 'INV_CABLE_3_TRNSLT_OE_B' U362-2 U363-12 NET 'CABLE_3_TRNSLT_OE_B' U363-11 NET 'CABLE_3_TRNSLT_OE_B' R385-1 # NET 'BULK_2V5' R385-2 # 2.5 V to the Pull-Up # # Oversight of the VME DTACK_B signal from the CMX card # NET 'BSPT_SEND_VME_DTACK_B' U362-9 NET 'INV_SEND_VME_DTACK_B' U362-8 U358-5 U358-2 # The connections from U358-1 and U358-6 i.e. the driver # output pins to the backplane connector DTACK_B pin is # shown in the nets file: vme_bus_interface_chips_n2p.txt # # Oversight of the TTCDec Translator OE_B Control Signals # NET 'BSPT_TTC_TRNSLT_OE_B' U362-3 NET 'INV_TTC_TRNSLT_OE_B' U362-4 U363-9 NET 'TTC_TRNSLT_OE_B' U363-8 NET 'TTC_TRNSLT_OE_B' R392-1 # NET 'BULK_2V5' R392-2 # 2.5 V to the Pull-Up NET 'BSPT_TTC_RESET_TRNSLT_OE_B' U362-11 NET 'INV_TTC_RESET_TRNSLT_OE_B' U362-10 U366-2 NET 'TTC_RESET_TRNSLT_OE_B' U366-3 NET 'TTC_RESET_TRNSLT_OE_B' R393-1 # NET 'BULK_2V5' R393-2 # 2.5 V to the Pull-Up # # Oversight of the VME-OCB Bus Interface Management Signals # NET 'BSPT_VME_D_BUS_TRNCVR_OE_B' U362-5 NET 'INV_VME_D_BUS_TRNCVR_OE_B' U362-6 U366-9 NET 'VME_D_BUS_TRNCVR_OE_B' U366-8 NET 'VME_D_BUS_TRNCVR_OE_B' R390-1 # NET 'BULK_3V3' R390-2 # 3.3 V to the Pull-Up NET 'BSPT_OCB_ADRS_AND_CTRL_TRNSLT_OE_B' U362-13 NET 'INV_OCB_ADRS_AND_CTRL_TRNSLT_OE_B' U362-12 U366-12 NET 'OCB_ADRS_AND_CTRL_TRNSLT_OE_B' U366-11 NET 'OCB_ADRS_AND_CTRL_TRNSLT_OE_B' R391-1 # NET 'BULK_2V5' R391-2 # 2.5 V to the Pull-Up # # Now include the Power and Ground connections to # the 6 chips that are in the Hardwired Oversight Logic # section of the CMX card. This includes U358 which # is the DTACK_B driver and thus is part of the VME # Interface section. And now add the U366 chip. # # Power and Ground for U358 and U360:U364 and U366 NET 'BULK_3V3' U358-14 U360-14 U361-14 # 5.0V power NET 'GROUND' U358-7 U360-7 U361-7 # Ground NET 'BULK_3V3' U362-14 U363-14 U364-14 # 5.0V power NET 'GROUND' U362-7 U363-7 U364-7 # Ground NET 'BULK_3V3' U366-14 # 5.0V power NET 'GROUND' U366-7 # Ground # ByPass Capacitors for U358 and U360:U364 and for U366 NET 'BULK_3V3' C425-1 C426-1 # ByPass Cap 5.0V power NET 'BULK_3V3' C427-2 C428-2 # ByPass Cap 5.0V power NET 'GROUND' C425-2 C426-2 # ByPass Cap Ground connections NET 'GROUND' C427-1 C428-1 # ByPass Cap Ground connections NET 'BULK_3V3' C451-1 C452-1 # ByPass Cap 5.0V power NET 'BULK_3V3' C453-2 C454-2 # ByPass Cap 5.0V power NET 'GROUND' C451-2 C452-2 # ByPass Cap Ground connections NET 'GROUND' C453-1 C454-1 # ByPass Cap Ground connections NET 'BULK_3V3' C455-1 C456-1 # ByPass Cap 5.0V power NET 'BULK_3V3' C457-2 C458-2 # ByPass Cap 5.0V power NET 'GROUND' C455-2 C456-2 # ByPass Cap Ground connections NET 'GROUND' C457-1 C458-1 # ByPass Cap Ground connections NET 'BULK_3V3' C461-1 C462-2 # ByPass Cap 5.0V power NET 'GROUND' C461-2 C462-1 # ByPass Cap Ground connections # # Tie-Downs of UnUsed Input Pins on U358, U365, and U366 # --------------------------------------------------------- NET 'GROUND' U358-10 U358-9 # Tie-Down U358 Unused Input Pins NET 'GROUND' U358-13 U358-12 # Tie-Down U358 Unused Input Pins NET 'GROUND' U365-13 # Tie-Down U365 Unused Input Pins NET 'GROUND' U366-4 U366-5 # Tie-Down U366 Unused Input Pins # # CMX-0 Nets File # # Hardwired Oversight Logic # ----------------------------- # # # Original Rev. 27-Feb-2013 # Rev. 5-Apr-2013 # Most Recent Rev. 10-Jul-2013 Swap the relative position of BF and TP pins # # # # This file holds all of the nets that connect to the J14 # DeBug Connector. This connector provides 10 signals # to or from each of the 3 FPGAs as well as a number of # Ground connections. The intent of this connector is # to allow external view of signals on a scope of logic # analyzer using the J14 ground pins as reference or # in an "emergency" to allow additional signal connections # between FPGAs. # # All signals on this connector are 2.5V CMOS levels. # All pins can be either inputs or outputs to their FPGA. # # This DeBug, Emergency Connection header is also often # called an Access Connector. # # J14 is a 40 pin SMD header 2mm metric. It's pinout # is setup as follows: The intent is to distribute the # Ground pins. # # # Odd Numbered Pins Even Numbered Pins # --------------------- ---------------------- # # 1 GROUND 2 GROUND # 3 BSPT_DEBUG_0 4 BSPT_DEBUG_1 # 5 BSPT_DEBUG_2 6 BSPT_DEBUG_3 # 7 BSPT_DEBUG_4 8 BSPT_DEBUG_5 # 9 BSPT_DEBUG_6 10 BSPT_DEBUG_7 # 11 GROUND 12 GROUND # 13 BSPT_DEBUG_8 14 BSPT_DEBUG_9 # 15 TP_DEBUG_0 16 TP_DEBUG_1 # 17 TP_DEBUG_2 18 TP_DEBUG_3 # 19 TP_DEBUG_4 20 TP_DEBUG_5 # 21 GROUND 22 GROUND # 23 TP_DEBUG_6 24 TP_DEBUG_7 # 25 TP_DEBUG_8 26 TP_DEBUG_9 # 27 BF_DEBUG_0 28 BF_DEBUG_1 # 29 BF_DEBUG_2 30 BF_DEBUG_3 # 31 GROUND 32 GROUND # 33 BF_DEBUG_4 34 BF_DEBUG_5 # 35 BF_DEBUG_6 36 BF_DEBUG_7 # 37 BF_DEBUG_8 38 BF_DEBUG_9 # 39 GROUND 40 GROUND # # These signals will travel on layer 6 NET 'GROUND' J14-1 # Ground Pin NET 'GROUND' J14-2 # Ground Pin NET 'BSPT_DEBUG_0' J14-3 #> T06 # 2.5V I/O BSPT DeBug Signal 0 NET 'BSPT_DEBUG_1' J14-4 #> T06 # 2.5V I/O BSPT DeBug Signal 1 NET 'BSPT_DEBUG_2' J14-5 #> T06 # 2.5V I/O BSPT DeBug Signal 2 NET 'BSPT_DEBUG_3' J14-6 #> T06 # 2.5V I/O BSPT DeBug Signal 3 NET 'BSPT_DEBUG_4' J14-7 #> T06 # 2.5V I/O BSPT DeBug Signal 4 NET 'BSPT_DEBUG_5' J14-8 #> T06 # 2.5V I/O BSPT DeBug Signal 5 NET 'BSPT_DEBUG_6' J14-9 #> T06 # 2.5V I/O BSPT DeBug Signal 6 NET 'BSPT_DEBUG_7' J14-10 #> T06 # 2.5V I/O BSPT DeBug Signal 7 NET 'GROUND' J14-11 # Ground Pin NET 'GROUND' J14-12 # Ground Pin NET 'BSPT_DEBUG_8' J14-13 #> T06 # 2.5V I/O BSPT DeBug Signal 8 NET 'BSPT_DEBUG_9' J14-14 #> T06 # 2.5V I/O BSPT DeBug Signal 9 NET 'TP_DEBUG_0' J14-15 #> T06 # 2.5V I/O TP DeBug Signal 0 NET 'TP_DEBUG_1' J14-16 #> T06 # 2.5V I/O TP DeBug Signal 1 NET 'TP_DEBUG_2' J14-17 #> T06 # 2.5V I/O TP DeBug Signal 2 NET 'TP_DEBUG_3' J14-18 #> T06 # 2.5V I/O TP DeBug Signal 3 NET 'TP_DEBUG_4' J14-19 #> T06 # 2.5V I/O TP DeBug Signal 4 NET 'TP_DEBUG_5' J14-20 #> T06 # 2.5V I/O TP DeBug Signal 5 NET 'GROUND' J14-21 # Ground Pin NET 'GROUND' J14-22 # Ground Pin NET 'TP_DEBUG_6' J14-23 #> T06 # 2.5V I/O TP DeBug Signal 6 NET 'TP_DEBUG_7' J14-24 #> T06 # 2.5V I/O TP DeBug Signal 7 NET 'TP_DEBUG_8' J14-25 #> T06 # 2.5V I/O TP DeBug Signal 8 NET 'TP_DEBUG_9' J14-26 #> T06 # 2.5V I/O TP DeBug Signal 9 NET 'BF_DEBUG_0' J14-27 #> T06 # 2.5V I/O BF DeBug Signal 0 NET 'BF_DEBUG_1' J14-28 #> T06 # 2.5V I/O BF DeBug Signal 1 NET 'BF_DEBUG_2' J14-29 #> T06 # 2.5V I/O BF DeBug Signal 2 NET 'BF_DEBUG_3' J14-30 #> T06 # 2.5V I/O BF DeBug Signal 3 NET 'GROUND' J14-31 # Ground Pin NET 'GROUND' J14-32 # Ground Pin NET 'BF_DEBUG_4' J14-33 #> T06 # 2.5V I/O BF DeBug Signal 4 NET 'BF_DEBUG_5' J14-34 #> T06 # 2.5V I/O BF DeBug Signal 5 NET 'BF_DEBUG_6' J14-35 #> T06 # 2.5V I/O BF DeBug Signal 6 NET 'BF_DEBUG_7' J14-36 #> T06 # 2.5V I/O BF DeBug Signal 7 NET 'BF_DEBUG_8' J14-37 #> T06 # 2.5V I/O BF DeBug Signal 8 NET 'BF_DEBUG_9' J14-38 #> T06 # 2.5V I/O BF DeBug Signal 9 NET 'GROUND' J14-39 # Ground Pin NET 'GROUND' J14-40 # Ground Pin # # CMX-0 Nets File # # ESD Strip and Front-Panel Ground Nets # ----------------------------------------- # # # Original Rev. 9-July-2013 # Most Recent Rev. 9-July-2013 # # # # This file holds the nets for ground connections to the # ESD Strips and to the Front Panel and board stiffener # mechanics. # # # # Components referenced in this file include: # # ESD_1 and ESD_2 the ESD Strips one pin components # # R631, R632 0805 resistors in series with the ESD Strips # to break the ground loops. # # # ESD Strip Grounds: # -------------------- NET 'ESD_TOP_STRIP' ESD_2-1 R632-2 # Top ESD Strip ground NET 'ESD_BOT_STRIP' ESD_1-1 R631-2 # Bottom ESD Strip ground NET 'GROUND' R631-1 R632-1 # Ground ESD Strip Series Resistors # # CMX-0 Nets File # # # Power Supply Monitoring Nets # ----------------==========-------- # # # Original Rev. 21-Dec-2012 # Rev. 22-Jul-2013 Re-order allocation of BF SysMon resources # Rev. 2-Aug-2013 Drop the BULK_5V0_N bus. Monitor BULK_5V0. # Most Recent Rev. 5-Aug-2013 Added C1942:C1964 filters on the Virtex System Monitor Inputs # # # # This file contains the nets for the power supply # Monitoring. This includes: # # - The nets that feed analog monitoring signals # to the Base Function FPGA System Monitor circuits. # # - The nets that feed analog monitoring signals # to the J13 voltage current monitoring connector. # # - The nets that feed analog monitoring signals # to the CAN-Bus based monitoring circuits are # in the file can_bus_monitoring_nets. # # # # Manual Monitor Points Connector J13 # # Now include the nets for the Manual Monitor Connector J13. # This connector lets one plug in and see the 9 Voltages and # 7 Currents on the card. Each output pin on this connector # is protected with a 100 Ohm series resistor. # Ground the even number pins in J13. NET 'GROUND' J13-2 J13-4 J13-6 J13-8 J13-10 NET 'GROUND' J13-12 J13-14 J13-16 J13-18 J13-20 NET 'GROUND' J13-22 J13-24 J13-26 J13-28 J13-30 NET 'GROUND' J13-32 J13-34 J13-36 J13-38 J13-40 # BSPT_CORE Monitor Points NET 'BSPT_CORE' R1901-2 # Sample BSPT_CORE Voltage NET 'MON_BSPT_CORE_V' R1901-1 J13-1 # 100 Ohm series to Volt Monitor pin NET 'MON_BSPT_CORE_V' C1871-1 # Filter Cap on the Volt Monitor pin NET 'GROUND' C1871-2 # Ground the Filter Capacitor. NET 'BSPT_CORE_CS_AMP_OUT' R1807-1 # Current Sense Amp I-to-V Resistor NET 'GROUND' R1807-2 # Ground the I-to-V Resistor NET 'BSPT_CORE_CS_AMP_OUT' R1902-2 # Current Sense Amp Series Resistor NET 'MON_BSPT_CORE_I' R1902-1 J13-3 # 100 Ohm series to Amp Monitor pin NET 'MON_BSPT_CORE_I' C1872-1 # Filter Cap on the Amp Monitor pin NET 'GROUND' C1872-2 # Ground the Filter Capacitor. # BF_CORE Monitor Points NET 'BF_CORE' R1903-2 # Sample BF_CORE Voltage NET 'MON_BF_CORE_V' R1903-1 J13-5 # 100 Ohm series to Volt Monitor pin NET 'MON_BF_CORE_V' C1873-1 # Filter Cap on the Volt Monitor pin NET 'GROUND' C1873-2 # Ground the Filter Capacitor. NET 'BF_CORE_CS_AMP_OUT' R1757-1 # Current Sense Amp I-to-V Resistor NET 'GROUND' R1757-2 # Ground the I-to-V Resistor NET 'BF_CORE_CS_AMP_OUT' R1904-2 # Current Sense Amp Series Resistor NET 'MON_BF_CORE_I' R1904-1 J13-7 # 100 Ohm series to Amp Monitor pin NET 'MON_BF_CORE_I' C1874-1 # Filter Cap on the Amp Monitor pin NET 'GROUND' C1874-2 # Ground the Filter Capacitor. # GTX_AVTT Monitor Points NET 'GTX_AVTT' R1905-2 # Sample GTX_AVTT Voltage NET 'MON_GTX_AVTT_V' R1905-1 J13-9 # 100 Ohm series to Volt Monitor pin NET 'MON_GTX_AVTT_V' C1875-1 # Filter Cap on the Volt Monitor pin NET 'GROUND' C1875-2 # Ground the Filter Capacitor. NET 'GTX_AVTT_CS_AMP_OUT' R1707-1 # Current Sense Amp I-to-V Resistor NET 'GROUND' R1707-2 # Ground the I-to-V Resistor NET 'GTX_AVTT_CS_AMP_OUT' R1906-2 # Current Sense Amp Series Resistor NET 'MON_GTX_AVTT_I' R1906-1 J13-11 # 100 Ohm series to Amp Monitor pin NET 'MON_GTX_AVTT_I' C1876-1 # Filter Cap on the Amp Monitor pin NET 'GROUND' C1876-2 # Ground the Filter Capacitor. # GTX_AVCC Monitor Points NET 'GTX_AVCC' R1907-2 # Sample GTX_AVCC Voltage NET 'MON_GTX_AVCC_V' R1907-1 J13-13 # 100 Ohm series to Volt Monitor pin NET 'MON_GTX_AVCC_V' C1877-1 # Filter Cap on the Volt Monitor pin NET 'GROUND' C1877-2 # Ground the Filter Capacitor. NET 'GTX_AVCC_CS_AMP_OUT' R1657-1 # Current Sense Amp I-to-V Resistor NET 'GROUND' R1657-2 # Ground the I-to-V Resistor NET 'GTX_AVCC_CS_AMP_OUT' R1908-2 # Current Sense Amp Series Resistor NET 'MON_GTX_AVCC_I' R1908-1 J13-15 # 100 Ohm series to Amp Monitor pin NET 'MON_GTX_AVCC_I' C1878-1 # Filter Cap on the Amp Monitor pin NET 'GROUND' C1878-2 # Ground the Filter Capacitor. # TP_CORE Monitor Points NET 'TP_CORE' R1909-2 # Sample TP_CORE Voltage NET 'MON_TP_CORE_V' R1909-1 J13-17 # 100 Ohm series to Volt Monitor pin NET 'MON_TP_CORE_V' C1879-1 # Filter Cap on the Volt Monitor pin NET 'GROUND' C1879-2 # Ground the Filter Capacitor. NET 'TP_CORE_CS_AMP_OUT' R1607-1 # Current Sense Amp I-to-V Resistor NET 'GROUND' R1607-2 # Ground the I-to-V Resistor NET 'TP_CORE_CS_AMP_OUT' R1910-2 # Current Sense Amp Series Resistor NET 'MON_TP_CORE_I' R1910-1 J13-19 # 100 Ohm series to Amp Monitor pin NET 'MON_TP_CORE_I' C1880-1 # Filter Cap on the Amp Monitor pin NET 'GROUND' C1880-2 # Ground the Filter Capacitor. # BULK_3V3 Monitor Points NET 'BULK_3V3' R1911-2 # Sample BULK_3V3 Voltage NET 'MON_BULK_3V3_V' R1911-1 J13-21 # 100 Ohm series to Volt Monitor pin NET 'MON_BULK_3V3_V' C1881-1 # Filter Cap on the Volt Monitor pin NET 'GROUND' C1881-2 # Ground the Filter Capacitor. NET 'BULK_3V3_CS_AMP_OUT' R1557-1 # Current Sense Amp I-to-V Resistor NET 'GROUND' R1557-2 # Ground the I-to-V Resistor NET 'BULK_3V3_CS_AMP_OUT' R1912-2 # Current Sense Amp Series Resistor NET 'MON_BULK_3V3_I' R1912-1 J13-23 # 100 Ohm series to Amp Monitor pin NET 'MON_BULK_3V3_I' C1882-1 # Filter Cap on the Amp Monitor pin NET 'GROUND' C1882-2 # Ground the Filter Capacitor. # BULK_2V5 Monitor Points NET 'BULK_2V5' R1913-2 # Sample BULK_2V5 Voltage NET 'MON_BULK_2V5_V' R1913-1 J13-25 # 100 Ohm series to Volt Monitor pin NET 'MON_BULK_2V5_V' C1883-1 # Filter Cap on the Volt Monitor pin NET 'GROUND' C1883-2 # Ground the Filter Capacitor. NET 'BULK_2V5_CS_AMP_OUT' R1507-1 # Current Sense Amp I-to-V Resistor NET 'GROUND' R1507-2 # Ground the I-to-V Resistor NET 'BULK_2V5_CS_AMP_OUT' R1914-2 # Current Sense Amp Series Resistor NET 'MON_BULK_2V5_I' R1914-1 J13-27 # 100 Ohm series to Amp Monitor pin NET 'MON_BULK_2V5_I' C1884-1 # Filter Cap on the Amp Monitor pin NET 'GROUND' C1884-2 # Ground the Filter Capacitor. # BULK_5V0 Monitor Point NET 'BULK_5V0' R1915-2 # Sample BULK_5V0 Voltage NET 'MON_BULK_5V0_V' R1915-1 J13-29 # 100 Ohm series to Volt Monitor pin NET 'MON_BULK_5V0_V' C1885-1 # Filter Cap on the Volt Monitor pin NET 'GROUND' C1885-2 # Ground the Filter Capacitor. # VREF_P Monitor Point NET 'VREF_P' R1916-2 # Sample VREF_P Voltage NET 'MON_VREF_P_V' R1916-1 J13-31 # 100 Ohm series to Volt Monitor pin NET 'MON_VREF_P_V' C1886-1 # Filter Cap on the Volt Monitor pin NET 'GROUND' C1886-2 # Ground the Filter Capacitor. # # Base Function System Monitor Auxiliary Analog Inputs # # Resistor Voltage Dividers are used to scale input # signals to the 0.0V to +1.0V range of the 12 # available Base-Function Auxiliary Analog Inputs # # We are using the 12 available Base-Function # System-Monitor Auxiliary Analog Inputs to # measure the following Voltages and Currents: # # The "AKA" Components are used to route the Ground # side of the differential analog pair to the # relivant Ground pin outside of the FPGAs footprint. # # The 12 available System Monitor Auxiliary Analog # inputs are: 01, 03, 04, 07, 08, 09, 10, 11, 12, # 13, 14, 15 and are used in order to monitor # the following: # # BF_CORE Voltage and Current # GTX_AVTT Voltage and Current # GTX_AVCC Voltage and Current # TP_CORE Current # BULK_3V3 Voltage and Current # BULK_2V5 Voltage and Current # VREF_P Voltage # # BF_CORE BF System-Monitor Points NET 'MON_BF_CORE_V' R1941-2 # Sample the MON_BF_CORE_V NET 'BF_SYSMON_04_P' R1941-1 R1942-2 C1942-2 # Scale to +1V F.S. NET 'GROUND' AKA1942-2 R1942-1 C1942-1 # Ground Voltage Divider NET 'BF_SYSMON_04_N' AKA1942-1 # Neg Diff Analog Input NET 'MON_BF_CORE_I' R1943-2 # Sample the MON_BF_CORE_I NET 'BF_SYSMON_03_P' R1943-1 R1944-2 C1944-2 # Scale to +1V F.S. NET 'GROUND' AKA1944-2 R1944-1 C1944-1 # Ground Voltage Divider NET 'BF_SYSMON_03_N' AKA1944-1 # Neg Diff Analog Input # GTX_AVTT BF System-Monitor Points NET 'MON_GTX_AVTT_V' R1945-2 # Sample the MON_GTX_AVTT_V NET 'BF_SYSMON_01_P' R1945-1 R1946-2 C1946-2 # Scale to +1V F.S. NET 'GROUND' AKA1946-2 R1946-1 C1946-1 # Ground Voltage Divider NET 'BF_SYSMON_01_N' AKA1946-1 # Neg Diff Analog Input NET 'MON_GTX_AVTT_I' R1947-2 # Sample the MON_GTX_AVTT_I NET 'BF_SYSMON_07_P' R1947-1 R1948-2 C1948-2 # Scale to +1V F.S. NET 'GROUND' AKA1948-2 R1948-1 C1948-1 # Ground Voltage Divider NET 'BF_SYSMON_07_N' AKA1948-1 # Neg Diff Analog Input # GTX_AVCC BF System-Monitor Points NET 'MON_GTX_AVCC_V' R1949-2 # Sample the MON_GTX_AVCC_V NET 'BF_SYSMON_11_P' R1949-1 R1950-2 C1950-2 # Scale to +1V F.S. NET 'GROUND' AKA1950-2 R1950-1 C1950-1 # Ground Voltage Divider NET 'BF_SYSMON_11_N' AKA1950-1 # Neg Diff Analog Input NET 'MON_GTX_AVCC_I' R1951-2 # Sample the MON_GTX_AVCC_I NET 'BF_SYSMON_08_P' R1951-1 R1952-2 C1952-2 # Scale to +1V F.S. NET 'GROUND' AKA1952-2 R1952-1 C1952-1 # Ground Voltage Divider NET 'BF_SYSMON_08_N' AKA1952-1 # Neg Diff Analog Input # TP_CORE BF System-Monitor Point NET 'MON_TP_CORE_I' R1953-2 # Sample the MON_TP_CORE_I NET 'BF_SYSMON_14_P' R1953-1 R1954-2 C1954-2 # Scale to +1V F.S. NET 'GROUND' AKA1954-2 R1954-1 C1954-1 # Ground Voltage Divider NET 'BF_SYSMON_14_N' AKA1954-1 # Neg Diff Analog Input # BULK_3V3 BF System-Monitor Points NET 'MON_BULK_3V3_V' R1955-2 # Sample the MON_BULK_3V3_V NET 'BF_SYSMON_12_P' R1955-1 R1956-2 C1956-2 # Scale to +1V F.S. NET 'GROUND' AKA1956-2 R1956-1 C1956-1 # Ground Voltage Divider NET 'BF_SYSMON_12_N' AKA1956-1 # Neg Diff Analog Input NET 'MON_BULK_3V3_I' R1957-2 # Sample the MON_BULK_3V3_I NET 'BF_SYSMON_10_P' R1957-1 R1958-2 C1958-2 # Scale to +1V F.S. NET 'GROUND' AKA1958-2 R1958-1 C1958-1 # Ground Voltage Divider NET 'BF_SYSMON_10_N' AKA1958-1 # Neg Diff Analog Input # BULK_2V5 BF System-Monitor Points NET 'MON_BULK_2V5_V' R1959-2 # Sample the MON_BULK_2V5_V NET 'BF_SYSMON_09_P' R1959-1 R1960-2 C1960-2 # Scale to +1V F.S. NET 'GROUND' AKA1960-2 R1960-1 C1960-1 # Ground Voltage Divider NET 'BF_SYSMON_09_N' AKA1960-1 # Neg Diff Analog Input NET 'MON_BULK_2V5_I' R1961-2 # Sample the MON_BULK_2V5_I NET 'BF_SYSMON_13_P' R1961-1 R1962-2 C1962-2 # Scale to +1V F.S. NET 'GROUND' AKA1962-2 R1962-1 C1962-1 # Ground Voltage Divider NET 'BF_SYSMON_13_N' AKA1962-1 # Neg Diff Analog Input # VREF_P BF System-Monitor Point NET 'MON_VREF_P_V' R1963-2 # Sample the MON_VREF_P_V NET 'BF_SYSMON_15_P' R1963-1 R1964-2 C1964-2 # Scale to +1V F.S. NET 'GROUND' AKA1964-2 R1964-1 C1964-1 # Ground Voltage Divider NET 'BF_SYSMON_15_N' AKA1964-1 # Neg Diff Analog Input # # CMX-0 Nets File # # Jumper Controlled "Ground" Connections # # to the CMX Ground Planes # ------------------------------------------- # # # Original Rev. 28-June-2013 # Current Rev. 24-Sept-2013 # # # # # This file holds the Net Statments for the # Jumper Controlled Ground Connections to the # CMX Ground Planes. # # # SFP Cages Slow Optical Transceivers # --------------------------------------- # # Each SFP Cage can individually be tied to the CMX # pcb ground planes through 2 0603 Zero Ohm Jumpers, # or left floating, or grounded with a series # resistor to break the ground loops. # # # Cage for SFP #1 NET 'SFP1_GND_A' SFP1-26 JMP91A-1 # Jumper A to Cage pin 26 NET 'SFP1_GND_B' SFP1-21 JMP91B-2 # Jumper A to Cage pin 26 NET 'GROUND' JMP91A-2 JMP91B-1 # Connection to Ground Plane # Cage for SFP #2 NET 'SFP2_GND_A' SFP2-26 JMP92A-1 # Jumper A to Cage pin 26 NET 'SFP2_GND_B' SFP2-21 JMP92B-2 # Jumper A to Cage pin 26 NET 'GROUND' JMP92A-2 JMP92B-1 # Connection to Ground Plane # Cage for SFP #3 NET 'SFP3_GND_A' SFP3-26 JMP93A-1 # Jumper A to Cage pin 26 NET 'SFP3_GND_B' SFP3-21 JMP93B-2 # Jumper A to Cage pin 26 NET 'GROUND' JMP93A-2 JMP93B-1 # Connection to Ground Plane # Cage for SFP #4 NET 'SFP4_GND_A' SFP4-26 JMP94A-1 # Jumper A to Cage pin 26 NET 'SFP4_GND_B' SFP4-21 JMP94B-2 # Jumper A to Cage pin 26 NET 'GROUND' JMP94A-2 JMP94B-1 # Connection to Ground Plane # For now I need to keep pins #34, #35, and #36 of each # SFP Cage connected to the GROUND net. This is bacause # currently cage pins 34, 35, and 36 are used as a # ground point for 2 pins in the SFP connector and as # the Ground Return for the Differential Via Pairs # that take 1 Gbps data into or out from the SFP # optical component. # # For now the current plan is to cut pins 34, 35, and 36 # off of the SFP Cage. These 3 pins are at the back of # the cage and they do not include the tab that controls # the height of the SFP Cage above the top of the pcb. # # The plan is to solder together the split at the back # of the stamped metal cage, cut off the 3 pins, file # the pin stubs down flat, exacto knife off any burs # of metal, air hose off the parts, and finally repack # them for shipment. NET 'GROUND' SFP1-34 SFP1-35 SFP1-36 # Ground SFP1 pins 34,35,36 NET 'GROUND' SFP2-34 SFP2-35 SFP2-36 # Ground SFP1 pins 34,35,36 NET 'GROUND' SFP3-34 SFP3-35 SFP3-36 # Ground SFP1 pins 34,35,36 NET 'GROUND' SFP4-34 SFP4-35 SFP4-36 # Ground SFP1 pins 34,35,36 # # CTP Connectors J10/J11 Pins 34/68 # ------------------------------------- # # Pins 34 and 68 of the CTP Connectors J10 and J11 # may be tied to the CMX Ground Plane through # Jumper JMP97 and JMP98. NET 'GND_J10_34_68' JMP97-1 # Jumper for J10 Pin 34/68 Ground NET 'GND_J11_34_68' JMP98-2 # Jumper for J11 Pin 34/68 Ground NET 'GROUND' JMP97-2 JMP98-1 # Connection to Ground Plane # # Grounds to the J10/J11 CTP Connector Bodies # ----------------------------------------------- # # # Jumpers JMP95A and JMP95B ground the bodies of # the J10 and J11 CTP Connectors. # # The bodies of J10 and J11 are tied to the Front Panel # and thus to the Stiffener Bars and to the Backplane # Guide Pin Receptacle. # NET 'GND_J10_BODY' J10-69 JMP95A-2 # Net to the body of J10 NET 'GND_J11_BODY' J11-69 JMP95B-2 # Net to the body of J11 NET 'GROUND' JMP95A-1 JMP95B-1 # Connection to Ground Plane # # Grounds to the 18 Backplane Pins # ------------------------------------------ # # # Jumpers JMP96A and JMP96B ground 18 pins # in the backplane connectors J4, J5, and J6. # NET 'REAR_CG_GND' JMP96A-1 JMP96B-1 # Net to the pins in Backplane # Connectors J4, J5, and J6. NET 'GROUND' JMP96A-2 JMP96B-2 # Connection to Ground Plane # # Grounds to the BF & TP Heat-Sinks # ------------------------------------- # # # Jumper resistors: R801 and R802 ground the BF Heat-Sink. # # Jumper resistors: R803 and R804 ground the TP Heat-Sink. # NET 'BF_HS_GND_1' HS1-1 R801-2 # Jumper-resistors to the NET 'BF_HS_GND_2' HS1-4 R802-2 # Base Function FPGA Heat-Sink NET 'GROUND' R801-1 R802-1 # Ground end of jumper-resistors NET 'TP_HS_GND_1' HS2-3 R803-2 # Jumper-resistors to the NET 'TP_HS_GND_2' HS2-4 R804-2 # Topological Processor FPGA Heat-Sink NET 'GROUND' R803-1 R804-1 # Ground end of jumper-resistors # # CMX-0 Nets File # # ByPass Capacitors Base Function VCCINT Core Supply # ------------------------------------------------------- # # # Original Rev. 15-Nov-2012 # Most Recent Rev. 3-Aug-2013 # # # # This file holds the nets for ALL of Base Function FPGA # BF_CORE supply bypass Capacitors. # ========= # # This net list file includes nets to the following components: # # C71:C78 220 nFd 0603 # C79:C86 4.7 uFd 0603 # C87:C92 33 uFd Tant B # C93:C96 330 uFd Tant D plus 6 more 330 uFd Tantalums # located at the DC/DC Converter # # # See the list of "Randomly Added Wherever They Will Fit" # BF_CORE bypass capacitors at the end of the organized list. # # # # 220 nFd Bypass Capacitors on the BF_CORE supply # NET 'BF_CORE' C71-1 C72-1 C73-1 C74-1 NET 'GROUND' C71-2 C72-2 C73-2 C74-2 NET 'BF_CORE' C75-1 C76-1 C77-1 C78-1 NET 'GROUND' C75-2 C76-2 C77-2 C78-2 # # 4.7 uFd Bypass Capacitors on the BF_CORE supply # NET 'BF_CORE' C79-1 C80-1 C81-1 C82-1 NET 'GROUND' C79-2 C80-2 C81-2 C82-2 NET 'BF_CORE' C83-1 C84-1 C85-1 C86-1 NET 'GROUND' C83-2 C84-2 C85-2 C86-2 # # 33 uFd Bypass Capacitors on the BF_CORE supply # NET 'BF_CORE' C87-1 C88-1 C89-1 NET 'GROUND' C87-2 C88-2 C89-2 NET 'BF_CORE' C90-1 C91-1 C92-1 NET 'GROUND' C90-2 C91-2 C92-2 # # 330 uFd Bypass Capacitors on the BF_CORE supply # NET 'BF_CORE' C93-1 C94-1 C95-1 C96-1 NET 'GROUND' C93-2 C94-2 C95-2 C96-2 # # Randomly Added Wherever They Will Fit # ------------------------------------- # # BF_CORE Bypass Capacitors # NET 'BF_CORE' C197-1 C198-1 NET 'GROUND' C197-2 C198-2 # # CMX-0 Nets File # # # Power Supply Hi/Low Supervisor Nets # ----------------======-------------------- # # # Original Rev. 21-Dec-2012 # Most Recent Rev. 2-Aug-2013 # # # # The CMX card uses two AD12914-2 IC to monitor the # output of the DCDC Converters. The converter outputs # are monitored for both Under Volt and for Over Volt # conditions. Once all 7 supplies have been stable # for about 1 second then the PRE_BOARD_POWER_OK signal # is asserted HI. If any supply then goes out of # tolerance for more than a few 10s of usec this will # force the PRE_BOARD_POWER_OK signal will be pulled # back Low for about one second. # # # Most Reference Designators for the Power Supply # Hi/Low Supervisor are in the range 1851:1899. # # The output from the two AD12914-2 Hi/Low # Supervisors goes to the nets listed in the file: # # power_supply_brd_pwr_ok_n2p.txt # # # # U1861 and u1862 AD12914-2 Voltage Monitors: # ----------------------------------------------- # U1861 Voltage Monitors # # Voltage Monitor U1861 Channel #1 BULK_2V5 NET 'BULK_2V5' R1861-2 # Top side of the Voltage Divider NET 'MON_BULK_2V5_UV' R1861-1 R1862-2 # HI Tap on BULK_2V5 Volt Divider NET 'MON_BULK_2V5_UV' U1861-1 # U1861 Ch #1 VH1 pin #1 NET 'MON_BULK_2V5_OV' R1862-1 R1863-2 # Low Tap on BULK_2V5 Volt Divider NET 'MON_BULK_2V5_OV' U1861-2 # U1861 Ch #1 VL1 pin #2 NET 'GROUND' R1863-1 # Low side of the Voltage Divider # # Voltage Monitor U1861 Channel #2 BULK_3V3 NET 'BULK_3V3' R1864-2 # Top side of the Voltage Divider NET 'MON_BULK_3V3_UV' R1864-1 R1865-2 # HI Tap on BULK_3V3 Volt Divider NET 'MON_BULK_3V3_UV' U1861-3 # U1861 Ch #2 VH2 pin #3 NET 'MON_BULK_3V3_OV' R1865-1 R1866-2 # Low Tap on BULK_3V3 Volt Divider NET 'MON_BULK_3V3_OV' U1861-4 # U1861 Ch #2 VL2 pin #4 NET 'GROUND' R1866-1 # Low side of the Voltage Divider # # Voltage Monitor U1861 Channel #3 TP_CORE NET 'TP_CORE' R1867-2 # Top side of the Voltage Divider NET 'MON_TP_CORE_UV' R1867-1 R1868-2 # HI Tap on TP_CORE Volt Divider NET 'MON_TP_CORE_UV' U1861-5 # U1861 Ch #3 VH3 pin #5 NET 'MON_TP_CORE_OV' R1868-1 R1869-2 # Low Tap on TP_CORE Volt Divider NET 'MON_TP_CORE_OV' U1861-6 # U1861 Ch #3 VL3 pin #6 NET 'GROUND' R1869-1 # Low side of the Voltage Divider # # Voltage Monitor U1861 Channel #4 GTX_AVCC NET 'GTX_AVCC' R1870-2 # Top side of the Voltage Divider NET 'MON_GTX_AVCC_UV' R1870-1 R1871-2 # HI Tap on GTX_AVCC Volt Divider NET 'MON_GTX_AVCC_UV' U1861-7 # U1861 Ch #4 VH4 pin #7 NET 'MON_GTX_AVCC_OV' R1871-1 R1872-2 # Low Tap on GTX_AVCC Volt Divider NET 'MON_GTX_AVCC_OV' U1861-8 # U1861 Ch #4 VL4 pin #8 NET 'GROUND' R1872-1 # Low side of the Voltage Divider # U1862 Voltage Monitors # # Voltage Monitor U1862 Channel #1 GTX_AVTT NET 'GTX_AVTT' R1873-2 # Top side of the Voltage Divider NET 'MON_GTX_AVTT_UV' R1873-1 R1874-2 # HI Tap on GTX_AVTT Volt Divider NET 'MON_GTX_AVTT_UV' U1862-1 # U1862 Ch #1 VH1 pin #1 NET 'MON_GTX_AVTT_OV' R1874-1 R1875-2 # Low Tap on GTX_AVTT Volt Divider NET 'MON_GTX_AVTT_OV' U1862-2 # U1862 Ch #1 VL1 pin #2 NET 'GROUND' R1875-1 # Low side of the Voltage Divider # # Voltage Monitor U1862 Channel #2 BF_CORE NET 'BF_CORE' R1876-2 # Top side of the Voltage Divider NET 'MON_BF_CORE_UV' R1876-1 R1877-2 # HI Tap on BF_CORE Volt Divider NET 'MON_BF_CORE_UV' U1862-3 # U1862 Ch #2 VH2 pin #3 NET 'MON_BF_CORE_OV' R1877-1 R1878-2 # Low Tap on BF_CORE Volt Divider NET 'MON_BF_CORE_OV' U1862-4 # U1862 Ch #2 VL2 pin #4 NET 'GROUND' R1878-1 # Low side of the Voltage Divider # # Voltage Monitor U1862 Channel #3 BSPT_CORE NET 'BSPT_CORE' R1879-2 # Top side of the Voltage Divider NET 'MON_BSPT_CORE_UV' R1879-1 R1880-2 # HI Tap on BSPT_CORE Volt Divider NET 'MON_BSPT_CORE_UV' U1862-5 # U1862 Ch #3 VH3 pin #5 NET 'MON_BSPT_CORE_OV' R1880-1 R1881-2 # Low Tap on BSPT_CORE Volt Divider NET 'MON_BSPT_CORE_OV' U1862-6 # U1862 Ch #3 VL3 pin #6 NET 'GROUND' R1881-1 # Low side of the Voltage Divider # # Voltage Monitor U1862 Channel #4 BULK_5V0 NET 'BULK_5V0' R1882-2 # Top side of the Voltage Divider NET 'MON_BULK_5V0_UV' R1882-1 R1883-2 # HI Tap on BULK_5V0 Volt Divider NET 'MON_BULK_5V0_UV' U1862-7 # U1862 Ch #4 VH4 pin #7 NET 'MON_BULK_5V0_OV' R1883-1 R1884-2 # Low Tap on BULK_5V0 Volt Divider NET 'MON_BULK_5V0_OV' U1862-8 # U1862 Ch #4 VL4 pin #8 NET 'GROUND' R1884-1 # Low side of the Voltage Divider # # Voltage Monitor UV_B and OV_B pins # # PRE_BOARD_POWER_OK goes HI when all monitored # voltages are within their tolerances. # NET 'PRE_BOARD_POWER_OK' U1861-11 U1861-12 # Under Volt and Over Volt NET 'PRE_BOARD_POWER_OK' U1862-11 U1862-12 # Open Drain pins # # U1861 AD12914-2 Power and Ground Connections. NET 'BULK_5V0' R1891-2 # +5V Power for the U1861 AD12914-2 NET 'VOLT_MONIT_1_POW' R1891-1 C1863-1 # Filtered power for U1861 NET 'VOLT_MONIT_1_POW' U1861-16 u1861-14 # U1861 Vdd and SEL pins NET 'GROUND' C1863-2 # Ground the power filter cap. NET 'GROUND' U1861-9 # U1861 AD12914-2 GROUND connection # # U1862 AD12914-2 Power and Ground Connections. NET 'BULK_5V0' R1892-2 # +5V Power for the U1862 AD12914-2 NET 'VOLT_MONIT_2_POW' R1892-1 C1864-1 # Filtered power for U1862 NET 'VOLT_MONIT_2_POW' U1862-16 U1862-14 # U1862 Vdd and SEL pins NET 'GROUND' C1864-2 # Ground the power filter cap. NET 'GROUND' U1862-9 # U1862 AD12914-2 GROUND connection # # Timing Capacitors for U1861 and U1862 AD12914-2 NET 'VOLT_MONIT_1_TIME' U1861-15 C1861-1 # Timing Capacitor for U1861 NET 'GROUND' C1861-2 # Ground for U1861 Timing Capacitor NET 'VOLT_MONIT_2_TIME' U1862-15 C1862-1 # Timing Capacitor for U1862 NET 'GROUND' C1862-2 # Ground for U1862 Timing Capacitor # # NO Connection Pins on U1861 and u1862 NET 'No_Conn_U1861_REF_P10' U1861-10 # No Connection to Reference pin NET 'No_Conn_U1861_DIS_P13' U1861-13 # No Connection to DIS pin NET 'No_Conn_U1862_REF_P10' U1862-10 # No Connection to Reference pin NET 'No_Conn_U1862_DIS_P13' U1862-13 # No Connection to DIS pin # # CMX-0 Nets File # # Where-Ever Bulk 3V3 ByPass Capacitors # ----------------------------------------- # # # Original Rev. 8-Aug-2013 # Most Recent Rev. 18-Aug-2013 # # # # This file holds the nets for the "extra" bypass capacitors # on the BULK_3V3 power supply net that were added wherever # they would rationally fit after the main trace routing # work on the CMX card was finished. # # # Components referenced in this file include: # # Reserve all the reference designators # C951:C999 for these "extra" BULK_3V3 # bypass capacitors. # # C951:C957 B case Tantalum Caps # # # Up by the Hardwired Oversight Logic: # ------------------------------------ NET 'BULK_3V3' C951-1 C952-1 # BULK_3V3 connection NET 'GROUND' C951-2 C952-2 # Ground connection # Just under the VME-- Interface: # ------------------------------- NET 'BULK_3V3' C953-1 # BULK_3V3 connection NET 'GROUND' C953-2 # Ground connection # By the Backplane Cable LVDS Transceivers: # ----------------------------------------- NET 'BULK_3V3' C954-1 C955-1 # BULK_3V3 connection NET 'GROUND' C954-2 C955-2 # Ground connection # By the TTCDec 3.3V to 2.5V Translators: # --------------------------------------- NET 'BULK_3V3' C956-1 C957-1 # BULK_3V3 connection NET 'GROUND' C956-2 C957-2 # Ground connection # By the Front Panel CTP LVDS Transceivers: # ----------------------------------------- NET 'BULK_3V3' C958-1 C959-1 # BULK_3V3 connection NET 'GROUND' C958-2 C959-2 # Ground connection # By the System ACE and CF Memory Module: # --------------------------------------- NET 'BULK_3V3' C960-1 # BULK_3V3 connection NET 'GROUND' C960-2 # Ground connection # In the North-West corner by the LEDs: # ------------------------------------- NET 'BULK_3V3' C961-1 # BULK_3V3 connection NET 'GROUND' C961-2 # Ground connection # Wherever 100 nFd Caps West of Base Function # --------------------------------------------- NET 'BULK_3V3' C962-1 C963-1 # BULK_3V3 connection NET 'GROUND' C962-2 C963-2 # Ground connection NET 'BF_CORE' C964-1 C965-1 # BF_CORE connection NET 'GROUND' C964-2 C965-2 # Ground connection NET 'BULK_2V5' C966-1 C967-1 # BULK_2V5 connection NET 'GROUND' C966-2 C967-2 # Ground connection NET 'BULK_2V5' C968-1 # BULK_2V5 connection NET 'GROUND' C968-2 # Ground connection # # CMX-0 Nets File # # Spare Translator Nets # -======----------------------------------- # # # Original Rev. 06-Sept-2013 # Most Recent Rev. 10-Oct-2013 # # # This file holds the nets for all of the Signal, Power, # and Ground connections for a Spare 74AVCAH164245 Translator # located just west of the two Avago transmitters # # The direction and enable pins from the two halves of SU1 # can be independently setup via Jumpers for voltage translation # between BULK_2V5 and BULK_3V3 # # # DIRECTION signals # # The Direction of the two halves of the spare translator SU1 # can be set independently for direction "A"-->"B" (High) or "B"-->"A" (Low) # by using an appropriate jumper at site SR1 or SR2 for section 1 # and SR5 or SR6 for section 2 of the translator NET 'SPARE_TRNSLT_DIR_1' SU1-1 SR1-1 SR2-1 NET 'GROUND' SR2-2 NET 'BULK_2V5' SR1-2 NET 'SPARE_TRNSLT_DIR_2' SU1-24 SR5-1 SR6-1 NET 'GROUND' SR5-2 NET 'BULK_2V5' SR6-2 # # OUTPUT_ENABLE_B signals # # The Output Enable of the two halves of the spare translator SU1 # can be set independently as Disabled (High) or Enabled (Low) # by using an appropriate jumper at site SR3 or SR4 for section 1 # and SR7 or SR8 for section 2 of the translator NET 'SPARE_TRNSLT_OE_1_B' SU1-48 SR3-2 SR4-2 NET 'GROUND' SR4-1 NET 'BULK_2V5' SR3-1 NET 'SPARE_TRNSLT_OE_2_B' SU1-25 SR7-2 SR8-2 NET 'GROUND' SR7-1 NET 'BULK_2V5' SR8-1 # 4x channels of each section are connected to one side of a resistor. # The resistor may be installed or a white wire may be soldered # directly at the resistor pad nearest the IO pin. NET 'SPARE_1B1' SU1-2 SR10-2 # 3.3V side of upper half spare channel #1 NET 'SPARE_1B3' SU1-5 SR11-2 # 3.3V side of upper half spare channel #2 NET 'SPARE_1B5' SU1-8 SR12-2 # 3.3V side of upper half spare channel #3 NET 'SPARE_1B7' SU1-11 SR13-2 # 3.3V side of upper half spare channel #4 NET 'SPARE_2B2' SU1-14 SR14-2 # 3.3V side of lower half spare channel #1 NET 'SPARE_2B4' SU1-17 SR15-2 # 3.3V side of lower half spare channel #2 NET 'SPARE_2B6' SU1-20 SR16-2 # 3.3V side of lower half spare channel #3 NET 'SPARE_2B8' SU1-23 SR17-2 # 3.3V side of lower half spare channel #4 NET 'SPARE_1A1' SU1-47 SR20-1 # 2.5V side of upper half spare channel #1 NET 'SPARE_1A3' SU1-44 SR21-1 # 2.5V side of upper half spare channel #2 NET 'SPARE_1A5' SU1-41 SR22-1 # 2.5V side of upper half spare channel #3 NET 'SPARE_1A7' SU1-38 SR23-1 # 2.5V side of upper half spare channel #4 NET 'SPARE_2A2' SU1-35 SR24-1 # 2.5V side of lower half spare channel #1 NET 'SPARE_2A4' SU1-32 SR25-1 # 2.5V side of lower half spare channel #2 NET 'SPARE_2A6' SU1-29 SR26-1 # 2.5V side of lower half spare channel #3 NET 'SPARE_2A8' SU1-26 SR27-1 # 2.5V side of lower half spare channel #4 # Power and ByPass for SU1 74AVCAH164245 # power is BULK_2V5 (A) and BULK_3V3 (B) NET 'BULK_3V3' SU1-7 SU1-18 # SU1 3.3V Vccb power NET 'BULK_2V5' SU1-31 SU1-42 # SU1 2.5V Vcca power NET 'GROUND' SU1-4 SU1-10 # SU1 Ground connections NET 'GROUND' SU1-15 SU1-21 # SU1 Ground connections NET 'GROUND' SU1-28 SU1-34 # SU1 Ground connections NET 'GROUND' SU1-39 SU1-45 # SU1 Ground connections NET 'BULK_3V3' C292-2 C293-2 # ByPass Cap 3.3V Vccb power NET 'BULK_2V5' C291-1 C294-1 # ByPass Cap 2.5V Vcca power NET 'GROUND' C292-1 C293-1 # ByPass Cap Ground connections NET 'GROUND' C291-2 C294-2 # ByPass Cap Ground connections # # CMX-0 Nets File # # Life Boats and Ground Loops # ------------------------------- # # # Original Rev. 11-Sept-2013 # Current Rev. 24-Sept-2013 # # # # # This file holds the nets for various "life boat" features # that we have included in the CMX card and it holds the # ground nets for "single pin via components" that can be # used to install Ground Loops for Test Probe connection # on the CMX card. # NET 'GROUND' WRP17-1 WRP18-1 # Ground Loop near the # TTCDec and Clock Generator NET 'GROUND' WRP19-1 WRP20-1 # Ground Loop near the # MTP Front-Panel Feedthroughs NET 'GROUND' WRP21-1 WRP22-1 # Ground Loop just SW of the # J13 Voltage Monitor Connector NET 'GROUND' WRP23-1 WRP24-1 # Ground Loops just East of NET 'GROUND' WRP25-1 WRP26-1 # the CTP Front-Panel Connectors NET 'GROUND' WRP27-1 WRP28-1 NET 'GROUND' WRP29-1 NET 'GROUND' WRP30-1 # Ground Loop just East of # the J12 Front-Panel Connector NET 'GROUND' WRP31-1 # Ground Loop between MiniPODs # MP4 and MP5 NET 'GROUND' WRP32-1 # Ground Loop between MiniPODs # MP1 and MP2 NET 'GROUND' WRP33-1 # Ground Loop between CAN-Bus # Processor and Clock Generator NET 'GROUND' WRP34-1 # Ground Loop just North of BSPT # FPGA by the Hardwired Oversignt # Logic NET 'GROUND' WRP35-1 WRP36-1 # Ground Loop or white wire path # just South of Debug Connector # Surface pads from a resistor geometry to help emergency access # to a few of the J14 Debug Connector signals. # The components are numbered counter-clockwise. NET 'BSPT_DEBUG_4' SR51-2 # North-West of J14 NET 'BSPT_DEBUG_6' SR52-2 # NET 'TP_DEBUG_0' SR53-2 # NET 'TP_DEBUG_6' SR54-2 # NET 'BF_DEBUG_0' SR55-2 # NET 'BF_DEBUG_4' SR56-2 # NET 'BF_DEBUG_6' SR57-2 # South-West of J14 NET 'BF_DEBUG_7' SR58-1 # South-East of J14 NET 'BF_DEBUG_5' SR59-1 # NET 'BF_DEBUG_1' SR60-1 # NET 'TP_DEBUG_7' SR61-1 # NET 'TP_DEBUG_1' SR62-1 # NET 'BSPT_DEBUG_7' SR63-1 # NET 'BSPT_DEBUG_1' SR64-1 # North-East of J14 # Surface pads from a resistor geometry to help emergency access # to the unused J13 Power Supply Monitoring Connector signals. NET 'MON_SPARE_1' SR71-1 J13-33 NET 'MON_SPARE_2' SR72-1 J13-35 NET 'MON_SPARE_3' SR73-1 J13-37 NET 'MON_SPARE_4' SR74-1 J13-39