# # CMX-0 Nets File # # BSPT_FPGA TTCDec Signals Nets # -------------======---------------- # # # Original Rev. 11-Nov-2012 # Most Recent Rev. 20-Jun-2013 Swap BUF_TTC_SUB_ADRS_4 and _5 to help trace layout # # # # This file holds all of the nets that connect the # Board Support FPGA with the TTCDec Mezzanine Card # # # Notes: # # - The TTCDec Output signals are translated to 2.5V CMOS # level and series terminated before being send on a bus # to the BSPT_FPGA (with taps to BF and TP FPGAs as needed). # # # The components referenced in this file are: # # U351 the BSPT_FPGA # # # TTCDec Outputs # # Buffered, Series Terminated, 2.5V TTC Output Bus # Signal Pins on the Board Support FPGA # # These signals will travel north on layer 6 and west on layer 7 NET 'BUF_TTC_BRCST_2' U351-P15 #> T06 # Buffered TTC_BRCST_2 NET 'BUF_TTC_BRCST_3' U351-P14 #> T06 # Buffered TTC_BRCST_3 NET 'BUF_TTC_BRCST_4' U351-N14 #> T06 # Buffered TTC_BRCST_4 NET 'BUF_TTC_BRCST_5' U351-M16 #> T06 # Buffered TTC_BRCST_5 NET 'BUF_TTC_BRCST_6' U351-M15 #> T06 # Buffered TTC_BRCST_6 NET 'BUF_TTC_BRCST_7' U351-M14 #> T06 # Buffered TTC_BRCST_7 NET 'BUF_TTC_BRCST_STR_1' U351-M13 #> T06 # Buffered TTC_BRCST_STR_1 NET 'BUF_TTC_BRCST_STR_2' U351-L15 #> T06 # Buffered TTC_BRCST_STR_2 NET 'BUF_TTC_SIN_ERR_STR' U351-L14 #> T06 # Buffered TTC_SIN_ERR_STR NET 'BUF_TTC_DB_ERR_STR' U351-L13 #> T06 # Buffered TTC_DB_ERR_STR NET 'BUF_TTC_CLK_40_L1A' U351-K14 #> T06 # Buffered TTC_CLK_40_L1A NET 'BUF_TTC_BNCH_CNT_RES' U351-K15 #> T06 # Buffered TTC_BNCH_CNT_RES NET 'BUF_TTC_EV_CNT_RES' U351-K16 #> T06 # Buffered TTC_EV_CNT_RES NET 'BUF_TTC_EV_CNT_H_STR' U351-K18 #> T06 # Buffered TTC_EV_CNT_H_STR NET 'BUF_TTC_EV_CNT_L_STR' U351-K20 #> T06 # Buffered TTC_EV_CNT_L_STR NET 'BUF_TTC_BNCH_CNT_STR' U351-J13 #> T06 # Buffered TTC_BNCH_CNT_STR NET 'BUF_TTC_B_CNT_0' U351-J14 #> T06 # Buffered TTC_B_CNT_0 NET 'BUF_TTC_B_CNT_1' U351-J15 #> T06 # Buffered TTC_B_CNT_1 NET 'BUF_TTC_B_CNT_2' U351-J16 #> T06 # Buffered TTC_B_CNT_2 NET 'BUF_TTC_B_CNT_3' U351-J17 #> T06 # Buffered TTC_B_CNT_3 NET 'BUF_TTC_B_CNT_4' U351-J18 #> T06 # Buffered TTC_B_CNT_4 NET 'BUF_TTC_B_CNT_5' U351-J19 #> T06 # Buffered TTC_B_CNT_5 NET 'BUF_TTC_B_CNT_6' U351-J20 #> T06 # Buffered TTC_B_CNT_6 NET 'BUF_TTC_B_CNT_7' U351-H14 #> T06 # Buffered TTC_B_CNT_7 NET 'BUF_TTC_B_CNT_8' U351-H15 #> T06 # Buffered TTC_B_CNT_8 NET 'BUF_TTC_B_CNT_9' U351-H17 #> T06 # Buffered TTC_B_CNT_9 NET 'BUF_TTC_B_CNT_10' U351-H18 #> T06 # Buffered TTC_B_CNT_10 NET 'BUF_TTC_B_CNT_11' U351-H19 #> T06 # Buffered TTC_B_CNT_11 NET 'BUF_TTC_DQ_0' U351-H20 #> T06 # Buffered TTC_DQ_0 NET 'BUF_TTC_DQ_1' U351-G14 #> T06 # Buffered TTC_DQ_1 NET 'BUF_TTC_DQ_2' U351-G15 #> T06 # Buffered TTC_DQ_2 NET 'BUF_TTC_DQ_3' U351-G16 #> T06 # Buffered TTC_DQ_3 NET 'BUF_TTC_L1_ACCEPT' U351-G17 #> T06 # Buffered TTC_L1_ACCEPT NET 'BUF_TTC_SER_B_CH' U351-G18 #> T06 # Buffered TTC_SER_B_CH NET 'BUF_TTC_D_OUT_STR' U351-G20 #> T06 # Buffered TTC_D_OUT_STR NET 'BUF_TTC_READY' U351-F16 #> T06 # Buffered TTC_READY (STATUS_1) NET 'BUF_TTC_STATUS_2' U351-F17 #> T06 # Buffered TTC_STATUS_2 NET 'BUF_TTC_D_OUT_0' U351-F18 #> T06 # Buffered TTC_D_OUT_0 NET 'BUF_TTC_D_OUT_1' U351-F19 #> T06 # Buffered TTC_D_OUT_1 NET 'BUF_TTC_D_OUT_2' U351-F20 #> T06 # Buffered TTC_D_OUT_2 NET 'BUF_TTC_D_OUT_3' U351-E18 #> T06 # Buffered TTC_D_OUT_3 NET 'BUF_TTC_D_OUT_4' U351-E19 #> T06 # Buffered TTC_D_OUT_4 NET 'BUF_TTC_D_OUT_5' U351-E20 #> T06 # Buffered TTC_D_OUT_5 NET 'BUF_TTC_D_OUT_6' U351-D18 #> T06 # Buffered TTC_D_OUT_6 NET 'BUF_TTC_D_OUT_7' U351-D20 #> T06 # Buffered TTC_D_OUT_7 NET 'BUF_TTC_SUB_ADRS_0' U351-C19 #> T06 # Buffered TTC_SUB_ADRS_0 NET 'BUF_TTC_SUB_ADRS_1' U351-C20 #> T06 # Buffered TTC_SUB_ADRS_1 NET 'BUF_TTC_SUB_ADRS_2' U351-B19 #> T06 # Buffered TTC_SUB_ADRS_2 NET 'BUF_TTC_SUB_ADRS_3' U351-B20 #> T06 # Buffered TTC_SUB_ADRS_3 NET 'BUF_TTC_SUB_ADRS_4' U351-B18 #> T06 # Buffered TTC_SUB_ADRS_4 NET 'BUF_TTC_SUB_ADRS_5' U351-A18 #> T06 # Buffered TTC_SUB_ADRS_5 NET 'BUF_TTC_SUB_ADRS_6' U351-D17 #> T06 # Buffered TTC_SUB_ADRS_6 NET 'BUF_TTC_SUB_ADRS_7' U351-C17 #> T06 # Buffered TTC_SUB_ADRS_7 ##NET 'BUF_TTC_Spare_1_3' U351-xyz # Buffered TTC_Spare_1_3 ##NET 'BUF_TTC_Spare_2_3' U351-xyz # Buffered TTC_Spare_2_3 ##NET 'BUF_TTC_Spare_3_3' U351-xyz # Buffered TTC_Spare_3_3 # # The 3.3V logic level connections with the TTCDec # will be to I/O Bank #3 on the BSPT_FPGA # # Input Control Signals to the TTCDec # # The TTCDec receives 3 control type signals from the # the Board Support FPGA. These are 3.3V CMOS signals. # NET 'TTC_PD' U351-T4 #> T06 # Clock Changeover Mode: Protected or DeBug NET 'TTC_CLK_SEL' U351-U1 #> T06 # Select 40 MHz rock or TTCrx clock source NET 'TTC_RESET_B' U351-T3 #> T06 # Reset the TTCrx ASIC # # I2C Bus Signals to the TTCDec # # The TTCDec has an I2C Bus connection with the Board # Support FPGA. The 2 lines of the I2C Bus are 3.3V CMOS signals. # # These 2 signals have series terminator resistors # R324 and R325 near the Board Support FPGA. # NET 'ST_TTC_SCL' U351-V1 R324-2 # I2C Serial Clock BSPT_FPGA --> Series Term NET 'TTC_SCL' R324-1 #> T06 # I2C Serial Clock Series Term --> TTCDec NET 'ST_TTC_SDA' U351-U3 R325-2 # I2C Serail Data BSPT <-> Series Term NET 'TTC_SDA' R325-1 #> T06 # I2C Serail Data Series Term <-> TTCDec # # Control Enabling of the Outputs on the translator/buffer # chips U151:U154 (only 1/2 of the U154) that drive the # TTCDec Output Bus. NET 'BSPT_TTC_TRNSLT_OE_B' U351-G3 # Control signal from the BSPT # FPGA to the Hardwired Oversight # Logic and then to the TTCDec # Translators. The signal from # U363 in the Oversight Logic to # the TTCDec Translators is # named: TTC_TRNSLT_OE_B. # # Control Enabling the Output of the section of the # translator/buffer chip U154 that drives the Geo_Adrs # onto some Chip_ID lines when the TTCDec is being Reset. # For now this is just sketched to place holder U998. NET 'BSPT_TTC_RESET_TRNSLT_OE_B' U351-G1 # Control signal from the BSPT # FPGA to the Hardwired Oversight # Logic and then to the TTCDec # Translators. The signal from # U358 in the Oversight Logic to # the TTCDec Translators is # named: TTC_RESET_TRNSLT_OE_B.