# # CMX-0 Nets File # # Board Support FPGA - All Other Nets # ------------------------------------- # # # Original Rev. 26-Feb-2013 # Rev. 20-Jun-2013 Swap TP_TO_FROM_BSPT_3 and _4 to help trace layout # Rev. 21-Jun-2013 Move BF <--> TP: REQ, LED, To/From, and BSPT_DeBug # Rev: 10-Jul-2013 Reorder debug pin assignment for straight route near # debug connector # Rev: 11-Sep-2013 Add connections from unused 3V3 pins to SR Comps. # Most Recent Rev: 20-Sep-2013 Add JMP101:JMP105 for the 5-bit CMX Card Serial Number. # # # # # This file holds All of the Other nets that connect to the # Board Support FPGA. # # Specifically this file holds the BSPT connections for: # # 1. The "package pins" on BSPT FPGA, e.g. SUSPEND, AWAKE, PUDC_B # # 2. The LED associated pins, i.e. control signals from BF & TP # drive signals to the LEDs # # 3. VME/OCB Management signals, i.e. control of sending DTACK_B # control of data buffer direction and OE_B # # 4. Management of the Cable LVDS, i.e. direction request signals from the BF # FPGA, control signals to the Cable LVDS # Translators and Transceivers via the # Hardwired Oversight Logic # # 5. Management of the CTP LVDS, i.e. direction request signals from the BF and TP # FPGAs, control signals to the CTP LVDS # Translators and Transceivers via the # Hardwired Oversight Logic # # 6. An input pin for the ALLOW_BUSSED_IO signal 3.3V level # so that the BSPT FPGA can know if the Hardwired Oversight # Logic thinks that conditions are OK for nornal CMX # operation. # # 6. A jumper controlled input to BSPT that unambiguously # indicates whether or not the Topological Processor FPGA # is installed on this card. TP_FPGA_INSTALLED_B # # 7. DeBug, Spare Signals to Header J14 - 10 signals 2.5V logic level. # # 8. Spare connections: BF to/from BSPT and TP to/from BSPT # 8 each to/from BF and TP. All 2.5V signal. All I/O pins # on the BSPT FPGA. # # 9. The No_Conn pins on the BSPT FPGA, i.e. FPGA pins that # are not used on CMX. # # # # The "groups" of signals that connect to the Board Support # FPGA are organized into the following 6 nets files: # # bspt_fpga_configuration_n2p.txt # bspt_fpga_on_card_bus_nets_n2p.txt # bspt_fpga_optical_ctrl_monit_n2p.txt # bspt_fpga_power_and_ground_n2p.txt # bspt_fpga_system_ace_nets_n2p.txt # bspt_fpga_TTCDec_signals_n2p.txt # # # # The following 3 files each include a few connections to the # Board Support FPGA: # # clock_gen_and_dist_nets_n2p.txt # configuration_nets_n2p.txt # jtag_chains_n2p.txt # # # # Recall the setup of the BSPT I/O Bank Voltages that is # used on the CMX card: # # - I/O Banks #0, #1, #2 are all 2.5V CMOS logic signals. # # - I/O Bank #3 has a 3.3V CMOS logic signals. # # - The VCCAUX supply to the BSPT is 3.3 Volts and thus # the BSPT signals: SUSPEND, DONE, PROG_B, and JTAG # are all 3.3V levels. Recall that the Spartan 3A will # need the CONFIG VCCAUX=3.3" constraint. # # # # # The parts referenced in this file include: # # U351 BSPT_FPGA # JMP57 BSPT PUDC_B Control # R326 Pull-Up on BSPT PUDC_B pin # JMP49 Topological Processor Installed Jumper # R327 Pull-Up on TP_Installed Jumper # # # Board Support FPGA "Package Pins": SUSPEND, AWAKE, PUDC_B # ---------------------------------- # The Suspend feature of the Spartan 3A FPGA must be enabled # in the bit-stream otherwise it is not possible to use this # feature. The dedicated SUSPEND pin R15 will be grounded # in the CMX design. NET 'GROUND' U351-R15 # Ground the dedicated SUSPEND pin. # Because the Suspend feature will not be used the Dual purpose # pin U13 IO_L22P_2/AWAKE is a normal Bank #2 I/O pins and # may be used for 2.5V logic on the CMX card. # The PUDC_B pin, aka Pull-Up During Configure, is similar to # the HSWAP_EN pin on the Virtex parts. If PUDC_B is LOW then # before the device is initially configured and during each # subsequent configuration process a Pull-Up Resistor will # be placed on all I/O and all Input pins that are not actively # being used by the selected configuration process. The intent # of this is to keep these CMOS signals at a defined and valid # logic level. The strength of these pull-up resistors is: # 5.1k to 24k for 3.3V I/O banks, 6.2k to 33k for 2.5V I/O Banks. # # The state of the PUDC_B pin will be controlled by jumper JMP57. # Install JMP57 to pull PUDC_B LOW and thus enable the pull-up # resistors before and during BSPT configuration. # # Note that the IO_L32N_0/PUDC_B pin B2 will not be used # on the CMX card for normal I/O. NET 'BSPT_PUDC_B' U351-B2 # Control the IO_L32N_0/PUDC_B pin NET 'BSPT_PUDC_B' JMP57-1 R326-1 # Control the BSPT PUDC_B pin NET 'GROUND' JMP57-2 # Ground for the PUDC_B jumper NET 'BULK_2V5' R326-2 # BULK_2V5 for R326 pull-up # # The LED associated pins on BSPT FPGA: # ------------------------------------- # Both the Base Function and the Topological Processor # FPGAs provide 5 LED Illumination Request signals each # to the BSPT FPGA. These are 2.5V inputs to the BSPT # FPGA. BF or TP sets one of these lines HI when it wants # the LED that BSPT FPGA is currently associating with that # request line to be illuminated. These are all 2.5V I/O # pins on the BSPT FPGA used as inputs in this application. # LED Request #0 through #4 from the BF FPGA NET 'BF_LED_REQ_0' U351-Y16 # L28P-2 2.5V I/O used as Input NET 'BF_LED_REQ_1' U351-V17 # L31P-2 2.5V I/O used as Input NET 'BF_LED_REQ_2' U351-Y17 # L30P-2 2.5V I/O used as Input NET 'BF_LED_REQ_3' U351-Y18 # L30N-2 2.5V I/O used as Input NET 'BF_LED_REQ_4' U351-W20 # L01P-1 2.5V I/O used as Input # LED Request #0 through #4 from the TP FPGA NET 'TP_LED_REQ_0' U351-P20 # L10N-1 2.5V I/O used as Input NET 'TP_LED_REQ_1' U351-N15 # L12P-1 2.5V I/O used as Input NET 'TP_LED_REQ_2' U351-N17 # L12N-1 2.5V I/O used as Input NET 'TP_LED_REQ_3' U351-N18 # L13P-1 2.5V I/O used as Input NET 'TP_LED_REQ_4' U351-N19 # L13N-1 2.5V I/O used as Input # # The BSPT drives 9 of the 10 LEDs. The only LED that # BSPT does not drive is the BOARD_POWER_OK LED. # # Each LED has a pull-up resistor from its Anode to 3.3V. # The Drive signals from the BSPT FPGA go to the LED Cathodes. # The LED illuminates when the BSPT Drive signal is LOW. # These Drive signals are from the 3.3V I/O Bank #3. # These 3.3V LED Drive signals can be Open Drain. # The LED series resistors on CMX should result in a 2 mA LED current. # The LED components are labeled from 1 at the Top # through 5 at the Bottom. # Each LED component has a Left and a Right LED. # Each of these 10 LEDs has a Red and a Green section. # LED 1 Left is the BOARD_POWER_OK LED. # The Drive signals for the other 9 LEDs come from the BSPT FPGA. # NET 'LED_1R_GREEN_DRV' U351-H6 # Drive signal to LED 1 Right Green NET 'LED_2L_GREEN_DRV' U351-H4 # Drive signal to LED 2 Left Green NET 'LED_2R_GREEN_DRV' U351-H3 # Drive signal to LED 2 Right Green NET 'LED_3L_GREEN_DRV' U351-H2 # Drive signal to LED 3 Left Green NET 'LED_3L_RED_DRV' U351-J6 # Drive signal to LED 3 Left Red NET 'LED_3R_GREEN_DRV' U351-J5 # Drive signal to LED 3 Right Green NET 'LED_3R_RED_DRV' U351-J4 # Drive signal to LED 3 Right Red NET 'LED_4L_GREEN_DRV' U351-J3 # Drive signal to LED 4 Left Green NET 'LED_4L_RED_DRV' U351-J2 # Drive signal to LED 4 Left Red NET 'LED_4R_GREEN_DRV' U351-J1 # Drive signal to LED 4 Right Green NET 'LED_4R_RED_DRV' U351-K4 # Drive signal to LED 4 Right Red NET 'LED_5L_GREEN_DRV' U351-K3 # Drive signal to LED 5 Left Green NET 'LED_5L_RED_DRV' U351-K2 # Drive signal to LED 5 Left Red NET 'LED_5R_GREEN_DRV' U351-L5 # Drive signal to LED 5 Right Green NET 'LED_5R_RED_DRV' U351-L3 # Drive signal to LED 5 Right Red # VME/OCB Management Signals from BSPT FPGA: # ------------------------------------------ # # All 10 of the following signals come from the # On-Card-Bus Management function in the BSPT must control: # # - Control sending the VME DTACK_B signal from the CMX card. # This is a 3.3V control signal that passes through # Hardwired Oversight Logic on its way to the DTACK_B # VME driver chip. # # Before the BSPT FPGA is configured this signal must be # pulled HI. Once the CMX is ready for VME acces then # this signal should be taken LOW to request that the CMX # card assert its DTACK_B VME signal. NET 'BSPT_SEND_VME_DTACK_B' U351-D2 # L03N-3 3.3V Output # - Control the Direction of the VME Data Bus Transceiver # U352. This is a 3.3V control signal that runs directly # to the U352 VME Transceiver. # # Before the BSPT FPGA is configured this signal will be # pulled HI. Once the CMX is ready for VME acces then # this signal should be taken LOW for VME Writes and must # go HI for VME Reads. This signal must alwasy be in # the same state as the OCB_D_BUS_TRNSLT_DIR signal. NET 'VME_D_BUS_TRNCVR_DIR' U351-D3 # L01N-3 3.3V Output # - Control the Output_Enable_B of the VME Data Bus # Transceiver U352. This is a 3.3V control signal that # passes through Hardwired Oversight Logic on its way to # the U352 VME Transceiver. # # Before the BSPT FPGA is configured this signal must be # pulled HI. Once the CMX is ready for VME acces then # this signal should be taken LOW when this card is the # target of a VME Read or Write. NET 'BSPT_VME_D_BUS_TRNCVR_OE_B' U351-D1 # L05P-3 3.3V Output # - Control the Direction of the OCB Data Bus Translator # U355. This is a 2.5 control signal that runs directly # to the U355 OCB Translator. # # Before the BSPT FPGA is configured this signal will be # pulled HI. Once the CMX is ready for VME acces then # this signal should be taken LOW for VME Writes and must # go HI for VME Reads. This signal must alwasy be in # the same state as the VME_D_BUS_TRNCVR_DIR signal. NET 'OCB_D_BUS_TRNSLT_DIR' U351-A16 # L05N-0 2.5V Output # - Control the Output_Enable_B of the OCB Data Bus # Translator U355. This is a 2.5V control signal that # runs directly to the U355 OCB Translator. # # Before the BSPT FPGA is configured this signal must be # pulled HI. Once the CMX is ready for VME acces then # this signal should be taken LOW when this card is the # target of a VME Read or Write. NET 'OCB_D_BUS_TRNSLT_OE_B' U351-E15 # L03N-0 2.5V Output # - Control the LE signal to the U354 VME Receiver and to # the half of the U353 VME Receiver that is used for # "Address type" information. This is a 3.3V control # signal that runs directly to U354 and to the Address # section of the U353 Receiver. # # Before the BSPT FPGA is configured this LE signal will # be pulled HI. Once the CMX is ready for VME acces then # this LE signal can either remain HI to keep these # receivers transparent or else this LE signal may go LOW # at times so that these VME Receivers will "Hold" their # address information if this type of operation is desired. NET 'VME_ADRS_RECVR_LE' U351-C2 # L02N-3 3.3V Output # - Control the LE signal to the half of the U353 VME # Receiver that handles "Control type" information. # This LE signal must always hold this VME Receiver in # its transparent state. This is a 3.3V control signal # that runs directly to this section of the U353 Receiver. # # Before the BSPT FPGA is configured this LE signal will # be pulled HI. Once the CMX is ready for VME acces then # this LE signal should continue to be held HI to keep # this receiver's latch transparent. NET 'VME_CTRL_RECVR_LE' U351-D4 # L01P-3 3.3V Output # - Control the OE_B signal to all sections of both the # U353 and U354 Receivers for the VME Address and Control # type signals. This is a 3.3V control signal that runs # directly to the U353 and U354 chips. # # Before the BSPT FPGA is configured this signal must # be pulled HI. Once the CMX is ready for VME acces then # this signal should be taken LOW and stay LOW to enable # the output of these VME Receivers. NET 'VME_ADRS_AND_CTRL_RECVR_OE_B' U351-C1 # L03P-3 3.3V Output # - Control the DIR signal to all sections of both the # U356 and the U357 Translators for the OCB Address and # Control type signals. This is a 2.5V control that # goes directly to the U356 and U357 chips. # # Before the BSPT FPGA is configured this signal will # be pulled HI. Once the CMX is ready for VME acces then # this signal should be taken LOW and stay LOW to select # the B input to A output direction. NET 'OCB_ADRS_AND_CTRL_TRNSLT_DIR' U351-D15 # L06P-0 2.5V Output # - Control the OE_B signal to all sections of both the # U356 and the U357 Translators for the OCB Address and # Control type signals. This is a 3.3V control signal # that passes through Hardwired Oversight Logic before # it goes to U356 and U357. # # Before the BSPT FPGA is configured this signal must # be pulled HI. Once the CMX is ready for VME acces then # this signal should be taken LOW and stay LOW to enable # the translator outputs. NET 'BSPT_OCB_ADRS_AND_CTRL_TRNSLT_OE_B' U351-E3 # L10P-3 3.3V Output # Thus in total there are 10 OCB/VME Management signals # coming from the BSPT FPGA. 3 of these control signals # are 2.5V level. 7 of these control signals are 3.3V # level. 3 of these control signals have external # Hardwired Oversight Logic. # Management of the Backplane # LVDS Transceivers and Translators: # -------------------------------------- # # Recall that there are 3 Backplane Cables connected to # each CMX card. These cables from the top to the bottom are: # # Cable #1 consists of signals M_00 thru M_26 plus M_81 # Cable #2 consists of signals M_27 thru M_53 plus M_82 # Cable #3 consists of signals M_54 thru M_80 plus M_83 # # After passing through VLDS Transceivers and 3.3V <--> 2.5V # Translators the 28 signals on each of these cables are # connected to Select I/O pins on the Base Function FPGA. # The Translators and the VLDS Transceivers for each cable # can independently be setup to either receive signals from # the cable or to send signals onto the cable. The Base # Function FPGA requests the direction of these Transltors # and LVDS Transceivers with 3 direction request lines - # one line to request the direction of each Cable. # # The firmware in the Base Function FPGA must obey # 2 rules while managing the direction of the Backplane # LVDS Cables: # # - When BF requests that the Translators and LVDS # Transceivers for a given Backplane Cable are # either Inputs or Outputs it must also make certain # that its I/O pins associated with the 28 signals # for that Cable are also correctly setup as Inputs # or Outputs to match the direction of the Translators # and LVDS Transceivers. # # - When the BF does not want to use a given Backplane # cable it must request the direction of that cable # to be Input. # # The signal that the BF FPGA uses to request the # direction of the Translators and LVDS Transceivers # associated with a give Backplane Cable is called: # # BF_REQ_CABLE_n_INPUT # # # The BF FPGA sets this 2.5V CMOS signal HI when it wants # that Backplane Cable to be an Input. This signal is called # a Request because it must pass through the Board Support # FPGA where it becomes the actual control lines that run # to the Translator and LVDS Transceiver chips. For protection # of the components in these circuits the Output_Enable_B # line to the Translator chips passes through Hardwired # Oversignt Logic before it reaches the Translator chips. # # Logic in the Board Support FPGA confirms that the Base # Function FPGA is Configured before allowing the # BF_REQ_CABLE_n_INPUT request signal to manage the # control lines that run to the Translators and LVDS # Transceivers. # # Until the Base Function FPGA is Configured the logic in # the BSPT FPGA forces the Translators and LVDS Transceivers # to the following states: # # The LVDS Transceivers are set as Drivers # The Translators are set in the send data out direction # The Translators have their outputs disabled (3-stated) # # # The Hardwired Oversight Logic confirms: # that the Board_Power_OK signals is asserted and # that the BSPT_CONFIG_DONE signal is asserted and # that the CMX SAFE Jumper is installed and # that the BSPT_RUNNING_OK_B signal is asserted Low # before it allows any of the Translator Outputs to be enabled. # # From the BSPT FPGA there are 3 control signals that manage # the Translators and LVDS Transceivers for each of the 3 # cables. These signals are: # # CABLE_n_TRNCVR_DIR # CABLE_n_TRNSLT_DIR # CABLE_n_TRNSLT_OE_B # # # CABLE_n_TRNCVR_DIR is a 3.3V CMOS level signal that # runs directly to both the DRV_ENB and REC_ENB_B pin of the # DS91M040 LVDS Transceiver chips. Logic in the BSPT FPGA # must hold this signal HI until it confirms that the Base # Function FPGA is Configured and has rationally taken control # of requesting the direction that it wants on the 3 LVDS Cables. # Note that the level on CABLE_n_TRNCVR_DIR must always # match the level on CABLE_n_TRNSLT_DIR. # # CABLE_n_TRNSLT_DIR is a 2.5V CMOS level signal that # runs directly to the DIR pins on the 74AVCAH164245 Translator # chips. Before the Base Function FPGA is Configured, logic in # the BSPT FPGA should hold this signal either Hi. # Note that the level on CABLE_n_TRNSLT_DIR must always # match the level on CABLE_n_TRNCVR_DIR. # # CABLE_n_TRNSLT_OE_B is a 3.3V CMOS level signal that # passes through Hardwired Oversight Logic before running to # the OE_B pins on the 74AVCAH164245 Translator chips. Before # the Base Function FPGA is Configured, logic in the BSPT FPGA # must set this signal Hi. # # The current state of all 12 of the following signals may be # examined in a VME visible read only register in the BSPT FPGA. NET 'BF_REQ_CABLE_1_INPUT' U351-V15 # 2.5V I/O input to the BSPT # Hi --> BF Requests this LVDS # Cable to be an Input NET 'CABLE_1_TRNCVR_DIR' U351-W2 # 3.3V output from the BSPT # Hi --> LVDS Driver is Enabled NET 'CABLE_1_TRNSLT_DIR' U351-A17 # 2.5V output from the BSPT # Hi --> Translator direction for # LVDS Cables Output NET 'BSPT_CABLE_1_TRNSLT_OE_B' U351-E1 # 3.3V output from the BSPT # HI --> Disables the # Translator Outputs NET 'BF_REQ_CABLE_2_INPUT' U351-Y15 # 2.5V I/O input to the BSPT # Hi --> BF Requests this LVDS # Cable to be an Input NET 'CABLE_2_TRNCVR_DIR' U351-W1 # 3.3V output from the BSPT # Hi --> LVDS Driver is Enabled NET 'CABLE_2_TRNSLT_DIR' U351-D16 # 2.5V output from the BSPT # Hi --> Translator direction for # LVDS Cables Output NET 'BSPT_CABLE_2_TRNSLT_OE_B' U351-F4 # 3.3V output from the BSPT # HI --> Disables the # Translator Outputs NET 'BF_REQ_CABLE_3_INPUT' U351-W16 # 2.5V I/O input to the BSPT # Hi --> BF Requests this LVDS # Cable to be an Input NET 'CABLE_3_TRNCVR_DIR' U351-V2 # 3.3V output from the BSPT # Hi --> LVDS Driver is Enabled NET 'CABLE_3_TRNSLT_DIR' U351-C16 # 2.5V output from the BSPT # Hi --> Translator direction for # LVDS Cables Output NET 'BSPT_CABLE_3_TRNSLT_OE_B' U351-F3 # 3.3V output from the BSPT # HI --> Disables the # Translator Outputs # Management of the Front Panel CTP # LVDS Transceivers and Translators: # -------------------------------------- # # Recall that there are 2 Front Panel CTP Connection on each # CMX card. These connectors, top then bottom are: # # Connector J10 is signals CTP_00 thru CTP_31 plus CTP_64 # Connector J11 is signals CTP_32 thru CTP_63 plus CTP_65 # # After passing through VLDS Transceivers and 3.3V <--> 2.5V # Translators the 33 signals on each of these 2 CTP Connectors # are routed to Select I/O pins on the Base Function FPGA and # to Select I/O pin on the Topological Processor FPGA. # # Each CTP Connector has one set of LVDS Transceivers and # 2 sets of Translators. One set of Translators is associated # with the BF FPGA and the other set is associated with the # TP FPGA. # # The Translators and the VLDS Transceivers for each CTP # Connector can independently be setup to either receive # signals from the connector or to send signals to the CTP # Connector. When sending signals to the CTP Connector, # to prevent conflicting signals, either just the BF # Translators or else just the TP Translators may have # their outputs enabled. # # The Base Function and Topological Processor FPGAs each # can request the direction of these Transltors and LVDS # Transceivers with 2 direction request lines - one line # from each of these FPGAs to request the direction of # each of the CTP Connectors. # # The firmware in the BF and TP FPGAs must obey 2 rules # when requesting the direction of the CTP Connectors: # # - When one of these FPGAs requests that the Translators # and LVDS Transceivers for a given CTP Connector are # either Inputs or Outputs it must also make certain # that its I/O pins associated with the 33 signals # for that CTP Connector are also correctly setup as # Inputs or Outputs to match the direction of the # Translators and LVDS Transceivers. # # - When one of these FPGAs does not want to use a given # CTP Connector then it must request the direction # that CTP Connector to be an Input. # # The signal that the BF or TP FPGA uses to request the # direction of the Translators and LVDS Transceivers # associated with a give CTP Connector is called: # # BF_REQ_CTP_n_INPUT or # TP_REQ_CTP_n_INPUT # # # The FPGA sets this 2.5V CMOS signal HI when it wants that # CTP Connector to be an Input. This signal is called # a Request because it must pass through the Board Support # FPGA where it becomes the actual control lines that run # to the Translator and LVDS Transceiver chips. For protection # of the components in these circuits the Output_Enable_B # line to the Translator chips passes through Hardwired # Oversignt Logic before it reaches the Translator chips. # # Logic in the Board Support FPGA confirms that the BF or TP # FPGA is Configured before allowing the xy_REQ_CTP_n_INPUT # request signal to manage the control lines that run to the # Translators and LVDS Transceivers. # # Until the BF and TP FPGAs are Configured the logic in the # BSPT FPGA forces the Translators and LVDS Transceivers to # the following states: # # The LVDS Transceivers are set as LVDS Output Drivers # The Translators are set in the send data out to the CTP # The Translators have their outputs disabled (3-stated) # # From the TP_FPGA_INSTALLED_B jumper the BSPT logic knows # whether or not the TP FPGA is actually installed on a given # CMX card. When the TP is not installed then: # # Its TP_REQ_CTP_n_INPUT signals are ignored. # The DIR control signal to the Translators associated with # the TP FPGA are forced HI thus setting their direction # to be output. # The OE_B control signal to the Translators associated with # the TP FPGA are forced HI thus disabling the Translator # outputs. # # The Hardwired Oversight Logic confirms: # that the Board_Power_OK signals is asserted and # that the BSPT_CONFIG_DONE signal is asserted and # that the CMX SAFE Jumper is installed and # that the BSPT_RUNNING_OK_B signal is asserted Low # before it allows any of the Translator Outputs to be enabled. # # # From the BSPT FPGA there are 5 control signals that manage # the Translators and LVDS Transceivers for each of the two # CTP Connectora. These signals are: # # CTP_n_TRNCVR_DIR # CTP_n_BF_TRNSLT_DIR # CTP_n_BF_TRNSLT_OE_B # CTP_n_TP_TRNSLT_DIR # CTP_n_TP_TRNSLT_OE_B # # # CTP_n_TRNCVR_DIR is a 3.3V CMOS level signal that # runs directly to both the DRV_ENB and REC_ENB_B pin of the # DS91M040 LVDS Transceiver chips. Logic in the BSPT FPGA # must hold this signal HI until it confirms that the Base # Function FPGA (and if installed the TP FPGA) is Configured # and has rationally taken control of requesting the direction # that it wants on the 2 CTP Connectors to be. # # CTP_n_BF_TRNSLT_DIR and CTP_n_TP_TRNSLT_DIR are # 2.5V CMOS level signals that run directly to the DIR pins on # the 74AVCAH164245 Translator chips. Before the Base Function # FPGA (and if installed the TP FPGA) is Configured, logic # in the BSPT FPGA should hold this signal either Hi. When # the TP FPGA is NOT installed then the Direction signal to # its Translators should always be Hi. # # CTP_n_BF_TRNSLT_OE_B and CTP_n_TP_TRNSLT_OE_B are # 3.3V CMOS level signals that passes through Hardwired Oversight # Logic before running to the OE_B pins on the 74AVCAH164245 # Translator chips. Before the Base Function FPGA (and if # installed the TP FPGA) is Configured, logic in the BSPT FPGA # must set this signal Hi. When the TP FPGA is NOT installed # then the OE_B signal to its Translators must always be Hi. # # The current state of all 14 of the following signals may be # examined in a VME visible read only register in the BSPT FPGA. NET 'BF_REQ_CTP_1_INPUT' U351-P11 # 2.5V input only to the BSPT # Hi --> BF Requests this CTP # Connector to be an Input NET 'TP_REQ_CTP_1_INPUT' U351-P13 # 2.5V input only to the BSPT # Hi --> BF Requests this CTP # Connector to be an Input NET 'CTP_1_TRNCVR_DIR' U351-N4 # 3.3V output from the BSPT # Hi --> LVDS Driver is Enabled NET 'CTP_1_BF_TRNSLT_DIR' U351-Y5 # 2.5V output from the BSPT # Hi --> Translator direction # for CTP Connector Output NET 'BSPT_CTP_1_BF_TRNSLT_OE_B' U351-F2 # 3.3V output from the BSPT # HI --> Disables the # Translator Outputs NET 'CTP_1_TP_TRNSLT_DIR' U351-V5 # 2.5V output from the BSPT # Hi --> Translator direction # for CTP Connector Output NET 'BSPT_CTP_1_TP_TRNSLT_OE_B' U351-F1 # 3.3V output from the BSPT # HI --> Disables the # Translator Outputs NET 'BF_REQ_CTP_2_INPUT' U351-T11 # 2.5V input only to the BSPT # Hi --> BF Requests this CTP # Connector to be an Input NET 'TP_REQ_CTP_2_INPUT' U351-R14 # 2.5V input only to the BSPT # Hi --> BF Requests this CTP # Connector to be an Input NET 'CTP_2_TRNCVR_DIR' U351-N3 # 3.3V output from the BSPT # Hi --> LVDS Driver is Enabled NET 'CTP_2_BF_TRNSLT_DIR' U351-U5 # 2.5V output from the BSPT # Hi --> Translator direction # for CTP Connector Output NET 'BSPT_CTP_2_BF_TRNSLT_OE_B' U351-G5 # 3.3V output from the BSPT # HI --> Disables the # Translator Outputs NET 'CTP_2_TP_TRNSLT_DIR' U351-Y6 # 2.5V output from the BSPT # Hi --> Translator direction # for CTP Connector Output NET 'BSPT_CTP_2_TP_TRNSLT_OE_B' U351-G4 # 3.3V output from the BSPT # HI --> Disables the # Translator Outputs # BSPT Running OK Output Signal # --------------------------------- # # Besides just knowing that the BSPT FPGA is configured # we are also sending the Hardwired Overight Logic a signal # from the BSPT FPGA that tells this logic that from the # BSPT's point of view everything is OK and thus the # oversight logic is allowed to enable the bus type # operations. Note that this is a LOW active signal to # make it the opposite of the non-configured default pulled # high state of this ouput pin. The high state of this # pin is only 2.5V but it is going to a real TTL chip # that is guaranteed to see anything above 2.0V as a HI. NET 'BSPT_RUNNING_OK_B' U351-A3 # L30P-0 2.5V I/O Output # # Topological Processor FPGA Installed Jumper # ----------------------------------------------- # # This jumper JMP49 unambiguously indicates to the BSPT # whether or not the Topological Processor FPGA is installed # on this card. This signal, TP_FPGA_INSTALLED_B, has a # pull-up resistor to BULK_2V5 and jumper JMP49 to Ground. # # The TP_FPGA_INSTALLED_B signal is Low active. # Low means that the TP FPGA is installed. # # This jumper is to be installed only on cards that # have a Topological Processor FPGA installed on them. NET 'TP_FPGA_INSTALLED_B' U351-G8 # IP-0 2.5V In-Only # TP_FPGA_INSTALLED_B signal NET 'TP_FPGA_INSTALLED_B' JMP49-1 R327-1 # Control TP_FPGA_INSTALLED_B NET 'GROUND' JMP49-2 # Ground for the jumper NET 'BULK_2V5' R327-2 # BULK_2V5 for R327 pull-up # # Input for the ALLOW_BUSSED_IO signal # --------------------------------------- # # The BSPT receives the 3.3V ALLOW_BUSSED_IO so that it can # if the Hardwired Oversight Logic thinks that conditions # are OK for nornal card operation. NET 'ALLOW_BUSSED_IO' U351-G7 # Receive the ALLOW_BUSSED_IO # signal 3.3V Input-Only pin # # DeBug Signals - Spare Signals # ----------------------------------- # # Run 10 signals from the BSPT FPGA to Header J14. # These signals are are DeBug work or for emergency # connections between the FPGAs. These are 2.5V I/O pins. NET 'BSPT_DEBUG_0' U351-T17 # L03P-1 2.5V I/O DeBug Signal 0 NET 'BSPT_DEBUG_1' U351-P17 # L07N-1 2.5V I/O DeBug Signal 1 NET 'BSPT_DEBUG_2' U351-U17 # L31N-2 2.5V I/O DeBug Signal 2 NET 'BSPT_DEBUG_3' U351-R16 # L03N-1 2.5V I/O DeBug Signal 3 NET 'BSPT_DEBUG_4' U351-V16 # L29P-2 2.5V I/O DeBug Signal 4 NET 'BSPT_DEBUG_5' U351-P16 # L07P-1 2.5V I/O DeBug Signal 5 NET 'BSPT_DEBUG_6' U351-U16 # L29N-2 2.5V I/O DeBug Signal 6 NET 'BSPT_DEBUG_7' U351-R18 # L08P-1 2.5V I/O DeBug Signal 7 NET 'BSPT_DEBUG_8' U351-U15 # L27P-2 2.5V I/O DeBug Signal 8 NET 'BSPT_DEBUG_9' U351-R17 # L08N-1 2.5V I/O DeBug Signal 9 # # SFP Optical Component Reseived Signal Lost Monitor Signals # ---------------------------------------------------------------- # # These are monitor signals from the 4 SFP optical components. # They indicate voltage HI when the SFP receiver optical signal is lost. # # The need for these SFP Receiver Signal Lost signals was added # late in the CMX design when the review committee added the idea # of doing S-Link output from the CMX. # # Note that normally these would be 3.3V CMOS signal but we are # basically out of 3.3V I/O pins on the BSPT - so we are using only # 2.5V pull-ups on these SFP open-drain signals so they will appear # as 2.5V signals to the BSPT. # NET 'SFP1_RX_LOST' U351-Y2 # SFP1 Receiver Signal Lost BSPT Bank 2 2.5V I/O NET 'SFP2_RX_LOST' U351-Y3 # SFP2 Receiver Signal Lost BSPT Bank 2 2.5V I/O NET 'SFP3_RX_LOST' U351-W4 # SFP3 Receiver Signal Lost BSPT Bank 2 2.5V I/O NET 'SFP4_RX_LOST' U351-Y4 # SFP4 Receiver Signal Lost BSPT Bank 2 2.5V I/O # # Clock Signal to the Board Support FPGA # ---------------------------------------- # # Connect the 40.08 MHz DeSkew #1 LVDS Clock Signal # to the Board Support FPGA. This is the only clock # signal to the Board Support FPGA. NET 'CLK_40MHz08_DSKW_1_BSPT_LOGIC_DIR' U351-U11 # Clock 40.08 MHz NET 'CLK_40MHz08_DSKW_1_BSPT_LOGIC_CMP' U351-V12 # DeSkew #1 LHC Locked # # Spare connections: BF to/from BSPT and TP to/from BSPT # 8 each to/from BF and TP. All 2.5V signal. All I/O pins # on the BSPT FPGA. NET 'BF_TO_FROM_BSPT_0' U351-V19 # L02P-1 2.5V I/O NET 'BF_TO_FROM_BSPT_1' U351-U19 # L06P-1 2.5V I/O NET 'BF_TO_FROM_BSPT_2' U351-U20 # L06N-1 2.5V I/O NET 'BF_TO_FROM_BSPT_3' U351-T18 # L05P-1 2.5V I/O NET 'BF_TO_FROM_BSPT_4' U351-T20 # L05N-1 2.5V I/O NET 'BF_TO_FROM_BSPT_5' U351-R19 # L09P-1 2.5V I/O NET 'BF_TO_FROM_BSPT_6' U351-R20 # L09N-1 2.5V I/O NET 'BF_TO_FROM_BSPT_7' U351-P18 # L10P-1 2.5V I/O NET 'TP_TO_FROM_BSPT_0' U351-M20 # L17N-1 2.5V I/O NET 'TP_TO_FROM_BSPT_1' U351-M19 # L17P-1 2.5V I/O NET 'TP_TO_FROM_BSPT_2' U351-M18 # L14N-1 2.5V I/O NET 'TP_TO_FROM_BSPT_3' U351-M17 # L14P-1 2.5V I/O NET 'TP_TO_FROM_BSPT_4' U351-L19 # L18P-1 2.5V I/O NET 'TP_TO_FROM_BSPT_5' U351-L18 # L18N-1 2.5V I/O NET 'TP_TO_FROM_BSPT_6' U351-L17 # L20N-1 2.5V I/O NET 'TP_TO_FROM_BSPT_7' U351-L16 # L16N-1 2.5V I/O # # Inputs for the 5-bit CMX Card Serial Number # ---------------------------------------------- # # Jumpers JMP101:JMP105 set the 5-bit CMX Card Serial Number. # These 5 jumper run from from BSPT Input-Only pins to ground. # # There are no pull-up resistors on these lines - thus the # pull-ups internal to the BSPT for these pins must be # turned on. From the Spartan 3A data sheet these internal # pull-ups should be in the range of 5.1 to 33.1 k Ohm. NET 'CMX_SERIAL_NUM_1' JMP101-1 U351-G13 # Bit 1 of the CMX Card Seril Number NET 'CMX_SERIAL_NUM_2' JMP102-1 U351-G12 # Bit 2 of the CMX Card Seril Number NET 'CMX_SERIAL_NUM_3' JMP103-1 U351-G11 # Bit 3 of the CMX Card Seril Number NET 'CMX_SERIAL_NUM_4' JMP104-1 U351-G10 # Bit 4 of the CMX Card Seril Number NET 'CMX_SERIAL_NUM_5' JMP105-1 U351-G9 # Bit 5 of the CMX Card Seril Number NET 'GROUND' JMP101-2 JMP102-2 # Ground the other NET 'GROUND' JMP103-2 JMP104-2 # side of the NET 'GROUND' JMP105-2 # jumper # # No_Conn and SPR_Conn pins on the BSPT FPGA # ------------------------------------------------ # # The following list assigns a unique net-name to each of # the unused pins on the BSPT FPGA. In theory the BGA layout # vias for all of these pins may be removed. In theory these # pins do not need to appear in the UCF pin constraints. # # Note that a few of these pin have been routed out to not # installed "SR" components so that we can attach white wires # to them if necessary. These pins have net names of the # type SPR_Conn_BSPT_Pin i.e. a spare connection. NET 'SPR_Conn_BSPT_Pin_A2' U351-A2 SR37-1 # Spare Conn BSPT Pin A2 Bank 0 2.5V I/O NET 'No_Conn_BSPT_Pin_B3' U351-B3 # No Connect BSPT Pin B3 Bank 0 2.5V I/O NET 'No_Conn_BSPT_Pin_B17' U351-B17 # No Connect BSPT Pin B17 Bank 0 2.5V I/O NET 'No_Conn_BSPT_Pin_H9' U351-H9 # No Connect BSPT Pin H9 Bank 0 2.5V In-Only NET 'No_Conn_BSPT_Pin_H10' U351-H10 # No Connect BSPT Pin H10 Bank 0 2.5V In-Only NET 'No_Conn_BSPT_Pin_F11' U351-F11 # No Connect BSPT Pin F11 Bank 0 2.5V In-Only NET 'No_Conn_BSPT_Pin_H11' U351-H11 # No Connect BSPT Pin H11 Bank 0 2.5V In-Only NET 'No_Conn_BSPT_Pin_H12' U351-H12 # No Connect BSPT Pin H12 Bank 0 2.5V In-Only NET 'No_Conn_BSPT_Pin_E14' U351-E14 # No Connect BSPT Pin E14 Bank 0 2.5V In-Only NET 'No_Conn_BSPT_Pin_F14' U351-F14 # No Connect BSPT Pin F14 Bank 0 2.5V In-Only NET 'No_Conn_BSPT_Pin_U18' U351-U18 # No Connect BSPT Pin U18 Bank 1 2.5V I/O NET 'No_Conn_BSPT_Pin_V6' U351-V6 # No Connect BSPT Pin V6 Bank 2 2.5V I/O NET 'No_Conn_BSPT_Pin_V8' U351-V8 # No Connect BSPT Pin V8 Bank 2 2.5V I/O NET 'No_Conn_BSPT_Pin_R8' U351-R8 # No Connect BSPT Pin R8 Bank 2 2.5V In-Only NET 'SPR_Conn_BSPT_Pin_B1' U351-B1 SR33-1 # Spare Conn BSPT Pin B1 Bank 3 3.3V I/O NET 'SPR_Conn_BSPT_Pin_J8' U351-J8 SR32-1 # Spare Conn BSPT Pin J8 Bank 3 3.3V In-Only NET 'SPR_Conn_BSPT_Pin_K8' U351-K8 SR31-1 # Spare Conn BSPT Pin K8 Bank 3 3.3V In-Only NET 'SPR_Conn_BSPT_Pin_M6' U351-M6 SR36-2 # Spare Conn BSPT Pin M6 Bank 3 3.3V In-Only NET 'SPR_Conn_BSPT_Pin_M7' U351-M7 SR35-2 # Spare Conn BSPT Pin M7 Bank 3 3.3V In-Only NET 'SPR_Conn_BSPT_Pin_M8' U351-M8 SR34-2 # Spare Conn BSPT Pin M8 Bank 3 3.3V In-Only