# # CMX-0 Nets File # # Board Support FPGA - Configuration Nets # ----------------------------------------- # # # Original Rev. 1-Nov-2012 # Most Recent Rev. 4-Apr-2013 # # # # This file holds the nets for all of the connections involved # involved with the Configuration of the Board Support FPGA. # # # The parts referenced in this file include: # # U351 BSPT_FPGA # U359 Configuration PROM for the BSPT_FPGA # # R321 Pullup on the BSPT_FPGA INIT_B # R322 Pullup on the BSPT_FPGA DONE # R323 Pullup on the BSPT_FPGA PROG_B # # JMP4 Allows JTAG to the Config PROM to cause configuration of the BSPT_FPGA # # JMP51:JMP56 Set the BSPT FPGA M2, M1, M0 Configuration signals # # C441:C443 Bypass Capacitors for the BSPT_FPGA Configuration PROM # # # # XCF04SVOG20C Configuration PROM Nets # # This file shows all 20 pins of the Configuration PROM. # NET 'BSPT_CONFIG_DIN' U359-1 U351-W18 # Config PROM Data to the FPGA NET 'No_Conn_CONFIG_PROM_P2' U359-2 # DNC Do Not Connect Pin #2 NET 'BSPT_CONFIG_CCLK' U359-3 U351-Y19 # CCLK from the FPGA ## NET 'CONFIG_PROM_TDI' U359-4 # see the "JTAG_Chain" n2p file ## NET 'JTAG_TMS' U359-5 # see the "JTAG_Chain" n2p file ## NET 'JTAG_TCK' U359-6 # see the "JTAG_Chain" n2p file NET 'CONFIG_PROM_CF_BAR' U359-7 # Config PROM's CF_Bar output pin, # JTAG can cause this pin to pulse # and can tie it to BSPT_FPGA PROG_B. NET 'BSPT_CONFIG_INIT_B' U359-8 U351-Y14 # Config PROM OE/RESET_BAR pin is driven # by INIT_B from the FPGA which pulses # voltage low while the FPGA is clearing # its configuration memory, this # resets the Configuration PROM. NET 'No_Conn_CONFIG_PROM_P9' U359-9 # DNC Do Not Connect Pin #9 NET 'BSPT_CONFIG_DONE' U359-10 U351-W19 # Config PROM CE_bar pin is driven by # the BSPT_FPGA DONE signal. When the # FPGA finishes configuration it drives # the PROM's CE_bar to the voltage hi, i.e. # inactive state. Power down the PROM. NET 'GROUND' U359-11 NET 'No_Conn_CONFIG_PROM_P12' U359-12 # DNC Do Not Connect Pin #12 NET 'CONFIG_PROM_CEO_BAR' U359-13 # PROM CEO_bar pin - No Connection # This pin allows the PROM to pass # CEO to the next device. NET 'No_Conn_CONFIG_PROM_P14' U359-14 # DNC Do Not Connect Pin #14 NET 'No_Conn_CONFIG_PROM_P15' U359-15 # DNC Do Not Connect Pin #15 NET 'No_Conn_CONFIG_PROM_P16' U359-16 # DNC Do Not Connect Pin #16 ## NET 'Config_PROM_TDO' U359-17 # see the "JTAG_Chain" n2p file NET 'BULK_3V3' U359-18 # Config PROM Internal 3.3V NET 'BULK_2V5' U359-19 # Config PROM Output Buf 2.5V NET 'BULK_3V3' U359-20 # Config PROM JTAG Buf 3.3V # # Bypass Capacitors on the Configuration PROM for BSPT_FPGA NET 'BULK_3V3' C441-1 C443-1 # Vcc Int Vcc JTAG 3.3V NET 'BULK_2V5' C442-1 # Vcc Config I/O 2.5V NET 'GROUND' C441-2 C442-2 C443-2 # Bypass Cap Grounds # # Jumper to allow the JTAG Config Instruction to the # Config PROM to cause the Board Support FPGA to Configure. # This is Jumper 4. I.E. Connect the CF_Bar pulse from # the Config PROM to the PROG_B pin on the BSPT FPGA. NET 'CONFIG_PROM_CF_BAR' JMP4-1 # CF_BAR signal from the Config PROM NET 'BSPT_CONFIG_PROG_B' U351-D5 JMP4-2 # PROG_B pin on the BSPT_FPGA # # Pullup Resistors on the BSPT_FPGA Configuration signals NET 'BSPT_CONFIG_INIT_B' R321-1 # Pull up on BSTP Config INIT_B pull to 2.5V NET 'BSPT_CONFIG_DONE' R322-1 # Pull up on BSTP Config DONE pull to 3.3V NET 'BSPT_CONFIG_PROG_B' R323-1 # Pull up on BSTP Config PROG_B pull to 3.3V NET 'BULK_2V5' R321-2 # Pull up to 2.5V NET 'BULK_3V3' R322-2 R323-2 # Pull up to 3.3V # # M2, M1, M0 Configuration Mode Signals for the Board Support FPGA # Set via Jumpers JMP51:JMP56 NET 'BSPT_M2' JMP51-1 JMP52-2 U351-W3 # BSPT M2 Control JMP31-JMP52 NET 'BSPT_M1' JMP53-1 JMP54-2 U351-U4 # BSPT M1 Control JMP33-JMP54 NET 'BSPT_M0' JMP55-1 JMP56-2 U351-V4 # BSPT M0 Control JMP35-JMP56 NET 'GROUND' JMP51-2 JMP53-2 JMP55-2 # Ground the Pull-Down Jumpers NET 'BULK_2V5' JMP52-1 JMP54-1 JMP56-1 # Tie the Pull-Ups to BULK_2V5