# # CMX-0 Nets File # # Board Support FPGA On-Card-Bus Nets # ----------------------------------------- # # # Original Rev. 31-Oct-2012 # Most Recent Rev. 7-Apr-2013 # # # # This file holds the nets for all connections of the On-Card-Bus # to the Board Support FPGA. # # This file is NOT the nets for the management of the OCB by the BSPT_FPGA. # # All lines in the OCB are 2.5V logic levels. All of these lines # connect to I/O Back 0 of the Spartan 3A Board Support FPGA. # I/O Bank 1 is operated with a 2.5V VCC IO. # # On the BSPT FPGA, 2.5V I/O pins have been used for the OCB # even through one could use Input-Only pins for things like # address lines. In this way, the BSPT could "master" a cycle # to the BF or TP for testing or something like that. There # were enough 2.5V I/O pins to do this and still have spares. # # On-Card_Bus Connection to BSPT FPGA Bank 0 # ---------------------------------------------- NET 'OCB_GEO_ADRS_1' U351-A4 # L29P-0 2.5V I/O NET 'OCB_GEO_ADRS_2' U351-C4 # L29N-0 2.5V I/O NET 'OCB_GEO_ADRS_3' U351-A5 # L26P-0 2.5V I/O NET 'OCB_D00' U351-B5 # L26N-0 2.5V I/O NET 'OCB_D01' U351-C5 # L28P-0 2.5V I/O NET 'OCB_D02' U351-A6 # L25P-0 2.5V I/O NET 'OCB_D03' U351-C6 # L25N-0 2.5V I/O NET 'OCB_D04' U351-D6 # L28N-0 2.5V I/O NET 'OCB_D05' U351-E6 # L31P-0 2.5V I/O NET 'OCB_D06' U351-F6 # L31N-0 2.5V I/O NET 'OCB_D07' U351-A7 # L24N-0 2.5V I/O NET 'OCB_D08' U351-B7 # L24P-0 2.5V I/O NET 'OCB_D09' U351-C7 # L21P-0 2.5V I/O NET 'OCB_D10' U351-E7 # L27P-0 2.5V I/O NET 'OCB_D11' U351-F7 # L27N-0 2.5V I/O NET 'OCB_D12' U351-A8 # L18N-0 2.5V I/O NET 'OCB_D13' U351-B8 # L20P-0 2.5V I/O NET 'OCB_D14' U351-C8 # L20N-0 2.5V I/O NET 'OCB_D15' U351-D8 # L21N-0 2.5V I/O NET 'OCB_A23' U351-E8 # L23P-0 2.5V I/O NET 'OCB_A22' U351-F8 # L23N-0 2.5V I/O NET 'OCB_A21' U351-A9 # L18P-0 2.5V I/O NET 'OCB_A20' U351-B9 # L19P-0 2.5V I/O NET 'OCB_A19' U351-C9 # L19N-0 2.5V I/O NET 'OCB_A18' U351-E9 # L22P-0 2.5V I/O NET 'OCB_A17' U351-F9 # L22N-0 2.5V I/O NET 'OCB_DS_B' U351-A10 # L16P-0 2.5V I/O NET 'OCB_WRITE_B' U351-C10 # L16N-0 2.5V I/O NET 'OCB_SYS_RESET_B' U351-D10 # L17P-0 2.5V I/O NET 'OCB_GEO_ADRS_0' U351-E10 # L17N-0 2.5V I/O NET 'OCB_GEO_ADRS_4' U351-E11 # L15N-0 2.5V I/O NET 'OCB_GEO_ADRS_5' U351-D11 # L15P-0 2.5V I/O NET 'OCB_GEO_ADRS_6' U351-C11 # L14N-0 2.5V I/O NET 'OCB_A16' U351-B11 # L14P-0 2.5V I/O NET 'OCB_A15' U351-F12 # L12N-0 2.5V I/O NET 'OCB_A14' U351-D12 # L12P-0 2.5V I/O NET 'OCB_A13' U351-C12 # L11N-0 2.5V I/O NET 'OCB_A12' U351-B12 # L13P-0 2.5V I/O NET 'OCB_A11' U351-A12 # L13N-0 2.5V I/O NET 'OCB_A10' U351-F13 # L09N-0 2.5V I/O NET 'OCB_A09' U351-E13 # L09P-0 2.5V I/O NET 'OCB_A08' U351-C13 # L10N-0 2.5V I/O NET 'OCB_A07' U351-B13 # L11P-0 2.5V I/O NET 'OCB_A06' U351-D14 # L10P-0 2.5V I/O NET 'OCB_A05' U351-C14 # L07P-0 2.5V I/O NET 'OCB_A04' U351-A14 # L07N-0 2.5V I/O NET 'OCB_A03' U351-C15 # L06N-0 2.5V I/O NET 'OCB_A02' U351-B15 # L08P-0 2.5V I/O NET 'OCB_A01' U351-A15 # L08N-0 2.5V I/O # # If the OCB signals were all layout out on one layer in # their natural order they would appear as vertical traces # running down on the East side of the BSPT, BF, and TP # FPGAs. In their natural order the signals going from # West to East are: # # GA1:GA3, D00:D15, A23:A17, DS_B, Write_B, Reset_B, # GA0, GA4:GA6, A16:A01 #