#
#                      CMX-0  Nets File
#
#      MiniPod  High-Speed Optical  Control and Monitor  Nets
#     -=======------------------------------------------------
#
#
#                                                 Original Rev.   4-Dec-2012
#                                              Most Recent Rev.  25-Mar-2013
#
#
#
#  This file holds the Board Control FPGA end of all of the
#  nets for the  Control and Monitor of both the 5 MiniPod
#  High-Speed Optical Components  and  the 4 Low-Speed SFP
#  optical comoonents.
#
#  High-Speed MiniPod Optical Components:
#
#    Recall that there are 2 MiniPod Transmitters, MP1 and MP2,
#    that are associated with the Base Function FPGA.
#
#    Recall that there are 3 MiniPod Receivers, MP3, MP4, and MP5
#    that are associated with the Topological Processor FPGA.
#
#    All of the MiniPod components receive a Two Wire Serial
#    Control and Monitoring Bus.  There are separate TWS Buses
#    for the Base Function MiniPod Transmitters  and  for the
#    Topological Processor MiniPod Receivers.  These 2 TWS
#    Buses run to the Board Support FPGA.
#
#    In addition there is a separate Interrupt_B signal from
#    each of the 5 MiniPod components that runs to the Board
#    Support FPGA.  From the Board Support FPGA there is a
#    Reset_B signal that runs to the 2 MiniPod Transmitters
#    and a separate Reset_B signal that runs to the 3 MiniPod
#    Receivers.
#
#
#  Low-Speed SFP Optical Components
#
#
#
#  The components that are involved with these nets include:
#
#
#
#



#
#     Low-Spped Optical Component  Control and Monitoring Nets
#    ----------------------------------------------------------
#

#   SFP1  Control and Monitoring Signals

NET  'SFP1_TX_FAULT'        U351-G6    # SFP1 Transmitter Fault    3.3V Input-Only
NET  'SFP1_TX_DISABLE'      U351-L1    # SFP1 Transmitter Disable  3.3V Output
NET  'SFP1_MOD_SER_DATA'    U351-M5    # SFP1 2 Wire Serial Data   3.3V I/O
NET  'SFP1_MOD_SER_CLK'     U351-M4    # SFP1 2 Wire Serial Clock  3.3V Output
NET  'SFP1_MOD_PRESENT'     U351-H7    # SFP1 Module Present->Low  3.3V Input-Only


#   SFP2  Control and Monitoring Signals

NET  'SFP2_TX_FAULT'        U351-J7    # SFP2 Transmitter Fault    3.3V Input-Only
NET  'SFP2_TX_DISABLE'      U351-M3    # SFP2 Transmitter Disable  3.3V Output
NET  'SFP2_MOD_SER_DATA'    U351-M2    # SFP2 2 Wire Serial Data   3.3V I/O
NET  'SFP2_MOD_SER_CLK'     U351-M1    # SFP2 2 Wire Serial Clock  3.3V Output
NET  'SFP2_MOD_PRESENT'     U351-K7    # SFP2 Module Present->Low  3.3V Input-Only


#   SFP3  Control and Monitoring Signals

NET  'SFP3_TX_FAULT'        U351-K6    # SFP3 Transmitter Fault    3.3V Input-Only
NET  'SFP3_TX_DISABLE'      U351-N2    # SFP3 Transmitter Disable  3.3V Output
NET  'SFP3_MOD_SER_DATA'    U351-N1    # SFP3 2 Wire Serial Data   3.3V I/O
NET  'SFP3_MOD_SER_CLK'     U351-P4    # SFP3 2 Wire Serial Clock  3.3V Output
NET  'SFP3_MOD_PRESENT'     U351-K5    # SFP3 Module Present->Low  3.3V Input-Only


#   SFP4  Control and Monitoring Signals

NET  'SFP4_TX_FAULT'        U351-L7    # SFP4 Transmitter Fault    3.3V Input-Only
NET  'SFP4_TX_DISABLE'      U351-P3    # SFP4 Transmitter Disable  3.3V Output
NET  'SFP4_MOD_SER_DATA'    U351-P1    # SFP4 2 Wire Serial Data   3.3V I/O
NET  'SFP4_MOD_SER_CLK'     U351-R5    # SFP4 2 Wire Serial Clock  3.3V Output
NET  'SFP4_MOD_PRESENT'     U351-L6    # SFP4 Module Present->Low  3.3V Input-Only






#
#    High-Spped Optical Component  Control and Monitoring Nets
#   -----------------------------------------------------------
#

#
#    MiniPods 1 and 2    Transmitters for the Base Function FPGA
#   ------------------

#  MiniPods 1,2  TWS Serial Data

NET  'MP12_SDA'       U351-R4      # SDA connection to the BSPT   3.3V I/O
NET  'MP12_SDA'       R371-1       # Pull-Up for default Serial Data state
NET  'BULK_3V3'       R371-2       # Pull-Up to 3.3V connection


#  MiniPods 1,2  TWS Serail Clock

NET  'MP12_SCL'       U351-T1      # SCL connection to the BSPT   3.3V Output
NET  'MP12_SCL'       R372-1       # Pull-Up for default Serial Clock state
NET  'BULK_3V3'       R372-2       # Pull-Up to 3.3V connection


#
#  MiniPods 1,2  Reset_B  Signal

NET  'MP12_RESET_B'   U351-T2      # MiniPods 1,2  Reset_B    3.3V Output
NET  'MP12_RESET_B'   R373-1       # Pull-Up for default RESET_B state
NET  'BULK_3V3'       R373-2       # Pull-Up to 3.3V connection


#
#  MiniPod #1  Connections for Interrupt_B

NET  'MP1_INTRPT_B'   U351-P7      # MP1 Interrupt_B   3.3V In-Only pin


#
#  MiniPod #2  Connections for Interrupt_B

NET  'MP2_INTRPT_B'   U351-P6      # MP2 Interrupt_B   3.3V In-Only pin





#
#    MiniPods 3,4,5    Receivers for the Topological Processor FPGA
#   ----------------

#  MiniPods 3,4,5  TWS Serial Data

NET  'MP345_SDA'       U351-R1     # SDA connection to the BSPT   3.3V I/O
NET  'MP345_SDA'       R374-1      # Pull-Up for default Serial Data state
NET  'BULK_3V3'        R374-2      # Pull-Up to 3.3V connection


#  MiniPods 3,4,5  TWS Serail Clock

NET  'MP345_SCL'       U351-R2     # SCL connection to the BSPT   3.3V Output
NET  'MP345_SCL'       R375-1      # Pull-Up for default Serial Clock state
NET  'BULK_3V3'        R375-2      # Pull-Up to 3.3V connection


#
#  MiniPods 3,4,5  Reset_B  Signal

NET  'MP345_RESET_B'   U351-R3     # MiniPods 3,4,5  Reset_B    3.3V Output
NET  'MP345_RESET_B'   R376-1      # Pull-Up for default RESET_B state
NET  'BULK_3V3'        R376-2      # Pull-Up to 3.3V connection


#
#  MiniPod #3  Connections for Interrupt_B

NET  'MP3_INTRPT_B'   U351-P5      # MP3 Interrupt_B   3.3V In-Only pin


#
#  MiniPod #4  Connections for Interrupt_B

NET  'MP4_INTRPT_B'   U351-N7      # MP4 Interrupt_B   3.3V In-Only pin


#
#  MiniPod #5  Connections for Interrupt_B

NET  'MP5_INTRPT_B'   U351-N6      # MP5 Interrupt_B   3.3V In-Only pin