# # CMX-0 Nets File # # BSPT_FPGA System-ACE Nets # -------------==========-------- # # # Original Rev. 13-Nov-2012 # Most Recent Rev. 7-July-2013 # # # # This file holds all of the nets that connect the # Board Support FPGA with the System-ACE chip. # # # Notes: # # - In the System-ACE documents this is typically called # the MPU connection to the System-ACE. # # - All of these MPU connections with the System-ACE # are 2.5V CMOS signal levels. # # - Note that the BSPT FPGA supplies the 20 MHz clock # to the MPU Port of the System-ACE. In this way # the activities in the BSPT FPGA that talk to the # MPU Port can be synchronous with the clock that # goes to the ACE MPU Port. This is a 20 MHz # 2.5V CMOS signal. # # - After these MPU connections this file will then # include some FPGA Configuration management signal # connections with the System-ACE. These are also # handled by the Board Support FPGA and are 2.5V # signals. # # - The MPU signals between the System-ACE and the BSPT # FPGA are series terminated near the BSPT. The # bi-directional MPU data lines are series terminated # at both ends. # # # The components referenced in this file include: # # U321 the System-ACE # U351 the BSPT_FPGA # # N361:N366 8 Resistor 47 Ohm Networks # # # All of these BSPT pins are 2.5V I/O except for # 3 pins that are 2.5V Input-Only: # # ACE_MPIRQ is U351-P9 2.5V In-Only # ACE_MPBRDY is U351-N9 2.5V In-Only # ACE_CFG_INIT_B is U351-P8 2.5V In-Only # # # A rational order in which to land the System-ACE signals # in Bank #2 of the BSPT FPGA starting in the S.W. corner # is the following: # # BSPT_ACE_CLK, ACE_ERRLED_B, ACE_STATLED_B, # ACE_CFG_MODE, # ACE_CFG_ADRS_2, ACE_CFG_ADRS_1, ACE_CFG_ADRS_0, # ACE_CFG_INIT_B, # ACE_MPOE_B, ACE_MPWE_B, # ACE_MP_ADRS_0, ACE_MP_ADRS_1, ACE_MP_ADRS_2, ACE_MP_ADRS_3, # ACE_MP_DATA_00, ACE_MP_DATA_01, ACE_MP_DATA_02, ACE_MP_DATA_03, # ACE_MP_DATA_04, ACE_MP_DATA_05, ACE_MP_DATA_06, ACE_MP_DATA_07, # ACE_MP_DATA_08, ACE_MP_DATA_09, ACE_MP_DATA_10, ACE_MP_DATA_11, # ACE_MP_DATA_12, ACE_MP_DATA_13, ACE_MP_DATA_14, ACE_MP_DATA_15, # ACE_MP_ADRS_4, ACE_MP_ADRS_5, ACE_MP_ADRS_6, ACE_MPCE_B' # ACE_MPIRQ, ACE_MPBRDY, # ACE_RESET_B' # # # The signals that need series termination between the # System-ACE and the BSPT FPGA are the following: # # BSPT_ACE_CLK, # # ACE_MPOE_B, ACE_MPWE_B, ACE_MPCE_B', ACE_MPIRQ, ACE_MPBRDY # # ACE_MP_ADRS_0, ACE_MP_ADRS_1, ACE_MP_ADRS_2, ACE_MP_ADRS_3, # ACE_MP_ADRS_4, ACE_MP_ADRS_5, ACE_MP_ADRS_6, # # ACE_MP_DATA_00, ACE_MP_DATA_01, ACE_MP_DATA_02, ACE_MP_DATA_03, # ACE_MP_DATA_04, ACE_MP_DATA_05, ACE_MP_DATA_06, ACE_MP_DATA_07, # ACE_MP_DATA_08, ACE_MP_DATA_09, ACE_MP_DATA_10, ACE_MP_DATA_11, # ACE_MP_DATA_12, ACE_MP_DATA_13, ACE_MP_DATA_14, ACE_MP_DATA_15 # # # MPU Connections between BSPT_FPGA and the System-ACE # ------------------------------------------------------ # # System-ACE Clock Generated by the BSPT FPGA 20 MHz 2.5V CMOS NET 'BSPT_ACE_CLK' U351-V14 # 20 MHz Clock signal to the System-ACE # # Define some Control, Status, and LED pins on the System-ACE NET 'ACE_RESET_B' U351-W14 # System-ACE RESET input Vccl Int_PU NET 'ACE_STATLED_B' U351-T6 # System-ACE Status LED output pin open-drain NET 'ACE_ERRLED_B' U351-U6 # System-ACE Error LED output pin open-drain # # Define the MPU interface pins on the System-ACE # NET 'BSPT_ACE_MPCE_B' U351-W6 # System-ACE MP Chip Enable _B input Vccl Int_PU NET 'BSPT_ACE_MPWE_B' U351-R7 # System-ACE MP Write Enable _B input Vccl Int_PU NET 'BSPT_ACE_MPOE_B' U351-W8 # System-ACE MP Output Enable _B input Vccl Int_PU NET 'BSPT_ACE_MPIRQ' U351-N9 # System-ACE MP Interrupt Request output Vccl In-Only NET 'BSPT_ACE_MPBRDY' U351-P9 # System-ACE MP Data Buffer Ready output Vccl In-Only NET 'BSPT_ACE_MP_ADRS_0' U351-Y13 # System-ACE MP Address 0 input Vccl NET 'BSPT_ACE_MP_ADRS_1' U351-T14 # System-ACE MP Address 1 input Vccl NET 'BSPT_ACE_MP_ADRS_2' U351-W13 # System-ACE MP Address 2 input Vccl NET 'BSPT_ACE_MP_ADRS_3' U351-V9 # System-ACE MP Address 3 input Vccl NET 'BSPT_ACE_MP_ADRS_4' U351-W9 # System-ACE MP Address 4 input Vccl NET 'BSPT_ACE_MP_ADRS_5' U351-Y9 # System-ACE MP Address 5 input Vccl NET 'BSPT_ACE_MP_ADRS_6' U351-T8 # System-ACE MP Address 6 input Vccl NET 'BSPT_ACE_MP_DATA_00' U351-V13 # System-ACE MP Data 00 in/out Vccl NET 'BSPT_ACE_MP_DATA_01' U351-U13 # System-ACE MP Data 01 in/out Vccl NET 'BSPT_ACE_MP_DATA_02' U351-T13 # System-ACE MP Data 02 in/out Vccl NET 'BSPT_ACE_MP_DATA_03' U351-R13 # System-ACE MP Data 03 in/out Vccl NET 'BSPT_ACE_MP_DATA_04' U351-Y12 # System-ACE MP Data 04 in/out Vccl NET 'BSPT_ACE_MP_DATA_05' U351-W12 # System-ACE MP Data 05 in/out Vccl NET 'BSPT_ACE_MP_DATA_06' U351-T12 # System-ACE MP Data 06 in/out Vccl NET 'BSPT_ACE_MP_DATA_07' U351-R12 # System-ACE MP Data 07 in/out Vccl NET 'BSPT_ACE_MP_DATA_08' U351-Y11 # System-ACE MP Data 08 in/out Vccl NET 'BSPT_ACE_MP_DATA_09' U351-V11 # System-ACE MP Data 09 in/out Vccl NET 'BSPT_ACE_MP_DATA_10' U351-T10 # System-ACE MP Data 10 in/out Vccl NET 'BSPT_ACE_MP_DATA_11' U351-U10 # System-ACE MP Data 11 in/out Vccl NET 'BSPT_ACE_MP_DATA_12' U351-V10 # System-ACE MP Data 12 in/out Vccl NET 'BSPT_ACE_MP_DATA_13' U351-W10 # System-ACE MP Data 13 in/out Vccl NET 'BSPT_ACE_MP_DATA_14' U351-T9 # System-ACE MP Data 14 in/out Vccl NET 'BSPT_ACE_MP_DATA_15' U351-U9 # System-ACE MP Data 15 in/out Vccl # # Define signals that control FPGA Configuration by the System-ACE # NET 'ACE_CFG_INIT_B' U351-P8 # Sys-ACE Configuration JTAG INIT input Vccl NET 'ACE_CFG_ADRS_0' U351-T7 # Sys-ACE Config Address Select 0 input Vccl Init_PD NET 'ACE_CFG_ADRS_1' U351-Y7 # Sys-ACE Config Address Select 1 input Vccl Init_PD NET 'ACE_CFG_ADRS_2' U351-V7 # Sys-ACE Config Address Select 2 input Vccl Init_PD NET 'ACE_CFG_MODE' U351-U7 # Sys-ACE Config Mode Pin input Vccl Init_PU # # Define the connections through the Series Terminator # Resistor Networks N361 : N364 # # Resistor Network N361 Clock and Control Signals: NET 'GROUND' N361-16 # Guard NET 'GROUND' N361-1 # Guard NET 'BSPT_ACE_MPCE_B' N361-15 # BSPT ACE Clock Output to NET 'ACE_MPCE_B' N361-2 # run to the System-ACE NET 'GROUND' N361-14 # Guard the Clock signal NET 'GROUND' N361-3 # Guard the Clock signal NET 'BSPT_ACE_MPWE_B' N361-13 # MPWE_B from the BSPT NET 'ACE_MPWE_B' N361-4 # to the System-ACE NET 'GROUND' N361-12 # Guard NET 'GROUND' N361-5 # Guard NET 'BSPT_ACE_MPOE_B' N361-11 # MPOE_B from the BSPT NET 'ACE_MPOE_B' N361-6 # to the System-ACE NET 'GROUND' N361-10 # Guard NET 'GROUND' N361-7 # Guard NET 'BSPT_ACE_CLK' N361-9 # MPCE_B from the BSPT NET 'ACE_CLOCK' N361-8 # to the System-ACE # Resistor Network N362 MPU Address Lines: NET 'BSPT_ACE_MP_ADRS_6' N362-16 # MP_ADRS_6 from BSPT NET 'ACE_MP_ADRS_6' N362-1 # to the System-ACE NET 'BSPT_ACE_MP_ADRS_5' N362-15 # MP_ADRS_5 from BSPT NET 'ACE_MP_ADRS_5' N362-2 # to the System-ACE NET 'BSPT_ACE_MP_ADRS_4' N362-14 # MP_ADRS_4 from BSPT NET 'ACE_MP_ADRS_4' N362-3 # to the System-ACE NET 'BSPT_ACE_MP_ADRS_3' N362-13 # MP_ADRS_3 from BSPT NET 'ACE_MP_ADRS_3' N362-4 # to the System-ACE NET 'GROUND' N362-12 # Guard NET 'GROUND' N362-5 # Guard NET 'BSPT_ACE_MP_ADRS_2' N362-11 # MP_ADRS_2 from BSPT NET 'ACE_MP_ADRS_2' N362-6 # to the System-ACE NET 'BSPT_ACE_MP_ADRS_0' N362-10 # MP_ADRS_0 from BSPT NET 'ACE_MP_ADRS_0' N362-7 # to the System-ACE NET 'BSPT_ACE_MP_ADRS_1' N362-9 # MP_ADRS_1 from BSPT NET 'ACE_MP_ADRS_1' N362-8 # to the System-ACE # Resistor Network N363 Hi Order MPU Data Lines: # at the BSPT FPGA end of the data lines: NET 'BSPT_ACE_MP_DATA_15' N363-16 # MP_DATA_15 BSPT NET 'LINE_ACE_MP_DATA_15' N363-1 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_14' N363-15 # MP_DATA_14 BSPT NET 'LINE_ACE_MP_DATA_14' N363-2 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_13' N363-14 # MP_DATA_13 BSPT NET 'LINE_ACE_MP_DATA_13' N363-3 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_12' N363-13 # MP_DATA_12 BSPT NET 'LINE_ACE_MP_DATA_12' N363-4 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_11' N363-12 # MP_DATA_11 BSPT NET 'LINE_ACE_MP_DATA_11' N363-5 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_10' N363-11 # MP_DATA_10 BSPT NET 'LINE_ACE_MP_DATA_10' N363-6 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_09' N363-10 # MP_DATA_09 BSPT NET 'LINE_ACE_MP_DATA_09' N363-7 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_08' N363-9 # MP_DATA_08 BSPT NET 'LINE_ACE_MP_DATA_08' N363-8 # to/from the System-ACE # Resistor Network N364 Low Order MPU Data Lines # at the BSPT FPGA end of the data lines: NET 'BSPT_ACE_MP_DATA_07' N364-16 # MP_DATA_07 BSPT NET 'LINE_ACE_MP_DATA_07' N364-1 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_06' N364-15 # MP_DATA_06 BSPT NET 'LINE_ACE_MP_DATA_06' N364-2 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_05' N364-14 # MP_DATA_05 BSPT NET 'LINE_ACE_MP_DATA_05' N364-3 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_04' N364-13 # MP_DATA_04 BSPT NET 'LINE_ACE_MP_DATA_04' N364-4 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_03' N364-12 # MP_DATA_03 BSPT NET 'LINE_ACE_MP_DATA_03' N364-5 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_02' N364-11 # MP_DATA_02 BSPT NET 'LINE_ACE_MP_DATA_02' N364-6 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_01' N364-10 # MP_DATA_01 BSPT NET 'LINE_ACE_MP_DATA_01' N364-7 # to/from the System-ACE NET 'BSPT_ACE_MP_DATA_00' N364-9 # MP_DATA_00 BSPT NET 'LINE_ACE_MP_DATA_00' N364-8 # to/from the System-ACE