# # CMX-0 Nets File # # # Clock Distribution Nets # --------------------------- # # # Original Rev. 17-Nov-2012 # Most Recent Rev. 16-July-2013 # # # # Starting on 2-July-2013 move the design to using Connor # Winfiled SFX-524G PLLs. # # This file originally held the nets that distribute a single # 40 MHz and a somg;e 320 MHz Clock both locked to the LHC to # the various Logic and GTX Transceivers on the CMX card. # # In the CMX prototype review the clock requirements were # expanded to include 2 phases of 40.08 MHz LHC clock, a # 320.64 MHz LHC clock, and 2 local crystal oscillator based # clocks (as well as the ACE and CAN-Bus micro-processor # clocks). This file now includes the generation and # distribution of both the LHC locked and the local crystal # oscillator based clocks. # # The list of generators, distributors, and consumers of the # various clock signals is best understood by studying the # drawing named "26_clocks_overall_view.pdf" in the circuit # diagrams section of the CMX web site. The clocks handled # by this file will just be listed here: # # 40.08 MHz LHC DeSkew-1 Logic Clock to BSPT, BF, TP, and # reference for the 320.64 MHz clock # # 40.08 MHz LHC DeSkew-2 Logic Clock to the BF and TP # # 320.64 MHz LHC Logic and GTX clock to Bf and TP # # 40.000 MHz Crystal Oscillator #1 GTX Clock to BF # # 40.000 or 100.000 MHz Crystal Oscillator #2 GTX Clock # to BF and TP # # Note that all Logic Clks are LVDS and all GTX Clks are LVPECL. # # # # The major ICs involved in the new Clock Generation and # Distribution system on the CMX card are the following: # # Crystal Oscillator #1 U371 typically 40.000 MHz # Fanout for above U372 NB6L611 # # Crystal Oscillator #2 U373 typically 40.000/100.000 MHz # Fanout for above U374 NB6L611 # # PLL 320.6296 MHz U375 Connor-Winfield SFX-524G-CRN2 # Fanout for above U376 MC100LVEP111 # # PLL 40.0787 MHz DeSkew-1 U377 Connor-Winfield SFX-524G-CRN1 # Fanout for above U378 MC100LVEP111 # # PLL 40.0787 MHz DeSkew-2 U379 Connor-Winfield SFX-524G-CRN1 # Fanout for above U380 NB6L611 # # # First take care of the direct Power and Ground connections # to these IC and to their bypass capacitors. Note that all # of these components are powered from the filtered CLK_3V3 # power plane. # Crystal Oscillator #1 U371 typically 40.000 MHz NET 'CLK_3V3' U371-6 C1421-2 C1422-1 NET 'GROUND' U371-3 C1421-1 C1422-2 # Fanout for above U372 NB6L611 NET 'CLK_3V3' U372-5 U372-8 U372-13 U372-16 NET 'GROUND' U372-7 U372-14 U372-15 U372-17 U372-18 U372-19 U372-20 NET 'CLK_3V3' C1423-1 C1424-2 NET 'GROUND' C1423-2 C1424-1 # Crystal Oscillator #2 U373 typically 40.000/100.000 MHz NET 'CLK_3V3' U373-6 C1425-2 C1426-1 NET 'GROUND' U373-3 C1425-1 C1426-2 # Fanout for above U374 NB6L611 NET 'CLK_3V3' U374-5 U374-8 U374-13 U374-16 NET 'GROUND' U374-7 U374-14 U374-15 U374-17 U374-18 U374-19 U374-20 NET 'CLK_3V3' C1427-1 C1428-2 NET 'GROUND' C1427-2 C1428-1 # PLL 320.6296 MHz U375 Connor-Winfield SFX-524G-CRN2 NET 'CLK_3V3' U375-9 C1429-2 C1430-2 NET 'GROUND' U375-2 U375-8 C1429-1 C1430-1 # Fanout for above U376 MC100LVEP111 NET 'CLK_3V3' U376-1 U376-9 U376-16 U376-25 U376-32 NET 'GROUND' U376-8 U376-33 U376-34 U376-35 U376-36 NET 'CLK_3V3' C1431-1 C1432-2 NET 'GROUND' C1431-2 C1432-1 # PLL 40.0787 MHz DeSkew-1 U377 Connor-Winfield SFX-524G-CRN1 NET 'CLK_3V3' U377-9 C1433-2 C1434-2 NET 'GROUND' U377-2 U377-8 C1433-1 C1434-1 # Fanout for above U378 MC100LVEP111 NET 'CLK_3V3' U378-1 U378-9 U378-16 U378-25 U378-32 NET 'GROUND' U378-8 U378-33 U378-34 U378-35 U378-36 NET 'CLK_3V3' C1435-1 C1436-2 NET 'GROUND' C1435-2 C1436-1 # PLL 40.0787 MHz DeSkew-2 U379 Connor-Winfield SFX-524G-CRN1 NET 'CLK_3V3' U379-9 C1437-2 C1438-2 NET 'GROUND' U379-2 U379-8 C1437-1 C1438-1 # Fanout for above U380 NB6L611 NET 'CLK_3V3' U380-5 U380-8 U380-13 U380-16 NET 'GROUND' U380-7 U380-14 U380-15 U380-17 U380-18 U380-19 U380-20 NET 'CLK_3V3' C1439-1 C1440-2 NET 'GROUND' C1439-2 C1440-1 # # Now include the L30 filter inductor for the CLK_3V3 # and its tantalum and distributed ceramic capacitors. NET 'CLK_3V3' L30-2 # Connection to Clk_Gen Power Bus NET 'BULK_3V3' L30-1 # Connection to Bulk 3.3V Power NET 'CLK_3V3' C1441-1 C1442-2 C1443-1 C1444-2 C1445-1 NET 'GROUND' C1441-2 C1442-1 C1443-2 C1444-1 C1445-2 NET 'CLK_3V3' C1446-1 C1447-1 C1448-1 NET 'GROUND' C1446-2 C1447-2 C1448-2 # # Now include all of the nets associated with the # Crystal Oscillator #1 and its distribution. # Pull-Up on the Crystal Osc #1 Enable pin. NET 'ENABLE_XTAL_OSC_1' U371-1 R471-1 # Xtal Osc #1 Enable Pull-Up NET 'CLK_3V3' R471-2 # Pull-Up Resistor to 3.3V # Couple the Xtal Osc #1 output to its Fanout chip input NET 'XTAL_OSC_1_OUT_DIR' U371-4 R456-2 U372-3 # Xtal Osc #1 DIR Output FO CMP In NET 'XTAL_OSC_1_OUT_CMP' U371-5 R455-2 U372-2 # Xtal Osc #1 CMP Output FO DIR In NET 'GROUND' R455-1 R456-1 # Pull-Down Resistors NET 'TERMINATOR_TIE_U372' U372-1 U372-4 # Connect the U372 Terminator. # The Vbb pin on U372 a NB6L611 fanout pin #6 is No_Conn. NET 'No_Conn_U372_VBB_PIN_6' U372-6 # No Conn U372 Vbb pin #6. # Outputs from the Xtal Osc #1 Fanout, Outputs 0 and 1 NET 'XTAL_OSC_1_FO_0_DIR' U372-12 R401-1 C1401-1 # Xtal Osc #1 Fanout #0 DIR NET 'XTAL_OSC_1_FO_0_CMP' U372-11 R402-1 C1402-1 # Xtal Osc #1 Fanout #0 CMP NET 'GROUND' R401-2 R402-2 # Pull-Down Resistors NET 'XTAL_OSC_1_FO_1_DIR' U372-10 R403-1 C1403-1 # Xtal Osc #1 Fanout #1 DIR NET 'XTAL_OSC_1_FO_1_CMP' U372-9 R404-1 C1404-1 # Xtal Osc #1 Fanout #1 CMP NET 'GROUND' R403-2 R404-2 # Pull-Down Resistors NET 'CLK_40MHz000_XTAL_1_BF_TRNCV_DIR' C1401-2 # 40.000 MHz Crystal Osc #1 NET 'CLK_40MHz000_XTAL_1_BF_TRNCV_CMP' C1402-2 # GTX Clk to the BF FPGA # Transmitter QUAD 118 # # Now include all of the nets associated with the # Crystal Oscillator #2 and its distribution. # Pull-Up on the Crystal Osc #2 Enable pin. NET 'ENABLE_XTAL_OSC_2' U373-1 R472-1 # Xtal Osc #2 Enable Pull-Up NET 'CLK_3V3' R472-2 # Pull-Up Resistor to 3.3V # Couple the Xtal Osc #2 output to its Fanout chip input NET 'XTAL_OSC_2_OUT_DIR' U373-4 R458-2 U374-3 # Xtal Osc #2 DIR Output FO CMP In NET 'XTAL_OSC_2_OUT_CMP' U373-5 R457-2 U374-2 # Xtal Osc #2 CMP Output FO DIR In NET 'GROUND' R457-1 R458-1 # Pull-Down Resistors NET 'TERMINATOR_TIE_U374' U374-1 U374-4 # Connect the U374 Terminator. # The Vbb pin on U374 a NB6L611 fanout pin #6 is No_Conn. NET 'No_Conn_U374_VBB_PIN_6' U374-6 # No Conn U374 Vbb pin #6. # Outputs from the Xtal Osc #2 Fanout, Outputs 0 and 1 NET 'XTAL_OSC_2_FO_0_DIR' U374-12 R405-1 C1405-1 # Xtal Osc #2 Fanout #0 DIR NET 'XTAL_OSC_2_FO_0_CMP' U374-11 R406-1 C1406-1 # Xtal Osc #2 Fanout #0 CMP NET 'GROUND' R405-2 R406-2 # Pull-Down Resistors NET 'XTAL_OSC_2_FO_1_DIR' U374-10 R407-1 C1407-1 # Xtal Osc #2 Fanout #1 DIR NET 'XTAL_OSC_2_FO_1_CMP' U374-9 R408-1 C1408-1 # Xtal Osc #2 Fanout #1 CMP NET 'GROUND' R407-2 R408-2 # Pull-Down Resistors NET 'CLK_100MHz000_XTAL_2_TP_TRNCV_DIR' C1405-2 # 100.000 MHz Crystal Osc #2 NET 'CLK_100MHz000_XTAL_2_TP_TRNCV_CMP' C1406-2 # GTX Clk to the TP FPGA. # Transmitter QUAD 110 NET 'CLK_100MHz000_XTAL_2_BF_TRNCV_DIR' C1407-2 # 100.000 MHz Crystal Osc #2 NET 'CLK_100MHz000_XTAL_2_BF_TRNCV_CMP' C1408-2 # GTX Clk to the BF FPGA # Transmitter QUAD 117 # # Now include all of the nets associated with the # 40.08 MHz DeSkew-2 clock signal and its distribution. # -------=== # Connect the TTCDec DeSkew-2 output from R255 to # the 40.0787 MHz PLL reference clock input NET 'PLL_DESKEW_2_FIN' R255-1 U379-1 # DeSkew 2 PLL FIn pin # Connor-Winfield SFX-524G Reset pin NET 'No_Conn_U379_3' U379-3 # Float this pin --> Not Reseting the PLL. # Connor-Winfield SFX-524G No Connect pins NET 'No_Conn_U379_4' U379-4 # SFX-524G No Connect Pin Number 4. NET 'No_Conn_U379_5' U379-5 # SFX-524G No Connect Pin Number 5. # 40.08 MHz DeSkew-2 PLL Outputs to the U380 Fanout chip NET 'PLL_DESKEW_2_OUT_DIR' U379-6 R469-2 U380-2 # PLL DeSkew 2 Output DIR NET 'PLL_DESKEW_2_OUT_CMP' U379-7 R470-2 U380-3 # PLL DeSkew 2 Output CMP NET 'GROUND' R469-1 R470-1 # Pull-Down Resistors NET 'TERMINATOR_TIE_U380' U380-1 U380-4 # Connect the U380 Terminator. # The Vbb pin on U380 a NB6L611 fanout pin #6 is No_Conn. NET 'No_Conn_U380_VBB_PIN_6' U380-6 # No Conn U380 Vbb pin #6. # Outputs from the PLL DeSkew 2 Fanout, Outputs 0 and 1 NET 'PLL_DESKEW_2_FO_0_DIR' U380-12 R447-1 # DeSkew 2 PLL Fanout #0 DIR NET 'PLL_DESKEW_2_FO_0_CMP' U380-11 R448-1 # DeSkew 2 PLL Fanout #0 CMP NET 'PLL_DESKEW_2_FO_1_DIR' U380-10 R451-1 # DeSkew 2 PLL Fanout #1 DIR NET 'PLL_DESKEW_2_FO_1_CMP' U380-9 R452-1 # DeSkew 2 PLL Fanout #1 CMP # Fanout outputs connected to the consumers of PLL DeSkew 2 clock signals. NET 'CLK_40MHz08_DSKW_2_TP_LOGIC_DIR' R447-2 R449-2 # 40.08 MHz DSK-2 LHC Logic NET 'CLK_40MHz08_DSKW_2_TP_LOGIC_CMP' R448-2 R450-2 # Clk to the Topological FPGA NET 'CLK_40MHz08_DSKW_2_BF_LOGIC_DIR' R451-2 R453-2 # 40.08 MHz DSK-2 LHC Logic NET 'CLK_40MHz08_DSKW_2_BF_LOGIC_CMP' R452-2 R454-2 # Clk to the Base Function FPGA # Ground the attenuator resistors on the PLL DeSkew 2 fanout clock signals. NET 'GROUND' R449-1 R450-1 # Attenuator Pull-Down Resistors NET 'GROUND' R453-1 R454-1 # Attenuator Pull-Down Resistors # # Now include all of the nets associated with the # 40.08 MHz DeSkew-1 clock signal and its distribution. # -------=== # Connect the TTCDec DeSkew-1 output from either R254 or # R256 the 40.0787 MHz DeSkew-1PLL reference clock input. NET 'PLL_DESKEW_1_FIN' R254-1 U377-1 # DeSkew 1 PLL FIn pin NET 'PLL_DESKEW_1_FIN' R256-1 # Connor-Winfield SFX-524G Reset pin NET 'No_Conn_U377_3' U377-3 # Float this pin --> Not Reseting the PLL. # Connor-Winfield SFX-524G No Connect pins NET 'No_Conn_U377_4' U377-4 # SFX-524G No Connect Pin Number 4. NET 'No_Conn_U377_5' U377-5 # SFX-524G No Connect Pin Number 5. # 40.08 MHz DeSkew-1 PLL Outputs to the U378 Fanout chip NET 'PLL_DESKEW_1_OUT_DIR' U377-6 U378-3 # PLL DeSkew 1 Output DIR NET 'PLL_DESKEW_1_OUT_CMP' U377-7 U378-4 # PLL DeSkew 1 Output CMP NET 'PLL_DESKEW_1_OUT_DIR' R465-2 R463-2 # PLL DeSkew 1 Output DIR NET 'PLL_DESKEW_1_OUT_CMP' R466-2 R464-2 # PLL DeSkew 1 Output CMP NET 'GROUND' R465-1 R466-1 # Pull-Down Resistors NET 'CLK_3V3' R463-1 R464-1 # Term to Clk 3.3V # Pull-Down on the Input Select pin of the U378 MC100LVEP111 # Fanout chip ship so that it will use its CLK0 & CLK0_B input # pins. Also No-Conn its Vbb reference pin and its CLK1 pins. NET 'SELECT_INPUT_0_U378_FO' U378-2 R474-2 # U378 Select Pull-Down NET 'GROUND' R474-1 # Ground the Pull-Down NET 'No_Conn_U378_VBB_PIN_5' U378-5 # Unused Vbb Reference NET 'No_Conn_U378_CLK1_PIN_6' U378-6 # Unused CLK1 NET 'No_Conn_U378_CLK1_B_PIN_7' U378-7 # Unused CLK_B # Output 0 from the PLL DeSkew 1 Fanout, to the 320.64 MHz PLL NET 'PLL_DESKEW_1_FO_0_DIR' U378-31 U375-1 # DeSkew 1 PLL Fanout #0 DIR # runs to the 320 MHZ PLL FIN NET 'PLL_DESKEW_1_FO_0_CMP' U378-30 # DeSkew 1 PLL Fanout #0 CMP NET 'PLL_DESKEW_1_FO_0_DIR' R430-2 R432-2 # PLL DeSkew 1 FanOut #0 DIR NET 'PLL_DESKEW_1_FO_0_CMP' R429-2 R431-2 # PLL DeSkew 1 FanOut #0 CMP NET 'GROUND' R430-1 R429-1 # Pull-Down Resistors NET 'CLK_3V3' R432-1 R431-1 # Term to Clk 3.3V # Output 1 and 2 from the PLL DeSkew 1 # Fanout are not connected. NET 'No_Conn_PLL_DESKEW_1_FO_1_DIR' U378-29 # No_Conn PLL DeSkew 1 FanOut #1 DIR NET 'No_Conn_PLL_DESKEW_1_FO_1_CMP' U378-28 # No_Conn PLL DeSkew 1 FanOut #1 CMP NET 'No_Conn_PLL_DESKEW_1_FO_2_DIR' U378-27 # No_Conn PLL DeSkew 1 FanOut #2 DIR NET 'No_Conn_PLL_DESKEW_1_FO_2_CMP' U378-26 # No_Conn PLL DeSkew 1 FanOut #2 CMP # Output 3 from the PLL DeSkew 1 Fanout, to the Topological FPGA NET 'PLL_DESKEW_1_FO_3_DIR' U378-24 R433-1 # DeSkew 1 PLL Fanout #3 DIR NET 'PLL_DESKEW_1_FO_3_CMP' U378-23 R434-1 # DeSkew 1 PLL Fanout #3 CMP # DeSkew 1 Fanout Output 3 connected to the TP FPGA Logic Clock input pin. NET 'CLK_40MHz08_DSKW_1_TP_LOGIC_DIR' R433-2 R435-2 # 40.08 MHz DSK-1 LHC Logic NET 'CLK_40MHz08_DSKW_1_TP_LOGIC_CMP' R434-2 R436-2 # Clk to the Topological FPGA # Ground the attenuator resistors on the PLL DeSkew 1 fanout clock signals. NET 'GROUND' R435-1 R436-1 # Attenuator Pull-Down Resistors # Output 4 from the PLL DeSkew 1 Fanout, to the Base Function FPGA NET 'PLL_DESKEW_1_FO_5_DIR' U378-22 R437-1 # DeSkew 1 PLL Fanout #4 DIR NET 'PLL_DESKEW_1_FO_5_CMP' U378-21 R438-1 # DeSkew 1 PLL Fanout #4 CMP # DeSkew 1 Fanout Output 4 connected to the TP FPGA Logic Clock input pin. NET 'CLK_40MHz08_DSKW_1_BF_LOGIC_DIR' R437-2 R439-2 # 40.08 MHz DSK-1 LHC Logic NET 'CLK_40MHz08_DSKW_1_BF_LOGIC_CMP' R438-2 R440-2 # Clk to the Base Function FPGA # Ground the attenuator resistors on the PLL DeSkew 1 fanout clock signals. NET 'GROUND' R439-1 R440-1 # Attenuator Pull-Down Resistors # Output 5 from the PLL DeSkew 1 # Fanout is not connected. NET 'No_Conn_PLL_DESKEW_1_FO_5_DIR' U378-20 # No_Conn PLL DeSkew 1 FanOut #5 DIR NET 'No_Conn_PLL_DESKEW_1_FO_5_CMP' U378-19 # No_Conn PLL DeSkew 1 FanOut #5 CMP # Output 6 from the PLL DeSkew 1 Fanout, to the Board Support FPGA NET 'PLL_DESKEW_1_FO_6_DIR' U378-18 R441-1 # DeSkew 1 PLL Fanout #6 DIR NET 'PLL_DESKEW_1_FO_6_CMP' U378-17 R442-1 # DeSkew 1 PLL Fanout #6 CMP # DeSkew 1 Fanout Output 6 connected to the TP FPGA Logic Clock input pin. NET 'CLK_40MHz08_DSKW_1_BSPT_LOGIC_DIR' R441-2 R443-2 # 40.08 MHz DSK-1 LHC Logic NET 'CLK_40MHz08_DSKW_1_BSPT_LOGIC_CMP' R442-2 R444-2 # Clk to the BSPT FPGA # Ground the attenuator resistors on the PLL DeSkew 1 fanout clock signals. NET 'GROUND' R443-1 R444-1 # Attenuator Pull-Down Resistors # Output 7 and 8 from the PLL DeSkew 1 # Fanout are not connected. NET 'No_Conn_PLL_DESKEW_1_FO_7_DIR' U378-15 # No_Conn PLL DeSkew 1 FanOut #7 DIR NET 'No_Conn_PLL_DESKEW_1_FO_7_CMP' U378-14 # No_Conn PLL DeSkew 1 FanOut #7 CMP NET 'No_Conn_PLL_DESKEW_1_FO_8_DIR' U378-13 # No_Conn PLL DeSkew 1 FanOut #8 DIR NET 'No_Conn_PLL_DESKEW_1_FO_8_CMP' U378-12 # No_Conn PLL DeSkew 1 FanOut #8 CMP # Output 9 from the PLL DeSkew 1 Fanout, to monitor test points NET 'PLL_DESKEW_1_FO_9_DIR' U378-11 R446-2 # DeSkew 1 PLL Fanout #9 DIR NET 'PLL_DESKEW_1_FO_9_CMP' U378-10 R445-2 # DeSkew 1 PLL Fanout #9 CMP NET 'GROUND' R445-1 R446-1 # Pull-Down Resistors # # Now include all of the nets associated with the # 320.64 MHz clock signal and its distribution. # ---------- # # This PLL based clock signal fans out both as a # LVDS Logic clock to both the BF and TP and BF FPGAs # and fans out as a LVPECL GTX clock to the transceivers # in both the BF and TP FPGAs. # # Connor-Winfield SFX-524G Reset pin NET 'No_Conn_U375_3' U375-3 # Float this pin --> Not Reseting the PLL. # Connor-Winfield SFX-524G No Connect pins NET 'No_Conn_U375_4' U375-4 # SFX-524G No Connect Pin Number 4. NET 'No_Conn_U375_5' U375-5 # SFX-524G No Connect Pin Number 5. # 320.64 MHz PLL Outputs to the U376 Fanout chip NET 'PLL_320MHz64_OUT_DIR' U375-6 U376-3 # PLL 320.64 MHz Output DIR NET 'PLL_320MHz64_OUT_CMP' U375-7 U376-4 # PLL 320.64 MHz Output CMP NET 'PLL_320MHz64_OUT_DIR' R461-2 R459-2 # PLL 320.64 MHz Output DIR NET 'PLL_320MHz64_OUT_CMP' R462-2 R460-2 # PLL 320.64 MHz Output CMP NET 'GROUND' R461-1 R462-1 # Pull-Down Resistors NET 'CLK_3V3' R459-1 R460-1 # Term to Clk 3.3V # Pull-Down on the Input Select pin of the U376 MC100LVEP111 # Fanout chip ship so that it will use its CLK0 & CLK0_B input # pins. Also No-Conn its Vbb reference pin and its CLK1 pins. NET 'SELECT_INPUT_0_U376_FO' U376-2 R473-2 # U376 Select Pull-Down NET 'GROUND' R473-1 # Ground the Pull-Down NET 'No_Conn_U376_VBB_PIN_5' U376-5 # Unused Vbb Reference NET 'No_Conn_U376_CLK1_PIN_6' U376-6 # Unused CLK1 NET 'No_Conn_U376_CLK1_B_PIN_7' U376-7 # Unused CLK_B # Outputs 0 from the 320.64 MHz PLL Fanout is not connected. NET 'No_Conn_PLL_320MHz64_FO_0_DIR' U376-31 # No_Conn 320 Mhz PLL FanOut #0 DIR NET 'No_Conn_PLL_320MHz64_FO_0_CMP' U376-30 # No_Conn 320 Mhz PLL FanOut #0 CMP # Output 1 from the 320.64 MHz PLL Fanout, GTX Clk to the Topological FPGA NET 'PLL_320MHz64_FO_1_DIR' U376-29 R409-1 C1409-1 # 320.64 MHz PLL Fanout #1 DIR NET 'PLL_320MHz64_FO_1_CMP' U376-28 R410-1 C1410-1 # 320.64 MHz PLL Fanout #1 CMP NET 'GROUND' R409-2 R410-2 # Pull-Down Resistors NET 'CLK_320MHz64_LHC_TP_QUAD_117_DIR' C1409-2 # 320.64 MHz PLL LHC Clk NET 'CLK_320MHz64_LHC_TP_QUAD_117_CMP' C1410-2 # to the TP FPGA GTX 117 # Output 2 from the 320.64 MHz PLL Fanout, GTX Clk to the Topological FPGA NET 'PLL_320MHz64_FO_2_DIR' U376-27 R411-1 C1411-1 # 320.64 MHz PLL Fanout #2 DIR NET 'PLL_320MHz64_FO_2_CMP' U376-26 R412-1 C1412-1 # 320.64 MHz PLL Fanout #2 CMP NET 'GROUND' R411-2 R412-2 # Pull-Down Resistors NET 'CLK_320MHz64_LHC_TP_QUAD_114_DIR' C1411-2 # 320.64 MHz PLL LHC Clk NET 'CLK_320MHz64_LHC_TP_QUAD_114_CMP' C1412-2 # to the TP FPGA GTX 114 # Output 3 from the 320.64 MHz PLL Fanout, GTX Clk to the Topological FPGA NET 'PLL_320MHz64_FO_3_DIR' U376-24 R413-1 C1413-1 # 320.64 MHz PLL Fanout #3 DIR NET 'PLL_320MHz64_FO_3_CMP' U376-23 R414-1 C1414-1 # 320.64 MHz PLL Fanout #3 CMP NET 'GROUND' R413-2 R414-2 # Pull-Down Resistors NET 'CLK_320MHz64_LHC_TP_QUAD_111_DIR' C1413-2 # 320.64 MHz PLL LHC Clk NET 'CLK_320MHz64_LHC_TP_QUAD_111_CMP' C1414-2 # to the TP FPGA GTX 111 # Output 4 from the 320.64 MHz PLL Fanout, Logic Clk to the Topological FPGA NET 'PLL_320MHz64_FO_4_DIR' U376-22 R419-1 # 320.64 MHz PLL Fanout #4 DIR NET 'PLL_320MHz64_FO_4_CMP' U376-21 R420-1 # 320.64 MHz PLL Fanout #4 CMP # 320.64 MHz PLL Fanout Output 4 connected to the TP FPGA Logic Clock input pin. NET 'CLK_320MHz64_LHC_TP_LOGIC_DIR' R419-2 R421-2 # 320.64 MHz LHC Logic NET 'CLK_320MHz64_LHC_TP_LOGIC_CMP' R420-2 R422-2 # Clk to the TP FPGA # Ground the attenuator resistors on the 320.64 MHz PLL fanout clock signals. NET 'GROUND' R421-1 R422-1 # Attenuator Pull-Down Resistors # Output 5 from the 320.64 MHz PLL Fanout, GTX Clk to the Base Function FPGA NET 'PLL_320MHz64_FO_5_DIR' U376-20 R415-1 C1415-1 # 320.64 MHz PLL Fanout #5 DIR NET 'PLL_320MHz64_FO_5_CMP' U376-19 R416-1 C1416-1 # 320.64 MHz PLL Fanout #5 CMP NET 'GROUND' R415-2 R416-2 # Pull-Down Resistors NET 'CLK_320MHz64_LHC_BF_QUAD_114_DIR' C1415-2 # 320.64 MHz PLL LHC Clk NET 'CLK_320MHz64_LHC_BF_QUAD_114_CMP' C1416-2 # to the BF FPGA GTX 114 # Output 6 from the 320.64 MHz PLL Fanout, GTX Clk to the Base Function FPGA NET 'PLL_320MHz64_FO_6_DIR' U376-18 R417-1 C1417-1 # 320.64 MHz PLL Fanout #6 DIR NET 'PLL_320MHz64_FO_6_CMP' U376-17 R418-1 C1418-1 # 320.64 MHz PLL Fanout #6 CMP NET 'GROUND' R417-2 R418-2 # Pull-Down Resistors NET 'CLK_320MHz64_LHC_BF_QUAD_111_DIR' C1417-2 # 320.64 MHz PLL LHC Clk NET 'CLK_320MHz64_LHC_BF_QUAD_111_CMP' C1418-2 # to the BF FPGA GTX 111 # Output 7 from the 320.64 MHz PLL Fanout, Logic Clk to the Base Function FPGA NET 'PLL_320MHz64_FO_7_DIR' U376-15 R423-1 # 320.64 MHz PLL Fanout #7 DIR NET 'PLL_320MHz64_FO_7_CMP' U376-14 R424-1 # 320.64 MHz PLL Fanout #7 CMP # 320.64 MHz PLL Fanout Output 7 connected to the BF FPGA Logic Clock input pin. NET 'CLK_320MHz64_LHC_BF_LOGIC_DIR' R423-2 R425-2 # 320.64 MHz LHC Logic NET 'CLK_320MHz64_LHC_BF_LOGIC_CMP' R424-2 R426-2 # Clk to the TP FPGA # Ground the attenuator resistors on the 320.64 MHz PLL fanout clock signals. NET 'GROUND' R425-1 R426-1 # Attenuator Pull-Down Resistors # Outputs 8 from the 320.64 MHz PLL Fanout is not connected. NET 'No_Conn_PLL_320MHz64_FO_8_DIR' U376-13 # No_Conn 320 Mhz PLL FanOut #8 DIR NET 'No_Conn_PLL_320MHz64_FO_8_CMP' U376-12 # No_Conn 320 Mhz PLL FanOut #8 CMP # Output 9 from the 320.64 MHz PLL Fanout, to monitor test points NET 'PLL_320MHz64_FO_9_DIR' U376-11 R428-2 # 320.64 MHz PLL Fanout #9 DIR NET 'PLL_320MHz64_FO_9_CMP' U376-10 R427-2 # 320.64 MHz PLL Fanout #9 CMP NET 'GROUND' R427-1 R428-1 # Pull-Down Resistors # PLL Monitoring Signals # # Each of the 3 PLLs has 2 monitoring signals: # # - Lock Detect logic signal that can be monitored by # one of the Board Support FPGA DeBug signals # # - VCXO Control Voltage analog monitor signal that # is routed to a via where it can be monitored by # an external DVM. # # Note that the following resistors are actually Jumpers # # - R481 jumpers the 320.64 MHz PLL Lock Detect to BSPT_DEBUG_6 # # - R482 jumpers the DeSkew-1 PLL Lock Detect to BSPT_DEBUG_5 # # - R483 jumpers the DeSkew-2 PLL Lock Detect to BSPT_DEBUG_7 # # # There are 3 sections below - one for each PLL. # # # 320.64 MHz PLL U375 Monitoring # # 320.64 MHz PLL Lock-Det and VMon pins. NET 'PLL_320MHz64_LOCK_DET' U375-10 # Lock Status of the 320.64 MHz PLL NET 'PLL_320MHz64_LOCK_DET' R478-1 # U375 to decoupling resistor NET 'PLL_320MHz_LOCK_DET_RES' R478-2 # Decoupling resistor 1 to NET 'PLL_320MHz_LOCK_DET_RES' R481-2 # Jumper resistor to BSPT DeBug_6 NET 'BSPT_DEBUG_6' R481-1 # Monitor the 320.64 MHz PLL Lock Detect # on Board Support FPGA BSPT_DEBUG_6 NET 'PLL_320MHz64_V_MON' R475-2 # to the decoupling resistor R475 NET 'MONITOR_320MHz_VCXO' R475-1 # Via to monitor the 320.64 MHz NET 'MONITOR_320MHz_VCXO' WRP11-1 # PLL VCXO Control Voltage NET 'GROUND' WRP12-1 # Ground Reference Via # # DeSkew-1 PLL U377 40.08 MHz Monitoring # # 40.08 MHz DeSkew-1 PLL Lock-Det and VMon pins. NET 'PLL_DESKEW_1_LOCK_DET' U377-10 # Lock Status of the DeSkew 1 PLL NET 'PLL_DESKEW_1_LOCK_DET' R479-1 # U377 to decoupling resistor NET 'PLL_DESKEW_1_LOCK_DET_RES' R479-2 # Decoupling resistor 1 to NET 'PLL_DESKEW_1_LOCK_DET_RES' R482-1 # Jumper resistor to BSPT DeBug_5 NET 'BSPT_DEBUG_5' R482-2 # Monitor the DeSkew 1 PLL Lock Detect # on Board Support FPGA BSPT_DEBUG_5 NET 'PLL_DESKEW_1_V_MON' R476-2 # to the decoupling resistor R476 NET 'MONITOR_DESKEW_1_VCXO' R476-1 # Via to monitor the DeSkew 1 NET 'MONITOR_DESKEW_1_VCXO' WRP13-1 # PLL VCXO Control Voltage NET 'GROUND' WRP14-1 # Ground Reference Via # # DeSkew-2 PLL U379 40.08 MHz Monitoring # # 40.08 MHz DeSkew-2 PLL Lock-Det and VMon pins. NET 'PLL_DESKEW_2_LOCK_DET' U379-10 # Lock Status of the DeSkew 2 PLL NET 'PLL_DESKEW_2_LOCK_DET' R480-1 # U379 to decoupling resistor NET 'PLL_DESKEW_2_LOCK_DET_RES' R480-2 # Decoupling resistor 1 to NET 'PLL_DESKEW_2_LOCK_DET_RES' R483-1 # Jumper resistor to BSPT DeBug_7 NET 'BSPT_DEBUG_7' R483-2 # Monitor the DeSkew 2 PLL Lock Detect # on Board Support FPGA BSPT_DEBUG_7 NET 'PLL_DESKEW_2_V_MON' R477-2 # to the decoupling resistor R476 NET 'MONITOR_DESKEW_2_VCXO' R477-1 # Via to monitor the DeSkew 2 NET 'MONITOR_DESKEW_2_VCXO' WRP15-1 # PLL VCXO Control Voltage NET 'GROUND' WRP16-1 # Ground Reference Via