# # CMX-0 Nets File # # # CONFIGURATION Nets # ---------------------- # # # Original Rev. 3-Jan-2013 # Most Recent Rev. 7-Apr-2013 # # # # This file holds most of the nets that are involved with # the CONFIGURATION of the Virtex FPGAs; Base Function and # Topological Processor. # # - Many of these nets involve connections to the System-ACE # chip or the Board Support FPGA. # # - Most of these Virtex FPGA nets are from Bank #0 and # their pin connections are given in: # # .../Base_Fpga_Power/bf_fpga_ff1759_bank_0_and_special_n2p.txt # # .../TP_Fpga_Power/tp_fpga_ff1759_bank_0_and_special_n2p.txt # # # These are all 2.5V CMOS level nets. # # # This file includes Jumpers to separately contor the M2, # M1, M0 pins on both of the Virtex-6 FPGAs. # # This file also includes jumpers that connect the INIT_B # signal from the 2 Virtex-6 FPGAs to the System-ACE # CFGINIT_B input pin. This circuit includes a 4.7k Ohm # pull-up to 2.5V on the CFGINIT_B signal - R334. # # This file also includes connections to the Virtex FPGA # PROG_B and DONE pins. # # Finally there is a list of Virtex Configuration pins # that are not used in the CMX design. # # # The components involved in this Net List file are: # # U1, U2 Virtex FPGAs # U321 System-ACE # U351 Board Support Spartan 3A FPGA # JMP31:JMP36 BF FPGA M2,M1,M0 jumpers # JMP41:JMP46 TP FPGA M2,M1,M0 jumpers # JMP75, JMP76 INIT_B Select Jumpers # R334, R335 4.7k Pull-Up resistors on BF and TP INIT_B # R336, R337 4.7k Pull-Up resistors on BF and TP PROG_B # R338, R339 1.0k Pull-Up resistors on BF and TP DONE # R341, R342 4.7k Pull-Up resistors on BF and TP CCLK # R343, R344 4.7k Pull-Up resistors on BF and TP DIN # R345, R346 4.7k Pull-Up resistors on BF and TP CSI_B # R347, R348 4.7k Pull-Dn resistors on BF and TP RDWR_B # # # Start with the M2, M1, M0 Jumpers that control the # Configuration of the Base Function FPGA. Pin Numbers: AL10, AM11, AL11 NET 'BF_M2' JMP31-1 JMP32-2 # BF M2 Control JMP31 is Pull-Down NET 'BF_M1' JMP33-1 JMP34-2 # BF M1 Control JMP33 is Pull-Down NET 'BF_M0' JMP35-1 JMP36-2 # BF M0 Control JMP35 is Pull-Down NET 'GROUND' JMP31-2 JMP33-2 JMP35-2 # Ground the Pull-Down Jumpers NET 'BULK_2V5' JMP32-1 JMP34-1 JMP36-1 # Tie the Pull-Ups to BULK_2V5 # # Now the M2, M1, M0 Jumpers that control the # Configuration of the Topological FPGA. Pin Numbers: AL10, AM11, AL11 NET 'TP_M2' JMP41-1 JMP42-2 # TP M2 Control JMP41 is Pull-Down NET 'TP_M1' JMP43-1 JMP44-2 # TP M1 Control JMP43 is Pull-Down NET 'TP_M0' JMP45-1 JMP46-2 # TP M0 Control JMP45 is Pull-Down NET 'GROUND' JMP41-2 JMP43-2 JMP45-2 # Ground the Pull-Down Jumpers NET 'BULK_2V5' JMP42-1 JMP44-1 JMP46-1 # Tie the Pull-Ups to BULK_2V5 # # BF and TP PROGRAM_B Pins pin number M11 # # PROGRAM_B is an Input pin with a permanent internal # weak pull-up. Normally the user pulses this pin Low # to initiate configuration. But on the CMX card this # FPGA is only configuraed via JTAG from the System-ACE # and this method does not require pulling PROGRAM_B Low # to initiate configuration. On CMX the Virtex PROGRAM_B # pin will be pulled up and connected to an input pin on # the BSPT FPGA just in case we need to pulse PROGRAM_B. # CMX will use a 4.7k Ohm pull-up to BULK_2V5. # NET 'BF_PROGRAM_B' R336-1 # BF PROG_B Pull-Up NET 'BF_PROGRAM_B' U351-V20 # BF PROG_B connection to the BSPT NET 'TP_PROGRAM_B' R337-1 # TP PROG_B Pull-Up NET 'TP_PROGRAM_B' U351-T15 # TP PROG_B connection to the BSPT NET 'BULK_2V5' R336-2 R337-2 # Tie to 2.5 Volts the Pull-Up Resistors # The PROG_B nets on the Base Function and Topological Processor # FPGAs are connected to pins in their Bank #0 n2p file. # # # BF and TP INIT_B Pins pin number N11 # # Now connect the INIT_B pins from the Base Function and # from the Topological Processor FPGAs to the CFGINIT_B pin # on the System-ACE chip, i.e. pin 78. This is done with # Jumpers JMP75 and JMP76 so that you can control which FPGA # INIT_B signal(s) the System-ACE sees. Seperately pull-up # each of the Virtex FPGA INIT_B pins with a 4.7k Ohm resistor. # From each of the Virtex FPGA INIT_B pins run a line to an # input on the Board Support FPGA so that it/we can monitor # the state of these FPGA INIT_B pins. # NET 'BF_INIT_B' JMP75-1 # BF FPGA INIT_B_0 to Jumper NET 'BF_INIT_B' R334-1 # Pull-Up on the BF INIT_B pin NET 'BF_INIT_B' U351-N12 # BF FPGA INIT_B_0 to Input pin on BSPT NET 'TP_INIT_B' JMP76-1 # TP FPGA INIT_B_0 to Jumper NET 'TP_INIT_B' R335-1 # Pull-Up on the TP INIT_B pin NET 'TP_INIT_B' U351-R10 # TP FPGA INIT_B_0 to Input pin on BSPT NET 'ACE_CFG_INIT_B' JMP75-2 JMP76-2 # Sys-ACE Configuration JTAG INIT input Vccl NET 'BULK_2V5' R334-2 R335-2 # Tie to 2.5 Volts the Pull-Up Resistors # The INIT_B nets on the Base Function and Topological Processor # FPGAs are connected to pins in their Bank #0 n2p file. # # # BF and TP DONE Pins pin number N10 # # DONE is a complicated Bidirectional normally open-drain # pin. DONE can also be setup as a driven output pin. # Its basic function is to indicate that the FPGA has been # successfully Configured. DONE goes HI when the FPGA # has successfully been Configured. The DONE pin needs # to have an external Pull-Up resistor. Xilinx often # uses a strong pull-up current on the DONE pin, # e.g. a 330 Ohm resistor. For now on CMX we will use # a 1k Ohm pull-up resistor. On CMX DONE is routed to # an input pin on the BSPT FPGA. On CMX we should use # the Bit-Gen option that makes DONE an open-drain pin # (not a driven pin). # NET 'BF_CONFIG_DONE' R338-1 # BF DONE Pull-Up NET 'BF_CONFIG_DONE' U351-P12 # BF DONE connection to a BSPT input NET 'TP_CONFIG_DONE' R339-1 # TP DONE Pull-Up NET 'TP_CONFIG_DONE' U351-P10 # TP DONE connection to a BSPT input NET 'BULK_2V5' R338-2 R339-2 # Tie to 2.5 Volts the Pull-Up Resistors # The PROG_B nets on the Base Function and Topological Processor # FPGAs are connected to pins in their Bank #0 n2p file. # # # Unused Virtex Configuration pins in the CMX design # # BF and TP CCLK Pins pin number K10 # # This pin is not used in the Configuration method # that will be used on CMX for this FPGA. This pin # can be either an input or a driven output in other # configuration modes. So far I have found nothing # in the Virtex documentation that say what we should # do with this pin when it is not used. It is not # safe to let a CMOS input just float. On CMX I # will run this to a Pull-Up resistor. # NET 'BF_CCLK' R341-1 # BF CCLK Pull-Up NET 'TP_CCLK' R342-1 # TP CCLK Pull-Up NET 'BULK_2V5' R341-2 R342-2 # Tie to 2.5 Volts the Pull-Up Resistors # The CCLK nets on the Base Function and Topological Processor # FPGAs are connected to pins in their Bank #0 n2p file. # # BF and TP DIN Pins pin number L10 # # This is an input pin for serial mode Configuration data. # This pin is not used in the Configuration method that # will be used on CMX card for this FPGA. So far I have # found nothing in the Virtex documentation that say what # we should do with this pin when it is not used. It is # not safe to let a CMOS input just float. On CMX I # will run this to a Pull-Up resistor. # NET 'BF_DIN' R343-1 # BF DIN Pull-Up NET 'TP_DIN' R344-1 # TP DIN Pull-Up NET 'BULK_2V5' R343-2 R344-2 # Tie to 2.5 Volts the Pull-Up Resistors # The DIN nets on the Base Function and Topological Processor # FPGAs are connected to pins in their Bank #0 n2p file. # # BF and TP DOUT_BUSY Pins pin number AK10 # # This is in Output pin. This signal is not used in # the method that CMX will use to configure this FPGA. # We have no use for this pin in the CMX design. Thus # we will permanently and irrevocably connect nothing # to this pin. This pins will not have a via. # # BF and TP CSI_B Pins pin number T10 # # This is an Input. It is used to enable or disable # SelectMAP data bus during SelectMAP Configuration. # CMX will not use this methode for Configuration. # So far I have found nothing in the Virtex documentation # that say what we should do with this pin when it is not # used. It is not safe to let a CMOS input just float. # On CMX I will run this to a Pull-Up resistor. Pulling # Hi disables the unused SelectMAP Bus. # NET 'BF_CSI_B' R345-1 # BF CSI_B Pull-Up NET 'TP_CSI_B' R346-1 # TP CSI_B Pull-Up NET 'BULK_2V5' R345-2 R346-2 # Tie to 2.5 Volts the Pull-Up Resistors # The CSI_B nets on the Base Function and Topological Processor # FPGAs are connected to pins in their Bank #0 n2p file. # # BF and TP RDWR_B Pins pin number J10 # # This is an Input. It is used to control the direction # of the SelectMAP data bus. CMX will not use this methode # for Configuration. So far I have found nothing in the # Virtex documentation that say what we should do with this # pin when it is not used. It is not safe to let a CMOS # input just float. On CMX I will run this to a Pull-Down # resistor. Pulling Low makes the SelectMAP Bus an input. # NET 'BF_RDWR_B' R347-1 # BF RDWR_B Pull-Down NET 'TP_RDWR_B' R348-1 # TP RDWR_B Pull-Down NET 'GROUND' R347-2 R348-2 # Tie to Ground # The RDWR_B nets on the Base Function and Topological Processor # FPGAs are connected to pins in their Bank #0 n2p file. #