# # CMX-0 Nets File # # JTAG Chains TEST and Configuration Nets # ------------------------------------------- # # # Original Rev. 22-Aug-2012 # Most Recent Rev. 3-Sept-2013 # # # # This file holds the nets for both of the JTAG chains on the # CMX card. There is a "TEST" and a "Configuration" JTAG # chain on the CMX card. TEST and Configuration are the names # given by Xilinx to the two JTAG ports on the System-Ace chip. # # The TEST JTAG chain starts at the front panel JTAG connector, # J12, runs to the TEST port on the System-Ace U321, and then # to the TTCDec mezzanine card TTC_Mez, and then to the # Configuration PROM for the Board Support FPGA, and then # to the Spartan 3A BSPT FPGA itself, and then finally back # to the J12 connector. This is a 3.3 Volt JTAG chain. # # The front panel TEST JTAG chain is buffered right were it # enters the CMX card on J12. 74LVC04A chips are used to # buffer these JTAG signals. There are pull-up resistors # on the TEST TMS TCK and TDI signals as they enter on J12. # # The Configuration JTAG chain starts at the Configuration port # of the System-Ace U321, runs to the Base Function FPGA U1, # and then runs to the Topological Processor FPGA U2, and then # finally runs back to the System-Ace Configuration port. # This is a 2.5V JTAG chain. # # # This design includes jumpers so that one can jump around # any of the devices in either the JTAG TEST Chain or in the # JTAG CONFIG Chain. # # # This design includes fuse F3 that supplies BULK_3V3 to # pin 2 on the front panel TEST JTAG connector J12. # # # Recal the Xilinx "standard" JTAG connector pinout. # # Xilinx uses the normal standard pin numbering vs physical # layout system for the 14 pin connector on their JTAG Pod. # # Unlike most cabling systems Xilinx puts the Ground on # the odd numbered pins and puts the signals on the even # numbered pins. # # CMX uses the normal standard pin numbering scheme for # its J12 connector near the bottom of the front panel. # # The first 5 signals on CMX connector J12 match the # pinout used by Xilinx so that a 1-to-1 cable can be # used for just this section of J12 to connect a # Xilinx JTAG pod to the CMX card's J12 connector. # # The only difference is that CMX will use a 2x8 16 pin # connector for its J12. The first 10 pins of J12 match # the Xilinx JTAG Pod connector. # # # Note that: # # - J12 pins 11 and 12 are used for CAN-Bus uProcessor # Reset and Mode control signals from the Programmer. # # - J12 pins 13 and 14 are used for RS-232 communications # with the CAN-Bus microprocessor. # # - J12 pins 15 and 16 are used for Front Panel Access # Signals #1 and #2. # # - The cable between the Xilinx JTAG Pod and the CMX J12 # connector must connect only pins 1 through 10, i.e. # the first 5 signal/ground pairs from the JTAG Pod. # # - The Xilinx Pod signals named Vtst and INIT are not # connected to the CMX card - these are not JTAG signals. # # # # # CMX J12 Connector Pin-Out TEST JTAG # # All odd pins, 1 through 9, are Ground # # pin #2 Fused 3.3 Volt proper voltage to power the "pod". # This is 3.3V for the CMX. It must be fused. # # pin #4 TMS This could have a series terminator/limiter # CMM pulls TMS up with 4.7k Ohm. # # pin #6 TCK This could have a series terminator/limiter # CMM pulls TCK up with 4.7k Ohm. # # pin #8 TDO This could have a series terminator/limiter # This is Test Data from CMX to the Pod # # pin #10 TDI This could have a series terminator/limiter # CMM pulls TDI up with 4.7k Ohm. # This is Test Data from the Pod to CMX # # pin #11 Mode Control signal to the CAN-Bus uProcessor. # # pin #12 Reset Signal to the CAN-Bus uProcessor. # # pins #13 and #14 are the RS-232 signals with the # CAN-Bus micro-controller # # pins #15 and #16 are two Front Panel Access Signals # # Note that the Ground pins associated with the JTAG # section of J12, i.e. 5 odd odd pins 1 through 9 # will also be used as grounds for the Access # Signal and RS-232 functions of J12. # # # Components referenced in this file include: # # J12 front panel JTAG connection to the TEST JTAG chain # U1 Base Function FPGA Virtex-6 # U2 Topological Processor FPGA Virtex-6 # U321 System-Ace # U322 TEST JTAG Buffer chip # U323 TEST JTAG Buffer chip # U351 Board Support FPGA Spartan 3a # U359 Config_PROM for the BSPT_FPGA # # JMP61:JMP68 Jumpers in the JTAG TEST Chain # JMP71:JMP76 Jumpers in the JTAG CONFIG Chain # # R331:R333 4.7k Pull-Up resistors on J12 TEST Chain # # R313:R315 47 Ohm series terminators in the Config JTAG chain # # F3 Fuse for the TEST JTAG Connector VCC Pin # # C333:C336 Bypass capacitors for U322 and U323 # # # # TEST JTAG Chain: # ------------------ # # Nets for the pins on the J12 # front panel TEST JTAG chain connector NET 'GROUND' J12-1 J12-3 J12-5 # front panel connector NET 'GROUND' J12-7 J12-9 # for the TEST JTAG chain NET 'TEST_TMS_from_J12' J12-4 # TMS received on J12 pin #4 NET 'TEST_TCK_fron_J12' J12-6 # TCK received on J12 pin #6 NET 'TEST_J12_to_ACE_TDI' J12-10 # TDI received on J12 pin #10 # going to the System-Ace Test port NET 'TEST_TDO_BUF_OUT' J12-8 # Buffered TDO from the BSPT FPGA # sent out on J12 pin #8 # J12 TEST JTAG Chain Pull-Up Resistors NET 'TEST_TMS_from_J12' R331-1 # Pull_Up TMS received on J12 NET 'TEST_TCK_fron_J12' R332-1 # Pull_Up TCK received on J12 NET 'TEST_J12_to_ACE_TDI' R333-1 # Pull-Up TDI received on J12 NET 'BULK_3V3' R331-2 R332-2 R333-2 # BULK_3V3 To Pull_ups # # Buffer the TEST JTAG Signals # ------------------------------ # Buffer the TEST TMS Signal NET 'TEST_TMS_from_J12' U322-1 # Input to the TEST JTAG TMS Buffer NET 'TEST_TMS_2_BUF_STAGE' U322-2 U323-1 # 2nd stage TEST TMS Buffer NET 'TEST_TMS_2_BUF_STAGE' U323-3 # 2nd stage TEST TMS Buffer NET 'TEST_TMS_BUF_OUT_1' U323-2 # Output of 2nd stage TEST TMS Buf 1 NET 'TEST_TMS_BUF_OUT_2' U323-4 # Output of 2nd stage TEST TMS Buf 2 # Buffer the TEST TCK Signal NET 'TEST_TCK_fron_J12' U322-3 # Input to the TEST JTAG TCK Buffer NET 'TEST_TCK_2_BUF_STAGE' U322-4 U323-5 # 2nd stage TEST TCK Buffer NET 'TEST_TCK_2_BUF_STAGE' U323-9 # 2nd stage TEST TCK Buffer NET 'TEST_TCK_BUF_OUT_1' U323-6 # Output of 2nd stage TEST TCK Buf 1 NET 'TEST_TCK_BUF_OUT_2' U323-8 # Output of 2nd stage TEST TCK Buf 2 # Buffer the TEST TDI Signal NET 'TEST_J12_to_ACE_TDI' U322-5 # Input to the TEST JTAG TDI Buffer NET 'TEST_TDI_2_BUF_STAGE' U322-6 U322-9 # 2nd stage TEST TDI Buffer NET 'TEST_TDI_BUF_OUT' U322-8 # Output of 2nd stage TEST TDI Buffer # Buffer the TEST TDO Signal NET 'TEST_TDO_TO_BUF' U322-13 # Buffer input for TEST TDO from BSPT FPGA NET 'TEST_TDO_2_BUF_STAGE' U322-12 U322-11 # 2nd stage TEST TDO Buffer NET 'TEST_TDO_BUF_OUT' U322-10 # TEST TDO 2nd Buffer Output to J12 # # Nets on the System-Ace TEST port # NET 'TEST_TMS_BUF_OUT_2' U321-98 # TMS into the System-Ace Test port NET 'TEST_TCK_BUF_OUT_2' U321-101 # TCK into the System-Ace Test port NET 'TEST_TDI_BUF_OUT' U321-102 # TDI from the Buffer to System # Ace Test port TDI pin and to NET 'TEST_TDI_BUF_OUT' JMP62-1 # Jumper around the System-ACE NET 'TEST_ACE_TDO_to_JUMPER' U321-97 # TDO from the System-Ace NET 'TEST_ACE_TDO_to_JUMPER' JMP61-1 # going to JMP61 NET 'TEST_JUMPER_to_TTCDec_TDI' JMP61-2 # Jumpers to select the signal NET 'TEST_JUMPER_to_TTCDec_TDI' JMP62-2 # going to the TTCDec TDI # # Nets on the TTCDec Mezzanine JTAG port # NET 'TEST_TMS_BUF_OUT_2' TTC_Mez-H1_51 # TMS into the TTCDec Mezzanine NET 'TEST_TCK_BUF_OUT_2' TTC_Mez-H1_55 # TCK into the TTCDec Mezzanine NET 'TEST_JUMPER_to_TTCDec_TDI' TTC_Mez-H1_49 # TDO from the System-Ace # Test port going to the # TTCDec TDI pin and the NET 'TEST_JUMPER_to_TTCDec_TDI' JMP64-1 # Jumper around the TTCDec NET 'TEST_TTCDec_TDO_to_JUMPER' TTC_Mez-H1_53 # TDO from the TTCDec NET 'TEST_TTCDec_TDO_to_JUMPER' JMP63-1 # going to JMP63 NET 'TEST_JUMPER_to_PROM_TDI' JMP63-2 # Jumpers to select the signal NET 'TEST_JUMPER_to_PROM_TDI' JMP64-2 # going to the Config PROM TDI # # Nets on the JTAG port of the Configuration PROM for the BSPT_FPGA # NET 'TEST_TMS_BUF_OUT_1' U359-5 # TMS into the Config_PROM NET 'TEST_TCK_BUF_OUT_1' U359-6 # TCK into the Config_PROM NET 'TEST_JUMPER_to_PROM_TDI' U359-4 # TDO from the TTCDec Mezzanine # going to the Config_PROM TDI and NET 'TEST_JUMPER_to_PROM_TDI' JMP66-1 # the Jumper around the Config PROM NET 'TEST_PROM_TDO_to_JUMPER' U359-17 # TDO from the Config_PROM NET 'TEST_PROM_TDO_to_JUMPER' JMP65-1 # going to JMP65 NET 'TEST_JUMPER_to_BSPT_TDI' JMP65-2 # Jumpers to select the signal NET 'TEST_JUMPER_to_BSPT_TDI' JMP66-2 # going to the BSPT FPGA TDI. # # Nets on the JTAG port of the Spartan 3A BSPT_FPGA # NET 'TEST_TMS_BUF_OUT_1' U351-E4 # TMS into the BSPT FPGA NET 'TEST_TCK_BUF_OUT_1' U351-A19 # TCK into the BSPT FPGA NET 'TEST_JUMPER_to_BSPT_TDI' U351-F5 # TDO from the Config_PROM # going to the BSPT FPGA TDI and NET 'TEST_JUMPER_to_BSPT_TDI' JMP68-1 # the Jumper around the BSPT_FPGA NET 'TEST_BSPT_TDO_to_JUMPER' U351-E17 # TDO from the BSPT FPGA NET 'TEST_BSPT_TDO_to_JUMPER' JMP67-1 # going to JMP67 NET 'TEST_TDO_TO_BUF' JMP67-2 # Jumpers to select the signal NET 'TEST_TDO_TO_BUF' JMP68-2 # going to the TEST TDO Buffer # and then to J12 TDO pin #8. # # Now the 3.3 Volt Fused Power to the TEST JTAG VCC Pin # NET 'BULK_3V3' F3-2 # BULK_3V3 power to the TEST JTAG Fuse. NET 'TEST_JTAG_VCC' F3-1 J12-2 # Fused 3.3V Power to TEST JTAG Connector # # Configuration JTAG Chain: # --------------------------- # # # Nets on the System-Ace Configuration port # NET 'CFG_TMS_from_ACE_to_Term' U321-85 R314-1 # CFG JTAG TMS from ACE to Term NET 'CFG_TCK_from_ACE_to_Term' U321-80 R315-1 # CFG JTAG TCK from ACE to Term NET 'CFG_ACE_TDO_to_Term' U321-82 R313-1 # JTAG Data from ACE to Term NET 'CFG_TP_TDO_to_ACE_TDI' U321-81 # JTAG Data from TP FPGA to ACE # # The CFG_TMS, CFG_TCK, and CFG_TDO loop through series terminators # NET 'CFG_TMS_from_ACE' R314-2 # CFG JTAG TMS from ACE Term NET 'CFG_TCK_from_ACE' R315-2 # CFG JTAG TCK from ACE Term NET 'CFG_ACE_TDO_to_BF_TDI' R313-2 # JTAG Data from ACE Term to BF FPGA # # Jumpers around the Base Function FPGA # NET 'CFG_ACE_TDO_to_BF_TDI' JMP72-1 # CFG JTAG Data from ACE to BF NET 'CFG_BF_TDO' JMP71-1 # CFG JTAG Data from BF NET 'CFG_TP_TDI' JMP72-2 # CFG JTAG Data To TP NET 'CFG_TP_TDI' JMP71-2 # CFG JTAG Data To TP # # Jumpers around the Topological Processor FPGA # NET 'CFG_TP_TDI' JMP74-1 # CFG JTAG Data from BF to TP NET 'CFG_TP_TDO' JMP73-1 # CFG JTAG Data from TP NET 'CFG_TP_TDO_to_ACE_TDI' JMP74-2 # CFG JTAG Data To ACE NET 'CFG_TP_TDO_to_ACE_TDI' JMP73-2 # CFG JTAG Data To ACE # # The JTAG nets on the Base Function and Topological Processor # FPGAs are connected in their Bank #0 n2p file. # # # Connect power and ground to buffers U322 and U323. # Include their bypass capacitors C333:C336. NET 'BULK_3V3' U322-14 U323-14 # Power to the buffers NET 'GROUND' U322-7 U323-7 # Ground to the buffers NET 'BULK_3V3' C333-2 C334-2 C335-2 C336-2 # Bypass Caps. NET 'GROUND' C333-1 C334-1 C335-1 C336-1 # Bypass Caps.