#
#                   CMX-0  Nets File
#
#             Virtex  FPGA  Special  Pins
#            -======----------------------
#
#
#                                                 Original Rev. 24-Jan-2013
#                                              Most Recent Rev. 28-Jan-2013
#
#
#
#  The purpose of this file is to provide a description of
#  the special  Bank #0  pins on the Virtex FPGAs that
#  are not described and connected to a net in some other
#  part of the overall CMX design.
#
#  Recall that all of the Bank #0 pins are assigned net-names
#  in the files:
#
#   .../Base_Fpga_Power/bf_fpga_ff1759_bank_0_and_special_n2p.txt
#     .../TP_Fpga_Power/tp_fpga_ff1759_bank_0_and_special_n2p.txt
#
#
#  Once defined in the above file, many of these special
#  Bank #0 pins,  e.g. the System-Monitor pins  and  Configuration
#  pins,  are then included elsewhere in the overall CMX design.
#
#  This file will describe all of the special pins that have
#  not been included elsewhere.  The intent is to provide a
#  rational for how we are handling each of these pins in the
#  CMX design..
#




#  BF and TP  HSWAPEN  Pins     pin number P10
#
#  The  HSWAPEN  pin controls whether or not pull-up
#  resistors are connected to all normal Select I/O pins
#  Pre-Configuration.
#
#    - Bank #0 pins are not part of this setup.
#
#    - HSWAPEN  LOW --> Pull-Up during Pre-Configuration
#
#    - HSWAPEN  HI  --> Tri-State all Select I/O pins
#                       during Pre-Configuration
#
#    - In most places the Xilinx Documentation says that
#      HSWAPEN controls what happens during Configuration
#      but what they mean is during Pre-Configuration,
#      i.e. during the time between when power is turned
#      ON and the device is first configured.  Only after
#      that is the HSWAPEN controlling what happens strictly
#      during configuration.
#
#    - The HSWAPEN pin itself always has a weak pull-up
#      resistor connected to it.   Ah but the book says
#      that this pull-up on the HSWAPEN pin does not always
#      provide a reliable 1.   They say that the HSWAPEN
#      pin should be connected to either enable or disable
#      this feature.
#
#    - In general the Xilinx books appear to recommend
#      enabling these Select I/O pin pull-up during
#      Configuration.
#
#    - I'm not certain what to do with the HSWAPEN pin
#      on the CMX card - thus bring it to a pair of jumpers.
#
#    - I believe that the value of this pre-configuration
#      pull-up current with 2.5V I/O is  80 uAmps.
#      I.E. no problem is this FPGA pin happens to be
#      driven by an external device but just right to
#      define a valid logic level if this FPGA pin runs
#      only to input pins on external devices.
#

NET  'BF_HSWAPEN'   JMP37-1   JMP38-2    # BF  HSWAPEN  Control Jumpers

NET  'TP_HSWAPEN'   JMP47-1   JMP48-2    # TP  HSWAPEN  Control Jumpers

NET  'GROUND'       JMP37-2   JMP47-2    # Tie Jumpers to GROUND

NET  'BULK_2V5'     JMP38-1   JMP48-1    # Tie Jumpers to 2.5 Volts

#  The HSWAPEN nets on the Base Function and Topological Processor
#  FPGAs are connected to pins in their Bank #0 n2p file.
#





#
#  BF and TP  BF_VBATT  Pins     pin number R10
#
#  VBATT is a power supply pin for the Decryptor Key memory.
#  The book says that when VBATT is not used to connect
#  this pin to either VccAUX or to GROUND.  CMX will not
#  use the Decryptor Key VBATT supply.  CMX will
#  permanently and irrevocably Ground this pin.
#





#  BF and TP  BF_VFS  Pins     pin number AH10
#
#  VFS is a power supply pin for programming the EFUSE.
#  The book says to Ground the VFS pin when it is not
#  being used.  CMX will not use the EFUSE.  Thus CMX
#  will permanently and irrevocably Ground this pin.
#