# # CMX-0 Nets File # # Front-Panel LVDS CTP Management Nets # --===========---------------------------- # # # Original Rev. 1-Nov-2012 # Most Recent Rev. 25-Apr-2013 # # # # This file holds the nets involved in the management of the # Front-Panel LVDS CTP Transceivers and Level Translators. # ---------------------- # # # As of 2-Nov-2012 the intent is to provide management of the # front panel CTP LVDS connections so that: # # BF can independently Drive, Receive, or Ignore the # upper J10 and lower J11 print panel LVDS connectors # # and # # TP can independently Drive, Receive, or Ignore the # upper J10 and lower J11 front panel LVDS connectors. # # Specifically for example, BF could drive all lines on the # upper J10 connector while TP is driving all lines on the # lower J11 connector. # # The implementation of this independed control is straight # forward except that the physical layout of signsls 64 and 65 # in the Translator chips U69 and U74 is a little different # and there are separate Transceivers, i.e. U68 for thes # selected signal 64 in the upper CTP connector J10 and # U59 for the selected signal 65 in the lower CTP connector # J11. # # # Recall the Layout of the Translator and Transceiver Chips: # # Base Function Topology # Signals Translation/MUX Translation/MUX Transceiver Connector # ------- --------------- --------------- ----------- --------- # # 0:31 U77 and U78 U72 and U73 U60:U67 J10 # # 32:63 U75 and U76 U69 and U70 U51:U58 J11 # # 64 U74 sec. 1 U74 sec. 2 U68 J10 # # 65 U71 sec. 1 U71 sec. 2 U59 J11 # # # # # The control to the OE_B pins to the CTP Translator chips # come from U361 in the Hardwired Oversight Logic section. # # These OE_B signals to the Translator chips are named: # # CTP_1_BF_TRNSLT_OE_B CTP_2_BF_TRNSLT_OE_B # # CTP_1_TP_TRNSLT_OE_B CTP_2_TP_TRNSLT_OE_B # # These control signals originate in the BSPT FPGA but # pass through the Hardwired Oversight Logic on their # way to the OE_B pins on the Translator chips. As these # signals come out of the BSPT FPGA that are named: # # BSPT_CTP_1_BF_TRNSLT_OE_B BSPT_CTP_2_BF_TRNSLT_OE_B # # BSPT_CTP_1_TP_TRNSLT_OE_B BSPT_CTP_2_TP_TRNSLT_OE_B # # The UPPER i.e. J10 set of Front-Panel LVDS CTP Management Signals # ----- --- -------------------- # Upper Connector J10 Base Function Translation and MUX Control Signals NET 'CTP_1_BF_TRNSLT_DIR' U77-1 U77-24 # Direction of BF Translators 15:0 NET 'CTP_1_BF_TRNSLT_DIR' U78-1 U78-24 # Direction of BF Translators 31:16 NET 'CTP_1_BF_TRNSLT_DIR' U74-1 # Direction of BF Translators 64 NET 'CTP_1_BF_TRNSLT_OE_B' U77-25 U77-48 # Output Enable Bar of BF Translators 15:0 NET 'CTP_1_BF_TRNSLT_OE_B' U78-25 U78-48 # Output Enable Bar of BF Translators 31:16 NET 'CTP_1_BF_TRNSLT_OE_B' U74-48 # Output Enable Bar of BF Translators 64 # Upper Connector J10 Topological Translation and MUX Control Signals NET 'CTP_1_TP_TRNSLT_DIR' U72-1 U72-24 # Direction of TP Translators 15:0 NET 'CTP_1_TP_TRNSLT_DIR' U73-1 U73-24 # Direction of TP Translators 31:16 NET 'CTP_1_TP_TRNSLT_DIR' U74-24 # Direction of TP Translators 64 NET 'CTP_1_TP_TRNSLT_OE_B' U72-25 U72-48 # Output Enable Bar of TP Translators 15:0 NET 'CTP_1_TP_TRNSLT_OE_B' U73-25 U73-48 # Output Enable Bar of TP Translators 31:16 NET 'CTP_1_TP_TRNSLT_OE_B' U74-25 # Output Enable Bar of TP Translators 64 # Upper Connector J10 Tranceiver Control Signals NET 'CTP_1_TRNCVR_DIR' U60-13 U60-15 U60-26 U60-28 # Receiver Enb_B 3:0 NET 'CTP_1_TRNCVR_DIR' U61-13 U61-15 U61-26 U61-28 # Receiver Enb_B 7:4 NET 'CTP_1_TRNCVR_DIR' U62-13 U62-15 U62-26 U62-28 # Receiver Enb_B 11:8 NET 'CTP_1_TRNCVR_DIR' U63-13 U63-15 U63-26 U63-28 # Receiver Enb_B 15:12 NET 'CTP_1_TRNCVR_DIR' U64-13 U64-15 U64-26 U64-28 # Receiver Enb_B 19:16 NET 'CTP_1_TRNCVR_DIR' U65-13 U65-15 U65-26 U65-28 # Receiver Enb_B 23:20 NET 'CTP_1_TRNCVR_DIR' U66-13 U66-15 U66-26 U66-28 # Receiver Enb_B 27:24 NET 'CTP_1_TRNCVR_DIR' U67-13 U67-15 U67-26 U67-28 # Receiver Enb_B 31:28 NET 'CTP_1_TRNCVR_DIR' U68-13 U68-15 U68-26 U68-28 # Receiver Enb_B 64 NET 'CTP_1_TRNCVR_DIR' U60-14 U60-16 U60-25 U60-27 # Driver Enable 3:0 NET 'CTP_1_TRNCVR_DIR' U61-14 U61-16 U61-25 U61-27 # Driver Enable 7:4 NET 'CTP_1_TRNCVR_DIR' U62-14 U62-16 U62-25 U62-27 # Driver Enable 11:8 NET 'CTP_1_TRNCVR_DIR' U63-14 U63-16 U63-25 U63-27 # Driver Enable 15:12 NET 'CTP_1_TRNCVR_DIR' U64-14 U64-16 U64-25 U64-27 # Driver Enable 19:16 NET 'CTP_1_TRNCVR_DIR' U65-14 U65-16 U65-25 U65-27 # Driver Enable 23:20 NET 'CTP_1_TRNCVR_DIR' U66-14 U66-16 U66-25 U66-27 # Driver Enable 27:24 NET 'CTP_1_TRNCVR_DIR' U67-14 U67-16 U67-25 U67-27 # Driver Enable 31:28 NET 'CTP_1_TRNCVR_DIR' U68-14 U68-16 U68-25 U68-27 # Driver Enable 64 NET 'FRONT_UPPER_LVDS_FAILSAFE' U60-9 U60-32 U61-9 U61-32 # Receiver Failsafe NET 'FRONT_UPPER_LVDS_FAILSAFE' U62-9 U62-32 U63-9 U63-32 # Receiver Failsafe NET 'FRONT_UPPER_LVDS_FAILSAFE' U64-9 U64-32 U65-9 U65-32 # Receiver Failsafe NET 'FRONT_UPPER_LVDS_FAILSAFE' U66-9 U66-32 U67-9 U67-32 # Receiver Failsafe NET 'FRONT_UPPER_LVDS_FAILSAFE' U68-9 U68-32 # Receiver Failsafe NET 'FRONT_UPPER_LVDS_MASTER_ENB' U60-10 U61-10 U62-10 U63-10 # Trncvr Master Enable NET 'FRONT_UPPER_LVDS_MASTER_ENB' U64-10 U65-10 U66-10 U67-10 # Trncvr Master Enable NET 'FRONT_UPPER_LVDS_MASTER_ENB' U68-10 # Trncvr Master Enable # The LOWER i.e. J11 set of Front-Panel LVDS CTP Management Signals # ----- --- -------------------- # Upper Connector J11 Base Function Translation and MUX Control Signals NET 'CTP_2_BF_TRNSLT_DIR' U75-1 U75-24 # Direction of BF Translators 47:32 NET 'CTP_2_BF_TRNSLT_DIR' U76-1 U76-24 # Direction of BF Translators 63:48 NET 'CTP_2_BF_TRNSLT_DIR' U71-1 # Direction of BF Translators 65 NET 'CTP_2_BF_TRNSLT_OE_B' U75-25 U75-48 # Output Enable Bar of BF Translators 47:32 NET 'CTP_2_BF_TRNSLT_OE_B' U76-25 U76-48 # Output Enable Bar of BF Translators 63:48 NET 'CTP_2_BF_TRNSLT_OE_B' U71-48 # Output Enable Bar of BF Translators 65 # Upper Connector J11 Topological Translation and MUX Control Signals NET 'CTP_2_TP_TRNSLT_DIR' U69-1 U69-24 # Direction of TP Translators 47:32 NET 'CTP_2_TP_TRNSLT_DIR' U70-1 U70-24 # Direction of TP Translators 63:48 NET 'CTP_2_TP_TRNSLT_DIR' U71-24 # Direction of TP Translators 65 NET 'CTP_2_TP_TRNSLT_OE_B' U69-25 U69-48 # Output Enable Bar of TP Translators 47:32 NET 'CTP_2_TP_TRNSLT_OE_B' U70-25 U70-48 # Output Enable Bar of TP Translators 63:48 NET 'CTP_2_TP_TRNSLT_OE_B' U71-25 # Output Enable Bar of TP Translators 65 # Upper Connector J11 Tranceiver Control Signals NET 'CTP_2_TRNCVR_DIR' U51-13 U51-15 U51-26 U51-28 # Receiver Enb_B 35:32 NET 'CTP_2_TRNCVR_DIR' U52-13 U52-15 U52-26 U52-28 # Receiver Enb_B 39:36 NET 'CTP_2_TRNCVR_DIR' U53-13 U53-15 U53-26 U53-28 # Receiver Enb_B 43:40 NET 'CTP_2_TRNCVR_DIR' U54-13 U54-15 U54-26 U54-28 # Receiver Enb_B 47:44 NET 'CTP_2_TRNCVR_DIR' U55-13 U55-15 U55-26 U55-28 # Receiver Enb_B 51:48 NET 'CTP_2_TRNCVR_DIR' U56-13 U56-15 U56-26 U56-28 # Receiver Enb_B 55:52 NET 'CTP_2_TRNCVR_DIR' U57-13 U57-15 U57-26 U57-28 # Receiver Enb_B 59:56 NET 'CTP_2_TRNCVR_DIR' U58-13 U58-15 U58-26 U58-28 # Receiver Enb_B 63:60 NET 'CTP_2_TRNCVR_DIR' U59-13 U59-15 U59-26 U59-28 # Receiver Enb_B 65 NET 'CTP_2_TRNCVR_DIR' U51-14 U51-16 U51-25 U51-27 # Driver Enable 35:32 NET 'CTP_2_TRNCVR_DIR' U52-14 U52-16 U52-25 U52-27 # Driver Enable 39:36 NET 'CTP_2_TRNCVR_DIR' U53-14 U53-16 U53-25 U53-27 # Driver Enable 43:40 NET 'CTP_2_TRNCVR_DIR' U54-14 U54-16 U54-25 U54-27 # Driver Enable 47:44 NET 'CTP_2_TRNCVR_DIR' U55-14 U55-16 U55-25 U55-27 # Driver Enable 51:48 NET 'CTP_2_TRNCVR_DIR' U56-14 U56-16 U56-25 U56-27 # Driver Enable 55:52 NET 'CTP_2_TRNCVR_DIR' U57-14 U57-16 U57-25 U57-27 # Driver Enable 59:56 NET 'CTP_2_TRNCVR_DIR' U58-14 U58-16 U58-25 U58-27 # Driver Enable 63:60 NET 'CTP_2_TRNCVR_DIR' U59-14 U59-16 U59-25 U59-27 # Driver Enable 65 NET 'FRONT_LOWER_LVDS_FAILSAFE' U51-9 U51-32 U52-9 U52-32 # Receiver Failsafe NET 'FRONT_LOWER_LVDS_FAILSAFE' U53-9 U53-32 U54-9 U54-32 # Receiver Failsafe NET 'FRONT_LOWER_LVDS_FAILSAFE' U55-9 U55-32 U56-9 U56-32 # Receiver Failsafe NET 'FRONT_LOWER_LVDS_FAILSAFE' U57-9 U57-32 U58-9 U58-32 # Receiver Failsafe NET 'FRONT_LOWER_LVDS_FAILSAFE' U59-9 U59-32 # Receiver Failsafe NET 'FRONT_LOWER_LVDS_MASTER_ENB' U51-10 U52-10 U53-10 U54-10 # Trncvr Master Enable NET 'FRONT_LOWER_LVDS_MASTER_ENB' U55-10 U56-10 U57-10 U58-10 # Trncvr Master Enable NET 'FRONT_LOWER_LVDS_MASTER_ENB' U59-10 # Trncvr Master Enable # # There are 2 functions of the DS91M040 LVDS Transceivers # that will be controlled only by the placement of # jumpers on the CMX card. These functions are: # Receiver Failsafe and Master_Enable # # Receiver Failsafe # # These are jumpers that pull the FSEN1 and FSEN2 pins # down to ground. There is a separate jumper for each # group of transceivers, i.e. the front upper J10 and # the front lower j11 CTP Cable LVDS transceivers. # Normally we expect both of these jumpers to be installed # so that all both cables will have "Type 1" i.e. voltage # symmetric receivers. These 2 jumpers are reference # designators JMP8 and JMP9. JMP8 controlls the Upper # CTP connector J10. JMP9 controlls the Lower CTP # connector J11. # NET 'FRONT_UPPER_LVDS_FAILSAFE' JMP8-1 # Upper Cable Failsafe Jumper NET 'FRONT_LOWER_LVDS_FAILSAFE' JMP9-1 # Lower Cable Failsafe Jumper NET 'GROUND' JMP8-2 JMP9-2 # Pull-Down to Ground # Master Enable # # When Master Enable is voltage HI then the DS91M040 # LVDS Transceiver will power up and operate. We expect # to always have these transceivers powered up. These # jumpers will actually be given resistor reference # designators on the CMX card because we never expect # to remove or change them. These will be nominal 1k # Ohm resistors from the Master Enable pin to BULK_3V3. # There will be a separate jumper (resistor) for each # group of tranceivers that services a front panel # CTP cable connector, i.e. R184 enables the # transceivers for the upper CTP connector J10 and # R185 enables the transceivers for the lower CTP # connector J11. # NET 'FRONT_UPPER_LVDS_MASTER_ENB' R184-1 # Lower Cable Trncvr Master Enable NET 'FRONT_LOWER_LVDS_MASTER_ENB' R185-1 # Upper Cable Trncvr Master Enable NET 'BULK_3V3' R184-2 R185-2 # Pull-Up to 3.3 Volts