############################################################################################ # # CMX Net-to-Resource File for the # TP Function FPGA IO signals used for Front Panel CTP Output # -=============------------------------------------------------ # # # Original Rev. 19-Nov-2012 Place holder # Rev: 11-Dec-2012 Copy Base FPGA pin assignment # Rev: 14-Jan-2013 Assign outer pins from IO banks 36, 37, 38 and route on layers 2,3,4,5 # Rev: 05-Apr-2013 Tentatively flag these signals to belong to layer 6 # Most Recent Rev: 04-Jun-2013 Update position of signal #65 after final location of 5th translator # # # Signal Nets referenced in this file: # ------------------------------------ # # There are 0, 1 or 2 CTP cables connected to a given CMX card. # A Crate CMX with only Base CMX functionality does not send any data to the CTP # A System CMX in a CPM crate sends information to the CTP over one cable # A System CMX in a JEM crate sends information to the CTP over two cables # A Crate CMX with TP functionality would probably send information to the CTP over two cables # # 'TP_DOUT_CTP_xx' are the CTP output signals from the TP FPGA with xx=00 to 65. # Each CTP output cable carries 33 LVDS signals consisting of 31 data bits, one clock # and one parity bit. # xx=0 to 30 carry data bits on cable #1 # xx=31 carry the clock on cable #1 # xx=64 carry the parity on cable #1 # xx=32 to 62 carry data bits on cable #2 # xx=63 carry the clock on cable #2 # xx=65 carry the parity on cable #2 # Note that regional clock signals are assigned to CTP output signals # 31 and 63 # for flexibility, so that the CTP output cables could be used as inputs instead. # # These CTP output signals are assigned here to resources in IO banks ??2 and ?? # # The rest of the circuitry used to drive the LVDS cables is in the file front_panel_ctp_driver_n2p.txt # in the Net_Lists/Front_Panel_CTP_IO_Nets directory # # # Note: Trace layer information is appended as comments below. # ----- # # NET 'TP_DOUT_CTP_00' U2- #> F02 #> T02 00 D22 # # ^ ^ ^ ^ ^ # | | | | | # Tailored comment flag to help with string searches -----------------+ | | | | # | | | | # Target Trace Layer number to use for this net --------------------------+ | | | # as it exits the FPGA (to reach a nearby via if needed) | | | # F01 is top layer, F02 the first inner layer, etc | | | # | | | # Target Trace Layer number to use for this net ---------------------------------+ | | # as it reaches the level translator near the front of the card | | # T01 is top layer, T02 the first inner layer, etc | | # | | # Signal number is repeated to help manual entry of Pin Number ---------------------+ | # | # Target Pin Number read from paper study -----------------------------------------------+ # and cross-checked after Match_Res2Pin # ############################################################################################ # # CTP Cable #1 # NET 'TP_DOUT_CTP_00' U2- #> F02 #> T06 00 D22 NET 'TP_DOUT_CTP_01' U2- #> F02 #> T06 01 B22 NET 'TP_DOUT_CTP_02' U2- #> F02 #> T06 02 A22 NET 'TP_DOUT_CTP_03' U2- #> F02 #> T06 03 B23 NET 'TP_DOUT_CTP_04' U2- #> F02 #> T06 04 C23 NET 'TP_DOUT_CTP_05' U2- #> F02 #> T06 05 A24 NET 'TP_DOUT_CTP_06' U2- #> F02 #> T06 06 B24 NET 'TP_DOUT_CTP_07' U2- #> F02 #> T06 07 A25 NET 'TP_DOUT_CTP_08' U2- #> F02 #> T06 08 C25 NET 'TP_DOUT_CTP_09' U2- #> F02 #> T06 09 A26 NET 'TP_DOUT_CTP_10' U2- #> F02 #> T06 10 B26 NET 'TP_DOUT_CTP_11' U2- #> F02 #> T06 11 A27 NET 'TP_DOUT_CTP_12' U2- #> F02 #> T06 12 B27 NET 'TP_DOUT_CTP_13' U2- #> F02 #> T06 13 B28 NET 'TP_DOUT_CTP_14' U2- #> F03 #> T06 14 F22 NET 'TP_DOUT_CTP_15' U2- #> F03 #> T06 15 E22 NET 'TP_DOUT_CTP_16' U2- #> F03 #> T06 16 D23 NET 'TP_DOUT_CTP_17' U2- #> F03 #> T06 17 E24 NET 'TP_DOUT_CTP_18' U2- #> F03 #> T06 18 C24 NET 'TP_DOUT_CTP_19' U2- #> F03 #> T06 19 D25 NET 'TP_DOUT_CTP_20' U2- #> F03 #> T06 20 C26 NET 'TP_DOUT_CTP_21' U2- #> F03 #> T06 21 D27 NET 'TP_DOUT_CTP_22' U2- #> F03 #> T06 22 C28 NET 'TP_DOUT_CTP_23' U2- #> F04 #> T06 23 K22 NET 'TP_DOUT_CTP_24' U2- #> F04 #> T06 24 G22 NET 'TP_DOUT_CTP_25' U2- #> F04 #> T06 25 E23 NET 'TP_DOUT_CTP_26' U2- #> F04 #> T06 26 F24 NET 'TP_DOUT_CTP_27' U2- #> F04 #> T06 27 F25 NET 'TP_DOUT_CTP_28' U2- #> F04 #> T06 28 E25 NET 'TP_DOUT_CTP_29' U2- #> F04 #> T06 29 D26 NET 'TP_DOUT_CTP_30' U2- #> F04 #> T06 30 E27 NET 'TP_DOUT_CTP_31' U2- #> F05 #> T06 31 J22 NET 'TP_DOUT_CTP_64' U2- #> F05 #> T06 64 F26 # # CTP Cable #2 # NET 'TP_DOUT_CTP_32' U2- #> F02 #> T06 32 B17 NET 'TP_DOUT_CTP_33' U2- #> F02 #> T06 33 A17 NET 'TP_DOUT_CTP_34' U2- #> F02 #> T06 34 B18 NET 'TP_DOUT_CTP_35' U2- #> F02 #> T06 35 B19 NET 'TP_DOUT_CTP_36' U2- #> F02 #> T06 36 A19 NET 'TP_DOUT_CTP_37' U2- #> F02 #> T06 37 C20 NET 'TP_DOUT_CTP_38' U2- #> F02 #> T06 38 A20 NET 'TP_DOUT_CTP_39' U2- #> F02 #> T06 39 D20 NET 'TP_DOUT_CTP_40' U2- #> F02 #> T06 40 A21 NET 'TP_DOUT_CTP_41' U2- #> F02 #> T06 41 B21 NET 'TP_DOUT_CTP_42' U2- #> F02 #> T06 42 C21 NET 'TP_DOUT_CTP_43' U2- #> F03 #> T06 43 D17 NET 'TP_DOUT_CTP_44' U2- #> F03 #> T06 44 C18 NET 'TP_DOUT_CTP_45' U2- #> F03 #> T06 45 C19 NET 'TP_DOUT_CTP_46' U2- #> F03 #> T06 46 E19 NET 'TP_DOUT_CTP_47' U2- #> F03 #> T06 47 E20 NET 'TP_DOUT_CTP_48' U2- #> F03 #> T06 48 D21 NET 'TP_DOUT_CTP_49' U2- #> F03 #> T06 49 F21 NET 'TP_DOUT_CTP_50' U2- #> F04 #> T06 50 E17 NET 'TP_DOUT_CTP_51' U2- #> F04 #> T06 51 D18 NET 'TP_DOUT_CTP_52' U2- #> F04 #> T06 52 E18 NET 'TP_DOUT_CTP_53' U2- #> F04 #> T06 53 F19 NET 'TP_DOUT_CTP_54' U2- #> F04 #> T06 54 F20 NET 'TP_DOUT_CTP_55' U2- #> F04 #> T06 55 G21 NET 'TP_DOUT_CTP_56' U2- #> F04 #> T06 56 H21 NET 'TP_DOUT_CTP_57' U2- #> F05 #> T06 57 F16 NET 'TP_DOUT_CTP_58' U2- #> F05 #> T06 58 F17 NET 'TP_DOUT_CTP_59' U2- #> F05 #> T06 59 G17 NET 'TP_DOUT_CTP_60' U2- #> F05 #> T06 60 G18 NET 'TP_DOUT_CTP_61' U2- #> F05 #> T06 61 G19 NET 'TP_DOUT_CTP_62' U2- #> F05 #> T06 62 H20 NET 'TP_DOUT_CTP_63' U2- #> F05 #> T06 63 L22 NET 'TP_DOUT_CTP_65' U2- #> F05 #> T06 65 J21