############################################################################################ # # CMX Net-to-Resource File for the # TP Function FPGA IO signals used the highspeed GTX Receivers # -=============------------------------------------------------- # # # Original Rev. 16-Mar-2012 # Rev. 5-Dec-2012 Rename nets and add termination resistors # Rev: 11-Dec-2012 File name changed for uniformity and consistency # between Base and TP files # Rev: 31-Dec-2012 Change the net-name on the MGTAVTTRCAL_115 # Calibration Resistor pin. # Rev: 23-May-2013 Assign full net names, including fiber number, to the # GTX Receivers in Quads 113, 114, 115, i.e. MiniPOD MP4. # Rev: 24-May-2013 Assign full net names, including fiber number, to the # GTX Receivers in Quads 110, 111, 112, i.e. MiniPOD MP3 # and to Quads 116, 117, 118, i.e. MiniPOD MP5. # Most Recent Rev: 8-Oct-2013 Change some GTX Transceiver - MiniPOD Fiber assignments # to allow better trace length match of DIR and CMP traces. # # # Receiver 1 MiniPOD MP3 # --------===----------===== NET 'MP3_F01_QUAD_110_REC_0_DIR' U2- NET 'MP3_F01_QUAD_110_REC_0_CMP' U2- NET 'MP3_F07_QUAD_110_REC_1_DIR' U2- NET 'MP3_F07_QUAD_110_REC_1_CMP' U2- NET 'MP3_F05_QUAD_110_REC_2_DIR' U2- NET 'MP3_F05_QUAD_110_REC_2_CMP' U2- NET 'MP3_F03_QUAD_110_REC_3_DIR' U2- NET 'MP3_F03_QUAD_110_REC_3_CMP' U2- NET 'MP3_F09_QUAD_111_REC_0_DIR' U2- NET 'MP3_F09_QUAD_111_REC_0_CMP' U2- NET 'MP3_F11_QUAD_111_REC_1_DIR' U2- NET 'MP3_F11_QUAD_111_REC_1_CMP' U2- NET 'MP3_F10_QUAD_111_REC_2_DIR' U2- NET 'MP3_F10_QUAD_111_REC_2_CMP' U2- NET 'MP3_F08_QUAD_111_REC_3_DIR' U2- NET 'MP3_F08_QUAD_111_REC_3_CMP' U2- NET 'MP3_F00_QUAD_112_REC_0_DIR' U2- NET 'MP3_F00_QUAD_112_REC_0_CMP' U2- NET 'MP3_F04_QUAD_112_REC_1_DIR' U2- NET 'MP3_F04_QUAD_112_REC_1_CMP' U2- NET 'MP3_F06_QUAD_112_REC_2_DIR' U2- NET 'MP3_F06_QUAD_112_REC_2_CMP' U2- NET 'MP3_F02_QUAD_112_REC_3_DIR' U2- NET 'MP3_F02_QUAD_112_REC_3_CMP' U2- # Receiver 2 MiniPOD MP4 # --------===----------===== NET 'MP4_F01_QUAD_113_REC_0_DIR' U2- NET 'MP4_F01_QUAD_113_REC_0_CMP' U2- NET 'MP4_F03_QUAD_113_REC_3_DIR' U2- NET 'MP4_F03_QUAD_113_REC_3_CMP' U2- NET 'MP4_F05_QUAD_113_REC_2_DIR' U2- NET 'MP4_F05_QUAD_113_REC_2_CMP' U2- NET 'MP4_F07_QUAD_113_REC_1_DIR' U2- NET 'MP4_F07_QUAD_113_REC_1_CMP' U2- NET 'MP4_F09_QUAD_114_REC_0_DIR' U2- NET 'MP4_F09_QUAD_114_REC_0_CMP' U2- NET 'MP4_F11_QUAD_114_REC_1_DIR' U2- NET 'MP4_F11_QUAD_114_REC_1_CMP' U2- NET 'MP4_F10_QUAD_114_REC_2_DIR' U2- NET 'MP4_F10_QUAD_114_REC_2_CMP' U2- NET 'MP4_F08_QUAD_114_REC_3_DIR' U2- NET 'MP4_F08_QUAD_114_REC_3_CMP' U2- NET 'MP4_F02_QUAD_115_REC_0_DIR' U2- NET 'MP4_F02_QUAD_115_REC_0_CMP' U2- NET 'MP4_F04_QUAD_115_REC_1_DIR' U2- NET 'MP4_F04_QUAD_115_REC_1_CMP' U2- NET 'MP4_F06_QUAD_115_REC_2_DIR' U2- NET 'MP4_F06_QUAD_115_REC_2_CMP' U2- NET 'MP4_F00_QUAD_115_REC_3_DIR' U2- NET 'MP4_F00_QUAD_115_REC_3_CMP' U2- # Receiver 3 MiniPOD MP5 # --------===----------===== NET 'MP5_F01_QUAD_116_REC_0_DIR' U2- NET 'MP5_F01_QUAD_116_REC_0_CMP' U2- NET 'MP5_F03_QUAD_116_REC_1_DIR' U2- NET 'MP5_F03_QUAD_116_REC_1_CMP' U2- NET 'MP5_F05_QUAD_116_REC_2_DIR' U2- NET 'MP5_F05_QUAD_116_REC_2_CMP' U2- NET 'MP5_F07_QUAD_116_REC_3_DIR' U2- NET 'MP5_F07_QUAD_116_REC_3_CMP' U2- NET 'MP5_F09_QUAD_117_REC_0_DIR' U2- NET 'MP5_F09_QUAD_117_REC_0_CMP' U2- NET 'MP5_F11_QUAD_117_REC_1_DIR' U2- NET 'MP5_F11_QUAD_117_REC_1_CMP' U2- NET 'MP5_F10_QUAD_117_REC_2_DIR' U2- NET 'MP5_F10_QUAD_117_REC_2_CMP' U2- NET 'MP5_F08_QUAD_117_REC_3_DIR' U2- NET 'MP5_F08_QUAD_117_REC_3_CMP' U2- NET 'MP5_F02_QUAD_118_REC_0_DIR' U2- NET 'MP5_F02_QUAD_118_REC_0_CMP' U2- NET 'MP5_F04_QUAD_118_REC_1_DIR' U2- NET 'MP5_F04_QUAD_118_REC_1_CMP' U2- NET 'MP5_F06_QUAD_118_REC_2_DIR' U2- NET 'MP5_F06_QUAD_118_REC_2_CMP' U2- NET 'MP5_F00_QUAD_118_REC_3_DIR' U2- NET 'MP5_F00_QUAD_118_REC_3_CMP' U2- # Now connect the GTX Termination Calibration Resistor # This is a precision 100 Ohm resistor. # See Chapter 5 page 274 of the # Virtex-6 GTX User Guide. # # The other half of these connections is in: # # ..../Everything_Else/dci_gtx_res_nets_n2p.txt # NET 'TP_MGTRREF' U2- # B11 Topological MGTRREF pin NET 'TP_GTX_AVTT' U2- # A12 Topological MGTAVTTRCAL # connected to the TP_GTX_AVTT bus # as indicated in the User Guide