############################################################################################ # # CMX Net-to-Resource File for the # TP Function FPGA IO signals used for the On-Card VME bus signals # -=============----------------------------------------------------- # # # Original Rev. 11-Dec-2012 Copy Base FPGA pin assignment # Most Recent Rev: 14-Jan-2013 Assign outer pins from IO banks 15, 16 &17 and route on layers 7 (most) & 6 (with via) # # # Signal Nets referenced in this file: # ------------------------------------ # # 'OCB_Axx' are the On-Card Bus Address lines to the Base FPGA with xx=01 to 23 # (note there is no "A00" signal) # # 'OCB_Dyy' are the On-Card Bus Data lines to the Base FPGA with yy=00 to 15 # # 'OCB_GEO_ADRS_z' are the On-Card Bus Geographic Section Address lines with z=0 to 6 # # # 'OCB_SYS_RESET_B' is the On-Card Bus VME SYS_RESET signal # The "_B" postfix is used to indicate that the reset request is active # when the electrical signal is low # # 'OCB_DS_B' is the On-Card Bus Data strobe. # The "_B" postfix is used to indicate that the data strobe signal is on the # falling edge of the electrical signal. # # 'OCB_WRITE_B' is the On-Card Bus Data Direction # The "_B" postfix is used to indicate that the Write direction is # requested when the electrical signal is low. # # # IO Banks used # ------------- # # Most signal nets are assigned to IO Bank 14 and a few to Io Bank 13 # - All address line nets are in IO Bank 14 # - All data line nets are in IO Bank 14 # - The Data Strobe net is assigned to a regional clock pin in IO Bank 14 # - The Board Select net is assigned to a regional clock pin in IO Bank 13 # - The Write Net is assigned to an IO input pin in Bank 13 # - The Sys_Reset net is assigned to an IO input pin in Bank 13 # # The bulk of IO Bank 13 is used for the CTP output signals # # Note: Trace layer information is appended as comments below. # ----- # # NET 'OCB_A01' U2- #> F07 #> T07 A01 AF41 # # ^ ^ ^ ^ ^ # | | | | | # Tailored comment flag to help with string searches ------------------+ | | | | # | | | | # Target Trace Layer number to use for this net --------------------------+ | | | # as it exits the FPGA (to reach a nearby via if needed) | | | # F01 is top layer, F02 the first inner layer, etc | | | # | | | # Target Trace Layer number to use for this net ---------------------------------+ | | # as it connects the VME bus transceiver section to the two FPGAs | | # T01 is top layer, T02 the first inner layer, etc | | # | | # Signal number is repeated to help manual entry of Pin Number ---------------------+ | # | # Target Pin Number read from paper drawing ---------------------------------------------+ # and cross-checked after Match_Res2Pin # ############################################################################################ # The lower Address (1:16), all Data lines, and the Data Strobe, will come in directly (no via) # The data strobe is assigned to a regional clock input pin (but probably not used as a clock) NET 'OCB_A01' U2- #> F07 #> T07 A01 AF41 NET 'OCB_A02' U2- #> F07 #> T07 A02 AF42 NET 'OCB_A03' U2- #> F07 #> T07 A03 AE40 NET 'OCB_A04' U2- #> F07 #> T07 A04 AE42 NET 'OCB_A05' U2- #> F07 #> T07 A05 AD41 NET 'OCB_A06' U2- #> F07 #> T07 A06 AD42 NET 'OCB_A07' U2- #> F07 #> T07 A07 AC41 NET 'OCB_A08' U2- #> F07 #> T07 A08 AC40 NET 'OCB_A09' U2- #> F07 #> T07 A09 AB42 NET 'OCB_A10' U2- #> F07 #> T07 A10 AB41 NET 'OCB_A11' U2- #> F07 #> T07 A11 AB39 NET 'OCB_A12' U2- #> F07 #> T07 A12 AA40 NET 'OCB_A13' U2- #> F07 #> T07 A13 AA41 NET 'OCB_A14' U2- #> F07 #> T07 A14 AA42 NET 'OCB_A15' U2- #> F07 #> T07 A15 Y40 NET 'OCB_A16' U2- #> F07 #> T07 A16 Y42 NET 'OCB_D00' U2- #> F07 #> T07 D00 L41 NET 'OCB_D01' U2- #> F07 #> T07 D01 L42 NET 'OCB_D02' U2- #> F07 #> T07 D02 M41 NET 'OCB_D03' U2- #> F07 #> T07 D03 M42 NET 'OCB_D04' U2- #> F07 #> T07 D04 N41 NET 'OCB_D05' U2- #> F07 #> T07 D05 P41 NET 'OCB_D06' U2- #> F07 #> T07 D06 P42 NET 'OCB_D07' U2- #> F07 #> T07 D07 R40 NET 'OCB_D08' U2- #> F07 #> T07 D08 R42 NET 'OCB_D09' U2- #> F07 #> T07 D09 T41 NET 'OCB_D10' U2- #> F07 #> T07 D10 T42 NET 'OCB_D11' U2- #> F07 #> T07 D11 U41 NET 'OCB_D12' U2- #> F07 #> T07 D12 U42 NET 'OCB_D13' U2- #> F07 #> T07 D13 V41 NET 'OCB_D14' U2- #> F07 #> T07 D14 W41 NET 'OCB_D15' U2- #> F07 #> T07 D15 W42 NET 'OCB_DS_B' U2- #> F07 #> T07 DS W32 # The upper Address (17:23), the Direction, SysReset, and all Geographic Address signals # will need to transition to another trace layer (tentatively trace layer 2) NET 'OCB_A17' U2- #> F02 #> T07 A17 W38 NET 'OCB_A18' U2- #> F02 #> T07 A18 W40 NET 'OCB_A19' U2- #> F02 #> T07 A19 V40 NET 'OCB_A20' U2- #> F02 #> T07 A20 U39 NET 'OCB_A21' U2- #> F02 #> T07 A21 T40 NET 'OCB_A22' U2- #> F02 #> T07 A22 R39 NET 'OCB_A23' U2- #> F02 #> T07 A23 P40 NET 'OCB_WRITE_B' U2- #> F02 #> T07 WRI Y39 NET 'OCB_SYS_RESET_B' U2- #> F02 #> T07 RES AA39 NET 'OCB_GEO_ADRS_0' U2- #> F02 #> T07 GA0 AB38 NET 'OCB_GEO_ADRS_1' U2- #> F02 #> T07 GA1 L40 NET 'OCB_GEO_ADRS_2' U2- #> F02 #> T07 GA2 M39 NET 'OCB_GEO_ADRS_3' U2- #> F02 #> T07 GA3 N40 NET 'OCB_GEO_ADRS_4' U2- #> F02 #> T07 GA4 AC39 NET 'OCB_GEO_ADRS_5' U2- #> F02 #> T07 GA5 AD40 NET 'OCB_GEO_ADRS_6' U2- #> F02 #> T07 GA6 AE39