############################################################################################ # # CMX Net-to-Resource File for the # Topo Function FPGA IO signals used for the connections to the Board Support FPGA # -=============------------------------------------------========================== # # # Original Rev. 28-Mar-2012 # Rev. 03-Apr-2013 find location for these 15x signals # Most Recent Rev. 20-Jun-2013 Swap TP_TO_FROM_BSPT_6 and _7 to help trace layout # # Signal Nets referenced in this file: # ------------------------------------ # # TP_REQ_CTP_n_INPUT (n=1:2) 2x direction request for CTP cable n sent to BSPT FPGA # # TP_LED_REQ_n (n=0:4) 5x LED state request sent to BSPT FPGA # # TP_TO_FROM_BSPT_n (n=0:7) 8x un-assigned Input or Ouput connections to BSPT FPGA # ############################################################################################ # 15x signals are going to the Board Support FPGA on layer 7 # These signals are listed in west to east order as they leave the FPGA area on layer 7 NET 'TP_REQ_CTP_1_INPUT' U2- #> F07 #> T07 A32 NET 'TP_REQ_CTP_2_INPUT' U2- #> F07 #> T07 B32 NET 'TP_LED_REQ_0' U2- #> F07 #> T07 B33 NET 'TP_LED_REQ_1' U2- #> F07 #> T07 A34 NET 'TP_LED_REQ_2' U2- #> F01 #> T07 B34 NET 'TP_LED_REQ_3' U2- #> F01 #> T07 A35 NET 'TP_LED_REQ_4' U2- #> F01 #> T07 C35 NET 'TP_TO_FROM_BSPT_0' U2- #> F06 #> T07 A36 NET 'TP_TO_FROM_BSPT_1' U2- #> F06 #> T07 B36 NET 'TP_TO_FROM_BSPT_2' U2- #> F01 #> T07 A37 NET 'TP_TO_FROM_BSPT_3' U2- #> F01 #> T07 B37 NET 'TP_TO_FROM_BSPT_4' U2- #> F01 #> T07 C38 NET 'TP_TO_FROM_BSPT_5' U2- #> F07 #> T07 B39 NET 'TP_TO_FROM_BSPT_6' U2- #> F07 #> T07 B41 NET 'TP_TO_FROM_BSPT_7' U2- #> F07 #> T07 C40